TW202143415A - Semiconductor structure and method for manufacturing a plurality thereof - Google Patents

Abstract

A semiconductor structure is provided. The semiconductor structure includes a first hybrid bonding structure, a memory structure, and a control circuit structure. The first hybrid bonding structure includes a first surface and a second surface. The memory structure is in contact with the first surface. The control circuit structure is configured to control the memory structure. The control circuit structure is in contact with the second surface. A system in package (SiP) structure and a method for manufacturing a plurality of semiconductor structures are also provided.

Description

Semiconductor structure and method for manufacturing plural semiconductor structures

The present disclosure relates to a semiconductor structure and a method of manufacturing a plurality of semiconductor structures. In particular, the disclosed semiconductor structure has a memory structure integrated with a logic structure through a wafer stacking technology.

Based on the prospect of high performance, the implementation of system-on-chip (SOC) has been greatly promoted; SOC, as a structure that embeds DRAM arrays into logic elements, is considered to be better for high-speed transmission of large amounts of data solution. However, the merging of DRAM and logic components needs to reduce the difference in the manufacturing process of the two. For example, the compatibility of the design rules of SOC, logic components and embedded DRAM is crucial.

The process of coordinating the compatibility of the logic element and the embedded DRAM mainly depends on several different methods. For example, the memory circuit is integrated into a logic element optimized by high-performance technology, or the logic circuit is integrated into a high-density, low-performance DRAM optimized by technology. Either option has advantages and disadvantages. Generally, combining DRAM and logic components on the same chip can produce huge advantages, but this is not easy to achieve, and the integration process is full of challenges. That is to say, because the manufacturing process of the logic element and the manufacturing process of the DRAM are incompatible in many aspects, it is necessary to propose a new method to solve the problem for the integration of these semiconductor structures.

An embodiment of the present invention relates to a semiconductor structure including: a first hybrid bonding structure having a first surface and a second surface; a memory structure contacting the first surface; and a control The circuit structure is used to control the memory structure and contact the second surface.

An embodiment of the present invention relates to a system-in-package structure, which includes: a first semiconductor structure having a first critical dimension; a second semiconductor structure stacked with the first semiconductor structure and having a The second critical dimension is in contact with the first semiconductor structure via a hybrid bonding interface; and a substrate, which is electrically connected to the first semiconductor structure and the second semiconductor structure via a first conductive bump; Wherein, the first critical dimension is different from the second critical dimension.

An embodiment of the present invention relates to a method of manufacturing a plurality of semiconductor structures. The method includes: forming a first hybrid bonding layer on a first wafer having a plurality of first memory structures; forming a second The hybrid bonding layer is on a second wafer having a plurality of control circuit structures; the first wafer and the second wafer are bonded through a first hybrid bonding step to connect the first hybrid bonding Layer and the second hybrid bonding layer, thereby obtaining a first bonding wafer; and at least the first wafer, the second wafer, the first hybrid bonding layer, and the second hybrid bonding layer Singulate to obtain a plurality of semiconductor structures.

This application claims the priority of U.S. Provisional Patent Application No. 63/021,608 filed on May 7, 2020, and the entire disclosure of the case is incorporated herein by reference.

The following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first member formed on or on a second member may include an embodiment in which the first member and the second member are formed in direct contact, and may also include additional members therein An embodiment that can be formed between the first member and the second member so that the first member and the second member may not directly contact. In addition, the present disclosure may repeat element symbols and/or letters in each example. This repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, spatial relative terms such as "below", "below", "below", "above", "above", "above" and the like can be used in this article To describe the relationship between one element or component and another element or component(s), it is illustrated in the figure. Spatial relative terms are intended to cover different orientations of devices in use or operation other than those depicted in the figures. The device can be oriented in other ways (rotated by 90 degrees or in other orientations) and therefore the spatial relative descriptors used in this article can be interpreted as well.

As used herein, terms such as "first", "second" and "third" describe various elements, components, regions, layers and/or sections, and these elements, components, regions, layers and/or regions The paragraph should not be restricted by these terms. These terms can only be used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Unless clearly indicated by the context, terms such as "first", "second" and "third" when used herein do not imply a sequence or order.

For example, high bandwidth memory (HBM) is a CPU or GPU memory system in which memory dies are vertically stacked on logic dies. The stacked memory dies are located on the logic die in the form of memory towers with distinguishable levels, in which every two adjacent memory dies are formed by micro bumps laterally surrounded by the molding material. Connected. Although these HBM stacks are not physically integrated into the CPU or GPU, they are already very close and are quickly connected to the CPU or GPU through the interposer. Therefore, the characteristics of the HBM are almost the same as the memory integrated into the chip.

Generally speaking, before operating stacked memory dies through micro bumps, these memory dies used in the HBM structure have usually undergone cutting tests, such as known good dies obtained through some standard electrical testing operations. Grain (known good die, KGD). These KGDs can then be stacked or packaged for high-end applications. Each memory die is bonded by micro bumps to form a memory stack (which may include control circuit die), and the memory die is further bonded to the silicon interposer by flip chip to form a wafer Chip-on-wafer (CoW) structure. However, the micro-bump operation will cause high costs, the process of selecting KGD will reduce the production efficiency, and the stacking defects caused by the micro-bump operation will reduce the production yield.

Therefore, some embodiments of the present disclosure provide a memory structure integrated with a control circuit, which is completed by wafer stacking instead of CoW operation. The control circuit may contain one or more logical structures. In other words, the memory structure on the control circuit can be manufactured through a hybrid bonding operation based on wafer-on-wafer or wafer-to-wafer. The memory stack (which may contain a control circuit) can be cut or separated after the hybrid bonding operation is completed. In this way, the production efficiency of forming memory stacks can be greatly improved, and the risk of stacking defects caused by micro bump operations can also be significantly reduced. As for the aspect where the KGD selection of the memory die is omitted, the test operation can be performed on the memory block of the memory die by providing a control circuit, without the use of a probe measuring or testing machine. For example, US Patent Application No. US 16/899,166 "Semiconductor Device and Manufacturing Method", which is used as reference material in this case.

FIG. 1A shows a semiconductor structure including a memory structure integrated with a control circuit structure through wafer stacking. In some embodiments, the control circuit structure may include at least one logic structure, for example, a transistor having the smallest line width of a semiconductor structure. As shown in the figure, the semiconductor structure includes a hybrid bonding structure 10, a memory structure 100, and a control circuit structure 200. The hybrid bonding structure 10 includes a first surface 101A and a second surface 201A opposite to the first surface 101A. The hybrid bonding structure 10 is sandwiched between the memory structure 100 and the control circuit structure 200. The hybrid bonding structure 10 is used to integrate the memory structure 100 and the control circuit structure 200. In some embodiments, the memory structure 100 is in contact with the first surface 101A of the hybrid bonding structure 10. The control circuit structure 200 is in contact with the second surface 201A of the hybrid bonding structure 10.

In some embodiments, the hybrid bonding structure 10 includes a first hybrid bonding layer 101 close to the memory structure 100 and a second hybrid bonding layer 201 close to the control circuit structure 200. The first hybrid bonding layer 101 is formed on the memory structure 100 and used for bonding the second hybrid bonding layer 201. The second hybrid bonding layer 201 is formed on the control circuit structure 200 and is used for bonding the first hybrid bonding layer 101. In some embodiments, each of the first hybrid bonding layer 101 and the second hybrid bonding layer includes a plurality of bonding pads surrounded by a side surface of a dielectric material. Examples of the dielectric material include oxide.

Hybrid bonding is a method that can connect two substrates or wafers by metal bonding and oxide bonding at the same time, which means that it can allow two substrates or wafers to be "face-to-face" or "face-to-back". Or "back-to-back" connection. For illustrative purposes, FIG. 1B shows the definition of the front and back sides of a semiconductor structure or semiconductor wafer. For a semiconductor structure 80 (for example, the memory structure 100 or the control circuit structure 200 shown in FIG. 1A) or a wafer, the semiconductor structure may include a semiconductor substrate 83 and a back-end process structure 85, and a front-end process structure The process structure 84 is formed on or in the semiconductor substrate 83. According to some embodiments, the surface of the back-end process structure 85 may be the front surface 81 of the semiconductor structure 80, and the surface of the semiconductor substrate 83 may be the back surface 82 of the semiconductor structure 80. However, this does not constitute a limitation of this embodiment. For the front or back of the semiconductor structure, the definition can also be exchanged. In some implementations, the position of the memory structure 100 and the position of the control circuit structure 200 can be vertically aligned through bonding, and the plurality of first bonding pads 102 of the first hybrid bonding layer 101 can therefore be bonded to the second hybrid bonding layer. The plurality of second bonding pads 202 of the bonding layer 201 are in contact; at the same time, the plurality of first oxide portions 103 of the first hybrid bonding layer 101 are connected with the plurality of second oxides of the second hybrid bonding layer 201 The object part 203 is in contact with each other. In these embodiments, the first bonding pad 102 of the first hybrid bonding layer 101 and the second bonding pad 202 of the second hybrid bonding layer 201 are distributed in mirror images.

In some embodiments, the first bonding pad 102 and the second bonding pad 202 are made of copper (Cu). In some embodiments, the first oxide portion 103 and the second oxide portion 203 are made of dielectric materials _{such as silicon dioxide (SiO 2 ).} In order to strengthen the copper-copper connection, the control of the surface flatness of the bonding pad is an important factor. For example, in some embodiments, the surface of the copper bonding pad can be controlled to be substantially flush with the silicon dioxide part by performing a chemical mechanical polishing (CMP) operation. In some embodiments, depending on the hybrid bonding operation performed, the silicon dioxide portion may slightly protrude from the copper bonding pad. In this disclosure, for example, the memory structure 100 and the control circuit structure 200 can be bonded by first contacting the first oxide portion 103 with the second oxide portion 203; the bond between the aforementioned oxide portions He can pass through van der Waals force. After that, an annealing operation may be performed to facilitate the connection between the first bonding pad 102 and the second bonding pad 202.

In some embodiments, the control circuit structure 200 is a DRAM control logic. In some embodiments, in addition to controlling the memory structure 100, the control circuit structure 200 can also be further used as a system-on-chip (SoC) integrated with a GPU or a CPU.

As shown in FIG. 2, the semiconductor structure of the present disclosure may include a system in package (SiP) structure. In these implementations, the system and package structure includes a first semiconductor structure 100', a second semiconductor structure 200', and a substrate 500. The second semiconductor structure 200' is stacked with the first semiconductor structure 100'. The second semiconductor structure 200' is in contact with the first semiconductor structure 100' via the hybrid bonding interface 1201. The substrate 500 is electrically connected to the first semiconductor structure 100' and the second semiconductor structure 200' via a first conductive bump connection portion 501. The first conductive bump connection portion 501 may include a plurality of solders, and these solders may be surrounded by a suitable underfill material (not shown in the figure).

In some embodiments, the first semiconductor structure 100' may include a plurality of memory dies (ie, memory dies 100A, 100B, 100C, 100D, etc.) stacked on the second semiconductor structure 200'. In some embodiments, at least two memory dies are hybrid bonded via a second hybrid bonding structure 20. In some embodiments, two adjacent memory die are hybrid bonded via the second hybrid bonding structure 20. The details of the second hybrid bonding structure 20 are the same as those of the first hybrid bonding structure 10 described previously, except that the bonding pads distributed in mirror images are formed on adjacent memory die at this time. In some embodiments, each memory die of the first semiconductor structure 100' may include a DRAM structure having a first critical dimension (that is, the smallest line width that can be achieved in the structure through the lithography process operation). ). Similarly, the second semiconductor structure 200' may include a logic structure having at least a second critical dimension (that is, the smallest line width that can be achieved in the structure through the lithography process operation). Since different technology nodes can be implemented to manufacture the first semiconductor structure 100' and the second semiconductor structure 200', the first critical dimension is different from the second critical dimension. In some embodiments, when the technology node implemented to manufacture the first semiconductor structure 100' is relatively advanced, the first critical dimension is smaller than the second critical dimension. In another embodiment, when the technology node implemented for manufacturing the second semiconductor structure 200' is relatively advanced, the first critical dimension is larger than the second critical dimension. It should be noted that when the first semiconductor structure 100' and the second semiconductor structure 200' are manufactured by the same technology node, the first critical dimension may be equal to the second critical dimension.

In the present disclosure, the number of memory die vertically stacked on the second semiconductor structure 200' through hybrid bonding can be customized. For example, in view of the fact that in the traditional structure, there are usually four or eight memory die stacked on the control circuit or logic die through the micro bumps. Accordingly, some embodiments of the present disclosure are based on Four memory dies are vertically stacked on the second semiconductor structure 200' through hybrid bonding as an example, but in fact, the number of memory dies is not limited to this number or range.

In some embodiments, the second semiconductor structure 200' is a DRAM control logic. In some embodiments, the second semiconductor structure 200' is a memory die 100A bonded to the first semiconductor structure 100' through the first hybrid bonding structure 10 shown in FIG. 1A. In some embodiments, the bonding structure in the first semiconductor structure 100' and the bonding structure between the first semiconductor structure 100' and the second semiconductor structure 200' are different from the second semiconductor structure 200' and the substrate 500 The bonding structure between. For example, the first hybrid bonding structure 10 and the second hybrid bonding structure 20 are formed through appropriate hybrid bonding operations, and are characterized by the hybrid bonding interface 1201; and the first conductive bump connection portion 501 is It is formed by proper micro-bump operation, and multiple solder bumps can be observed.

In some embodiments, the SiP structure may include a third semiconductor structure 300 electrically connected to the first semiconductor structure 100' and the second semiconductor structure 200' via a second conductive bump connection portion 401. The second conductive bump connection portion 401 may include a plurality of solders, and these solders may be surrounded by a suitable underfill material (not shown in the figure). In some embodiments, the third semiconductor structure 300 has a third critical dimension, which is smaller than the first critical dimension of the first semiconductor structure 100'. In some embodiments, the third semiconductor structure 300 is adjacent to a stack formed by the first semiconductor structure 100' and the second semiconductor structure 200'. In some embodiments, the third semiconductor structure 300 is used as an SOC for GPU or CPU.

In some embodiments, the SiP structure may include an interposer 400 between the substrate 500 and the second semiconductor structure 200'. The interposer 400 can be used to support the first semiconductor structure 100', the second semiconductor structure 200', and the third semiconductor structure 300. Although not shown in FIG. 2, the interposer 400 transmits signals laterally through the second conductive bump connection portion 401, the first conductive bump connection portion 501, and is located between the third semiconductor structure 300 and the second semiconductor structure 200' One of the redistribution layers is thus electrically connected to the first semiconductor structure 100 ′, the second semiconductor structure 200 ′, and the substrate 500. The redistribution layer of the interposer 400 can also enable the higher density I/Os near the second semiconductor structure 200' to be reorganized into lower density I/Os near the substrate 500.

As mentioned earlier, hybrid bonding allows two substrates or wafers to be connected in a "face-to-face" or "face-to-back" arrangement. In some embodiments, by virtue of different hybrid bonding schemes and many optional sequences when manufacturing the through holes of each memory die and logic die, the substrate or wafer of the memory die and the logic die The stacking can therefore have different application forms.

As shown in FIG. 3, in some embodiments, each memory structure and control circuit structure are manufactured through a via-last process. After the post-drilling process, through-silicon vias (TSV) are formed after the transistor is prepared and wire-bonded; in other words, the front-end process (FEOL) structure and the back-end process (BEOL) structure are both formed in the pass Before operations such as hole etching and via filling. In these embodiments, the logic die and the memory die can be stacked in a "face-to-face" arrangement, and the memory die in the memory structure can be stacked in a "back-to-back" arrangement (Scheme I) . On the other hand, the bonding pads scattered on the logic die and the bonding pads scattered on the memory die are distributed in mirror images. In addition, in the embodiment with the stacked arrangement of Scheme 1, the second surface 201A of the hybrid bonding structure 10 shown in FIG. The front-end process structure of structure 200.

As shown in FIG. 3, since the memory die is manufactured from a first wafer 61 (disclosed in FIG. 4A later), each memory die includes a first front surface 61A and a first back surface 61B; The circuit structure 200 is manufactured from a second wafer 62 (discussed in FIG. 4A later), and has a second front surface 62A and a second back surface 62B. The first hybrid bonding structure 10 is sandwiched between the control circuit structure 200 and the memory die 100A. In addition, each second hybrid bonding structure 20 is sandwiched between adjacent memory dies, for example, between memory dies 100A and 100B. In some embodiments, each second hybrid bonding structure 20 includes two first hybrid bonding layers 101, wherein the bonding pads located in the first hybrid bonding layers 101 are along the hybrid bonding interface 1201. It is a mirrored distribution.

The semiconductor structure shown in FIG. 3 can be manufactured with reference to FIGS. 4A to 4J. As shown in FIG. 4A, in some embodiments, the memory structure 100 (ie, memory die) and the control circuit structure 200 (ie, logic die) are formed on the first wafer 61 before the hybrid bonding operation. And second wafer 62. Each of the first wafer 61 and the second wafer 62 may include a plurality of die regions, and the present disclosure only shows one of the die regions as an example. In some embodiments, each memory structure 100 may include a first reserved area 631. Similarly, each control circuit structure 200 can include a second reserved area 632. The first reserved area 631 and the second reserved area 632 are reserved for subsequent operations to form a TSV there, because the position of the bonding pad can be related to the position of the TSV. As mentioned above, since the bonding pads in the hybrid bonding layer should be mirrored, when designing the layout of each memory structure 100 (ie, memory die) and control circuit structure 200 (ie, logic die) , The aforementioned first reserved area 631 and second reserved area 632 can be planned in advance.

As shown in FIG. 4B, a first TSV 104 and a second TSV 204 may be formed adjacent to the first front surface 61A of the first wafer 61 and the second front surface 62A of the second wafer 62, respectively. In some embodiments, the first TSV 104 and the second TSV 204 are formed by a via etching operation, and the hole structure of the via is filled with a conductive material by an electroplating operation. In the operation stage as shown in FIG. 4B, only one end of the first TSV 104 and the second TSV 204 may be exposed outside the first wafer 61 and the second wafer 62, respectively; however, in the subsequent wafer thinning operation In the middle (as shown in FIG. 4F and FIG. 4I), both ends of the first TSV 104 and the second TSV 204 can be exposed outside the first wafer 61 and the second wafer 62, respectively.

As shown in FIG. 4C, in some embodiments, after forming the first TSV 104 and the second TSV 204, a first metal layer 105 may be formed on the first surface 61A of the first wafer 61 to connect the first TSV 104 and the second TSV 204. TSV 104 and a top metal 106. Similarly, a second metal layer 205 can be formed on the second front surface 62A of the second wafer 62 to connect the second TSV 204 and a top metal 206.

As shown in FIG. 4D, in some embodiments, the first hybrid bonding layer 101 is formed on the first front surface 61A of the first wafer 61. Similarly, the second hybrid bonding layer 201 is formed on the first front surface 62A of the second wafer 62. In some embodiments, the first hybrid bonding layer 101 includes the first bonding pad 102 as shown in FIG. 1A. In some embodiments, the first hybrid bonding layer 101 further includes a plurality of first conductive vias 108 located in a first hybrid bonding portion 107 thereof. In other words, the first hybrid bonding portion 107 may include a metal via structure to connect the first bonding pad 102 and the first metal layer 105. Since the first conductive via 108 can be designed to have a small critical size (for example, a small diameter), in order to increase the product yield, a plurality of first conductive vias 108 corresponding to the first bonding pad 102 can be formed. To prevent connection defects caused by manufacturing operations. The first TSV 104 can be coupled to one end of the first conductive via 108 via the first metal layer 105, and the first bonding pad 102 can be in contact with the other end of the first conductive via 108. Similarly, in some embodiments, the second hybrid bonding layer 201 further includes a plurality of second conductive vias 208 located in a second hybrid bonding portion 207 thereof. The second TSV 204 can be coupled to one end of the second conductive via 208 via the second metal layer 205, and the second bonding pad 202 can be in contact with the other end of the second conductive via 208. The conductive vias in these embodiments can enhance the conductivity between the bonding pad and the TSV.

In addition, in some embodiments, the first hybrid bonding portion 107 may further include a third bonding pad 102', which is electrically disconnected from the memory structure 100. In other words, the third bonding pad 102' is a dummy bonding pad, which is only used for hybrid bonding and is not coupled to the first metal layer 105. Similarly, the second hybrid bonding part 207 may further include a fourth bonding pad 202' which is electrically disconnected from the control circuit structure 200. The third bonding pad 102' can be used for hybrid bonding to the fourth bonding pad 202' in a subsequent hybrid bonding operation.

As shown in FIG. 4E, the first wafer 61 is turned over and stacked on the second wafer 62 through a hybrid bonding operation, wherein the first front surface 61A faces the second front surface 62A, thereby performing two "Face-to-face" stacking between people. In this stacking, the first bonding pad 102 is in contact with the second bonding pad 202 for hybrid bonding and electrical connection; and the third bonding pad 102' is in contact with the fourth bonding pad 202'. Only used for mixed bonding. In some embodiments, the first wafer 61 and the second wafer 62 are hybrid bonded under suitable conditions. In some embodiments, the first TSV 104 and the second TSV 204 are formed in the first reserved area 631 and the second reserved area 632, respectively. After the hybrid bonding operation, it can be observed that the first TSV 104 and the second TSV 204 are located on the same side of the first bonding pad 102 and the second bonding pad 202 in the stacked structure.

Through the hybrid bonding operation described above, the first wafer 61 and the second wafer 62 are hybrid bonded. The first bonding layer 101 on the first wafer 61 is the second bonding layer 201 on the second wafer 62 Are connected to each other, thereby obtaining a first bonded wafer 64. In some embodiments, the first bonding wafer 64 can be singulated successively to obtain a plurality of semiconductor structures, wherein each semiconductor structure includes the memory structure 100 and the control circuit structure shown in FIG. 1A. 200. In some other embodiments, and will be mentioned in the following FIGS. 4F to 4G, depending on the product requirements and the current process technology, there may be other additional wafers that are the same as the first wafer 61 It can be bonded to the first bonding wafer 64, that is, stacking an extra number of memory dies on the logic die based on the wafer-to-wafer packaging basis.

As shown in FIG. 4F, in some embodiments, after bonding the first wafer 61 and the second wafer 62, the first wafer 61 is thinned from the first back surface 61B to expose the first TSV 104. The thinning operation can be performed by mechanical polishing, chemical mechanical polishing, wet etching, dry etching, or a combination thereof. In some embodiments, the thickness of the first wafer 61 may be thinned to less than 50 microns.

As shown in FIG. 4G, in some embodiments, another first hybrid bonding layer (for example, the fourth hybrid bonding layer 101B shown in the figure) may be formed on the first bonding wafer 64 and electrically conductive Connect to the exposed first TSV 104. In addition, as shown in FIG. 4H, in some embodiments, another first wafer (for example, the third wafer 61C with the third hybrid bonding layer 101C shown in the figure) may be hybrid bonded Operate and stack on the fourth hybrid bonding layer 101B formed in FIG. 4G in the previous disclosure. Regarding the part of the third wafer 61C, before forming the third hybrid bonding layer 101C on the third wafer 61C, a third TSV may be formed at the position of the third wafer 61C adjacent to the first front surface 61A. 104C.

The third hybrid bonding layer 101C and the fourth hybrid bonding layer 101B have to be connected through a hybrid bonding operation, and a second bonded wafer 65 can be obtained as a result. The second bonding wafer 65 can be thinned to expose the third TSV 104C for another round of stacking operation. In other words, the stacking of memory dies is essentially by repeatedly forming a memory wafer similar to the first wafer 61 with the first hybrid bonding layer 101 thereon, and forming the first hybrid bonding layer again 101, until a total of four or eight wafers are stacked through multiple hybrid bonding operations. In these embodiments, memory wafers similar to the first wafer 61 are stacked in the same direction. In other words, the memory dies of the memory structure are stacked in a “face-to-back” arrangement.

As shown in FIG. 4I, in some embodiments, a top first wafer 61' can omit the thinning operation shown in FIG. 4F, because it is no longer necessary to form a first hybrid bonding layer on it. Accordingly, a top first TSV 104' may not be exposed to a top first back surface 61B' of the top first wafer 61', and the thickness of a top memory die is larger than that of the top memory die and the control circuit structure The thickness of at least one memory die between 200. In some embodiments, after the memory dies are stacked through hybrid bonding, the second wafer 62 is thinned from the second back surface 62B to expose the second TSV 204. The thinning operation can be performed by mechanical polishing, chemical mechanical polishing, wet etching, dry etching, or a combination thereof. In some embodiments, the thickness of the second wafer 62 may be thinned to less than 50 microns.

As shown in FIG. 4J, after the second wafer 62 is thinned from the second back surface 62B, a bottom metal layer 209 may be formed on the second back surface 62B to be electrically connected to the second TSV 204. Then, the second conductive bump connecting portion 401 can be arranged to contact the bottom metal layer 209 to be electrically connected to the interposer 400.

Before the control circuit structure 200 and the memory structure 100 are stacked on the interposer 400, the stacked second wafer 62 and the first wafer 61 can be singulated to obtain a plurality of semiconductors as shown in FIG. 3 structure. As shown in FIG. 5A, in some embodiments, the singulation operation of the bonded wafer (ie, the first bonded wafer 64 or the second bonded wafer 65) includes performing a laser scribing operation. In some embodiments, a laser 70 may be used to cut at least a portion of the stacked wafer. In some embodiments, an unthinned wafer (such as the top first wafer 61' shown in FIG. 4I) can be used as a bulk substrate, and the dicing line 71 formed by the laser scribing can stop at Among the bulk substrates. In some embodiments, a mechanical cutting operation can be followed by a laser scribing operation; for example, as shown in FIG. 5B, a mechanical saw 72 is used to cut through the bulk substrate of the top first wafer 61', thereby completely Separate out a single memory stack.

In some embodiments, the operation of singulating the first wafer and the second wafer may include performing a plasma etching operation. As shown in FIG. 6A, a photoresist layer 73 can be disposed on the side of the bulk substrate of the wafer stack opposite to the top first wafer 61', and an anisotropic plasma etching can stop the formation of the stacked structure at A groove in the bulk substrate. As shown in FIG. 6B, successively, a polishing operation may be performed on the bulk substrate of the top first wafer 61' after the plasma etching operation, thereby completely separating a single memory stack. However, this is not a limitation of this embodiment. In other embodiments, a polishing operation may be performed on the bulk substrate of the top first wafer 61' first, and then a plasma etching operation may be performed on the stacked second wafer 62 and the first wafer 61 to separate A single memory stack is created.

By applying the above-mentioned singulation operation, the first wafer 61, the second wafer 62, the first hybrid bonding structure 10 between the first wafer 61 and the second wafer 62, and the adjacent first wafer The second hybrid bonding structure 20 between the wafers 61 can be completely separated to obtain a plurality of semiconductor structures including the above-mentioned structures. In some embodiments, as shown in FIG. 7, the memory structure 100 has a first side surface 100C', the first hybrid bonding structure 10 has a second side surface 10C, and the control circuit structure 200 has a third side Surface 200C; wherein, the first side surface 100C', the second side surface 10C, and the third side surface 200C have substantially the characteristic of a continuous line at a cross-sectional angle. In addition, due to the singulation operation, the continuous line may not be perfectly vertical due to the cutting edge produced by laser scribing or plasma etching, which means that in most cases, it may be cut to form a tapered groove. So that the continuous line contains a slope. After the cutting is completed, the tapered groove is transformed into an observable slope at the side surfaces of the memory structure 100, the first hybrid bonding structure 10, and the control circuit structure 200.

As shown in FIG. 8, in some embodiments, the logic die (ie, the control circuit structure 200) and the memory die 100A, 100B, 100C, and 100D may all be arranged in a "face-to-back" arrangement (Scheme II). In these embodiments, the reserved area for TSV in the logic die is substantially the same as the reserved area for TSV in the memory die, and as mentioned above, the first TSV 104 and the second TSV 204 is located on the same side of a specific pair of bonding pads. In addition, in the embodiment with the stacking arrangement of Scheme II, the second surface 201A shown in FIG. 1 is a front-end process structure closer to the control circuit structure 200 and farther from the back-end process structure of the control circuit structure 200. .

9A and 9B show the steps of preparing the semiconductor structure of FIG. 8. As shown in FIGS. 9A and 9B, the second wafer 62 may be thinned before the second back surface 62B to expose the second TSV 204 before the second hybrid bonding layer 201 is formed thereon. Thereafter, the bottom metal layer 209 may be formed on the second front surface 62A to be electrically connected to the exposed second TSV 204. Further, in these embodiments, the second wafer 62 is turned over to form the second hybrid bonding layer 201 on the second back surface 62B of the second wafer 62, and the second hybrid bonding layer 201 can then be combined with The first hybrid bonding layer 101 on the first front surface 61A of the first wafer 61 is hybrid bonded. The hybrid bonding operation mentioned here is the same as the aforementioned hybrid bonding operation, and is shown in FIG. 4E. For further details on stacking the same additional wafers as the first wafer 61 through hybrid bonding, forming the second conductive bump connection portion 401, and cutting the wafer, please refer to the previous disclosure of FIGS. 4F to 4J, which is concise It is omitted here for the sake of simplicity.

As shown in FIG. 10, in some embodiments, each memory structure and control circuit structure are manufactured through a via-middle process; this mid-stage drilling process is also called in some embodiments It is a via-first process. Through the mid-stage drilling process, the formation of TSV is performed after the formation of the transistor and earlier than the subsequent process operations; in other words, operations such as via etching and via filling are performed after the formation of the front-end process structure, but before Before metallization in the later process stage.

In these embodiments, the mixed-bonded logic die and memory die can be arranged in the form of Scheme I and Scheme II previously disclosed. In detail, as shown in FIG. 10, the logic die (ie, the control circuit structure 200) and the memory die 100A are stacked in a "face-to-face" arrangement, and the memory die 100A, 100B, 100C and 100D are stacked in a "face-to-back" arrangement (Scheme I). Because the second TSV 204 in the control circuit structure 200 is formed by a middle drilling process or a front drilling process, it has been electrically connected to a bottom of a metallization structure 210 in the control circuit structure 200. As far as the control circuit structure 200 has been stacked on the memory die 100A in a "face-to-face" arrangement, the second hybrid bonding layer 201' formed on the second front surface 62A of the second wafer can be omitted to form the first Two metal layers 205 (as shown in FIG. 3); instead, as shown in FIGS. 11A and 11B, the second conductive via 208 may be formed close to the second front surface 62A of the second wafer and contact The top metal 206 of the metallization structure 210. Similarly, the first hybrid bonding layer 101' formed on the first front surface 61A of the first wafer may omit the formation of the first metal layer 105 (as shown in FIG. 3); instead, the first conductive via 108 may be formed close to the second front surface 61A of the first wafer and contact the top metal 106 of the metallization structure.

As shown in FIG. 10, in contrast to the first hybrid bonding layer 101' and the second hybrid bonding layer 201' formed on the front surface of the wafer, the first hybrid bond formed on the first back surface 61B of the first wafer The bonding layer 101 and the second back surface 62B of the second wafer may still respectively have the first metal layer 105 and the bottom metal layer 209 to connect the TSV in series to the corresponding bonding pads. For further details about stacking a number of additional wafers identical to the first wafer through hybrid bonding, forming the second conductive bump connection portion 401, and cutting the wafer, please refer to FIGS. 4F to 4J for simplicity. See it and omit it here.

As shown in FIG. 12, in some embodiments, the logic die (ie, the control circuit structure 200) and the memory die 100A, 100B, 100C, and 100D in the memory structure are all processed through the middle drilling process or pre-drilling The process is formed, and the "face-to-back" arrangement is stacked (Scheme II). In these embodiments, due to the "face-to-back" arrangement, as shown in FIGS. 13A and 13B, the second hybrid bonding layer 201 can be formed on the second back 62B of the second wafer 62, and The second metal layer 205 is included. The second hybrid bonding layer 201 can be used for hybrid bonding to the first hybrid bonding layer 101' formed on the first front surface 61A of the first wafer 61, and the first hybrid bonding layer 101' does not include the first hybrid bonding layer 101'. A metal layer 105. For further details about stacking more first wafers through hybrid bonding, forming the second conductive bump connection portion 401 and the bottom metal layer 209, and the cutting operation of the wafer, please refer to FIGS. 4F to 4J, for the sake of brevity. And omitted here.

In some embodiments, the TSV structure of the logic die can be formed through a backside TSV process. That is, as shown in FIG. 14, a back TSV (BTSV) in the control circuit structure 200 is formed after the control circuit structure 200 and the memory die 100A are stacked in a "face-to-face" arrangement, and the memory The memory dies 100A, 100B, 100C, and 100D in the structure are stacked in a "face-to-back" arrangement (Scheme I). Referring to the structural changes shown in FIGS. 15A, 15B, and 15C, in some embodiments, the control circuit structure 200 and the memory dies 100A, 100B, 100C, and 100D are stacked after a hybrid bonding operation (as shown in FIG. 15A), the second wafer 62 is then thinned from its second back surface 62B (as shown in FIG. 15B). In some embodiments, the second wafer 62 is thinned so that the first metal layer 2102 (such as the bottom metal layer in the figure) and the second wafer The thickness between the second back surfaces 62B is less than about 10 microns. Subsequently, a via etching and a via filling operation are performed on the second back surface 62B of the second wafer 62 to form the BTSV 211, which is electrically connected to the metallization structure 210. For further details on stacking the first wafer through hybrid bonding, forming the second conductive bump connection portion 401 and the bottom metal layer 209, and the wafer cutting operation, please refer to the previous figures 4F to 4J, for the sake of brevity And omitted here.

As shown in FIG. 10, FIG. 12, and FIG. 14, in some embodiments, the second TSV 204 is substantially a semi-penetrating through hole, and one end of the second TSV 204 is in contact with a back-end process structure, such as a back-end process metal wire.

In short, based on the many embodiments mentioned above, the process efficiency of forming a memory stack can be significantly improved, and the risk of stacking defects caused by micro-bump operations can also be greatly reduced. In addition, compared with the existing technology, the present disclosure uses a large number of bonding pads to connect the memory structure and the control circuit structure, and uses a large number of bonding pads to connect the memory structure, which can also increase the memory of the existing memory system. Body access bandwidth.

In an exemplary aspect, the present disclosure provides a semiconductor structure. The semiconductor structure includes: a first hybrid bonding structure, a memory structure, and a control circuit structure. The first hybrid bonding structure has a first surface and a second surface. The memory structure is in contact with the first surface. The control circuit structure is used to control the memory structure, and the control circuit structure is in contact with the second surface.

In another exemplary aspect, the present disclosure provides a system-in-package structure. The system-in-package structure includes a first semiconductor structure, a second semiconductor structure, and a substrate. The first semiconductor structure has a first critical dimension. The second semiconductor structure is stacked with the first semiconductor structure. The second semiconductor structure has a second critical dimension and is in contact with the first semiconductor structure through a hybrid bonding interface. The substrate is electrically connected to the first semiconductor structure and the second semiconductor structure through a first conductive bump. The first critical dimension is different from the second critical dimension.

In yet another exemplary aspect, the present disclosure provides a method of manufacturing a plurality of semiconductor structures. It includes the following steps: a first hybrid bonding layer is formed on a first wafer with a plurality of first memory structures; a second hybrid bonding layer is formed on a second wafer with a plurality of control circuit structures On the circle; the first wafer and the second wafer are bonded through a first hybrid bonding step to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bond Bonded wafers; and at least the first wafer, the second wafer, the first hybrid bonding layer and the second hybrid bonding layer are singulated to obtain a plurality of semiconductor structures.

The foregoing content summarizes the structures of several embodiments, so that those familiar with the art can better understand the aspect of the present disclosure. Those familiar with the technology should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purpose and/or achieve the same advantages of the embodiments described herein. Those familiar with this technology should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions and alterations in this article without departing from the spirit and scope of this disclosure.

10: The first hybrid bonding structure 10C: Second side surface 20: The second hybrid bonding structure 61: First wafer 61’: First wafer on top 61A: First front 61B: The first back 61B’: Top first back 62: second wafer 62A: second front 62B: second back 64: The first bonding wafer 65: second bonding wafer 70: Laser 71: Cutting Road 72: mechanical saw 73: photoresist layer 80: semiconductor structure 81: positive 82: Back 83: Semiconductor substrate 84: Front-end process structure 85: Back-end process structure 100: Memory structure 100’: The first semiconductor structure 100A: memory die 100B: memory die 100C: memory die 100C’: the first side surface 100D: memory die 101: The first hybrid bonding layer 101’: The first hybrid bonding layer 101A: First surface 101B: Fourth hybrid bonding layer 101C: The third hybrid bonding layer 102: The first bond pad 102’: The third bonding pad 103: The first oxide part 104: The first TSV 104’: First TSV at the top 104C: Third TSV 105: the first metal layer 106: top metal 107: The first hybrid bonding part 108: first conductive via 200: Control circuit structure 200’: Second semiconductor structure 200C: third side surface 201: The second hybrid bonding layer 201’: The second hybrid bonding layer 201A: second surface 202: The second bond pad 202’: Fourth Bonding Pad 203: The second oxide part 204: Second TSV 205: second metal layer 206: top metal 207: The second hybrid bonding part 208: second conductive via 209: bottom metal layer 210: Metallized structure 2102: The first metal layer 211: BTSV 300: The third semiconductor structure 400: Intermediary board 401: second conductive bump connection part 500: substrate 501: first conductive bump connection part 631: first reserved area 632: second reserved area 1201: Hybrid bonding interface

When read in conjunction with the accompanying drawings, the aspect of the present disclosure is best understood from the following detailed description. It should be noted that according to standard practices in the industry, the various structures are not drawn to scale. In fact, the size of various structures can be increased or decreased arbitrarily for the sake of clarity.

FIG. 1A illustrates a cross-sectional view of some embodiments of the semiconductor structure according to the present disclosure.

FIG. 1B illustrates the definition of the front and back sides of a semiconductor structure or semiconductor wafer.

Figure 2 illustrates a cross-sectional view of some embodiments of the semiconductor structure according to the present disclosure.

FIG. 3 illustrates a cross-sectional view of some embodiments of the semiconductor structure according to the present disclosure.

4A to 4J illustrate cross-sectional views of some embodiments of forming a semiconductor structure according to the present disclosure.

5A to 5B illustrate cross-sectional views of some embodiments of forming a semiconductor structure according to the present disclosure.

6A to 6B illustrate cross-sectional views of some embodiments of forming a semiconductor structure according to the present disclosure.

FIG. 7 illustrates a cross-sectional view of some embodiments of the semiconductor structure according to the present disclosure.

FIG. 8 illustrates a cross-sectional view of some embodiments of the semiconductor structure according to the present disclosure.

9A-9B illustrate cross-sectional views of some embodiments of forming a semiconductor structure according to the present disclosure.

FIG. 10 illustrates a cross-sectional view of some embodiments of the semiconductor structure according to the present disclosure.

11A to 11B illustrate cross-sectional views of some embodiments of forming a semiconductor structure according to the present disclosure.

FIG. 12 illustrates a cross-sectional view of some embodiments of the semiconductor structure according to the present disclosure.

13A to 13B illustrate cross-sectional views of some embodiments of forming a semiconductor structure according to the present disclosure.

FIG. 14 illustrates a cross-sectional view of some embodiments of the semiconductor structure according to the present disclosure.

15A to 15C illustrate cross-sectional views of some embodiments of forming a semiconductor structure according to the present disclosure.

10: The first hybrid bonding structure

20: The second hybrid bonding structure

100’: The first semiconductor structure

100A: memory die

100B: memory die

100C: memory die

100D: memory die

102: The first bond pad

103: The first oxide part

200’: Second semiconductor structure

300: The third semiconductor structure

400: Intermediary board

401: second conductive bump connection part

500: substrate

501: first conductive bump connection part

1201: Hybrid bonding interface

Claims (20)

A semiconductor structure comprising: A first hybrid bonding structure having a first surface and a second surface; A memory structure contacting the first surface; and A control circuit structure for controlling the memory structure and contacting the second surface. The semiconductor structure according to claim 1, wherein the second surface is closer to a back-end process structure of the control circuit structure, and farther away from a front-end process structure of the control structure. The semiconductor structure according to claim 1, wherein the second surface is closer to a front-end process structure of the control circuit structure, and farther away from a back-end process structure of the control structure. The semiconductor structure according to claim 1, wherein the memory structure includes a plurality of memory dies stacked vertically, and at least two memory dies are mixed and bonded through a second hybrid bonding structure. The semiconductor structure according to claim 4, wherein the thickness of the top memory die of one of the memory dies is greater than that of the memory dies disposed between the top memory die and the control circuit structure The thickness of one of the grains. The semiconductor structure according to claim 1, wherein the memory structure and the control circuit structure are vertically bonded via the first hybrid bonding structure, the memory structure has a first side surface, and the first hybrid bond The combined structure has a second side surface, and the control circuit structure has a third side surface, and the first side surface, the second side surface, and the third side surface substantially form a cross-sectional view angle Continuous line. The semiconductor structure according to claim 6, wherein the semiconductor structure further includes a first through hole, and the control circuit structure further includes a second through hole, and the first hybrid bonding structure includes: A first hybrid bonding part having a plurality of first conductive vias and a first bonding pad, wherein the first through-holes are coupled to the plurality of first ends of the first conductive vias , And the first bonding pad is in contact with the plurality of second ends of the first conductive vias; and A second hybrid bonding part having a plurality of second conductive vias and a second bonding pad, wherein the second bonding pad is in contact with the first bonding pad, and the second through-hole is Are coupled to the plurality of first ends of the second conductive vias, and the second bonding pad is in contact with the plurality of second ends of the second conductive vias. The semiconductor structure according to claim 7, wherein the first hybrid bonding portion further includes a third bonding pad, and the second hybrid bonding portion further includes a fourth bonding pad in contact with the third bonding pad Pad, wherein the third bonding pad and the fourth bonding pad are electrically disconnected from the memory structure and the control circuit structure. The semiconductor structure according to claim 7, wherein the second through hole is a half through hole, one end of which is in contact with a post-process metal line A system-in-package structure, which includes: A first semiconductor structure having a first critical dimension; A second semiconductor structure stacked with the first semiconductor structure, which has a second critical dimension and is in contact with the first semiconductor structure via a hybrid bonding interface; and A substrate electrically connected to the first semiconductor structure and the second semiconductor structure via a first conductive bump; Wherein, the first critical dimension is different from the second critical dimension. The system-in-package structure described in claim 10 further includes: A third semiconductor structure, a second conductive bump is electrically connected to the first semiconductor structure and the second semiconductor structure, wherein the third semiconductor structure has a third critical dimension smaller than the first critical dimension; and An intermediate board supports the first semiconductor structure, the second semiconductor structure and the third semiconductor structure, and is connected to the substrate. The system-in-package structure according to claim 10, further comprising a first bonding pad located on the hybrid bonding interface, which contacts a second bonding pad at the hybrid bonding interface, wherein the first bonding pad The pad is electrically connected to a first through silicon through hole of the first semiconductor structure, and the second bonding pad is electrically connected to a second through silicon through hole of the second semiconductor structure. The system-in-package structure according to claim 10, wherein the first critical dimension is smaller than the second critical dimension. A method of manufacturing a plurality of semiconductor structures, the method comprising: Forming a first hybrid bonding layer on a first wafer having a plurality of first memory structures; Forming a second hybrid bonding layer on a second wafer having a plurality of control circuit structures; Bond the first wafer and the second wafer through a first hybrid bonding step to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer ;and At least the first wafer, the second wafer, the first hybrid bonding layer and the second hybrid bonding layer are singulated to obtain a plurality of semiconductor structures. The method according to claim 14, further comprising: Forming a third hybrid bonding layer on a third wafer having a plurality of second memory structures; Forming a fourth hybrid bonding layer on the first bonding wafer; and Bond the third wafer and the first bonded wafer through a second hybrid bonding step to connect the third hybrid bonding layer and the fourth hybrid bonding layer, thereby obtaining a second bonding Wafer. The method according to claim 15, further comprising: Before forming the first hybrid bonding layer on the first wafer, a first through hole is formed adjacent to a front surface of the first wafer, wherein the first hybrid bonding layer is formed on the first wafer The front of Before forming the second hybrid bonding layer on the second wafer, a second through hole is formed adjacent to a front surface of the second wafer, wherein the second hybrid bonding layer is formed on the second wafer The front of After bonding the first wafer and the second wafer and before forming the fourth hybrid bonding layer on the first bonded wafer, thin the first wafer from a back surface of the first wafer Round to expose the first through hole; Before forming the third hybrid bonding layer on the third wafer, forming a third through hole adjacent to a front surface of the third wafer; and The second wafer is thinned from a back surface of the second wafer to expose the second through hole. The method according to claim 15, further comprising: Before forming the first hybrid bonding layer on the first wafer, forming a first through hole adjacent to a front surface of the first wafer; Before forming the third hybrid bonding layer on the third wafer, forming a second through hole adjacent to a front surface of the third wafer; After bonding the first wafer and the second wafer and before bonding the third wafer and the first bonded wafer, thin the first wafer from a back surface of the first wafer to Exposing the first through hole; After bonding the third wafer and the first bonded wafer, thinning the first bonded wafer from a back surface of the second wafer to form a thinned second wafer; and A third through hole is formed in the thinned second wafer. The method according to claim 15, further comprising: Before forming the first hybrid bonding layer on the first wafer, a first through hole is formed adjacent to a front surface of the first wafer, wherein the first hybrid bonding layer is formed on the first wafer The front of Forming a second through hole adjacent to a front surface of the second wafer; Before forming the second hybrid bonding layer on the second wafer, the second wafer is thinned from a back surface of the second wafer to expose the second through hole, wherein the second hybrid bonding layer Is formed on the back side of the second wafer; and Before forming the third hybrid bonding layer on the third wafer, a third through hole is formed adjacent to a front surface of the third wafer. The method according to claim 14, wherein the step of singulating at least the first wafer and the second wafer includes: Perform a laser scribing operation; and Perform a mechanical cutting operation to continue the laser scribing operation. The method according to claim 14, wherein the step of singulating at least the first wafer and the second wafer includes: Perform a plasma etching operation; and Perform a grinding operation.

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