TW202141797A - Semiconductor device, integrated chip and method of manufacturing the same - Google Patents

Abstract

Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

Description

Diffusion barrier layer for source structure and drain structure to enhance transistor performance

Modern integrated chips use a wide range of devices to achieve different functions. Generally speaking, integrated chips include active devices and passive devices. The active device includes a transistor, such as a metal oxide semiconductor field effect transistor (MOSFET). Based on the switching speed of MOSFET devices, MOSFET devices are used in applications such as automotive electrical systems, power supplies, and power management applications. The switching speed is based at least in part on the drain-source on resistance (RDS(on)) of the MOSFET device. RDS(on) stands for "drain-source on-resistance" or the total resistance between the drain and source in the MOSFET when the MOSFET is "on". RDS(on) is related to current loss and is the basis of the maximum current rating of the MOSFET.

The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and not intended to be limiting. For example, in the following description, forming the first feature on or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include the first feature and the second feature. An embodiment in which an additional feature can be formed between the feature and the second feature so that the first feature and the second feature may not directly contact. In addition, the present disclosure may reuse reference numbers and/or letters in various examples. Such repeated use is for the sake of conciseness and clarity, and does not itself represent the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of explanation, this article may use, for example, "beneath", "below", "lower", "above", and "upper (Upper)" and other spatially relative terms are used to describe the relationship between one element or feature shown in the figure and another (other) element or feature. In addition to the orientations depicted in the figures, the terms of spatial relativity are intended to cover different orientations of the device in use or operation. The device can have other orientations (rotated by 90 degrees or in other orientations), and the spatial relativity descriptors used herein can also be interpreted accordingly.

In the past two decades, transistors (such as metal oxide semiconductor field-effect transistors (MOSFETs)) have used source and drain structures. The source and drain structures are usually used in the gate The structure is formed by implanting dopants in the substrate on opposite sides of the structure. In recent years, transistors with an epitaxial source structure and an epitaxial drain structure have begun to be widely used due to their improved performance and size. A transistor includes: a gate structure located on a well region of a substrate; and an epitaxial source/drain layer arranged in/on the substrate on opposite sides of the gate structure. The epitaxial source/drain layers each include a first dopant having a first doping type (for example, N-type). In addition, the well region of the substrate has a second doping type (for example, P type) that is opposite to the first doping type. The gate electrode includes a gate electrode overlying the gate dielectric layer. When the voltage applied to the gate electrode is equal to or greater than the threshold voltage of the transistor, the transistor is turned on. When the transistor is turned on, the voltage applied to the gate electrode causes a channel that can be selectively formed in the well region between the epitaxial source/drain layer. Channels that can be selectively formed include mobile charge carriers that can flow between the epitaxial source/drain layers. In order to increase the switching speed and increase the maximum rated current associated with the transistor, the RDS(on) can be reduced. There are many factors that affect RDS (on), such as the channel area under the gate structure, the diffusion resistance in the epitaxial source/drain layer, the resistance of the epitaxial source/drain layer, and the overlying conductive contact The contact resistance between the device and the epitaxial source/drain layer.

In order to reduce the RDS(on) of the transistor, the doping concentration of the first dopant (for example, phosphorus) in the epitaxial source/drain layer is relatively high (for example, greater than or equal to 10 ²¹ atoms/cm 3 ). This can, for example, reduce the resistance of the epitaxial source/drain layer and reduce the contact resistance between the overlying conductive contact and the epitaxial source/drain layer. However, as the doping concentration of the first dopant increases, the possibility that the first dopant diffuses out of the epitaxial source/drain layer increases. Therefore, the relatively high doping concentration of the first dopant may cause the first dopant to diffuse into the substrate. This will reduce the doping concentration of the first dopant in the epitaxial source/drain layer, thereby increasing the resistance of the epitaxial source/drain layer and subsequently increasing the RDS(on) of the transistor. In addition, the diffusion of the first dopant can shift the threshold voltage of the transistor, which can reduce the uniformity of the threshold voltage across the array of transistors each including the epitaxial source/drain layer, thereby reducing the electrical The effectiveness of the array of crystals.

Therefore, the present disclosure relates to a transistor device including a diffusion barrier layer disposed between the epitaxial source/drain layer and the semiconductor substrate. For example, the transistor device includes a gate structure overlying the well region of the semiconductor substrate. On opposite sides of the gate structure, an epitaxial source/drain layer is arranged in/on the semiconductor substrate. The epitaxial source/drain layers each include a first dopant (for example, phosphorus, arsenic, etc.) having a first doping type (for example, N-type), wherein the doping concentration of the first dopant is relatively high ( For example, greater than or equal to 1*10 ²¹ atoms/cubic centimeter). In addition, the diffusion barrier layer is directly disposed under each epitaxial source/drain layer, so that the diffusion barrier layer separates the epitaxial source/drain layer from the semiconductor substrate. The diffusion barrier layers each include a barrier dopant (for example, carbon) configured to reduce and/or prevent diffusion of the first dopant from the epitaxial source/drain layer to the semiconductor substrate (for example, to the well region). By reducing and/or preventing the diffusion of the first dopant, the relatively high concentration of the epitaxial source/drain layer can be maintained, thereby reducing the resistance of the epitaxial source/drain layer and reducing the resistance of the transistor device RDS (on). In addition, the transistor device may be part of an integrated wafer that includes an array of transistors on/in the semiconductor substrate. By reducing the diffusion of the first dopant, the two ends of the array can be maintained The uniformity of the threshold voltage, thereby enhancing the performance of the integrated chip.

1 shows a cross-sectional view of some embodiments of an integrated wafer 100 including a first transistor 110 having a first pair of epitaxy source/drain layers 116a and 116b and directly located on the first pair of epitaxy The first pair of diffusion barrier layers 114a and 114b under the source/drain layers 116a to 116b.

The integrated wafer 100 includes a semiconductor substrate 102. The semiconductor substrate 102 has a first well region 106 disposed between the sidewalls of the isolation structure 104. In some embodiments, the semiconductor substrate 102 may be or include a semiconductor wafer (for example, a silicon wafer), a silicon-on-insulator (SOI) substrate, an intrinsic single crystal silicon, another Suitable substrate, or similar. The isolation structure 104 extends from the top surface of the semiconductor substrate 102 to a point located below the top surface of the semiconductor substrate 102. The first transistor 110 includes a gate electrode 122, a sidewall spacer structure 120, a gate dielectric layer 124, and a first pair of source/drain structures 112a and 112b overlying the semiconductor substrate 102. The gate electrode 122 covers the first well region 106, and the gate dielectric layer 124 is disposed between the gate electrode 122 and the semiconductor substrate 102. The sidewall spacer structure 120 laterally surrounds the gate electrode 122 and the gate dielectric layer 124. In addition, the first pair of source/drain structures 112 a to 112 b are spaced apart on opposite sides of the gate electrode 122. In some embodiments, the first transistor 110 may be configured as a metal oxide semiconductor field effect transistor (MOSFET), a high voltage transistor, an n-channel metal oxide semiconductor (n-channel metal oxide semiconductor, nMOS) transistor , Planar metal oxide semiconductor (MOS) transistor, fin field-effect transistor (FinFET), gate-all-around FET (GAAFET), or similar.

An inter-level dielectric (ILD) layer 126 covers the semiconductor substrate 102 and the first transistor 110. In addition, a plurality of conductive contacts 128 are provided in the ILD layer 126, and the plurality of conductive contacts 128 cover the gate electrode 122 and the first pair of source/drain structures 112a to 112b. The silicide layer 118 is overlying the first pair of source/drain structures 112a to 112b, so that the silicide layer 118 is vertically disposed on the first pair of source/drain structures 112a to 112b and the overlying conductive contacts Between 128. In addition, the source/drain structures 112a to 112b include a first pair of epitaxial source/drain layers 116a to 116b and diffusion barrier layers 114a to 114b. The diffusion barrier layers 114a to 114b are vertically spaced between the first pair of epitaxial source/drain layers 116a to 116b and the semiconductor substrate 102.

The first pair of source/drain structures 112a to 112b includes a first source/drain structure 112a that can be configured as the source structure of the first transistor 110 and a drain structure that can be configured as the first transistor 110 Of the second source/drain structure 112b, or vice versa. In addition, the first pair of epitaxial source/drain layers 116a to 116b includes a first epitaxial source/drain layer 116a and a second epitaxial source/drain layer 116b. In an embodiment, the first epitaxial source/drain layer 116a may be configured as the source of the first transistor 110, and the second epitaxial source/drain layer 116b may be configured as the first transistor 110 The dip pole, or vice versa. In addition, the diffusion barrier layers 114a to 114b include a first diffusion barrier layer 114a and a second diffusion barrier layer 114b. The first diffusion barrier layer 114a is disposed between the semiconductor substrate 102 and the first epitaxial source/drain layer 116a, and the second diffusion barrier layer 114b is disposed between the semiconductor substrate 102 and the second epitaxial source/drain layer 116b between.

In some embodiments, the diffusion barrier layers 114a to 114b may be epitaxially grown on the semiconductor substrate 102, so that the first diffusion barrier layer 114a and the second diffusion barrier layer 114b may each be referred to as an epitaxial diffusion barrier layer. During the operation of the first transistor 110, by applying appropriate bias conditions to the gate electrode 122 and the first pair of source/drain structures 112a to 112b, the channel region 108 of the first well region 106 can be formed Selective conduction channel. In such an embodiment, charge carriers can flow in the channel region 108 between the first pair of source/drain structures 112a to 112b.

In some embodiments, the first epitaxial source/drain layer 116a and the second epitaxial source/drain layer 116b each include a first dopant having a first doping type (for example, N-type) and It may have a doping concentration in the range ^{between about 10 19} to 4*10 ^{21 atoms/cm3.} In some embodiments, the first well region 106 has a second doping type (for example, P-type) and may have a doping concentration in a range ^{between about 10 15} to 10 ^{17 atoms/cm 3.} In various embodiments, the first doping type is opposite to the second doping type. In still other embodiments, the diffusion barrier layers 114a to 114b each include a first dopant having a first doping type (for example, N-type) and may have a range of about 10 ¹⁹ to 4*10 ²¹ atoms/cm 3 The range between the first dopant concentration of the first dopant. In addition, the diffusion barrier layers 114a to 114b each include a barrier dopant (for example, carbon (C)) and may have a barrier dopant in the range of ^{about 10 19} to 3*10 ^{21 atoms/cm 3} The second doping concentration. In some embodiments, the barrier dopant may be referred to as a diffusion barrier substance. The first dopant may, for example, be or include phosphorus, arsenic, another suitable N-type dopant, or any combination of the foregoing materials. The barrier dopant may, for example, be or contain carbon (C), but other barrier dopants are suitable. Therefore, in some embodiments, the barrier dopant is different from the first dopant.

In order to reduce the resistance (for example, sheet resistance) of the first pair of epitaxial source/drain layers 116a to 116b, the first epitaxial source/drain layer 116a and the second epitaxial source/drain layer 116a The doping concentration of the first dopant in the pole layer 116b is relatively high (for example, greater than about 1*10 ²¹ atoms/cm 3 ). As the doping concentration of the first dopant increases, the first dopant diffuses out of the first pair of epitaxial source/drain layers 116a to 116b and diffuses to the semiconductor substrate 102 (for example, to the first well region 106) The possibility of increased. For example, if the first dopant contains phosphorus and the doping concentration is relatively high (for example, greater than about 1*10 ²¹ atoms/cm 3 ), the first dopant may easily diffuse out of the first pair of epitaxial source electrodes /Drain layers 116a to 116b. In addition, the barrier dopant (for example, carbon) is configured to reduce or prevent the diffusion of the first dopant (for example, phosphorus, arsenic, etc.). For example, the barrier dopant can act as substitute atoms and replace silicon atoms in the entire lattice of the diffusion barrier layers 114a to 114b, thereby reducing the crossing of the diffusion barrier layers 114a to 114b and/or the first pair of epitaxial source/ The diffusion of the first dopant of the lattice of the drain layers 116a to 116b. Therefore, since the diffusion barrier layers 114a to 114b are disposed between the first pair of epitaxial source/drain layers 116a to 116b and the semiconductor substrate 102 and contain barrier dopants, the diffusion barrier layers 114a to 114b reduce the first doping The agent diffuses from the first pair of epitaxial source/drain layers 116a to 116b to the semiconductor substrate 102. This is beneficial to maintain a relatively high doping concentration of the first dopant in the first pair of epitaxial source/drain layers 116a to 116b, thereby maintaining the first pair of epitaxial source/drain layers 116a to 116b. Reduced resistance (for example, reduced sheet resistance). In addition, reducing the diffusion of the first dopant has the effect of reducing the RDS(on) of the first transistor 110. Advantageously, a lower RDS(on) facilitates the flow of current in the first transistor 110, thereby increasing the switching speed and increasing the maximum rated current of the first transistor 110. In addition, reducing the diffusion of the first dopant into the semiconductor substrate 102 can reduce and/or prevent the deviation of the threshold voltage of the first transistor 110, thereby further enhancing the performance of the first transistor 110.

FIG. 2A shows a cross-sectional view of some embodiments of an integrated wafer 200 that includes a first transistor 110 disposed laterally adjacent to a second transistor 208.

The integrated wafer 200 includes a semiconductor substrate 102 having an N-type metal oxide semiconductor (P-type metal oxide semiconductor, PMOS) region 203 laterally adjacent to it. NMOS) area 201. The semiconductor substrate 102 includes a first semiconductor material layer 202, an insulating layer 204, and a second semiconductor material layer 206. In various embodiments, the semiconductor substrate 102 is a semiconductor-on-insulator (SOI) substrate, a partially-depleted semiconductor-on-insulator (PDSOI) substrate, or a fully-depleted insulator. Fully-depleted semiconductor-on-insulator (FDSOI) substrate, or another suitable semiconductor substrate. The first semiconductor material layer 202 can be, for example, or include crystalline silicon, single crystal silicon, doped silicon, intrinsic silicon, some other silicon materials, some other semiconductor materials, or any combination of the foregoing materials. In addition, the first semiconductor material layer 202 may have a face-center-cubic (fcc) structure with a [100] orientation. In an embodiment, the second semiconductor material layer 206 is or includes crystalline silicon, single crystal silicon, doped silicon, intrinsic silicon, some other silicon materials, some other semiconductor materials, or any combination of the foregoing materials. In addition, the insulating layer 204 may be, for example, or include a dielectric material, such as silicon dioxide, or another suitable material.

The first transistor 110 is disposed in the NMOS region 201 and the second transistor 208 is disposed in the PMOS region 203. In some embodiments, the first transistor 110 is configured as an NMOS transistor and the second transistor 208 is configured as a PMOS transistor. The first transistor 110 and the second transistor 208 respectively include a gate electrode 122, a sidewall spacer structure 120, and a gate dielectric layer 124. The gate electrode 122 may be, for example, or include polysilicon, doped polysilicon, a metal material (such as aluminum, copper, titanium, tantalum, tungsten, another suitable material, or any combination of the foregoing materials. The sidewall spacer structure 120 may be, for example, Or include silicon nitride, silicon carbide, another dielectric material, or any combination of the foregoing materials. In addition, the gate dielectric layer 124 may be, for example, or include silicon dioxide, a high-k dielectric material, or the like As used herein, a high-permittivity dielectric material is a dielectric material with a dielectric constant greater than 3.9.

The isolation structure 104 is disposed in the semiconductor substrate 102 and can continuously extend from the top surface of the first semiconductor material layer 202 to the second semiconductor material layer 206 via the insulating layer 204. The isolation structure 104 is configured to divide the device area of the semiconductor substrate 102, such as the NMOS area 201 and the PMOS area 203. In addition, the isolation structure 104 may be configured to provide electrical isolation between devices (for example, the first transistor 110 and the second transistor 208) disposed in/on the semiconductor substrate 102. The isolation structure 104 may be configured as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or the like, and may include, for example, a dielectric material, such as silicon dioxide, nitride Silicon, silicon carbide, another suitable dielectric material, or any combination of the foregoing materials.

The first transistor 110 further includes a first pair of source/drain structures 112a to 112b, the first pair of source/drain structures 112a to 112b overlying the first semiconductor material layer 202 and on the first transistor The gate electrode 122 of 110 is spaced apart on two opposite sides. In some embodiments, the first pair of source/drain structures 112a to 112b includes a first pair of epitaxial source/drain layers 116a to 116b and is spaced between the first semiconductor material layer 202 and the first pair of epitaxial source /Diffusion barrier layers 114a to 114b between drain layers 116a to 116b. The second transistor 208 further includes a second pair of epitaxial source/drain layers 210a to 210b. The second pair of epitaxial source/drain layers 210a to 210b is overlying the first semiconductor material layer 202 and is The gate electrode 122 of the second transistor 208 is spaced apart on opposite sides. In some embodiments, the second pair of epitaxial source/drain layers 210 a to 210 b are used as the second pair of source/drain structures of the second transistor 208. In addition, the gate electrode 122 of the second transistor 208 covers the second well region 212 provided in the first semiconductor material layer 202. The second well region 212 has the first doping type (for example, N-type) and may have ^{a doping concentration in the range of about 10 15} to 10 ¹⁷ atoms/cm 3 or another suitable doping concentration value. The second pair of epitaxial source/drain layers 210a to 210b may, for example, have a second doping type (for example, P-type), and the second doping type has a range of about 10 ¹⁹ to 4*10 ²¹ atoms/cube. The doping concentration in the range between centimeters, or another suitable doping concentration value. In various embodiments, the second doping type is opposite to the first doping type. In addition, the second pair of epitaxial source/drain layers 210a to 210b is grown as an epitaxial layer with a P-type material (for example, epitaxial silicon). In some embodiments, the second pair of epitaxial source/drain layers 210a to 210b includes silicon germanium (SiGe), or another suitable material. In addition, the second pair of epitaxial source/drain layers 210a to 210b includes a third epitaxial source/drain layer 210a and a fourth epitaxy disposed on opposite sides of the gate electrode 122 of the second transistor 208 The crystal source/drain layer 210b. In some embodiments, the first semiconductor material layer 202 has a second doping type (for example, P-type).

In addition, a silicide layer 118 is overlaid on the first pair of epitaxial source/drain layers 116a to 116b and the second pair of epitaxial source/drain layers 210a to 210b. The silicide layer 118 may be, for example, or include nickel silicide, titanium silicide, or another suitable material. The silicide layer 118 is configured to reduce the contact resistance between the first pair of epitaxial source/drain layers 116a to 116b and the second pair of epitaxial source/drain layers 210a to 210b and the overlying conductive contact 128 . The conductive contact 128 is disposed in the ILD layer 126. The conductive contact 128 may be, for example, or include tungsten, aluminum, copper, titanium nitride, tantalum nitride, ruthenium, another conductive material, or any combination of the foregoing materials. In addition, the ILD layer 126 may be, for example, or include silicon dioxide, a low-k dielectric material, or the like. As used herein, a low-k dielectric material is a dielectric material with a dielectric constant less than 3.9.

In some embodiments, the first epitaxial source/drain layer 116a and the second epitaxial source/drain layer 116b may each include, for example, a first dopant having a first doping type (eg, N-type) And may have a doping concentration of the first dopant, the doping concentration of the first dopant is about 3*10 ²¹ atoms/cm3, between about 10 ¹⁹ to 4*10 ²¹ atoms/cu Within centimeters, or another suitable doping concentration value. In still other embodiments, the first dopant may be or include phosphorus, arsenic, another suitable N-type dopant, or any combination of the foregoing materials. It should be understood that the first dopant containing another element is within the scope of the present disclosure. In addition, the first pair of epitaxial source/drain layers 116a to 116b is grown as an epitaxial layer with an N-type material (for example, epitaxial silicon). For example, the first pair of epitaxial source/drain layers 116a to 116b here includes an n-type semiconductor material including silicon and phosphorus, such as SiP. In still other embodiments, the atomic percentage of the first dopant in the first pair of epitaxial source/drain layers 116a to 116b may be about 6%, and may be between about 0.2% and 100%. Within the range of 8, or another suitable percentage value. In some embodiments, the first epitaxial source/drain layer 116a and the second epitaxial source/drain layer 116b may, for example, each consist of the following compound or substantially consist of the following compound: a compound of silicon and phosphorus, For example, SiP; or a compound of silicon and arsenic, such as SiAs. It should be understood that the first epitaxial source/drain layer 116a and the second epitaxial source/drain layer 116b containing other compounds or elements are within the scope of the present disclosure. In still other embodiments, the first pair of epitaxial source/drain layers 116a to 116b has a face-centered cubic (fcc) structure with a [100] orientation.

In some embodiments, if the doping concentration of the first dopant in the first epitaxial source/drain layer 116a and the second epitaxial source/drain layer 116b is substantially small (for example, less than about 10 ¹⁹ atoms/cm3), the sheet resistance of the first epitaxial source/drain layer 116a and the second epitaxial source/drain layer 116b increases. In still other embodiments, if the doping concentration of the first dopant in the first epitaxial source/drain layer 116a and the second epitaxial source/drain layer 116b is substantially large (for example, greater than about 4*10 ²¹ atoms/cm3), the first dopant may damage or distort the crystal lattices of the first epitaxial source/drain layer 116a and the second epitaxial source/drain layer 116b, thereby reducing the The stability of an epitaxial source/drain layer 116a and a second epitaxial source/drain layer 116b.

In still other embodiments, the diffusion barrier layers 114a to 114b each include a first dopant having a first doping type (for example, N-type) and may have a first doping concentration of the first dopant. The first doping concentration of the first dopant is about 1.2*10 ²⁰ atoms/cc, about 1.2*10 ²¹ atoms/cc, in the range of about 10 ¹⁹ to 4*10 ²¹ atoms/cc , Or another suitable doping concentration value. In some embodiments, the first dopant concentration of the first dopant in the diffusion barrier layers 114a to 114b is less than the first dopant concentration of the first dopant in the first pair of epitaxial source/drain layers 116a to 116b concentration. In various embodiments, the first atomic percent of the first dopant in each of the diffusion barrier layers 114a to 114b may be about 2 percent, and may be between about 0.2 to 8 percent. , Or another suitable percentage value. In various embodiments, the first atomic percentage of the first dopant in the diffusion barrier layers 114a to 114b is smaller than the atomic percentage of the first dopant in the first pair of epitaxial source/drain layers 116a to 116b. In addition, the diffusion barrier layers 114a to 114b include a barrier dopant (for example, carbon) and may have a second doping concentration of the barrier dopant, the second doping concentration of the barrier dopant being about 5.2*10 ²⁰ Atoms/cubic centimeter, in the range of about 10 ¹⁹ to 3*10 ²¹ atoms/cubic centimeter, or another suitable doping concentration value. The barrier dopant may, for example, be or contain carbon (C), but other barrier dopants are suitable. Therefore, in some embodiments, the barrier dopant is different from the first dopant. In various embodiments, the second atomic percentage of the barrier dopant in the diffusion barrier layers 114a to 114b may be about one percent, in the range of about 0.2 to 6 percent, or another An appropriate percentage value. Therefore, in some embodiments, the second atomic percentage of the barrier dopant in the diffusion barrier layers 114a to 114b is less than the first atomic percentage of the first dopant in the diffusion barrier layers 114a to 114b. In addition, the diffusion barrier layers 114a to 114b can be grown, for example, as epitaxial layers (for example, epitaxial silicon) with N-type materials and barrier dopants. For example, the diffusion barrier layers 114a to 114b may include n-type semiconductor materials including silicon, phosphorus, and carbon, such as SiCP. In some embodiments, the diffusion barrier layers 114a to 114b may, for example, each consist of or substantially consist of the following compounds: compounds of silicon, carbon, and phosphorus, such as SiCP; compounds of silicon, carbon, and arsenic, such as SiCas; silicon , Carbon and oxygen compounds, such as SiCO; or carbon-doped silicon, such as SiC. It should be understood that the diffusion barrier layers 114a to 114b containing other compounds or elements are within the scope of the present disclosure. In still other embodiments, the diffusion barrier layers 114a to 114b have a face-centered cubic (fcc) structure with a [100] orientation.

In some embodiments, if the first doping concentration of the first dopant in the diffusion barrier layers 114a to 114b is substantially small (for example, less than about 10 ¹⁹ atoms/cm3), the diffusion barrier layers 114a to 114b The sheet resistance increases. In still other embodiments, if the first doping concentration of the first dopant in the diffusion barrier layers 114a to 114b is substantially large (for example, greater than about 4*10 ²¹ atoms/cm3), the first doping The agent may damage or distort the crystal lattice of the diffusion barrier layers 114a to 114b, thereby reducing the stability of the diffusion barrier layers 114a to 114b. In still other embodiments, if the second doping concentration of the barrier dopant in the diffusion barrier layers 114a to 114b is substantially small (for example, less than about 10 ¹⁹ atoms/cc), the diffusion barrier layers 114a to 114b are reduced And/or the ability to prevent the diffusion of the first dopant is significantly reduced. In still other embodiments, if the second doping concentration of the barrier dopant in the diffusion barrier layers 114a to 114b is substantially large (for example, greater than about 3*10 ²¹ atoms/cm3), the barrier dopant may The crystal lattice of the diffusion barrier layers 114a to 114b is damaged or distorted, thereby reducing the stability of the diffusion barrier layers 114a to 114b.

In addition, the diffusion barrier layers 114a to 114b have a first thickness t1, the first pair of epitaxial source/drain layers 116a to 116b have a second thickness t2, and the first pair of source/drain structures 112a to 112b have a total thickness Ts. The total thickness Ts may be the sum of the first thickness t1 and the second thickness t2. The first thickness t1 is, for example, about 3 nanometers (nm), in the range of about 1 nanometer to 5 nanometers, or another suitable value. The second thickness t2 is, for example, about 15 nanometers, in the range of about 5 nanometers to 40 nanometers, or another suitable value. Therefore, in some embodiments, the second thickness t2 of the first pair of epitaxial source/drain layers 116a to 116b is greater than the first thickness t1 of the diffusion barrier layers 114a to 114b. In still other embodiments, the first thickness t1 is about 16.7 percent (for example, 0.167*Ts) of the total thickness Ts, and is between about 1 to 50 percent (for example, 0.01%) of the total thickness Ts. *Ts to 0.50*Ts), or another suitable value. In various embodiments, the second thickness t2 is about 83.3 percent (for example, 0.833*Ts) of the total thickness Ts, and is between about 50% to 99% (for example, 0.5*Ts) of the total thickness Ts. Ts to 0.99*Ts), or another suitable value.

In some embodiments, if the first thickness t1 is substantially small (for example, less than about 1 nanometer), the ability of the diffusion barrier layers 114a to 114b to reduce and/or prevent the diffusion of the first dopant is significantly reduced. In still other embodiments, if the first thickness t1 is substantially large (for example, greater than about 5 nm), the sheet resistance of the diffusion barrier layers 114a to 114b increases. In various embodiments, if the second thickness t2 is substantially small (for example, less than about 5 nm), the stability (for example, structural integrity) of the first pair of epitaxial source/drain layers 116a to 116b is reduced . In still other embodiments, if the second thickness t2 is substantially large (for example, greater than about 40 nm), the sheet resistance of the first pair of epitaxial source/drain layers 116a to 116b may increase.

2B shows a cross-sectional view of some alternative embodiments of the integrated wafer 200 shown in FIG. 2A, in which the bottom surfaces of the diffusion barrier layers 114a to 114b are disposed below the top surface 202t of the first semiconductor material layer 202 and are separated from the top surface 202t. A distance d1. In addition, the second pair of epitaxial source/drain layers 210a to 210b are disposed below the top surface 202t of the first semiconductor material layer 202 at a second distance d2 from the top surface 202t. In some embodiments, the channel region of the first transistor 110 is laterally disposed between the diffusion barrier layers 114a to 114b, and the channel region of the second transistor 208 is laterally disposed on the second pair of epitaxial source/drain electrodes. Between the pole layers 210a to 210b. In addition, the thickness Tfs of the first semiconductor material layer 202 is defined between the top surface 202t of the first semiconductor material layer 202 and the bottom surface 202bs of the first semiconductor material layer 202. The thickness Tfs of the first semiconductor material layer 202 may, for example, be in the range of about 20 nanometers to 30 nanometers. In various embodiments, the first distance d1 and the second distance d2 are in the range of about 5 nanometers to 29.5 nanometers, or another suitable value. In some embodiments, the first distance d1 is different from the second distance d2.

2C shows a cross-sectional view of some alternative embodiments of the integrated wafer 200 shown in FIG. 2A, in which the bottom surface of the diffusion barrier layer 114a to 114b is curved and the pair of epitaxial source/drain layers 116a to 116b The bottom surface is curved. In various embodiments, the bottom surfaces of the pair of epitaxial source/drain layers 116a to 116b are disposed below the top surface 202t of the first semiconductor material layer 202 in the vertical direction.

2D shows a cross-sectional view of some alternative embodiments of the integrated wafer 200 shown in FIG. 2A, in which the diffusion barrier layers 114a to 114b are each U-shaped and disposed in the space defined by the sidewall and upper surface of the first semiconductor material layer 202 Cavity.

2E shows a cross-sectional view of some alternative embodiments of the integrated wafer 200 shown in FIG. 2A, in which the first well region (106 shown in FIG. 2A) and the second well region (212 shown in FIG. 2A) are omitted. In such an embodiment, the thickness Tfs of the first semiconductor material layer 202 may be about 5 nanometers, in the range of about 0.5 nanometers to 15 nanometers, or another suitable thickness value. In addition, the first semiconductor material layer 202 may be, for example, or include intrinsic silicon, intrinsic single crystal silicon, another suitable material, or any combination of the foregoing materials.

3A shows a cross-sectional view of some embodiments of the integrated wafer 300 corresponding to some alternative embodiments of the integrated wafer 200 shown in FIG. 2A, wherein the diffusion barrier layers 114a to 114b are or include doping of the first semiconductor material layer 202 Area. In such an embodiment, the diffusion barrier layers 114a to 114b may be referred to as diffusion barrier regions. The diffusion barrier layers 114a to 114b include barrier dopants (for example, carbon) and may, for example, have a doping concentration of the barrier dopant, the doping concentration of the barrier dopant being about 5.2*10 ²⁰ atoms/cm3, It is in the range of about 10 ¹⁹ to 3*10 ²¹ atoms/cubic centimeter, or another suitable doping concentration value. The barrier dopant may, for example, be or contain carbon (C), but other barrier dopants are suitable. In various embodiments, the atomic percentage of the barrier dopants in the diffusion barrier layers 114a to 114b may be about 1, in the range of about 0.2 to 6 percent, or another suitable The percentage value of. In still other embodiments, the top surfaces of the diffusion barrier layers 114a to 114b are aligned with the top surface 202t of the first semiconductor material layer 202, and the bottom surfaces of the diffusion barrier layers 114a to 114b are disposed on the top of the first semiconductor material layer 202. At a point below the surface 202t. In still other embodiments, the dots are disposed above the bottom surface 202bs of the first semiconductor material layer 202. In addition, in some embodiments, the diffusion barrier layers 114a to 114b do not contain the first dopant (for example, phosphorus and/or arsenic), so that the diffusion barrier layer 114 is composed of or substantially composed of the following materials: The material of the semiconductor material layer 202 (for example, silicon) and the barrier dopant (for example, carbon), for example, SiC. In still other embodiments, the diffusion barrier layers 114a to 114b may use barrier dopants (e.g., carbon) and first dopants (e.g., phosphorus and/or arsenic) as shown and illustrated in FIG. 2A. Doped. In this embodiment, the diffusion barrier layers 114a to 114b each include a first dopant having a first doping type (for example, N-type) and may have a first doping concentration of the first dopant. The first doping concentration of the first dopant is in the range of about 10 ¹⁹ to 4*10 ²¹ atoms/cm 3, or another suitable doping concentration value.

3B shows a cross-sectional view of some alternative embodiments of the integrated wafer 300 shown in FIG. 3A, in which the diffusion barrier layers 114a to 114b (ie, the diffusion barrier regions) continuously extend from the top surface 202t of the first semiconductor material layer 202 to the first semiconductor material layer 202. The bottom surface 202bs of a layer 202 of semiconductor material. In this embodiment, the diffusion barrier layers 114a to 114b contact the top surface of the insulating layer 204.

3C shows a cross-sectional view of some alternative embodiments of the integrated wafer 300 shown in FIG. 3A, in which the first well region (106 shown in FIG. 3A) and the second well region (212 shown in FIG. 3A) are omitted. In such an embodiment, the thickness Tfs of the first semiconductor material layer 202 may be about 5 nanometers, in the range of about 0.5 nanometers to 15 nanometers, or another suitable thickness value. In addition, the regions of the first semiconductor material layer 202 that deviate from the diffusion barrier layers 114a to 114b may be, for example, or include intrinsic silicon, intrinsic single crystal silicon, another suitable material, or any combination of the foregoing materials.

3D shows a cross-sectional view of some embodiments of the integrated wafer 300 corresponding to some alternative embodiments of the integrated wafer 200 shown in FIG. 2A or FIG. 2B, in which the first pair of epitaxial source/drain layers 116a to 116b and The second pair of epitaxial source/drain layers 210a to 210b has a trapezoidal shape.

3E shows a cross-sectional view of some alternative embodiments of the integrated wafer 300 shown in FIG. 3D, in which the diffusion barrier layers 114a to 114b have a trapezoidal shape.

3F shows a cross-sectional view of some alternative embodiments of the integrated wafer 300 shown in FIG. 3D, in which the first well region (106 shown in FIG. 3D) and the second well region (212 shown in FIG. 3D) are omitted. In such an embodiment, the thickness Tfs of the first semiconductor material layer 202 may be about 5 nanometers, in the range of about 0.5 nanometers to 15 nanometers, or another suitable thickness value. In addition, the first semiconductor material layer 202 may be, for example, or include intrinsic silicon, intrinsic single crystal silicon, another suitable material, or any combination of the foregoing materials.

4A shows a schematic diagram 400a of some different alternative embodiments of the integrated wafer 200 shown in FIG. 2A, in which the first transistor 110 and the second transistor 208 are respectively configured as FinFET devices.

In some embodiments, the semiconductor substrate 102 includes a first fin structure 402a and a second fin structure 402b. Each of the first fin structure 402a and the second fin structure 402b extends parallel to each other in the first direction (for example, along the "y" direction). In still other embodiments, the first fin structure 402a and the second fin structure 402b are referred to as fins of the semiconductor substrate 102, respectively. The first fin structure 402a and the second fin structure 402b are laterally spaced apart from each other along the second direction (eg, along the "z" direction). In some embodiments, the first direction is orthogonal to the second direction. Each of the first fin structure 402a and the second fin structure 402b includes at least a part of the upper region of the semiconductor substrate 102, respectively. The upper region of the semiconductor substrate 102 extends in the vertical direction from the lower region of the semiconductor substrate 102 along the third direction (for example, along the “x” direction). The upper region of the semiconductor substrate 102 continuously extends through the isolation structure 104.

The first pair of source/drain structures 112a to 112b are disposed on the first fin structure 402a/on the first fin structure 402a. The source/drain structures 112a to 112b are spaced laterally (in the "y" direction). The gate electrode 122 and the gate dielectric layer 124 extend continuously from the first fin structure 402a to the second fin structure 402b along the second direction (for example, along the "z" direction). During the operation of the first transistor 110, by applying appropriate bias conditions to the gate electrode 122 and the first pair of source/drain structures 112a to 112b, selective conduction can be formed in the first fin structure 402a. aisle. The selective conductive channel extends between the first pair of source/drain structures 112a to 112b (in the "y" direction). In still other embodiments, the diffusion barrier layers 114 a to 114 b are disposed between the corresponding epitaxial source/drain layers 116 a to 116 b and the semiconductor substrate 102. In such an embodiment, each of the diffusion barrier layers 114a to 114b may be provided along the sidewall of the first fin structure 402a and/or the upper surface of a portion of the first fin structure 402a.

The second pair of epitaxial source/drain layers 210a to 210b are disposed on the second fin structure 402b/on the second fin structure 402b. The source/drain layers 210a to 210b are spaced laterally (in the "y" direction). During the operation of the second transistor 208, by applying appropriate bias conditions to the gate electrode 122 and the second pair of epitaxial source/drain layers 210a to 210b, a selective fin structure 402b can be formed. Sexual conduction channel. The selective conductive channel extends between the second pair of epitaxial source/drain layers 210a to 210b (in the "y" direction). In various embodiments, each of the source/drain layers 210a to 210b may be disposed along the sidewall of the second fin structure 402b and/or the upper surface of a portion of the second fin structure 402b. In still other embodiments, the first transistor 110 may be configured as an n-type FinFET device and the second transistor 208 may be configured as a p-type FinFET device.

4B shows a cross-sectional view 400b of some embodiments of the first transistor 110 and the second transistor 208 taken along the line A-A' shown in FIG. 4A. As shown in FIG. 4B, in some embodiments, the gate electrode 122 and the gate dielectric layer 124 continuously extend from the first fin structure 402a to the second fin structure 402b. 4C shows a cross-sectional view 400c of some embodiments of the first transistor 110 taken along the line B-B' shown in FIG. 4. As shown in FIG. 4C, in some embodiments, the gate dielectric layer 124 continuously extends laterally from the first diffusion barrier layer 114a to the second diffusion barrier layer 114b.

4D shows a schematic diagram 400d of some different alternative embodiments of the first transistor 110 and the second transistor 208 shown in FIG. 4A, wherein the first transistor 110 and the second transistor 208 are respectively configured as GAAFET devices. In still other embodiments, the first transistor 110 and the second transistor 208 may each be configured as a nanosheet field effect transistor (NSFET) and/or referred to as an NSFET.

In some embodiments, a plurality of nanostructures 404 are provided on each of the first fin structure 402a and the second fin structure 402b. In still other embodiments, the nanostructures 404 are stacked on top of each other in the vertical direction and may be spaced a non-zero distance from the corresponding underlying fin structures 402a to 402b in the vertical direction. In some embodiments, the plurality of nanostructures 404 includes two to twenty nanostructures, or other suitable number of nanostructures. For example, the plurality of nanostructures 404 overlying the corresponding first fin structure 402a includes three nanostructures. In various embodiments, each of the nanostructures 404 includes the same material as the semiconductor substrate 102. The first pair of source/drain structures 112a to 112b may, for example, be disposed on opposite sides of the corresponding plurality of nanostructures 404, so that the corresponding plurality of nanostructures 404 are arranged on the first pair of source/drain structures 112a to 112a to The space between 112b extends continuously in the lateral direction. The second pair of epitaxial source/drain layers 210a to 210b may be disposed on opposite sides of another corresponding plurality of nanostructures 404, for example, so that the other corresponding plurality of nanostructures 404 are in the second The epitaxial source/drain layers 210a to 210b extend continuously in the lateral direction. In still other embodiments, the first pair of source/drain structures 112a to 112b and the second pair of epitaxial source/drain layers 210a to 210b may each have a hexagonal profile, a diamond profile, a rectangular profile, or another A suitable profile.

4E shows a cross-sectional view 400e of some embodiments of the first transistor 110 and the second transistor 208 taken along the line A-A' shown in FIG. 4D. As shown in FIG. 4E, in some embodiments, the gate dielectric layer 124 continuously surrounds the outer circumference of each of the nanostructures 404. In addition, the gate electrode 122 may be disposed between the respective nanostructures 404 in the vertical direction. 4F shows a cross-sectional view 400f of some embodiments of the first transistor 110 taken along the line B-B' shown in FIG. 4D. As shown in FIG. 4F, in some embodiments, each of the nanostructures 404 continuously extends laterally from the first diffusion barrier layer 114a to the second diffusion barrier layer 114b.

5A to 5C show some different embodiments of the detailed layering of the first pair of source/drain structures 112a to 112b of the first transistor 110 shown in FIGS. 1, 2A to 2E, or 3A to 3F Cutaway view. In this embodiment, the source/drain structures 112a to 112b each include a multilayer stack of epitaxial layers.

5A, the source/drain structures 112a to 112b each include a first epitaxial layer 502 and a second epitaxial layer 504 located on the first epitaxial layer 502, wherein the first dopant is, for example, phosphorus (P ). In some embodiments, the first epitaxial layer 502 (in some embodiments, referred to as a diffusion barrier epitaxial layer) may be composed of or substantially composed of the following materials: silicon, a first dopant (for example, Phosphorus), and barrier dopants (for example, carbon), such as SiCP. In addition, the second epitaxial layer 504 (in some embodiments, referred to as an epitaxial source/drain layer) may be composed of or substantially composed of the following materials: silicon and a first dopant, such as SiP. In various embodiments, the doping concentration and/or atomic percentage of the first dopant and barrier dopant in the first epitaxial layer 502 may be the same as the diffusion barrier layers 114a to 114b of FIG. 2A. In still other embodiments, the doping concentration and/or atomic percentage of the first dopant in the second epitaxial layer 504 may be the same as the first pair of epitaxial source/drain layers 116a to 116b in FIG. 2A. In various embodiments, the doping concentration of the first dopant (for example, phosphorus) in the first epitaxial layer 502 is the same as the doping concentration of the first dopant (for example, phosphorus) in the second epitaxial layer 504 The concentrations can be different from each other. In an alternative embodiment, the doping concentration of the first dopant in the first epitaxial layer 502 is approximately the same as the doping concentration of the first dopant in the second epitaxial layer 504.

In still other embodiments, each of the first pair of source/drain structures 112 a to 112 b includes alternate stacked layers including a first epitaxial layer 502 and a second epitaxial layer 504. For example, as shown in FIG. 5B, alternate stacked layers may include two first epitaxial layers 502 and two second epitaxial layers 504. In another example, as shown in FIG. 5C, the alternating stacked layers may include three first epitaxial layers 502 and three second epitaxial layers 504. It should be understood that the alternate stacked layers may include any number of first epitaxial layers 502 and second epitaxial layers 504, for example. In various embodiments, the doping concentration of the elements in the plurality of first epitaxial layers 502 may be different from each other, and the doping concentration of the first dopant in the plurality of second epitaxial layers 504 may be different from each other. In some embodiments, since the first epitaxial layer 502 contains barrier dopants, each first epitaxial layer 502 can prevent the first dopant from overlying on the corresponding first epitaxial layer 502 and /Or one or more second epitaxial layers 504 located under the corresponding first epitaxial layer 502 are diffused.

6A to 6C show cross-sectional views of some embodiments of the detailed layering of the first pair of source/drain structures 112a to 112b corresponding to some alternative embodiments shown in FIGS. 5A to 5C, wherein the first dopant It is arsenic (As). Therefore, the first epitaxial layer 502 may, for example, be composed of or substantially composed of the following materials: silicon, arsenic, and carbon, such as SiCAs. The second epitaxial layer 504 may, for example, be composed of or substantially composed of the following materials: silicon and arsenic, such as SiAs.

7A to 7C show cross-sectional views of some embodiments of the detailed layering of the first pair of source/drain structures 112a to 112b corresponding to some alternative embodiments shown in FIGS. 5A to 5C, in which the second epitaxial layer The first dopant of 504 is phosphorus, and the first epitaxial layer 502 includes a second dopant, such as arsenic (As). In some embodiments, the first dopant is different from the second dopant, and both the first dopant and the second dopant are N-type dopants. In still other embodiments, the doping concentration and/or atomic percentage of the second dopant in the first epitaxial layer 502 is the same as the first dopant in the diffusion barrier layers 114a to 114b of FIG. 1 or FIG. 2A. The doping concentration and/or atomic percentage of is within the same range and/or the same value as the doping concentration and/or atomic percentage of the first dopant in the diffusion barrier layers 114a to 114b of FIG. 1 or FIG. 2A. Therefore, the first epitaxial layer 502 may, for example, be composed of or substantially composed of the following materials: silicon, arsenic, and carbon, such as SiCAs. The second epitaxial layer 504 may, for example, be composed of or substantially composed of the following materials: silicon and phosphorus, such as SiP.

8A to 8C show cross-sectional views of some embodiments of the detailed layering of the first pair of source/drain structures 112a to 112b corresponding to some alternative embodiments shown in FIGS. 5A to 5C, in which the first epitaxial layer The second dopant of 502 is phosphorus (P), and the first dopant of the second epitaxial layer 502 is arsenic (As). Therefore, the first epitaxial layer 502 may, for example, be composed of or substantially composed of the following materials: silicon, phosphorus, and carbon, such as SiCP. The second epitaxial layer 504 may, for example, be composed of or substantially composed of the following materials: silicon and arsenic, such as SiAs.

9A shows a graph 900a corresponding to some embodiments of the doping profile of a barrier dopant (eg, carbon) that spans the thickness Ts of the first source/drain structure 112a shown in FIGS. 1 to 8C. It should be understood that although the graph 900a shows and illustrates the doping profile spanning the thickness Ts of the first source/drain structure 112a, the doping profile shown may correspond to spanning the second source/drain structure shown in FIGS. 1 to 8C. The doping profile of the barrier dopant of the thickness Ts of the drain structure 112b. In such an embodiment, the second diffusion barrier layer 114b may have the same doping profile as the first diffusion barrier layer 114a described below. In addition, the y-axis of the graph 900a corresponds to the thickness Ts of the first source/drain structure 112a. The x-axis of the graph 900a corresponds to the doping concentration of the barrier dopant (for example, carbon) in the first source/drain structure 112a.

The doping concentration curve 902 corresponds to some embodiments of the doping concentration of the barrier dopant (for example, carbon) in the first source/drain structure 112a. As shown by the curve 902, the doping concentration of the barrier dopant continuously increases from the top surface 114t of the first diffusion barrier layer 114a to the horizontal line 901, and continuously decreases from the horizontal line 901 to the bottom surface 114bs of the first diffusion barrier layer 114a . In such an embodiment, the first diffusion barrier layer 114a may be formed by an epitaxial process, wherein the flow rate of the barrier dopant precursor gas is constant during the epitaxial process (for example, see FIG. 14), or the first diffusion barrier layer 114a The diffusion barrier layer 114a can be formed by a single implantation process (for example, see FIG. 23). Therefore, in some embodiments, the doping profile of the barrier dopant in the first diffusion barrier layer 114a follows a Gaussian distribution. In addition, the horizontal line 901 is, for example, parallel to the bottom surface 114bs of the first diffusion barrier layer 114a. It should be understood that the doping profile of the barrier dopant in the first diffusion barrier layer 114a with another distribution is within the scope of the present disclosure. The peak value of the doping concentration of the barrier dopant is set along the horizontal line 901.

9B shows a graph 900b corresponding to some alternative embodiments of the doping profile of barrier dopants (eg, carbon) across the thickness Ts of the first source/drain structure 112a shown in FIGS. 1 to 8C. It should be understood that although the graph 900b shows and illustrates the doping profile spanning the thickness Ts of the first source/drain structure 112a, the doping profile shown may be different from spanning the second source/drain structure shown in FIGS. 1 to 8. The thickness Ts of the pole structure 112b corresponds to the doping profile of the barrier dopant. In such an embodiment, the second diffusion barrier layer 114b may have the same doping profile as the first diffusion barrier layer 114a described below.

The first doping concentration curve 904 and the second doping concentration curve 906 correspond to some embodiments of the doping concentration of the barrier dopant (for example, carbon) in the first source/drain structure 112a. Referring to the first curve 904, the doping concentration of the barrier dopant may continuously increase from the top surface 114t of the first diffusion barrier layer 114a to the bottom surface 114bs of the first diffusion barrier layer 114a. In such an embodiment, the first diffusion barrier layer 114a may be formed by an epitaxial process, in which the flow rate of the barrier dopant precursor gas is gradually reduced during the epitaxial process (for example, see FIG. 14). Therefore, in some embodiments, the peak of the doping concentration of the barrier dopant is located along the bottom surface 114bs of the first diffusion barrier layer 114a.

Referring to the second curve 906, the doping concentration of the barrier dopant may continuously increase from the bottom surface 114bs of the first diffusion barrier layer 114a to the top surface 114t of the first diffusion barrier layer 114a. In such an embodiment, the first diffusion barrier layer 114a may be formed by a plurality of implantation processes, and each of the implantation processes may be configured to implant a different concentration of carbon in the first diffusion barrier layer 114a (for example, See Figure 23). In some embodiments, the peak of the doping concentration of the barrier dopant is located along the top surface 114t of the first diffusion barrier layer 114a. Therefore, as shown by the first curve 904 and the second curve 906, the doping profile of the barrier dopant in the first diffusion barrier layer 114a follows a gradient distribution. It should be understood that the doping profile of the barrier dopant in the first diffusion barrier layer 114a with another distribution is within the scope of the present disclosure.

Figure 10A shows a cross-sectional view of some embodiments of an integrated wafer 1000 that includes a first transistor device 110a laterally adjacent to a second transistor device 110b.

The integrated chip 1000 includes a plurality of source/drain structures 1002 to 1006. The multiple source/drain structures 1002 to 1006 include a first source/drain structure 1002, a second source/drain structure 1004, and a third source/drain structure 1006. In addition, the first transistor device 110 a and the second transistor device 110 b each include a gate electrode 122, a gate dielectric layer 124 and a sidewall spacer structure 120. The first source/drain structure 1002 and the second source/drain structure 1004 are disposed on opposite sides of the gate electrode 122 of the first transistor device 110a. In addition, the second source/drain structure 1004 and the third source/drain structure 1006 are disposed on opposite sides of the gate electrode 122 of the second transistor device 110b. Therefore, the second source/drain structure 1004 is directly disposed between the first transistor device 110a and the second transistor device 110b, so that the second source/drain structure 1004 is a common source/drain structure. In addition, each of the source/drain structures 1002 to 1006 includes an epitaxial source/drain layer 116 and a diffusion barrier layer 114. It should be understood that the epitaxial source/drain layer 116 may be configured as the epitaxial source/drain layer 116a to 116b shown in FIG. 2A, and the diffusion barrier layer 114 may be configured as the diffusion barrier layer 114a to 114a shown in FIG. 2A. 114b. In still other embodiments, the first transistor device 110a and the second transistor device 110b can each be configured as the first transistor 110 shown in FIG. 2A, so that the first transistor device 110a and the second transistor device 110b are two All are configured as N-type metal oxide semiconductor (NMOS) transistors. In addition, the thickness Tss of the second semiconductor material layer 206 may be greater than the thickness Tfs of the first semiconductor material layer 202. In addition, the thickness Tsw of the sidewall spacer structure 120 may be, for example, about 3 nanometers, 4 nanometers, 5 nanometers, in the range of about 3 nanometers to 6 nanometers, or another suitable value. The thickness Tii of the insulating layer 204 may be, for example, about 18 nanometers, in the range of about 15 nanometers to 20 nanometers, or another suitable value. In some embodiments, the thickness Tfs of the first semiconductor material layer 202 may be about 5 nanometers, in the range of about 5 nanometers to 30 nanometers, or another suitable value.

FIG. 10B shows a cross-sectional view of some embodiments of a section of the integrated wafer shown in FIG. 10A, in which the diffusion barrier layer 114 continuously extends from the sidewall of the sidewall spacer structure 120 to the upper surface of the first semiconductor material layer 202. In some embodiments, the diffusion barrier layer 114 and the first semiconductor material layer 202 each have a face-centered cubic (fcc) structure with a [100] orientation.

FIGS. 11-22 show a cross-sectional view 1100 to a cross-sectional view 2200 of some embodiments of the first method of forming an integrated wafer according to the present disclosure. The integrated wafer includes a first transistor disposed in/on the substrate and The second transistor, wherein the first transistor includes a diffusion barrier layer disposed between the substrate and the epitaxial source/drain layer. Although the cross-sectional view 1100 to the cross-sectional view 2200 shown in FIGS. 11 to 22 are described for the first method, it should be understood that the structure shown in FIGS. 11 to 22 is not limited to the first method, but may be independently independent In the first method. Although FIGS. 11-22 are described as a series of actions, it should be understood that these actions are not limited to the order shown, and the order of actions can be changed in other embodiments, and the disclosed method can also be applied to other structures . In other embodiments, some actions shown and/or explained may be omitted in whole or in part.

As shown in the cross-sectional view 1100 of FIG. 11, a semiconductor substrate 102 is provided, wherein the semiconductor substrate 102 includes an N-type metal oxide semiconductor (NMOS) region 201 that is laterally adjacent to a P-type metal oxide semiconductor (PMOS) region 203. The semiconductor substrate 102 includes a first semiconductor material layer 202, an insulating layer 204, and a second semiconductor material layer 206. In various embodiments, the semiconductor substrate 102 is a semiconductor-on-insulator (SOI) substrate. The first semiconductor material layer 202 may be, for example, or include crystalline silicon, doped silicon, intrinsic silicon, or the like. In addition, the first semiconductor material layer 202 may have a face-centered cubic (fcc) structure with a [100] orientation.

In addition, as shown in FIG. 11, a thinning process is performed on the first semiconductor material layer 202. In some embodiments, the thinning process reduces the initial thickness Tfi of the first semiconductor material layer 202 to a thickness Tfs. The initial thickness Tfi may, for example, be in the range of about 20 nanometers to 30 nanometers, or another suitable value. In addition, the thickness Tfs is, for example, about 5 nanometers, in the range of about 0.5 nanometers to 15 nanometers, or another suitable thickness value. The thinning process may, for example, include performing a planarization process (for example, a chemical mechanical planarization (CMP) process), a mechanical polishing process, an etching process, another suitable thinning process, or any combination of the foregoing processes. In an embodiment, the thinning process may only include an etching process, in which the first semiconductor material layer 202 is exposed to one or more etchant (for example, hydrochloric acid (HCl)), thereby reducing the thickness of the first semiconductor material layer 202 The thickness decreases from the initial thickness Tfi to the thickness Tfs.

As shown in the cross-sectional view 1200 shown in FIG. 12, a plurality of dummy gate structures 1202a to 1202b and a gate dielectric layer 124 are formed on the semiconductor substrate 102, and an isolation structure 104 is formed in the semiconductor substrate 102. In some embodiments, the dummy gate structures 1202a to 1202b may be configured as dummy gate electrode structures or referred to as dummy gate electrode structures. In addition, the plurality of dummy gate structures 1202a to 1202b includes a first dummy gate structure 1202a and a second dummy gate structure 1202b.

In addition, the process of forming the structure shown in FIG. 12 may include, for example, forming an isolation structure 104 in the semiconductor substrate 102 and forming a gate dielectric layer 124 on the semiconductor substrate 102. Subsequently, the plurality of dummy gate structures 1202a to 1202b are formed on the gate dielectric layer 124. The dummy gate structures 1202a to 1202b may include a polysilicon layer 1204, an upper dielectric layer 1208, and a lower dielectric layer 1206 disposed between the polysilicon layer 1204 and the upper dielectric layer 1208. In addition, a first spacer layer 1210 is deposited on the plurality of dummy gate structures 1202a to 1202b, and a second spacer layer 1212 is deposited on the first spacer layer 1210. It can be deposited, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable deposition or growth process. The first spacer layer 1210 and the second spacer layer 1212. In some embodiments, the first spacer layer 1210 and the second spacer layer 1212 may be or include silicon nitride, silicon carbide, another dielectric material, or any combination of the foregoing materials. In addition, a mask layer 1214 is formed on the semiconductor substrate 102 so that the mask layer 1214 covers the layers in the PMOS region 203 and does not cover and/or expose the regions of the NMOS region 201.

As shown in the cross-sectional view 1300 shown in FIG. 13, a patterning process is performed on the first spacer layer 1210 and the second spacer layer 1212 in the NMOS region 201, thereby forming the sidewall spacer structure 120 and the second spacer layer in the NMOS region 201 A source/drain opening 1302. In various embodiments, the sidewall spacer structure 120 includes a first spacer layer 1210 and a second spacer layer 1212 disposed along the sidewall of the first dummy gate structure 1202a. In some embodiments, the patterning process is performed according to the mask layer (1214 shown in FIG. 12), and then the removal process is performed to remove the mask layer from the semiconductor substrate 102 (1214 shown in FIG. 12). The patterning process may, for example, include performing a wet etching process, a dry etching process, or any combination of the foregoing processes.

As shown in the cross-sectional view 1400 shown in FIG. 14, diffusion barriers are formed in the first source/drain opening (1302 shown in FIG. 13) and on opposite sides of the first dummy gate structure 1202a in the NMOS region 201 Layers 114a to 114b. In some embodiments, the diffusion barrier layers 114a to 114b can be formed by a selective epitaxial growth process to selectively deposit the diffusion barrier layers 114a to 114a in the first source/drain openings (1302 shown in FIG. 13). 114b. In addition, the diffusion barrier layers 114a to 114b include, for example, silicon, a first dopant having a first doping type (for example, N-type) (for example, arsenic (As), phosphorus (P), or the like), and barriers Dopants (for example, carbon). The selective epitaxial growth process can be an epitaxial process or another form of deposition process, such as chemical vapor deposition (CVD), metal organic chemical vapor deposition (MO-CVD), plasma enhanced Type chemical vapor deposition (plasma enhanced chemical vapor deposition, PE-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, electron beam/thermal vapor deposition, etc.

In still other embodiments, the diffusion barrier layers 114a to 114b are formed such that the diffusion barrier layers 114a to 114b each have a first doping concentration of a first dopant, and the first doping concentration of the first dopant It is about 1.2*10 ²⁰ atoms/cc, about 1.2*10 ²¹ atoms/cc, in the range of about 10 ¹⁹ to 4*10 ²¹ atoms/cc, or another suitable doping concentration value. In various embodiments, the first atomic percent of the first dopant in each of the diffusion barrier layers 114a to 114b may be about 2 percent, and may be between about 0.2 to 8 percent. , Or another suitable percentage value. In addition, the diffusion barrier layers 114a to 114b are formed such that the diffusion barrier layers 114a to 114b each have a second doping concentration of the barrier dopant, and the second doping concentration of the barrier dopant is about 5.2*10 ²⁰ atoms. /Cubic centimeter, in the range of about 10 ¹⁹ to 3*10 ²¹ atoms/cubic centimeter, or another suitable doping concentration value. In various embodiments, the second atomic percentage of the barrier dopant in the diffusion barrier layers 114a to 114b may be about one percent, in the range of about 0.2 to 6 percent, or another An appropriate percentage value. Therefore, in some embodiments, the second atomic percentage of the barrier dopant in the diffusion barrier layers 114a to 114b is less than the first atomic percentage of the first dopant in the diffusion barrier layers 114a to 114b.

In addition, for example, it is assumed that the diffusion barrier layers 114a to 114b include silicon, carbon, and phosphorus (SiCP). The deposition of SiCP can be performed in a CVD reactor, an LPCVD reactor, or an ultra-high vacuum CVD (UHVCVD). The reactor temperature can be about 590 degrees Celsius or between about 500 degrees Celsius and 650 degrees Celsius. Additionally, the reactor pressure may be about 10 Torr or between about 10 Torr and 300 Torr. The carrier gas in the reactor can be composed of _{hydrogen (H 2} ) or nitrogen (N _{2 ).} Silicon precursor gas (for example, dichlorosilane (DCS or SiH ₂ Cl ₂ ), silane (SiH ₄ ) or disilane (Si ₂ H ₆ )) and chlorine precursor gas (for example, hydrogen chloride (HCl)) can be used to Implement deposition. In addition, the deposition can also use phosphorous source precursor gas (ie, the first dopant precursor gas) (for example, phosphorane (PH ₃ )) and carbon source precursor gas (ie, barrier dopant precursor gas) (For example, monomethylsilane (CH ₆ Si)). In some embodiments, the aforementioned deposition process may be referred to as a selective epitaxial growth process. In an alternative embodiment, an arsenic precursor gas may be used instead of the phosphorus precursor gas, so that the diffusion barrier layers 114a to 114b include SiCAs. Therefore, the diffusion barrier layers 114a to 114b can be grown and the diffusion barrier layers 114a to 114b are doped in situ using the first dopant and the barrier dopant, so that the diffusion barrier layers 114a to 114b are co-doped. ) Is a dopant having a first dopant and a barrier rib. In some embodiments, the flow rate of the barrier dopant precursor gas may be constant during the deposition process, so that the doping profile of the barrier dopant in the diffusion barrier layers 114a to 114b has a Gaussian distribution (for example, as shown in FIG. As shown and/or described in 9A). In an alternative embodiment, the flow rate of the barrier dopant precursor gas may be gradually reduced during the deposition process, so that the doping profile of the barrier dopant in the diffusion barrier layers 114a to 114b has a gradient distribution (for example, as shown in FIG. 9B Shown and/or described in). In still other embodiments, after the diffusion barrier layers 114a to 114b are grown, one or more doping processes may be performed on the diffusion barrier layers 114a to 114b to use the first dopant and/or barrier dopant selective The diffusion barrier layer 114 is ground doped, thereby adjusting the doping concentration of the first dopant and/or the barrier dopant to an appropriate value.

In another embodiment, forming the diffusion barrier layers 114a to 114b may include: depositing an epitaxial silicon layer in the first source/drain opening (1302 shown in FIG. 13); and performing one or more epitaxial silicon layers on the epitaxial silicon layer. A doping process, thereby forming the diffusion barrier layers 114a to 114b. The one or more doping processes may include selectively implanting a first dopant and a barrier dopant (for example, carbon) into the epitaxial silicon layer, so that the diffusion barrier layers 114a to 114b can be co-doped The dopant has a first dopant and a barrier dopant. In addition, the diffusion barrier layers 114a to 114b are formed to a first thickness t1, and the first thickness t1 may, for example, be in the range of about 1 nanometer to 5 nanometers. In addition, by using an epitaxial process to form the diffusion barrier layers 114a to 114b, the diffusion barrier layers 114a to 114b can have the same crystal structure and orientation as the first semiconductor material layer 202 (for example, face-centered cubic with [100] orientation (Fcc) structure). Since the diffusion barrier layers 114a to 114b contain barrier dopants (for example, carbon), the first dopant self-diffusion barrier layer can be relieved during subsequent processing steps and during the operation of the first transistor (110 shown in FIG. 20) 114a to 114b and/or the subsequent formed overlying doped layers (for example, the first pair of epitaxial source/drain layers 116a to 116b shown in FIG. 15).

As shown in the cross-sectional view 1500 of FIG. 15, a first pair of epitaxial source/drain layers 116a to 116b are formed on the diffusion barrier layers 114a to 114b and in the NMOS region 201, thereby forming a first pair of epitaxial source/drain layers 116a to 116b in the first dummy gate structure A first pair of source/drain structures 112a to 112b are formed on opposite sides of 1202a. The first pair of source/drain structures 112a to 112b includes a first pair of epitaxial source/drain layers 116a to 116b and diffusion barrier layers 114a to 114b. In some embodiments, the first pair of epitaxial source/drain layers 116a to 116b may be formed by a selective epitaxial growth process to selectively deposit the first pair of epitaxial sources on the diffusion barrier layers 114a to 114b The electrode/drain layers 116a to 116b. In addition, the first pair of epitaxial source/drain layers 116a to 116b includes, for example, silicon and a first dopant (for example, arsenic (As), phosphorus (P), or the like). The selective epitaxial growth process can be an epitaxial process or another form of deposition process, such as CVD, MO-CVD, PE-CVD, ALD, PVD, sputtering, electron beam/thermal evaporation, etc. In some embodiments, the first dopant in the first pair of epitaxial source/drain layers 116a to 116b may be different from the first dopant in the diffusion barrier layers 114a to 114b. In some embodiments, the first pair of epitaxial source/drain layers 116a to 116b is formed such that the first pair of epitaxial source/drain layers 116a to 116b has the doping concentration of the first dopant, so The doping concentration of the first dopant is about 3*10 ²¹ atoms/cc, in the range of about 10 ¹⁹ to 4*10 ²¹ atoms/cc, or another suitable doping concentration value. In still other embodiments, the atomic percentage of the first dopant in the first pair of epitaxial source/drain layers 116a to 116b may be about 6%, and may be between about 0.2% and 100%. Within the range of 8, or another suitable percentage value.

In addition, for example, suppose that the first pair of epitaxial source/drain layers 116a to 116b includes silicon and phosphorus (SiP). The deposition of SiP can be performed in a CVD reactor, an LPCVD reactor, or an ultra-high vacuum CVD (UHVCVD). The reactor temperature can be about 680 degrees Celsius or between about 550 degrees Celsius and 750 degrees Celsius. Additionally, the reactor pressure may be about 300 Torr or between about 50 Torr and 500 Torr. The carrier gas in the reactor can be composed of _{hydrogen (H 2} ) or nitrogen (N _{2 ).} Silicon precursor gas (for example, dichlorosilane (DCS or SiH ₂ Cl ₂ ), silane (SiH ₄ ) or disilane (Si ₂ H ₆ )) and chlorine precursor gas (for example, hydrogen chloride (HCl)) can be used to Implement deposition. In some embodiments, the aforementioned deposition process may be referred to as a selective epitaxial growth process. The deposition process may, for example, also use a phosphorous source precursor gas (ie, the first dopant precursor gas), such as phosphorane (PH ₃ ). In an alternative embodiment, for example, an arsenic precursor gas may be used instead of the phosphorus precursor gas, so that the first pair of epitaxial source/drain layers 116a to 116b include SiAs. Therefore, the first pair of epitaxial source/drain layers 116a to 116b can be grown and the first pair of epitaxial source/drain layers 116a to 116b can be doped in-situ using the first dopant. In still other embodiments, after growing the first pair of epitaxial source/drain layers 116a to 116b, one or more doping processes may be performed on the first pair of epitaxial source/drain layers 116a to 116b, The first pair of epitaxial source/drain layers 116a to 116b is selectively doped with the first dopant, thereby adjusting the doping concentration of the first dopant to an appropriate value.

In another embodiment, forming the first pair of epitaxial source/drain layers 116a to 116b may include: depositing an epitaxial silicon layer in/on the diffusion barrier layers 114a to 114b; and The epitaxial silicon layer performs one or more doping processes, thereby forming a first pair of epitaxial source/drain layers 116a to 116b. The one or more doping processes may include selectively implanting a first dopant into the epitaxial silicon layer, so that the first pair of epitaxial source/drain layers 116a to 116b is doped with the first dopant. Miscellaneous agents. In addition, the first pair of epitaxial source/drain layers 116a to 116b is formed to a second thickness t2, which may be in the range of about 5 nm to 40 nm, or another suitable thickness. Value. In addition, by using an epitaxial process to form the first pair of epitaxial source/drain layers 116a to 116b, the first pair of epitaxial source/drain layers 116a to 116b may have the same structure as the first semiconductor material layer 202 and/or The diffusion barrier layers 114a to 114b have the same crystal structure and orientation (for example, a face-centered cubic (fcc) structure with [100] orientation).

As shown in the cross-sectional view 1600 of FIG. 16, a mask layer 1602 is selectively formed on the structure shown in FIG. 15. The mask layer 1602 exposes/unmasks the area of the PMOS region 203.

As shown in the cross-sectional view 1700 of FIG. 17, a patterning process is performed on the first semiconductor material layer 202 according to the mask layer 1602, thereby forming a pattern in the first semiconductor material layer 202 and on opposite sides of the second dummy gate structure 1202b. A second source/drain layer opening 1702 is formed. The patterning process further forms the sidewall spacer structure 120 disposed along the two opposite sidewalls of the second dummy gate structure 1202b. In some embodiments, the patterning process may include performing a dry etching process, a wet etching process, or another suitable etching process on the unmasked area of the structure shown in FIG. 16.

As shown in the cross-sectional view 1800 shown in FIG. 18, a second pair of epitaxial source/drain layers 210a to 210b is formed in the second source/drain layer opening (1702 as shown in FIG. 17) and the second pair of epitaxial The source/drain layers 210a to 210b are disposed on opposite sides of the second dummy gate structure 1202b. In some embodiments, the second pair of epitaxial source/drain layers 210a to 210b may be selectively formed by a selective epitaxial growth process to selectively deposit the second pair on the first semiconductor material layer 202 The epitaxial source/drain layers 210a to 210b. In addition, the second pair of epitaxial source/drain layers 210a to 210b each include, for example, silicon germanium (SiGe) and each has a second doping type (e.g., P type) opposite to the first doping type (e.g., N type) type). The selective epitaxial growth process can be an epitaxial process or another form of deposition process, such as CVD, MO-CVD, PE-CVD, ALD, PVD, sputtering, electron beam/thermal evaporation, etc. In still other embodiments, the second pair of epitaxial source/drain layers 210a to 210b does not contain the first dopant and/or barrier dopant, so that the epitaxial source/drain layers 210a to 210b The doping concentration of the first dopant and/or barrier dopant in each is smaller than the corresponding doping concentration in the epitaxial source/drain layers 116a to 116b and the diffusion barrier layer 114, respectively. In addition, after forming the second pair of epitaxial source/drain layers 210a to 210b, one or more removal processes are performed to remove the mask layer 1602 and/or along the first semiconductor material layer 202 (not shown) Out) are provided on the top surface of the first spacer layer 1210 and the second spacer layer 1212.

As shown in the cross-sectional view 1900 of FIG. 19, a silicide layer 118 is formed on the first pair of epitaxial source/drain layers 116a to 116b and the second pair of epitaxial source/drain layers 210a to 210b. In some embodiments, the silicide layer 118 may be, for example, or include nickel silicide, titanium silicide, another suitable material, or any combination of the foregoing materials.

As shown in the cross-sectional view 2000 of FIG. 20, a lower interlayer dielectric (ILD) layer 2002 is deposited on the semiconductor substrate 102. In some embodiments, the lower ILD layer 2002 may be deposited by CVD, PVD, ALD, or another suitable growth or deposition process. The lower ILD layer 2002 may be, for example, or include silicon dioxide, a low-k dielectric material, or the like. In addition, a selective removal process is performed to remove the first dummy gate structure (1202a shown in FIG. 19) from the NMOS region 201, and then a gate electrode 122 is formed on the gate dielectric layer 124 in the NMOS region 201 , Thereby forming the first transistor 110. The selective removal process may include, for example: forming a mask layer (not shown) on the PMOS region 203 and/or on the region of the NMOS region 201; performing a patterning process on the NMOS region 201 according to the mask layer, by This removes the first dummy gate structure (1202a shown in FIG. 19) and forms a first gate electrode opening (not shown) on the gate dielectric layer 124 in the NMOS region 201. In addition, the gate electrode 122 forming the first transistor 110 is included on the gate dielectric layer 124 in the NMOS region 201 (for example, by CVD, PVD, sputtering, electroplating, electroless plating, or another suitable Deposition or growth process) to deposit gate electrode material.

As shown in the cross-sectional view 2100 of FIG. 21, a gate electrode 122 is formed on the gate dielectric layer 124 in the PMOS region 203, thereby forming the second transistor 208. Forming the gate electrode 122 of the second transistor 208 may, for example, include: forming a mask layer (not shown) on the NMOS region 201 and/or on the area of the PMOS region 203; Perform a patterning process to remove the second dummy gate structure (1202b shown in FIG. 20); and deposit gate electrode material on the gate dielectric layer 124 in the PMOS region 203 (for example, by CVD, PVD, sputtering, electroplating, electroless plating, or another suitable deposition or growth process), thereby forming the gate electrode 122 of the second transistor 208.

As shown in the cross-sectional view 2200 of FIG. 22, an upper ILD layer 2202 is formed on the lower ILD layer 2002, and a plurality of conductive contacts 128 are formed in the lower ILD layer 2002 and the upper ILD layer 2202. In some embodiments, the upper ILD layer 2202 may be deposited by CVD, PVD, ALD, or another suitable growth or formation process. In addition, the plurality of conductive contacts 128 may be formed, for example, by a single damascene process or another suitable forming process.

Figures 23 to 25 show cross-sectional views 2300 to 2500 of some embodiments of the second method of forming an integrated wafer according to the present disclosure. The integrated wafer includes a first transistor disposed in/on the substrate and The second transistor, wherein the first transistor includes a diffusion barrier layer disposed between the substrate and the epitaxial source/drain layer. In some embodiments, FIGS. 23-25 show some embodiments of actions that can be performed in place of the actions at FIGS. 14-18 of the first method. Therefore, the second method shows some alternative embodiments of the first method shown in FIGS. 11-22. For example, the second method may proceed from FIG. 11 to FIG. 13 to FIG. 23 to FIG. 25, and then proceed from FIG. 25 to FIG. 19 to FIG. 22 (ie, skip FIG. 14 to FIG. 18). In such an embodiment, the second method shows some alternative embodiments of forming the first pair of source/drain structures 112a to 112b.

As shown in the cross-sectional view 2300 of FIG. 23, a doping process is performed on the first semiconductor material layer 202, thereby forming diffusion barrier layers 114a to 114b in the first semiconductor material layer 202. In such an embodiment, the diffusion barrier layers 114a to 114b may be referred to as diffusion barrier regions. The doping process may include, for example, exposing unmasked regions of the first semiconductor material layer 202 (for example, during the doping process, using the first spacer layer 1210 and the second spacer layer 1212 as mask layers) to One or more dopants. In some embodiments, the one or more dopants may include barrier dopants (for example, carbon) and/or first dopants (for example, phosphorus, arsenic, or the like). In such an embodiment, the diffusion barrier layers 114a to 114b may be configured as shown and/or described in FIG. 3A. In still other embodiments, the diffusion barrier layers 114a to 114b do not contain the first dopant (for example, phosphorus and/or arsenic), so that the diffusion barrier layer 114 is composed of or substantially composed of the following materials: silicon and barriers Dopants (for example, carbon), such as SiC. In addition, the one or more dopants may be disposed at an angle with respect to the top surface of the first semiconductor material layer 202, wherein the angle is equal to or greater than 90 degrees.

In some embodiments, the diffusion barrier layers 114a to 114b are formed such that the diffusion barrier layers 114a to 114b each have a first dopant concentration of a first dopant, and the first dopant concentration of the first dopant is About 1.2*10 ²⁰ atoms/cc, about 1.2*10 ²¹ atoms/cc, in the range of about 10 ¹⁹ to 4*10 ²¹ atoms/cc, or another suitable doping concentration value. In various embodiments, the first atomic percent of the first dopant in each of the diffusion barrier layers 114a to 114b may be about 2 percent, and may be between about 0.2 to 8 percent. , Or another suitable percentage value. In addition, the diffusion barrier layers 114a to 114b are formed such that the diffusion barrier layers 114a to 114b each have a second doping concentration of the barrier dopant, and the second doping concentration of the barrier dopant is, for example, 5.2*10 ²⁰ atoms. /Cubic centimeter, in the range of about 10 ¹⁹ to 3*10 ²¹ atoms/cubic centimeter, or another suitable doping concentration value. In various embodiments, the second atomic percentage of the barrier dopant in the diffusion barrier layers 114a to 114b may be, for example, about 1%, in the range of about 0.2% to 6%, or Another suitable percentage value.

In some embodiments, the doping process includes performing a single implantation process, wherein the concentration of the one or more dopants implanted into the first semiconductor material layer 202 is constant during the single implantation process. In such an embodiment, the doping profile of carbon in the diffusion barrier layers 114a to 114b has a Gaussian distribution (for example, as shown and/or described in FIG. 9A). In an alternative embodiment, the doping process includes performing multiple implantation processes, where each implantation process can be configured to implant different concentrations of carbon in the diffusion barrier layers 114a to 114b. In such an embodiment, the doping profile of carbon in the diffusion barrier layers 114a to 114b has a gradient distribution (for example, as shown and/or described in FIG. 9B).

As shown in the cross-sectional view 2400 shown in FIG. 24, a first pair of epitaxial source/drain layers 116a to 116b are formed on the diffusion barrier layers 114a to 114b, thereby forming a first pair of source/drain structures 112a to 112a to 114b. 112b. In some embodiments, the first pair of epitaxial source/drain layers 116a to 116b are formed as shown and/or described in FIG. 15. In addition, as shown in FIG. 24, a mask layer 1602 is formed on the NMOS region 201, and a patterning process is performed on the first spacer layer 1210 and the second spacer layer 1212 according to the mask layer 1602, whereby the PMOS A second source/drain layer opening 1702 is formed in the region 203. In some embodiments, the patterning process does not overetch into the first semiconductor material layer 202.

As shown in the cross-sectional view 2500 of FIG. 25, a second pair of epitaxial source/drain layers 210a to 210b are formed on the first semiconductor material layer 202. In this embodiment, the bottom surfaces of the second pair of epitaxial source/drain layers 210 a to 210 b are arranged along the top surface of the first semiconductor material layer 202. In some embodiments, the second pair of epitaxial source/drain layers 210a to 210b are formed as shown and/or described in FIG. 18. In addition, after forming the second pair of epitaxial source/drain layers 210a to 210b, one or more removal processes are performed to remove the mask layer 1602 and/or along the first semiconductor material layer 202 (not shown) ) Are provided on the top surface of the first spacer layer 1210 and the second spacer layer 1212.

FIG. 26 shows a method 2600 of forming an integrated wafer according to some embodiments. The integrated wafer includes a first transistor and a second transistor disposed in/on the substrate, wherein the first transistor includes The diffusion barrier layer between the substrate and the epitaxial source/drain layer. Although the method 2600 is shown and/or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in a different order than shown and/or the actions may be performed simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, and the multiple actions or events can be performed separately or simultaneously with other actions or sub-actions. In some embodiments, some of the illustrated actions or events may be omitted, and other actions or events that are not illustrated may be included.

At act 2602, a plurality of dummy gate structures are formed on the semiconductor substrate. A first dummy gate structure is formed in the NMOS region of the semiconductor substrate, and a second dummy gate structure is formed in the PMOS region of the semiconductor substrate. FIG. 12 shows a cross-sectional view 1200 corresponding to some embodiments of act 2602.

At act 2604, a diffusion barrier layer is formed on opposite sides of the first dummy gate structure, wherein the diffusion barrier layer includes a barrier dopant. 13 and 14 show a cross-sectional view 1300 and a cross-sectional view 1400 corresponding to some embodiments of the act 2604. In addition, FIG. 23 shows a cross-sectional view 2300 corresponding to some alternative embodiments of act 2604.

At act 2606, a first pair of epitaxial source/drain layers is formed on the diffusion barrier layer, so that the first pair of epitaxial source/drain layers includes a first dopant that is different from the barrier dopant. FIG. 15 shows a cross-sectional view 1500 corresponding to some embodiments of act 2606. FIG. 24 shows a cross-sectional view 2400 corresponding to some alternative embodiments of act 2606.

At act 2608, a second pair of epitaxial source/drain layers are formed on opposite sides of the second dummy gate structure. 17 and 18 show a cross-sectional view 1700 and a cross-sectional view 1800 corresponding to some embodiments of the act 2608. 24 and 25 show a cross-sectional view 2400 and a cross-sectional view 2500 corresponding to some alternative embodiments of the action 2608.

At act 2610, a removal process is performed to remove the plurality of dummy gate structures. 20 and 21 show a cross-sectional view 2000 and a cross-sectional view 2100 corresponding to some embodiments of act 2610.

At act 2612, gate electrodes are formed in the NMOS region and the PMOS region of the semiconductor substrate. 20 and 21 show a cross-sectional view 2000 and a cross-sectional view 2100 corresponding to some embodiments of act 2612.

At act 2614, a plurality of conductive contacts are formed on the gate electrode and the first pair of epitaxial source/drain layers and the second pair of epitaxial source/drain layers. FIG. 22 shows a cross-sectional view 2200 corresponding to some embodiments of act 2612.

Therefore, in some embodiments, this application relates to a semiconductor structure including a diffusion barrier layer disposed between the semiconductor substrate and the epitaxial source/drain layer.

In some embodiments, the present application provides a semiconductor device, the semiconductor device includes: a gate electrode overlying a semiconductor substrate; an epitaxial source/drain layer disposed on the semiconductor substrate and on the side Upwardly adjacent to the gate electrode, wherein the epitaxial source/drain layer includes a first dopant; and a diffusion barrier layer located between the epitaxial source/drain layer and the semiconductor substrate, Wherein the diffusion barrier layer includes a barrier dopant different from the first dopant. In an embodiment, the diffusion barrier layer is co-doped to have the barrier dopant and the first dopant. In an embodiment, the doping concentration of the first dopant in the epitaxial source/drain layer is greater than the doping concentration of the first dopant in the diffusion barrier layer, wherein The doping concentration of the barrier dopant in the diffusion barrier layer is less than the doping concentration of the first dopant in the diffusion barrier layer. In an embodiment, the barrier dopant is configured to prevent the first dopant from diffusing from the epitaxial source/drain layer to the semiconductor substrate directly below the gate electrode Area. In an embodiment, the diffusion barrier layer includes epitaxial silicon, and the thickness of the epitaxial source/drain layer is greater than the thickness of the diffusion barrier layer. In an embodiment, the bottom surface of the diffusion barrier layer is disposed below the top surface of the semiconductor substrate, and the bottom surface of the epitaxial source/drain layer is located on all sides of the semiconductor substrate in the vertical direction. Above the top surface. In an embodiment, the diffusion barrier layer is substantially composed of silicon, carbon, and phosphorus (SiCP), and the epitaxial source/drain layer is substantially composed of silicon and phosphorus (SiP). In an embodiment, the diffusion barrier layer is substantially composed of silicon, carbon, and arsenic (SiCAs), and the epitaxial source/drain layer is substantially composed of silicon and arsenic (SiAs). In an embodiment, the diffusion barrier layer is a doped region of the semiconductor substrate extending from the top surface of the semiconductor substrate to a point located below the top surface of the semiconductor substrate, wherein the epitaxial source The pole/drain layer is arranged along the top surface of the diffusion barrier layer.

In some embodiments, the present application provides an integrated wafer, the integrated wafer includes: a semiconductor-on-insulator (SOI) substrate, including a first semiconductor layer, a second semiconductor layer and disposed on the first semiconductor layer and The insulating layer between the second semiconductor layers; N-type metal oxide semiconductor (NMOS) transistors are arranged on the first semiconductor layer, wherein the NMOS transistors include gate electrodes and are arranged on the The gate dielectric layer between the gate electrode and the first semiconductor layer, and a pair of source/drain structures arranged on opposite sides of the gate electrode, wherein the pair of source/ The drain structure includes: a first pair of epitaxial source/drain layers located on the first semiconductor layer, wherein the first pair of epitaxial source/drain layers includes a first N-type dopant; And a diffusion barrier layer disposed between the first semiconductor layer and the first pair of epitaxial source/drain layers, wherein the diffusion barrier layer includes a barrier different from the first N-type dopant Dopant. In an embodiment, the diffusion barrier layer includes the first N-type dopant at a first atomic percentage and the barrier dopant at a second atomic percentage, wherein the first atomic percentage is greater than the second atomic percentage. Atomic percentage. In an embodiment, the diffusion barrier layer is an epitaxial layer co-doped with a second N-type dopant and the barrier dopant, wherein the first N-type dopant is different from the second N-type dopant. Two N-type dopants. In an embodiment, the first N-type dopant includes phosphorus and the second N-type dopant includes arsenic. In an embodiment, the integrated wafer further includes: a P-type metal oxide semiconductor (PMOS) transistor disposed on the first semiconductor layer and laterally adjacent to the N-type metal oxide semiconductor transistor , Wherein the P-type metal oxide semiconductor transistor includes a second gate electrode, a second gate dielectric layer located under the second gate electrode, and two opposite sides disposed on the second gate electrode A second pair of epitaxial source/drain layers on the side, wherein the bottom surface of the second pair of epitaxial source/drain layers is aligned with the bottom surface of the diffusion barrier layer. In an embodiment, the first pair of epitaxial source/drain layers and the diffusion barrier layer have a trapezoidal shape. In an embodiment, the diffusion barrier layer is a doped region of the first semiconductor layer, so that the diffusion barrier layer continuously extends from the top surface of the first semiconductor layer to the top surface of the insulating layer.

In some embodiments, the present application provides a method of manufacturing an integrated wafer, the method comprising: forming a gate electrode structure on a semiconductor substrate; on the semiconductor substrate and laterally adjacent to the gate electrode The electrode structure forms a diffusion barrier layer, wherein the diffusion barrier layer includes a barrier dopant; and an epitaxial source/drain layer is formed on the diffusion barrier layer, so that the epitaxial source/drain layer includes A first dopant different from the barrier dopant, wherein the diffusion barrier layer is located between the epitaxial source/drain layer and the semiconductor substrate. In an embodiment, forming the diffusion barrier layer includes: forming a mask layer on the semiconductor substrate, wherein the mask layer includes a plurality of sidewalls, and the plurality of sidewalls define a source on the semiconductor substrate. Electrode/drain region opening; and performing a selective epitaxial growth process to selectively form the diffusion barrier layer in the source/drain region opening, wherein the selective epitaxial growth process includes using all The first dopant and the barrier dopant perform in-situ doping on the diffusion barrier layer. In an embodiment, the diffusion barrier layer is formed such that the doping profile of the barrier dopant in the diffusion barrier layer has a Gaussian distribution. In an embodiment, forming the epitaxial source/drain layer includes: performing a selective epitaxial growth process to selectively form the epitaxial source/drain along the top surface of the diffusion barrier layer Layer, wherein the bottom surface of the epitaxial source/drain layer is vertically above the top surface of the semiconductor substrate.

The features of several embodiments are summarized above, so that those familiar with the art can better understand various aspects of the present disclosure. Those familiar with the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purpose as the embodiments described in this article and/or achieve the same purposes as the embodiments described in this article. The same advantages. Those familiar with this technology should also realize that these equivalent structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions and alterations in this article without departing from the spirit and scope of this disclosure. .

100, 200, 300, 1000: integrated wafer 102: Semiconductor substrate 104: Isolation structure 106: first well region 108: Passage area 110, 110a: first transistor 110b: second transistor device 112a, 112b: source/drain structure 114, 114a, 114b: diffusion barrier layer 114bs, 202bs: bottom surface 114t, 202t: top surface 116, 116a, 116b, 210a, 210b: epitaxial source/drain layer 118: Silicide layer 120: Sidewall spacer structure 122: gate electrode 124: gate dielectric layer 126: Interlayer Dielectric (ILD) layer 128: Conductive contacts 201: N-type metal oxide semiconductor (NMOS) region 202: The first semiconductor material layer 203: P-type metal oxide semiconductor (PMOS) region 204: Insulation layer 206: second semiconductor material layer 208: Second Transistor 212: second well region 400a, 400d: schematic diagram 400b, 400c, 400e, 400f: cross-sectional view 402a: First fin structure/fin structure 402b: second fin structure/fin structure 404: Nanostructure 502: first epitaxial layer 504: second epitaxial layer 900a, 900b: charts 901: Horizontal Line 902: curve 904: first curve 906: second curve 1002, 1004, 1006: source/drain structure 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500: sectional view 1202a, 1202b: dummy gate structure 1204: Polysilicon layer 1206: Lower dielectric layer 1208: Upper dielectric layer 1210: first spacer layer 1212: second spacer layer 1214, 1602: mask layer 1302: first source/drain opening 1702: second source/drain layer opening 2002: Lower Interlayer Dielectric (ILD) layer 2202: Upper ILD layer 2600: method 2602, 2604, 2606, 2608, 2610, 2612, 2614: Action A-A’, B-B’: Line d1: first distance d2: second distance t1: first thickness t2: second thickness Tfi: initial thickness Tfs, Tii, Tss, Tsw: thickness Ts: total thickness/thickness x, y, z: direction

Reading the following detailed description in conjunction with the accompanying drawings will best understand each aspect of the present disclosure. It should be noted that in accordance with standard practices in this industry, various features are not drawn to scale. In fact, in order to make the discussion clear, the size of various features can be increased or decreased arbitrarily.

Figure 1 shows a cross-sectional view of some embodiments of an integrated wafer including a diffusion barrier layer spaced between an epitaxial source/drain layer and a substrate.

Figures 2A to 2E show cross-sectional views of some different embodiments of an integrated wafer including a first transistor and a second transistor disposed in/on the substrate, wherein the first transistor includes A diffusion barrier layer between the substrate and the epitaxial source/drain layer of the first transistor.

3A to 3C show cross-sectional views of some different embodiments of an integrated wafer including a diffusion barrier layer disposed in a substrate and an epitaxial source/drain region overlying the diffusion barrier layer.

3D to 3F show cross-sectional views of some different alternative embodiments of the integrated wafer shown in FIG. 2A.

4A to 4F show various views of some different alternative embodiments of the integrated wafer shown in FIG. 2A.

5A to 5C through 8A to 8C show cross-sectional views of some embodiments of the detailed layering of the epitaxial source/drain layer and the underlying diffusion barrier layer.

9A and 9B show various graphs corresponding to some different embodiments of the concentration of barrier dopants in each diffusion barrier layer shown in FIGS. 1 to 8B.

10A shows a cross-sectional view of some embodiments of integrated wafers that include first N-type metal oxide semiconductor (N-type metal oxide semiconductor, NMOS) transistors that are adjacent to and spaced apart from each other in the lateral direction The second NMOS transistor.

Figure 10B shows a cross-sectional view of some embodiments of a section of the integrated wafer shown in Figure 10A.

Figures 11-22 show cross-sectional views of some embodiments of a first method of forming an integrated wafer, the integrated wafer including a first transistor and a second transistor disposed in/on the substrate, wherein the first The transistor includes a diffusion barrier layer disposed between the substrate and the epitaxial source/drain layer.

Figures 23 to 25 show cross-sectional views of some embodiments of a second method of forming an integrated wafer, the integrated wafer including a first transistor and a second transistor disposed in/on the substrate, wherein the first The transistor includes a diffusion barrier layer disposed between the substrate and the epitaxial source/drain layer.

FIG. 26 shows a flowchart illustrating some embodiments of a method of forming an integrated wafer, the integrated wafer including a first transistor and a second transistor disposed in/on the substrate, wherein the first transistor includes A diffusion barrier layer arranged between the substrate and the epitaxial source/drain layer.

100: Integrated chip

102: Semiconductor substrate

104: Isolation structure

106: first well region

108: Passage area

110: The first transistor

112a, 112b: source/drain structure

114a, 114b: diffusion barrier layer

116a, 116b: epitaxy source/drain layer

118: Silicide layer

120: Sidewall spacer structure

122: gate electrode

124: gate dielectric layer

126: Interlayer Dielectric (ILD) layer

128: Conductive contacts

Claims (20)

A semiconductor device including: The gate electrode is overlaid on the semiconductor substrate; An epitaxial source/drain layer disposed on the semiconductor substrate and laterally adjacent to the gate electrode, wherein the epitaxial source/drain layer includes a first dopant; and A diffusion barrier layer is located between the epitaxial source/drain layer and the semiconductor substrate, wherein the diffusion barrier layer includes a barrier dopant different from the first dopant. The semiconductor device according to claim 1, wherein the diffusion barrier layer is co-doped with the barrier dopant and the first dopant. The semiconductor device according to claim 2, wherein the doping concentration of the first dopant in the epitaxial source/drain layer is greater than that of the first dopant in the diffusion barrier layer Doping concentration, wherein the doping concentration of the barrier dopant in the diffusion barrier layer is less than the doping concentration of the first dopant in the diffusion barrier layer. The semiconductor device according to claim 1, wherein the barrier dopant is configured to prevent the first dopant from diffusing from the epitaxial source/drain layer to the semiconductor substrate located at the gate The area directly below the electrode. The semiconductor device according to claim 1, wherein the diffusion barrier layer includes epitaxial silicon, and the thickness of the epitaxial source/drain layer is greater than the thickness of the diffusion barrier layer. The semiconductor device according to claim 1, wherein the bottom surface of the diffusion barrier layer is disposed below the top surface of the semiconductor substrate, and wherein the bottom surface of the epitaxial source/drain layer is located in a vertical direction Above the top surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein the diffusion barrier layer is substantially composed of silicon, carbon, and phosphorus (SiCP), and the epitaxial source/drain layer is substantially composed of silicon and phosphorus (SiP) . The semiconductor device according to claim 1, wherein the diffusion barrier layer is substantially composed of silicon, carbon, and arsenic (SiCAs), and the epitaxial source/drain layer is substantially composed of silicon and arsenic (SiAs) . The semiconductor device according to claim 1, wherein the diffusion barrier layer is a doped region of the semiconductor substrate, and the doped region extends from the top surface of the semiconductor substrate to the top of the semiconductor substrate. A point below the surface, where the epitaxial source/drain layer is arranged along the top surface of the diffusion barrier layer. An integrated wafer including: The semiconductor-on-insulator substrate includes a first semiconductor layer, a second semiconductor layer, and an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; An N-type metal oxide semiconductor transistor is arranged on the first semiconductor layer, wherein the N-type metal oxide semiconductor transistor includes a gate electrode, which is arranged on the gate electrode and the first semiconductor layer The gate dielectric layer in between, and a pair of source/drain structures disposed on opposite sides of the gate electrode, wherein the pair of source/drain structures includes: A first pair of epitaxial source/drain layers is located on the first semiconductor layer, wherein the first pair of epitaxial source/drain layers includes a first N-type dopant; and A diffusion barrier layer is disposed between the first semiconductor layer and the first pair of epitaxial source/drain layers, wherein the diffusion barrier layer includes a barrier dopant that is different from the first N-type dopant Miscellaneous agents. The integrated wafer according to claim 10, wherein the diffusion barrier layer includes the first N-type dopant at a first atomic percentage and the barrier dopant at a second atomic percentage, wherein the first The atomic percentage is not less than the second atomic percentage. The integrated wafer according to claim 10, wherein the diffusion barrier layer is an epitaxial layer co-doped with a second N-type dopant and the barrier dopant, wherein the first N-type dopant The dopant is different from the second N-type dopant. The integrated wafer according to claim 12, wherein the first N-type dopant includes phosphorus and the second N-type dopant includes arsenic. The integrated wafer described in claim 10 further includes: A P-type metal oxide semiconductor transistor is disposed on the first semiconductor layer and laterally adjacent to the N-type metal oxide semiconductor transistor, wherein the P-type metal oxide semiconductor transistor includes a second gate An electrode, a second gate dielectric layer under the second gate electrode, and a second pair of epitaxial source/drain layers disposed on opposite sides of the second gate electrode, wherein The bottom surface of the second pair of epitaxial source/drain layers is aligned with the bottom surface of the diffusion barrier layer. The integrated wafer according to claim 10, wherein the first pair of epitaxial source/drain layers and the diffusion barrier layer have a trapezoidal shape. The integrated wafer according to claim 10, wherein the diffusion barrier layer is a doped region of the first semiconductor layer, so that the diffusion barrier layer continuously extends from the top surface of the first semiconductor layer to the The top surface of the insulating layer. A method of manufacturing an integrated wafer, the method comprising: Forming a gate electrode structure on the semiconductor substrate; Forming a diffusion barrier layer on the semiconductor substrate and laterally adjacent to the gate electrode structure, wherein the diffusion barrier layer includes a barrier dopant; and An epitaxial source/drain layer is formed on the diffusion barrier layer, so that the epitaxial source/drain layer includes a first dopant different from the barrier dopant, wherein the diffusion barrier A layer is located between the epitaxial source/drain layer and the semiconductor substrate. The method according to claim 17, wherein forming the diffusion barrier layer includes: Forming a mask layer on the semiconductor substrate, wherein the mask layer includes a plurality of sidewalls that define source/drain region openings on the semiconductor substrate; and A selective epitaxial growth process is performed to selectively form the diffusion barrier layer in the source/drain region openings, wherein the selective epitaxial growth process includes using the first dopant and the The barrier dopant performs in-situ doping on the diffusion barrier layer. The method according to claim 18, wherein the diffusion barrier layer is formed such that a doping profile of the barrier dopant in the diffusion barrier layer has a Gaussian distribution. The method according to claim 17, wherein forming the epitaxial source/drain layer comprises: performing a selective epitaxial growth process to selectively form the epitaxial crystal along the top surface of the diffusion barrier layer The source/drain layer, wherein the bottom surface of the epitaxial source/drain layer is vertically above the top surface of the semiconductor substrate.

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