TW202141593A - Electrochemical additive manufacturing of interconnection features - Google Patents

Electrochemical additive manufacturing of interconnection features Download PDF

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TW202141593A
TW202141593A TW110104696A TW110104696A TW202141593A TW 202141593 A TW202141593 A TW 202141593A TW 110104696 A TW110104696 A TW 110104696A TW 110104696 A TW110104696 A TW 110104696A TW 202141593 A TW202141593 A TW 202141593A
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anode
deposition
layer
wafer
current
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大衛 潘
安德魯 埃德蒙茲
杰弗里 赫曼
查爾斯 帕特羅斯
卡里穆拉 沙伊克
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美商結構8實驗室股份有限公司
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Priority claimed from US16/941,372 external-priority patent/US10947632B1/en
Priority claimed from US17/112,909 external-priority patent/US11232956B2/en
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Abstract

A system and method of using electrochemical additive manufacturing to add interconnection features, such as wafer bumps or pillars, or similar structures like heatsinks, to a plate such as a silicon wafer. The plate may be coupled to a cathode, and material for the features may be deposited onto the plate by transmitting current from an anode array through an electrolyte to the cathode. Position actuators and sensors may control the position and orientation of the plate and the anode array to place features in precise positions. Use of electrochemical additive manufacturing may enable construction of features that cannot be created using current photoresist-based methods. For example, pillars may be taller and more closely spaced, with heights of 200 µm or more, diameters of 10 µm or below, and inter-pillar spacing below 20 µm. Features may also extend horizontally instead of only vertically, enabling routing of interconnections to desired locations.

Description

互連特徵之電化學積層製造Electrochemical multilayer manufacturing of interconnection features

本發明之一或多個實施例係關於電子學及三維列印領域。詳言之,本發明之一或多種實施例提供用以利用電化學積層製造在板體上添加互連特徵之系統及方法。One or more embodiments of the present invention are related to the fields of electronics and three-dimensional printing. In detail, one or more embodiments of the present invention provide a system and method for adding interconnection features on a board body using electrochemical build-up manufacturing.

積層製造,亦稱為三維列印,其係透過層疊程序,直接自CAD (電腦輔助繪圖) 模型生產具複雜性之結構部件及功能部件。積層製程以積層為名蓋因此過程係將材料選擇性沉積於基板上以建構成所需產品。積層製程亦通常涉及逐層堆積,意指待製造產品之層體係連續組成。Laminated manufacturing, also known as 3D printing, is to produce complex structural parts and functional parts directly from CAD (Computer Aided Drawing) models through a laminating process. The build-up process is called build-up, so the process is to selectively deposit materials on the substrate to build the desired product. The build-up process also usually involves layer-by-layer stacking, which means the continuous composition of the layer system of the product to be manufactured.

現有金屬積層製造技術因採用高成本之選擇性雷射燒熔 (SLM)及電子束熔燒(EBM)系統而使其難以廣泛應用。此外,目前業界之金屬積層製造裝置大多是使粉狀金屬受熱熔化後融為一體而形成所需部件,但由於金屬多具有高導熱性,未融化之金屬粉末通常在外緣處燒結,使得成品表面凹凸不平。Existing metal laminate manufacturing technology uses high-cost selective laser melting (SLM) and electron beam melting (EBM) systems, making it difficult to be widely used. In addition, most of the metal laminate manufacturing equipment in the industry currently melts powdered metal into one body to form the required parts. However, because most metals have high thermal conductivity, the unmelted metal powder is usually sintered at the outer edge to make the surface of the finished product. Uneven.

上述積層金屬製造方式之新興替代方案包括電化學反應製造。電化學製程是在電解質溶液中將帶電金屬離子鍍上物體表面,藉此建構金屬部件。此技術之重點係於沉積溶液(電解液)之存在下,使沉積陽極接近基板,而後對陽極供電,使電荷通過陽極,從而在基板上接近陽極之處創造電化學還原反應,並使材料沉積於基板上。一種採用電鍍技術之積層製造裝置範例可如本案發明人之美國發明專利第10,465,307號「電化學積層製造裝置」所述者。此裝置之新穎電化學積層製造方案係利用具有陽極陣列之列印頭同步製造一部件中各層之部分,而非在部件上移動單一陽極以先後建構該層體之部分。Emerging alternatives to the above-mentioned laminated metal manufacturing methods include electrochemical reaction manufacturing. The electrochemical process involves plating charged metal ions on the surface of an object in an electrolyte solution to construct metal parts. The focus of this technology is to make the deposition anode close to the substrate in the presence of the deposition solution (electrolyte), and then supply power to the anode to pass the charge through the anode, thereby creating an electrochemical reduction reaction on the substrate near the anode and depositing the material On the substrate. An example of a build-up manufacturing device using electroplating technology can be as described in the inventor’s US Patent No. 10,465,307 "Electrochemical build-up manufacturing device". The novel electrochemical multilayer manufacturing scheme of this device utilizes a print head with an anode array to simultaneously manufacture parts of each layer in a component, instead of moving a single anode on the component to construct parts of the layer sequentially.

本專利申請為2020年7月28日所提出美國發明專利申請第16/941,372號之部分延續案,該案主張2020年2月28日提出美國臨時專利申請第62/983,274號及2019年8月23日所提出美國臨時專利申請第62/890,815號之優先權,該等案件之說明書經參照併入本文。This patent application is a partial continuation of the U.S. Invention Patent Application No. 16/941,372 filed on July 28, 2020. The case claims that the U.S. Provisional Patent Application No. 62/983,274 was filed on February 28, 2020 and August 2019. Priority of US Provisional Patent Application No. 62/890,815 filed on the 23rd, and the descriptions of these cases are incorporated herein by reference.

本申請亦主張2020年8月24日所提出美國臨時專利申請第63/069,203號之優先權,該案之說明書經參照併入本文。This application also claims the priority of U.S. Provisional Patent Application No. 63/069,203 filed on August 24, 2020, and the description of the case is incorporated herein by reference.

此技藝中之已知積層製程通常是按照預先編程之圖案添加材料。例如,由列印頭以預先設定之速度,在預先設定之時間內送出材料,以建構部件之層體。在電化學製造中,材料沉積之速度及圖案取決於諸多動態因素,例如列印頭與該部件每一位置間之距離、電解質內局部金屬離子密度及電解質流動模式。是以使用嚴格預先編程(「開放迴路」)控制難以確保部件之品質。然如今電化學積層製程之回授控制方法尚未發展完備。The known build-up process in this art usually adds material according to a pre-programmed pattern. For example, the print head sends out materials at a preset speed within a preset time to construct a layer of parts. In electrochemical manufacturing, the speed and pattern of material deposition depend on many dynamic factors, such as the distance between the print head and each position of the part, the local metal ion density in the electrolyte, and the electrolyte flow pattern. Therefore, it is difficult to ensure the quality of components using strict pre-programming ("open loop") control. However, the feedback control method of the electrochemical multilayer process is not yet fully developed.

本發明之一或多個實施例係關於使用沉積回授控制之電化學積層製造方法,其係涉及陰極及陽極陣列置入電解質溶液中,而在待製造之物體上進行建構。所述陽極陣列中之沉積陽極可提供自陽極經由電解質溶液而流至陰極之電流,使材料沉積於陰極之上。此製程所依循之建造計畫包含對於所建造物體中多重層體之層體描述;每一層體描述可包括描述該層內不同位置處材料存在與否之目標地圖,以及一或多種影響該層體建立之程序參數。製造層體時,首先必須設定或確認陰極相對於陽極陣列之位置。而後基於層體描述,發送控制訊號至陽極陣列。繼之於整個陽極陣列上測量一或多個回授訊號,並經分析而產生沉積分析結果,顯示在該層體中不同位置之沉積進展程度。所述沉積分析可用於判定該層是否完成,並修改與該層關聯之程序參數。待一層完成後,可繼續進行後續層體製造。One or more embodiments of the present invention relate to an electrochemical layered manufacturing method using deposition feedback control, which involves placing an array of cathodes and anodes in an electrolyte solution and constructing them on an object to be manufactured. The deposition anode in the anode array can provide a current flowing from the anode to the cathode through the electrolyte solution, so that the material is deposited on the cathode. The construction plan followed by this process includes a layer description of the multiple layers in the constructed object; each layer description can include a target map describing the presence or absence of materials at different locations in the layer, and one or more that affect the layer Program parameters established by the body. When manufacturing the layered body, the position of the cathode relative to the anode array must first be set or confirmed. Then, based on the description of the layer body, a control signal is sent to the anode array. Then, one or more feedback signals are measured on the entire anode array, and after analysis, a deposition analysis result is generated, which shows the degree of deposition progress at different positions in the layer. The deposition analysis can be used to determine whether the layer is complete and modify the program parameters associated with the layer. After one layer is completed, the subsequent layer body manufacturing can be continued.

在一或多個實施例中,可於製造一或多層之前修改對應之層體描述,例如改變層體密度。In one or more embodiments, the corresponding layer description may be modified before one or more layers are manufactured, for example, the layer density may be changed.

回授訊號之分析可包括對訊號施加一或多種轉換,例如形態濾波或布林運算子。The analysis of the feedback signal may include applying one or more transformations to the signal, such as morphological filtering or Boolean operators.

回授訊號可例如包括陽極陣列上之電流地圖。對此電流地圖進行閾值運算可產生沉積分析。The feedback signal may include, for example, a current map on the anode array. Performing a threshold operation on this current map can produce a deposition analysis.

判定層體是否完成可例如包括比對該層體內實際沉積像素數目與所欲沉積像素數目。在本發明實施例中,可在實際對所欲沉積像素比率到達或超過一閾值時,判定該層已經完成。在本發明實施例中,當所欲沉積像素之所欲片段與實際沉積像素之差距在一閾值內時,表示該層體已經完成。在本發明實施例中,可將層體劃分為多個組成部分,並可對每一組成部分進行完成測試;當一層體之所有組成部分均完成時,可視為該層體已經完成。例如,當一組成部分中實際對所欲沉積像素之比率到達或超過一閾值時,或當該組成部分內所欲沉積像素之所欲片段與實際沉積像素之差距在一閾值內時,表示該組成部分已經完成。Determining whether the layer is completed can, for example, include comparing the actual number of pixels deposited in the layer with the number of pixels to be deposited. In the embodiment of the present invention, it can be determined that the layer has been completed when the actual ratio of the pixels to be deposited reaches or exceeds a threshold. In the embodiment of the present invention, when the gap between the desired segment of the pixel to be deposited and the actual deposited pixel is within a threshold, it means that the layer has been completed. In the embodiment of the present invention, the layer body can be divided into multiple component parts, and each component part can be tested for completion; when all the components of a layer body are completed, the layer body can be regarded as completed. For example, when the ratio of the actual pixel to the pixel to be deposited in a component reaches or exceeds a threshold, or when the difference between the desired segment of the pixel to be deposited and the pixel to be deposited in the component is within a threshold, it means that the The components have been completed.

在一或多個實施例中,層體描述可包括釐清層體是否具有懸伸。具有懸伸之層體製造可包括依序沉積該懸伸之部分,俾使其自一或多個先前沉積部分側向延伸而出。In one or more embodiments, the layer description may include clarifying whether the layer has an overhang. The production of an overhanging layer may include depositing the overhanging portions sequentially so that they extend laterally from one or more previously deposited portions.

在一或多個實施例中,層體目標地圖可劃分為不同區域,且層體之建構可包括交替活化與各區域關聯之沉積陽極。In one or more embodiments, the layer target map may be divided into different regions, and the construction of the layer body may include alternately activating the deposition anodes associated with each region.

在一或多個實施例中,製造一層體可包括計算自每一沉積陽極之所欲電流輸出之地圖,因而此電流輸出將產生對應於該層體之目標地圖之沉積。此電流地圖計算可涉及對該層體目標地圖施加一或多種轉換。In one or more embodiments, manufacturing a layer may include calculating a map of the desired current output from each deposition anode, so that this current output will produce a deposition corresponding to the target map of the layer. This current map calculation may involve applying one or more transformations to the layered target map.

在一或多個實施例中,修改與一層體關聯之程序參數可包括計算一或多個沉積陽極之活化電壓、電流或時間。In one or more embodiments, modifying the program parameters associated with a layer may include calculating the activation voltage, current, or time of one or more deposition anodes.

在一或多個實施例中,設定或確認陰極相對於陽極之位置可包括取得基於此相對位置而變化之感測器訊號,例如一電流值或一電壓值。In one or more embodiments, setting or confirming the position of the cathode relative to the anode may include obtaining a sensor signal that changes based on the relative position, such as a current value or a voltage value.

在一或多個實施例中,製造一層體可包括一或多個用以維護該陽極陣列或該電解質溶液條件之維護動作。例如,此等維護動作可替換一或多個已腐蝕沉積陽極之材料。維護動作可活化一或多個沉積陽極以移除形成於其上之薄膜。維護動作可包括移除電解質溶液中之氣泡。In one or more embodiments, manufacturing a layer may include one or more maintenance actions for maintaining the anode array or the condition of the electrolyte solution. For example, these maintenance actions can replace one or more materials that have corroded deposited anodes. The maintenance action can activate one or more deposition anodes to remove the thin films formed thereon. Maintenance actions may include removing bubbles in the electrolyte solution.

在一或多個實施例中,電化學積層製造可用於製造一或多個互連特徵,例如晶圓凸塊或柱體。一晶板,例如一矽晶圓或其他基板,可具有一或多個晶片塊,各設有一或多個連接點。該晶板可具有一導電晶種層。為建構電性耦接於上述連接點之互連特徵,導電晶種層可耦接於一電源供應器,接觸電解質,並與一陽極陣列對齊;自該陽極陣列中每一沉積陽極流出之電流可於控制下將材料沉積於晶板上之所欲位置,形成該所欲互連特徵。In one or more embodiments, electrochemical build-up manufacturing can be used to fabricate one or more interconnect features, such as wafer bumps or pillars. A wafer, such as a silicon wafer or other substrate, can have one or more chip blocks, each with one or more connection points. The crystal plate may have a conductive seed layer. In order to construct the interconnection feature that is electrically coupled to the above-mentioned connection points, the conductive seed layer can be coupled to a power supply, contact the electrolyte, and align with an anode array; the current flowing from each deposition anode in the anode array The material can be deposited on the desired position on the wafer under control to form the desired interconnection feature.

將晶板與陽極陣列對齊時,可使用一或多個感測器判定晶板相對於陽極陣列之三維位置及三維方向,並使用一或多個致動器修改晶板相對於陽極陣列之三維位置及三維方向。When aligning the crystal plate with the anode array, one or more sensors can be used to determine the three-dimensional position and direction of the crystal plate relative to the anode array, and one or more actuators can be used to modify the three-dimensional position of the crystal plate relative to the anode array. Position and three-dimensional direction.

在一或多個實施例中,沉積材料後,可將導電晶種層上未受互連特徵覆蓋之部分移除。在本發明實施例中,可使用電沉積增厚初始導電晶種層。In one or more embodiments, after the material is deposited, the portions of the conductive seed layer that are not covered by the interconnect features can be removed. In the embodiment of the present invention, electrodeposition may be used to thicken the initial conductive seed layer.

在一或多個實施例中,部分或全部互連特徵可具有並不實質垂直於晶板之部分;例如,其可水平延伸。此等部分之建構方式可為依序活化水平偏移陽極以使沉積水平增長。在本發明實施例中,可先沉積一或多個特徵之垂直部分,而後在晶板上沉積惰性材料,為後續之水平部分提供支撐。在本發明實施例中,非垂直特徵之建構方式可為旋轉晶板,使得先前建構之垂直段落轉為水平,而後再垂直沉積後續部分。In one or more embodiments, some or all of the interconnect features may have portions that are not substantially perpendicular to the wafer; for example, they may extend horizontally. These parts can be constructed by sequentially activating the horizontally offset anodes to increase the deposition level. In the embodiment of the present invention, the vertical part of one or more features can be deposited first, and then the inert material is deposited on the wafer to provide support for the subsequent horizontal part. In the embodiment of the present invention, the non-vertical feature can be constructed by rotating the wafer, so that the previously constructed vertical section is turned into horizontal, and then the subsequent part is deposited vertically.

在一或多個實施例中,所述陽極陣列可先後放置於靠近不同組晶片塊之位置,以建構每一晶片塊之互連特徵。In one or more embodiments, the anode arrays can be sequentially placed close to different groups of chips to construct interconnection features of each chip.

本發明之一或多個實施例可包括一電化學積層製造系統,其可例如用於產生互連特徵。所述系統可具有一反應室,其中容納可在電解作用下分解之離子溶液。該系統可具有一設置於反應室內且浸入離子溶液中之陽極陣列,並可具有一設置於反應室內之基板 ,基板以其表面上之導電晶種層接觸離子溶液。其可具有一機械式定位系統,用於修改陽極陣列及/或基板之位置及/或方向,且可具有一微控制器,係經編程而可向機械式定位系統發送控制訊號,以修改陽極陣列及基板之相對位置及方向,俾使陽極陣列與基板實質上共平面,並使陽極陣列與基板之一或多個特徵對齊。該微控制器亦可將互連特徵之三維模型添加至基板。基於此模型,微控制器可控制通過陽極陣列中每一陽極之電流,在基板上建構互連特徵。One or more embodiments of the present invention may include an electrochemical layered manufacturing system, which may be used, for example, to generate interconnect features. The system may have a reaction chamber in which an ionic solution that can be decomposed by electrolysis is contained. The system may have an anode array arranged in the reaction chamber and immersed in the ionic solution, and may have a substrate arranged in the reaction chamber, and the substrate contacts the ionic solution with a conductive seed layer on its surface. It may have a mechanical positioning system for modifying the position and/or orientation of the anode array and/or substrate, and may have a microcontroller, which can be programmed to send control signals to the mechanical positioning system to modify the anode The relative position and direction of the array and the substrate are such that the anode array and the substrate are substantially coplanar, and the anode array and the substrate are aligned with one or more features. The microcontroller can also add a three-dimensional model of interconnection features to the substrate. Based on this model, the microcontroller can control the current through each anode in the anode array to construct interconnection features on the substrate.

所述電化學積層製造系統之一或多個實施例可包括一或多個附加裝置,用於提供與導電晶種層之電性連接。One or more embodiments of the electrochemical layered manufacturing system may include one or more additional devices for providing electrical connection with the conductive seed layer.

在所述電化學積層製造系統之一或多個實施例中,該基板可具有二或多個晶片塊。該微控制器可使陽極陣列相對於該基板先後定位,步進通過所述晶片塊。例如,其可向機械式定位系統發送第一組控制訊號,使陽極陣列與所述二或多個晶片塊中之第一晶片塊對齊,而後控制通過所述陽極陣列中每一陽極之電流,藉此在第一晶片塊上建構互連特徵。隨後可向機械式定位系統發送第二組控制訊號,使陽極陣列與所述二或多個晶片塊中之第二晶片塊對齊,繼而控制通過所述陽極陣列中每一陽極之電流,藉此在第二晶片塊上建構互連特徵。In one or more embodiments of the electrochemical layered manufacturing system, the substrate may have two or more wafer blocks. The microcontroller can position the anode array relative to the substrate one after the other and step through the wafer block. For example, it can send a first set of control signals to a mechanical positioning system to align the anode array with the first of the two or more wafers, and then control the current passing through each anode in the anode array, In this way, interconnection features are constructed on the first wafer block. Then a second set of control signals can be sent to the mechanical positioning system to align the anode array with the second of the two or more wafers, and then control the current through each anode in the anode array, thereby Build interconnection features on the second wafer block.

以下說明使用電化學積層製造在晶板上增設互連特徵之系統及方法。本發明之一或多個實施例可用於製造物體,其涉及使電流通過電解質而在物體上沉積材料,並在沉積過程中監控回授訊號以於程序中適時調整製程參數。在本發明實施例中,待製造之物體可例如為其上增設有互連特徵之晶板,例如設有晶圓凸塊之矽晶圓。為深入闡明本發明實施例,於以下範例敘述中提出諸多具體細節,然對此技藝具有通常知識者應可實施本發明實施例,無需涵蓋在此所數具體細節之所有態樣。於其他實例中,為熟悉此技藝者所知之具體功能、數量或測量於此不加贅述,以模糊本發明之特點。在此雖以範例說明本發明,但本發明之界限應由請求項及所有等同物之完整範圍定義。The following describes the system and method for adding interconnection features on wafers using electrochemical build-up manufacturing. One or more embodiments of the present invention can be used to manufacture objects, which involve depositing materials on the objects by passing an electric current through an electrolyte, and monitoring feedback signals during the deposition process to adjust process parameters in a timely manner during the process. In the embodiment of the present invention, the object to be manufactured can be, for example, a wafer with interconnection features added thereto, such as a silicon wafer with wafer bumps. In order to clarify the embodiments of the present invention in depth, many specific details are presented in the following example descriptions. However, those with general knowledge of the art should be able to implement the embodiments of the present invention, and it is not necessary to cover all aspects of the specific details listed here. In other examples, specific functions, quantities, or measurements known to those familiar with the art will not be repeated here, so as to obscure the characteristics of the present invention. Although the present invention is illustrated with examples, the limits of the present invention should be defined by the full scope of the claims and all equivalents.

電化學積層製程係藉由在電解質溶液中還原表之帶電荷金屬離子而建構金屬部件。此技術仰賴在沉積溶液(電解質)內將沉積陽極放置於接近基板之處,並對陽極通電,促使電荷流經陽極,從而在基板上靠近陽極處產生電化學還原反應,並使材料沉積於基板上。電化學製造之難點在於材料沉積之速度及品質變動極大,且可能基於例如電流密度、電解質組成、電解質液流及陽極與先前沉積材料間之距離等多種因素,在不同時間及不同位置上發生變化。就此,本案發明人發現,於電化學積層製造中,建構高品質部件之重要因素在於採用「封閉迴路」回授控制系統於整個製造過程中監控沉積狀態並據以調整製造參數。此方案與多數三維列印機所採用,基於預先編程指令依序建構層體之「開放迴路」積層製程不同。The electrochemical layering process constructs metal parts by reducing the charged metal ions of the surface in an electrolyte solution. This technology relies on placing the deposition anode in the deposition solution (electrolyte) close to the substrate, and energizing the anode to cause the charge to flow through the anode, thereby generating an electrochemical reduction reaction on the substrate near the anode and depositing the material on the substrate superior. The difficulty of electrochemical manufacturing is that the speed and quality of material deposition vary greatly, and may vary at different times and at different locations based on various factors such as current density, electrolyte composition, electrolyte flow, and the distance between the anode and the previously deposited material. . In this regard, the inventor of the present case discovered that in electrochemical layered manufacturing, an important factor in the construction of high-quality components is the use of a "closed loop" feedback control system to monitor the deposition state during the entire manufacturing process and adjust manufacturing parameters accordingly. This solution is different from the "open loop" build-up process used by most 3D printers, which builds layers sequentially based on pre-programmed instructions.

圖1顯示包含沉積回授控制之電化學積層製程例示步驟。所示步驟僅為範例性質;其他實施例可能利用不同或額外步驟,且可能依不同順序執行操作。圖1之製程具有一規劃階段100及一建造階段120。於規劃階段100中,透過規劃步驟102對物體之模型101進行分析,以產生一用於建構該物體之建造計畫103。所述規劃步驟102可在任何處理器222上執行,例如但不限於電腦、微處理器、微控制器、桌上型電腦、攜帶型電腦、筆記型電腦、伺服器、行動裝置、平板電腦或網路或任何此等處理器。在本發明實施例中,規劃步驟102可例如將三維物體模型101分片為數層,並制定各層之建造計畫103。所述建造計畫103可包括各層之層體描述111;層體描述111可包括例如該層之目標地圖112及用於建構該層之各種程序參數113。所述目標地圖112可包括二維網格或影像,顯示該層體內待沉積材料之位置。層體之程序參數113可包括任何影響該層建構物理程序或電性程序之變因;此等參數可包括例如,但不限於,電流密度範圍、電壓範圍、層體高度、移動參數、懸伸控制、安全閾值、洩漏閾值、短路判定閾值、像素映射間隔與閾值、消泡值、融合、陽極清潔、島嶼化、短路距離、短路距離百分比、像素限制、慢電流控制值及最大斑點大小。圖1顯示物體第一層之例示層體描述111,其包括該層體之目標地圖112及該層體之程序參數113;後續層體同樣具有包含目標地圖及程序參數之層體描述111。該建造規劃步驟102亦可產生整體程序參數115,以供套用於所有層體之,或可做為適用於無特殊層體描述之層體之預設值。Figure 1 shows exemplary steps of an electrochemical layering process including deposition feedback control. The steps shown are merely exemplary; other embodiments may utilize different or additional steps, and operations may be performed in a different order. The manufacturing process of FIG. 1 has a planning stage 100 and a construction stage 120. In the planning stage 100, the model 101 of the object is analyzed through the planning step 102 to generate a construction plan 103 for constructing the object. The planning step 102 can be executed on any processor 222, such as but not limited to a computer, a microprocessor, a microcontroller, a desktop computer, a portable computer, a notebook computer, a server, a mobile device, a tablet computer, or Network or any such processor. In the embodiment of the present invention, the planning step 102 may, for example, divide the three-dimensional object model 101 into several layers, and formulate a construction plan 103 for each layer. The construction plan 103 may include a layer description 111 of each layer; the layer description 111 may include, for example, a target map 112 of the layer and various program parameters 113 used to construct the layer. The target map 112 may include a two-dimensional grid or image, showing the position of the material to be deposited in the layer. The process parameters 113 of the layer can include any variables that affect the physical or electrical processes of the layer’s construction; these parameters can include, for example, but not limited to, current density range, voltage range, layer height, movement parameters, overhang Control, safety threshold, leakage threshold, short circuit determination threshold, pixel mapping interval and threshold, defoaming value, fusion, anode cleaning, islanding, short circuit distance, short circuit distance percentage, pixel limit, slow current control value and maximum spot size. FIG. 1 shows an exemplary layer description 111 of the first layer of an object, which includes the target map 112 of the layer and the program parameters 113 of the layer; the subsequent layers also have the layer description 111 including the target map and the program parameters. The construction planning step 102 can also generate overall program parameters 115 for applying to all layers, or can be used as preset values for layers without special layer descriptions.

所述程序之建造階段120使用例如執行電化學沉積之設備,自該建造計畫103建構一物體。以下參照圖2說明可用於本發明一或多個實施例中之例示設備。為啟動建造程序,於步驟121中使陰極220表面接觸電解質溶液210;藉由使電流通過亦與溶液接觸之陽極陣列201,可將材料以電化學方式沉積於陰極220之上,從而建構物體。之後可在陰極220之基底或先前建構之層體上依序建造計畫103中之層體,有效擴大陰極2200以利沉積。步驟122包含針對建造計畫103中之各層而取得或載入層體描述111。層體描述111可例如載入可由電化學沉積設備中控制器所存取之記憶體;所述控制器可為任何類型之處理器。例如,於開始物體建構時可先載入或取得第一層體描述111。而後由控制器可執行步驟123以設定或確認該陽極與陰極220間之相對位置。由於層體係相繼建造,陽極與陰極220間之距離可能需要修改,以確保陽極與最新沉積表面間之距離維持在沉積程序可充分控制之範圍內。例如,電化學沉積設備可包括一致動器,其可移動陰極220及/或陽極,如下文參照圖2所述者。針對第一層,步驟123可例如涉及一「歸零」步驟,將陽極與陰極220間之初始相對位置設定為所欲初始值。用於歸零之具體方法可依沉積設備而異。例如,在一或多個實施例中,所述控制器可移動陰極220或陽極0,直到一或多個感測器223顯示兩者接觸(或足夠接近)為止,而後其可自此接觸位置偏移一所欲距離。在本發明實施例中,位置致動器224上可設有例如絕對或相對編碼器等感測以利歸零。The construction stage 120 of the procedure uses equipment for performing electrochemical deposition, for example, to construct an object from the construction project 103. Hereinafter, an exemplary device that can be used in one or more embodiments of the present invention will be described with reference to FIG. 2. To start the construction process, in step 121, the surface of the cathode 220 is contacted with the electrolyte solution 210; by passing current through the anode array 201 which is also in contact with the solution, materials can be electrochemically deposited on the cathode 220 to construct an object. Afterwards, the layers in the project 103 can be constructed sequentially on the substrate of the cathode 220 or the previously constructed layers, effectively expanding the cathode 2200 to facilitate deposition. Step 122 includes obtaining or loading the layer body description 111 for each layer in the construction plan 103. The layer description 111 can, for example, be loaded into a memory that can be accessed by a controller in the electrochemical deposition device; the controller can be any type of processor. For example, when starting the object construction, the first layer body description 111 can be loaded or obtained first. Then, the controller can execute step 123 to set or confirm the relative position between the anode and the cathode 220. As the layer system is constructed one after another, the distance between the anode and the cathode 220 may need to be modified to ensure that the distance between the anode and the newly deposited surface is maintained within a range that can be fully controlled by the deposition process. For example, the electrochemical deposition apparatus may include an actuator that can move the cathode 220 and/or the anode, as described below with reference to FIG. 2. For the first layer, step 123 may, for example, involve a “return to zero” step, which sets the initial relative position between the anode and the cathode 220 to a desired initial value. The specific method used for zeroing may vary depending on the deposition equipment. For example, in one or more embodiments, the controller can move the cathode 220 or the anode 0 until one or more sensors 223 indicate that the two are in contact (or close enough), and then they can contact the position from there. Offset a desired distance. In the embodiment of the present invention, the position actuator 224 may be provided with sensors such as absolute or relative encoders to facilitate zeroing.

對於第一層以後之層體,步驟123可確保陽極與陰極220間之相對位置正確,以開始新一層之材料沉積。在某些情況下,可能需要修改相對位置,例如使用致動器移動陽極或陰極220。例如,在某些情況下,物體之建構可包括相繼沉積一層體之材料,而後使陰極220相對於陽極重新定位,以使陰極220遠離陽極,準備沉積下一層,隨後沉積下一層之材料。在其他情況下,可在建構一層之過程中持續執行陽極與陰極220間之相對移動,稱為「滑動」,如此可於步驟123中,在載入新一層時,無需另行重新定位。For the layer body after the first layer, step 123 can ensure that the relative position between the anode and the cathode 220 is correct to start the material deposition of a new layer. In some cases, it may be necessary to modify the relative position, such as using an actuator to move the anode or cathode 220. For example, in some cases, the construction of an object may include successively depositing a layer of material, and then repositioning the cathode 220 relative to the anode, so that the cathode 220 is away from the anode, ready to deposit the next layer, and then the next layer of material. In other cases, the relative movement between the anode and the cathode 220 can be continuously performed during the process of constructing a layer, which is called "sliding", so that in step 123, when a new layer is loaded, there is no need to reposition it.

於步驟122載入層體描述111,且於步驟123設定或確認陰極220與陽極間之相對位置之後,建造階段120進入內部迴圈140步驟,用以建構載入層。如上所述,此迴圈140可為具有回授控制之封閉迴路,俾便於所述迴圈140之全程基於測得之回授訊號而修改建造步驟及程序參數。步驟125可包括各種經由電化學反應沉積材料之動作(例如使電流通過陽極)以及維持或調整陽極陣列201及電解質狀態或健康程度之動作。例示維護動作可包括例如,但不限於,移除電解質中之氣泡、攪動電解質以改變流速或改變電解質中之離子分布以及用以去除陽極上薄膜或補充陽極表面之動作。上述任一維護動作可以任何所需方式與沉積動作穿插進行。After loading the layer description 111 in step 122, and after setting or confirming the relative position between the cathode 220 and the anode in step 123, the construction phase 120 enters the inner loop 140 step to construct the loading layer. As described above, the loop 140 can be a closed loop with feedback control, so that the entire loop 140 can modify the construction steps and process parameters based on the measured feedback signal. Step 125 may include various actions of depositing materials through electrochemical reactions (for example, passing current through the anode) and actions of maintaining or adjusting the state or health of the anode array 201 and the electrolyte. Exemplary maintenance actions may include, for example, but not limited to, removing bubbles in the electrolyte, stirring the electrolyte to change the flow rate or changing the ion distribution in the electrolyte, and actions to remove the film on the anode or supplement the anode surface. Any of the above maintenance actions can be interspersed with the deposition actions in any desired manner.

於層體建構過程中之選定時間或固定週期,可執行步驟126以取得例如關於沉積進度之回授訊號。本發明之實施例可利用任何類型之感測器223取得回授訊號。例如,在一或多個實施例中,可測量通過陽極陣列201中每一陽極之電流(例如具有固定電壓);電流較高可能代表陽極與陰極220間之阻抗較低,關聯於每一陽極附近之陰極220上所沉積之材料量。於其他實施例中,可利用變動電壓波形,且可測量交流電(AC)訊號。本發明之實施例可利用其他回授訊號,例如陰極光學影像或至陰極220上不同位置之距離測量值。於步驟127中,對此等回授訊號進行分析以產生一沉積分析128,其可包括層體內不同位置沉積之材料量估計值。基於沉積分析128,可就該層之建構是否已經完成做出判定129。若該層完成,且測試132顯示尚有其他層體待建構,則於步驟122載入下一層,而後執行下一層之層體建構迴圈140;否則該物體之建構即為完成。在某些實施例中,產生沉積地圖可與沉積程序同時執行。例如,製造陽極陣列201時可加入額外感應元件,用以對通過各沉積陽極之電流或在各沉積陽極表面之電壓進行特性分析。例如,可使用類比至數位轉換器(ADC),此ADC之輸入以類似於陽極陣列201定址所用之多路傳輸方式連接至相繼排列之沉積陽極行。At a selected time or fixed period in the layer construction process, step 126 may be performed to obtain, for example, a feedback signal regarding the deposition progress. The embodiment of the present invention can use any type of sensor 223 to obtain the feedback signal. For example, in one or more embodiments, the current passing through each anode in the anode array 201 (for example, having a fixed voltage) can be measured; a higher current may mean that the impedance between the anode and the cathode 220 is lower, which is related to each anode. The amount of material deposited on the nearby cathode 220. In other embodiments, fluctuating voltage waveforms can be used, and alternating current (AC) signals can be measured. Embodiments of the present invention can use other feedback signals, such as cathode optical images or distance measurements to different positions on the cathode 220. In step 127, these feedback signals are analyzed to generate a deposition analysis 128, which may include estimates of the amount of material deposited at different positions in the layer. Based on the deposition analysis 128, a decision 129 can be made as to whether the construction of the layer has been completed. If the layer is completed and the test 132 shows that there are other layers to be constructed, the next layer is loaded in step 122, and then the layer construction loop 140 of the next layer is executed; otherwise, the construction of the object is completed. In some embodiments, the generation of the deposition map may be performed simultaneously with the deposition process. For example, when the anode array 201 is manufactured, additional sensing elements can be added to analyze the characteristics of the current passing through each deposition anode or the voltage on the surface of each deposition anode. For example, an analog-to-digital converter (ADC) can be used, and the input of the ADC is connected to successively arranged rows of deposition anodes in a multiplexing manner similar to that used for addressing the anode array 201.

若判定129顯示一層之沉積尚未完成,則於某些情況下可參考沉積分析128或來自回授訊號之其他資料而對用於建構該層之參數及控制訊號進行修改。可藉由判定130決定是否需要調整。若需要調整,則可修改一或多個程序參數131,從而改變驅動沉積(及維護)動作之控制訊號124。例如,若沉積分析128顯示一層中之特定區域已沉積有足夠材料,即可就對應於此區域之陽極進行電流之關斷(或降低)。If it is determined that 129 shows that the deposition of a layer has not been completed, in some cases, the parameters and control signals used to construct the layer can be modified by referring to the deposition analysis 128 or other data from the feedback signal. The decision 130 can be used to determine whether adjustment is required. If adjustment is required, one or more program parameters 131 can be modified to change the control signal 124 that drives the deposition (and maintenance) action. For example, if the deposition analysis 128 shows that a certain area in a layer has deposited enough material, the anode corresponding to this area can be turned off (or reduced).

圖2顯示可用於執行本發明一或多個實施例之建造步驟例示設備結構圖。該系統之列印頭200包含沉積陽極陣列201,及沉積陽極對應之沉積控制電路202陣列。在本發明實施例中,沉積控制電路202可排列成矩陣,藉此支撐高解析度陽極陣列。該沉積陽極陣列201可排列成二維網格;圖2顯示一截面圖。一網格控制電路203向沉積控制電路202發送控制訊號,控制通過陽極陣列201中之每一沉積陽極之電流量。通過陽極之電流係由一配電電路204所提供,其將來自一或多個電源供應器221之電力導引至沉積控制電路,再導引至陽極。列印頭200亦可包含其他元件,例如用以保護列印頭200元件不與電解質溶液210接觸之絕緣層。Fig. 2 shows a structural diagram of an exemplary equipment for construction steps that can be used to implement one or more embodiments of the present invention. The print head 200 of the system includes an array of deposition anodes 201 and an array of deposition control circuits 202 corresponding to the deposition anodes. In the embodiment of the present invention, the deposition control circuit 202 may be arranged in a matrix, thereby supporting a high-resolution anode array. The deposition anode array 201 can be arranged in a two-dimensional grid; FIG. 2 shows a cross-sectional view. A grid control circuit 203 sends a control signal to the deposition control circuit 202 to control the amount of current passing through each deposition anode in the anode array 201. The current through the anode is provided by a power distribution circuit 204, which directs the power from one or more power supplies 221 to the deposition control circuit and then to the anode. The print head 200 may also include other elements, such as an insulating layer for protecting the elements of the print head 200 from contact with the electrolyte solution 210.

列印頭200之沉積陽極陣列201可置入於電解質溶液210中。而後經由電化學反應可,使金屬電鍍在一耦接於陰極220之製成部件230上。藉由改變通過沉積陽極陣列201中每一陽極之電流,可於部件230建造出各種複雜精細之形狀。例如,於圖2中,陽極211通電而使金屬沉積於靠近部件230上靠近此陽極之處,但陽極212並未通電,因此該陽極附近並不會產生金屬沉積。The deposition anode array 201 of the print head 200 can be placed in the electrolyte solution 210. Then, through electrochemical reaction, the metal is electroplated on a finished part 230 coupled to the cathode 220. By changing the current passing through each anode in the deposited anode array 201, various complicated and delicate shapes can be constructed in the component 230. For example, in FIG. 2, the anode 211 is energized to deposit metal near the anode on the component 230, but the anode 212 is not energized, so no metal deposition occurs near the anode.

在一或多個實施例中,列印頭200可與處理器222整合。此處理器222可傳送訊號至網格控制電路203,後者再發送訊號至個別沉積控制電路202,以將沉積陽極陣列201中之陽極開啟或關閉(或改變通過每一陽極之電流強度)。處理器222可例如為,但不限於微控制器、微處理器、GPU、FPGA、SoC、單板電腦,攜帶型電腦、筆記型電腦、桌上型電腦、伺服器或網路或上述裝置之任何組合。處理器222可與用於分析物體模型以建構建造計畫103之處理器222為相同或不同。處理器222可連通於一或多個用以提供部件230上金屬沉積進度回授訊號之感測器223。感測器223可包括例如,但不限於,電流感測器、電壓感測器、計時器、攝影機、測距儀、刻度尺、力量感測器或壓力感測器。一或多個感測器223亦可用於測量陰極220與陽極間之距離,例如在開始製造一物體前之歸零,或在開始製造每一層體前設定或確認該陽極與陰極220間之相對位置。建造晶板相對於該電極陣列在沉積程序初始化時之準確定位對於沉積之成功與否及品質具有重要影響。實施例可利用各種類型之感測器223達成準確定位,包括但不限於,機械式、電氣式或光學式感測器,或其組合。在本發明實施例中,可利用機械式感測器例如壓力感測器、開關或荷重元偵測建造晶板何時移動至所需位置。在本發明實施例中,系統可部分通電,並移動陰極220以接近在已知位置上之已通電組成部分。當於陰極220或建造晶板上偵測到電壓或電流時,表示建造晶板處於一特定位置。本發明之實施例可利用其他類型之感測器偵測例如電容、阻抗、磁場,或透過霍爾效應判斷陰極/建造晶板相對於一已知部位之位置。本發明之實施例可利用光學感測器,例如雷射測距儀或可偵測光學路徑干擾之感測器。In one or more embodiments, the print head 200 can be integrated with the processor 222. The processor 222 can send a signal to the grid control circuit 203, which then sends a signal to the individual deposition control circuit 202 to turn the anodes in the deposition anode array 201 on or off (or change the current intensity through each anode). The processor 222 may be, for example, but not limited to a microcontroller, microprocessor, GPU, FPGA, SoC, single board computer, portable computer, notebook computer, desktop computer, server or network or any of the above devices Any combination. The processor 222 may be the same as or different from the processor 222 used to analyze the object model to construct the construction plan 103. The processor 222 may be connected to one or more sensors 223 for providing feedback signals of the metal deposition progress on the component 230. The sensor 223 may include, for example, but not limited to, a current sensor, a voltage sensor, a timer, a camera, a rangefinder, a scale, a force sensor, or a pressure sensor. One or more sensors 223 can also be used to measure the distance between the cathode 220 and the anode, such as resetting to zero before starting to manufacture an object, or setting or confirming the relative relationship between the anode and the cathode 220 before starting to manufacture each layer. Location. The accurate positioning of the wafer plate relative to the electrode array during the initialization of the deposition process has an important impact on the success and quality of the deposition. Embodiments can utilize various types of sensors 223 to achieve accurate positioning, including, but not limited to, mechanical, electrical, or optical sensors, or a combination thereof. In the embodiment of the present invention, a mechanical sensor such as a pressure sensor, a switch, or a load cell can be used to detect when the building wafer moves to a desired position. In the embodiment of the present invention, the system may be partially energized, and the cathode 220 may be moved to approach the energized component at a known position. When a voltage or current is detected on the cathode 220 or the construction wafer, it indicates that the construction wafer is at a specific position. Embodiments of the present invention can use other types of sensors to detect, for example, capacitance, impedance, and magnetic field, or determine the position of the cathode/built wafer relative to a known part through the Hall effect. Embodiments of the present invention can utilize optical sensors, such as laser rangefinders or sensors that can detect optical path interference.

陰極220及列印頭200中之任一或兩者可附加於一或多個位置致動器224上,用以控制陰極220與沉積陽極陣列201之相對位置。位置致動器224可控制垂直移動225,藉此在部件230建造為連續層體之過程中,使陰極220能夠升高(或使陽極降低)。在本發明實施例中,位置致動器224亦可使陰極220或沉積陽極陣列201相對於彼此水平移動,而可例如於晶片塊終製作大型部件。所述晶片塊可對應於半導體晶粒。在某些實施例中,晶片塊之數目可對應於相同半導體晶粒圖案。在某些實施例中,可在同類型晶粒頂部建造不同互連結構,如此一來,即便下方晶粒圖案相同,亦可達成晶片之客製化。Either or both of the cathode 220 and the print head 200 can be attached to one or more position actuators 224 to control the relative position of the cathode 220 and the deposition anode array 201. The position actuator 224 can control the vertical movement 225, thereby enabling the cathode 220 to rise (or lower the anode) during the construction of the component 230 as a continuous layer. In the embodiment of the present invention, the position actuator 224 can also move the cathode 220 or the deposition anode array 201 horizontally relative to each other, and can, for example, produce large parts at the end of the wafer block. The wafer block may correspond to a semiconductor die. In some embodiments, the number of wafer blocks may correspond to the same semiconductor die pattern. In some embodiments, different interconnection structures can be built on top of the same type of die. In this way, even if the pattern of the underlying die is the same, the customization of the wafer can be achieved.

列印頭200可連接於一電源供應器221(或多個電源供應器),其電流244通過沉積陽極陣列201而驅動部件230上之金屬沉積。電流可經由配電電路204而分配於整個沉積控制電路202陣列,所述配電電路204可例如包括一或多個電源匯流排。The print head 200 can be connected to a power supply 221 (or multiple power supplies), the current 244 of which drives the metal deposition on the component 230 through the deposition anode array 201. The current may be distributed to the entire deposition control circuit 202 array via the power distribution circuit 204, which may, for example, include one or more power bus bars.

在一或多個實施例中,系統亦可包括一容納有電解質溶液210之流體艙(未示於圖2),及一流體處理系統(亦未示於圖中)。流體系統可包括例如一槽體、一微粒過濾器、耐化學性管路及泵浦。分析設備可使用例如傳導性、高效液相層析、質量光譜分析、循環伏安剝除、分光光度計測量或類似方式,進行液槽酸鹼值、溫度及離子濃度之連續特性分析。液槽條件可使用冷卻器、加熱器維持並/或使用自動化補充系統以補充溶液蒸發損失及/或之沉積材料之離子損失。In one or more embodiments, the system may also include a fluid chamber (not shown in FIG. 2) containing the electrolyte solution 210, and a fluid processing system (also not shown in the figure). The fluid system may include, for example, a tank, a particulate filter, chemical-resistant tubing, and pumps. The analysis equipment can use, for example, conductivity, high performance liquid chromatography, mass spectroscopy, cyclic voltammetry stripping, spectrophotometer measurement or similar methods to analyze the continuous characteristics of the pH, temperature and ion concentration of the tank. The tank conditions can be maintained by coolers and heaters and/or an automated replenishment system can be used to supplement the evaporation loss of the solution and/or the ion loss of the deposition material.

雖然圖2所示系統僅具有單一沉積陽極陣列201,但其他實施例可具有多個沉積陽極陣列201。此等陽極陣列201可例如同時操作於不同電解質溶液210槽,或可經鋪設而使其合作而在共用陰極220或串聯陰極220上沉積材料。Although the system shown in FIG. 2 only has a single deposition anode array 201, other embodiments may have multiple deposition anode arrays 201. These anode arrays 201 can, for example, be operated in different electrolyte solution 210 tanks at the same time, or they can be laid to cooperate to deposit materials on a common cathode 220 or a series of cathodes 220.

圖3顯示參照物體模型101a所規劃之物體建造計畫103元件。物體模型101a可例如為三維CAD 模型,或任何對於物體形狀或材料特性之描述。建造規劃程序可將模型分片為數個層體,且可針對各層建立層體描述111。圖3顯示四個例示層,各對應於模型101a之一個水平切片。建造計畫103可具有任何數量之層體,且切片可為任何所欲厚度、形狀及方向。各層之層體描述111包括一目標地圖及一或多個程序參數。圖3所示之四層分別具有目標地圖112a至112d,及程序參數113a至113d。所述目標地圖可例如為二維影像,顯示該層中應沉積材料之處。在圖3之目標地圖112a至112d中,黑色像素表示待沉積於對應層體位置之材料,白色像素表示無材料待沉積。在本發明實施例中,該目標地圖112a至112d於不同位置可具有非二元值;例如,目標地圖112a至112d可描述為灰階影像。在本發明實施例中,目標地圖112a至112d可包含其他資訊,例如材料類型或每一位置待沉積之材料。FIG. 3 shows the components of the object construction plan 103 planned with reference to the object model 101a. The object model 101a can be, for example, a three-dimensional CAD model, or any description of the object shape or material properties. The construction planning program can divide the model into several layers, and can establish a layer description 111 for each layer. Figure 3 shows four exemplary layers, each corresponding to a horizontal slice of the model 101a. The construction plan 103 can have any number of layers, and the slices can have any desired thickness, shape, and direction. The layer description 111 of each layer includes a target map and one or more program parameters. The four layers shown in FIG. 3 respectively have target maps 112a to 112d, and program parameters 113a to 113d. The target map may be, for example, a two-dimensional image, showing where the material should be deposited in the layer. In the target maps 112a to 112d in FIG. 3, the black pixels indicate the material to be deposited at the corresponding layer position, and the white pixels indicate that there is no material to be deposited. In the embodiment of the present invention, the target maps 112a to 112d may have non-binary values at different positions; for example, the target maps 112a to 112d may be described as grayscale images. In the embodiment of the present invention, the target maps 112a to 112d may include other information, such as the type of material or the material to be deposited at each location.

圖3顯示層體之三種例示程序參數301至303。在本發明實施例中,具有層體描述111之程序參數可為任何數量。程序參數可描述任何影響層體製造或影響待執行維護活動之因素。例示程序參數301定義建構層體所用之電流密度,指定單位為例如製造設備所支援最大電流密度之百分比。例示程序參數302表示層體是否需要材料之側面沉積。此參數可基於建造規劃系統是否偵測到懸伸部位,如下文中參照圖6所述者。對於不需側面沉積之層體,在一或多個實施例中,製造系統可於製造該層之全程中使陰極之位置垂直於陽極,以便於該層體累積之同時,沉積材料與陽極可維持相對固定距離;此「滑移」動作可例如減少陽極與陰極220間產生短路之機會。例示程序參數303為該層體之目標高度。在某些情況下,所述層體高度可於初始層(例如目標地圖112d之層體)較高,以便清除氣泡。具有懸伸之層體(例如目標地圖112b之層體)可具有較低高度,以便例如確保建造時之尺寸穩定性。Fig. 3 shows three exemplary program parameters 301 to 303 of the layer body. In the embodiment of the present invention, the program parameters with the layer description 111 can be any number. The program parameters can describe any factors that affect the manufacturing of the layer body or affect the maintenance activities to be performed. The example program parameter 301 defines the current density used to construct the layer, and the specified unit is, for example, a percentage of the maximum current density supported by the manufacturing equipment. The example program parameter 302 indicates whether the layer requires side deposition of material. This parameter can be based on whether the overhang is detected by the construction planning system, as described below with reference to FIG. 6. For a layer that does not require side deposition, in one or more embodiments, the manufacturing system can make the position of the cathode perpendicular to the anode during the whole process of manufacturing the layer, so that while the layer is accumulated, the deposition material and the anode can be Maintain a relatively fixed distance; this "slip" action can, for example, reduce the chance of a short circuit between the anode and the cathode 220. The example program parameter 303 is the target height of the layer. In some cases, the height of the layer may be higher than that of the initial layer (for example, the layer of the target map 112d) to remove air bubbles. The overhanging layer (for example, the layer of the target map 112b) may have a lower height, for example, to ensure dimensional stability during construction.

層體之程序參數亦可包括陽極陣列201中每一陽極在建構該層時之目標輸出1007。於簡單情況下,此輸出1007可符合該層之目標地圖:可開通位於待沉積材料處之陽極,並關斷其他陽極。陽極輸出1007與目標地圖間之關係在其他情況下可能更為複雜,如圖11A、11B、11C及12所繪示者。The program parameters of the layer body can also include the target output 1007 of each anode in the anode array 201 when the layer is constructed. In simple cases, this output 1007 can meet the target map of the layer: the anode located at the material to be deposited can be turned on, and other anodes can be turned off. The relationship between the anode output 1007 and the target map may be more complicated in other cases, as shown in FIGS. 11A, 11B, 11C, and 12.

圖4繪示物體101a目標地圖112d之基底層403之密度操控。此層體係首先增設於陰極220,而後其他層體再建構於基底層403頂部。針對基底層403(或一組基底層403),宜減少其層密度,使其呈現多孔狀,以便於製造完成後將物體自陰極220取下。藉由操控目標地圖而減少待沉積材料處之像素數目,可達成降低密度之目的。例如,於其可能性較目標密度低100%之隨機位置,可將沉積關斷。於圖4中,將密度401參數套用於原始目標地圖112d以產生一修改後之目標地圖402,其中原始目標地圖之70%像素已經關斷(「關斷」像素在圖中以白色顯示)。此修改後之目標地圖402使基底層403沉積於陰極220之上(示於圖4之垂直斷面中)。額外層體404建構於基底層403頂部以完成部件。基底層403之多孔結構有助於自陰極220取下部件405。FIG. 4 illustrates the density manipulation of the base layer 403 of the target map 112d of the object 101a. This layer system is first added to the cathode 220, and then other layers are constructed on top of the base layer 403. For the base layer 403 (or a group of base layers 403), the layer density should be reduced to make it porous, so that the object can be removed from the cathode 220 after the manufacturing is completed. By manipulating the target map to reduce the number of pixels at the material to be deposited, the density can be reduced. For example, at random locations where the probability is 100% lower than the target density, the deposition can be turned off. In FIG. 4, the density 401 parameter is applied to the original target map 112d to generate a modified target map 402, in which 70% of the pixels of the original target map have been turned off (the "off" pixels are shown in white in the figure). The modified target map 402 has the base layer 403 deposited on the cathode 220 (shown in the vertical section of FIG. 4). The additional layer 404 is constructed on top of the base layer 403 to complete the part. The porous structure of the base layer 403 facilitates the removal of the component 405 from the cathode 220.

圖5及圖6顯示例示建造規劃及具有顯著懸伸之層體製造。懸伸是指水平延伸且於其下方層體並無材料支撐之特徵。於傳統塑膠材料三維列印中,此等懸伸必須具備明確之支撐結構,而後另於製造後步驟加以移除。但在電化學積層製造中,由於金屬離子可側向累積且融合成為無需下方支撐即具足夠強度之懸伸結構,因此可直接建構許多懸伸,無需添加支撐結構。圖5繪示在一或多個實施例中辨識懸伸之方式。可例如運用差分運算501將層體之目標地圖112b與下方層體(或下方多層)之目標地圖112c比對,從而產生異動資料比對地圖502,其中顯示添加材料但於下方未設支撐之區域503。若此等區域在區域503中之尺寸較大,建造規劃系統可判定504懸伸需要特殊處理,例如側面建構,如圖6所示者。圖6之例示製造步驟係用以製造目標地圖112b之層體在目標地圖112c之下方層體之區域601c上方懸伸之小型部分601b。此部分601b為有效架設於二支撐柱610上之「橋樑」。支撐柱610上已於先前層體中製成,其頂部對應於目標地圖112c之區域601c。橋樑於目標地圖112b之層體以三個例示子步驟建構。首先,將材料611增設於支撐柱610頂部;此子步驟對應於目標地圖112b之子集621。其次,將材料612自支撐柱610側向增設而出,對應於目標地圖112b之子集622。第三,在中段側向增設材料613,對應於目標地圖112b之子集623,產生最終結構614。所需側面建造步驟數量可能因例如懸伸大小及材料結合強度而異。Figures 5 and 6 show an exemplary construction plan and the manufacture of a layered body with significant overhang. Overhang refers to the feature of horizontal extension and no material support on the underlying layer. In traditional three-dimensional printing of plastic materials, these overhangs must have a clear support structure, and then be removed in a post-manufacturing step. However, in electrochemical layered manufacturing, since metal ions can accumulate laterally and fuse into an overhang structure with sufficient strength without supporting underneath, many overhangs can be directly constructed without adding support structures. Fig. 5 shows how to identify overhangs in one or more embodiments. For example, the difference operation 501 can be used to compare the target map 112b of the layer body with the target map 112c of the layer below (or multiple layers below), thereby generating an abnormal data comparison map 502, which shows the area where materials are added but no support is provided below 503. If the size of these areas in the area 503 is larger, the construction planning system can determine 504 that the overhang requires special treatment, such as side construction, as shown in FIG. 6. The illustrated manufacturing step of FIG. 6 is used to manufacture the small part 601b of the layer body of the target map 112b overhanging the area 601c of the layer body below the target map 112c. This part 601b is a "bridge" effectively erected on the two supporting columns 610. The support column 610 has been made in the previous layer, and its top corresponds to the area 601c of the target map 112c. The layered body of the bridge on the target map 112b is constructed in three exemplified sub-steps. First, the material 611 is added to the top of the support column 610; this sub-step corresponds to the subset 621 of the target map 112b. Secondly, the material 612 is added laterally from the supporting column 610, corresponding to the subset 622 of the target map 112b. Third, a material 613 is added laterally in the middle section, which corresponds to a subset 623 of the target map 112b, resulting in a final structure 614. The number of side construction steps required may vary depending on, for example, overhang size and material bonding strength.

在一或多個實施例中,懸伸處理亦可包括降低懸伸區域層體高度,以達成所需沉積。具體做法可例如為改變層體高度而使懸伸距離符合某像素間距之某種比率。例如,若要製作像素間距為50 um之45度懸伸,層體高度可設定為50 um,如此將使懸伸距離為50 um (1像素寬度)。在60度懸伸上,層體高度為29 um以內可使懸伸距離為50 um。以上兩種範例均為1:1比率,其中每層懸伸距離增加1像素。若為2:1比率,則層體高度加倍,因此各層之懸伸距離為100 um或2像素。如此可產生更為穩定且固定之懸伸建造,不受懸伸角度影響。In one or more embodiments, the overhanging treatment may also include reducing the height of the layer in the overhanging area to achieve the desired deposition. The specific method can be, for example, changing the height of the layer body so that the overhang distance matches a certain ratio of a certain pixel pitch. For example, to make a 45-degree overhang with a pixel pitch of 50 um, the layer height can be set to 50 um, so that the overhang distance will be 50 um (1 pixel width). At 60 degree overhang, the height of the layer body is within 29 um and the overhang distance can be 50 um. The above two examples are of a 1:1 ratio, where the overhang distance of each layer is increased by 1 pixel. If the ratio is 2:1, the height of the layer is doubled, so the overhang distance of each layer is 100 um or 2 pixels. In this way, a more stable and fixed overhang construction can be produced, regardless of the overhang angle.

圖7至圖10顯示例示回授訊號及其分析,以判定層體是否建造完成或是否需要修改層體製程參數。圖7顯示一基於電流感測器223a之回授方法,所述電流感測器223a可例如連接至沉積陽極陣列201之陽極。由於陽極與陰極220間之阻抗會隨陽極距離陰極220上沉積傳導材料之遠近而變化,可利用電流感測器223a估算最接近陽極陣列201中每一陽極處之沉積程度。例如,陽極可設為已知電壓,則通過每一陽極之電流可與此阻抗成反比。圖7顯示例示陽極701至706,及一已部分建構之例示部件230a。電流感測器223a測量通過每一陽極之電流710。就陽極703而言,陽極已與沉積材料形成短路;因此測得之電流713極高。就陽極704而言,陽極非常接近沉積材料,但並非完全短路,因此測得之電流714低於短路陽極703之電位719。陽極701遠離沉積材料,因此測得之電流711極小。Figures 7 to 10 show examples of feedback signals and their analysis to determine whether the layer is built or whether it is necessary to modify the parameters of the layer system. FIG. 7 shows a feedback method based on the current sensor 223a, which can be connected to the anode of the deposition anode array 201, for example. Since the impedance between the anode and the cathode 220 varies with the distance between the anode and the conductive material deposited on the cathode 220, the current sensor 223a can be used to estimate the degree of deposition closest to each anode in the anode array 201. For example, the anode can be set to a known voltage, and the current through each anode can be inversely proportional to this impedance. FIG. 7 shows exemplary anodes 701 to 706, and a partially constructed exemplary component 230a. The current sensor 223a measures the current 710 through each anode. In the case of anode 703, the anode has formed a short circuit with the deposited material; therefore, the measured current 713 is extremely high. As for the anode 704, the anode is very close to the deposited material, but is not completely short-circuited, so the measured current 714 is lower than the potential 719 of the short-circuited anode 703. The anode 701 is far away from the deposited material, so the measured current 711 is extremely small.

在一或多個實施例中,回授訊號,例如電流710感測器之資料,可經處理而進一步產生部件內不同位置之沉積程度分析。此處理可例如基於已知或估計沉積程度與回授訊號間之關係。圖8顯示由電流感測器223a所測得電流之二維地圖801例示分析。於此地圖801中,較亮像素對應於較高測得電流。電流地圖801之步驟127之分析可例如運用閾值運算802以選擇超過指定電流強度之像素,產生初步沉積分析128。此例示沉積分析128為二元影像,其中白色像素顯示較高沉積區域,黑色像素顯示較低沉積區域。閾值運算802僅屬說明性質;其他實施例可利用任何適當方式分析地圖801之回授訊號而產生沉積分析128。此沉積分析128而後可用於判定129層體之沉積是否完成,並判定130是否需要為後續層體建構修改任何程序參數。圖9A及圖9B顯示判定129之層體完成度例示分析,圖10顯示判定130之關於程序參數修改例示分析。In one or more embodiments, the feedback signal, such as the data of the current 710 sensor, can be processed to further generate an analysis of the degree of deposition at different locations within the component. This processing can be based on the known or estimated relationship between the degree of deposition and the feedback signal, for example. FIG. 8 shows an example analysis of a two-dimensional map 801 of the current measured by the current sensor 223a. In this map 801, brighter pixels correspond to higher measured currents. The analysis of step 127 of the current map 801 can, for example, use the threshold operation 802 to select pixels that exceed a specified current intensity to generate a preliminary deposition analysis 128. This example deposition analysis 128 is a binary image, where white pixels show higher deposition areas and black pixels show lower deposition areas. The threshold operation 802 is only illustrative; other embodiments can use any suitable method to analyze the feedback signal of the map 801 to generate the sedimentation analysis 128. This deposition analysis 128 can then be used to determine whether the deposition of the layer 129 is complete, and to determine whether any program parameters need to be modified for subsequent layer construction. 9A and 9B show an example analysis of the layer completion degree of the judgment 129, and FIG. 10 shows an example analysis of the program parameter modification of the judgment 130.

圖9A顯示比對沉積分析128與層體目標地圖900以判定層體製造是否完成之例示程序。目標地圖900標明層體中應沉積材料之處,其中黑色像素對應於材料,白色像素對應於無材料。沉積分析128顯示高電流區域,其可表示例如陽極與沉積材料接觸或極為接近處之短路區域。在本發明實施例中,沉積分析128可經進一步處理以估計層體中已經沉積材料之處。例如,可利用任何轉換技術修改沉積分析128之影像,包括但不限於形態濾波、線性或非線性濾波或布林運算。圖9A所示運算901為膨脹運算(其為一形態濾波);此運算藉由在白色像素區域邊界添加像素而將之擴大。結果之修改後地圖911可提供明確顯示何處已有沉積,由於例如接近短路陽極之位置陽極亦可能具有高度沉積。而後可將此修改後之地圖911與目標地圖比對,藉此判定層體估計沉積與所欲沉積之符合程度。運算902首先反轉目標地圖900,使反轉後之目標地圖912與修改後之地圖911之沉積分析皆以白色像素對應於沉積位置。反轉目標地圖912中之白色(「開通」)像素數913表示層體中有多少位置應接受材料沉積。而後修改後之沉積地圖911與反轉後之目標地圖912可在運算920中「AND」;產生之地圖921顯示對應於應有材料沉積(根據目標地圖)及確有材料沉積(根據沉積分析)位置之像素。於地圖921中白色(「開通」)像素數922可繼而比對於所欲「開通」像素數913;上述數值之比率923即為該層完成程度之百分比。在本發明實施例中,此完成百分率可比對於一閾值,當達成或超過閾值百分比時,即表示該層完成。圖9A所示之運算901、902及920僅屬說明性質;其他實施例可運用任何轉換或運算處理沉積分析128或目標地圖900,以判定層體是否製造完成,包括但不限於形態學運算,例如運算901,或布林運算,例如運算902及運算920。FIG. 9A shows an exemplary procedure for comparing the deposition analysis 128 with the layer target map 900 to determine whether the layer has been manufactured. The target map 900 indicates where the material should be deposited in the layer, where the black pixels correspond to the material, and the white pixels correspond to no material. The deposition analysis 128 shows a high current area, which can represent, for example, a short circuit area where the anode is in contact with or in close proximity to the deposition material. In an embodiment of the invention, the deposition analysis 128 may be further processed to estimate where material has been deposited in the layer. For example, any conversion technique can be used to modify the image of the deposition analysis 128, including but not limited to morphological filtering, linear or non-linear filtering, or Bollinger operations. The operation 901 shown in FIG. 9A is an expansion operation (which is a morphological filter); this operation expands the white pixel region by adding pixels to the boundary. As a result, the revised map 911 can provide a clear indication of where there has been deposition, as the anode may also have a high degree of deposition due to, for example, a location close to the short-circuited anode. Then, the revised map 911 can be compared with the target map to determine the degree of conformity between the estimated deposition of the layer body and the desired deposition. Operation 902 first inverts the target map 900, so that the deposition analysis of the inverted target map 912 and the modified map 911 both correspond to the deposition location with white pixels. The number of white ("open") pixels 913 in the reversal target map 912 indicates how many positions in the layer body should accept material deposition. Then the modified deposition map 911 and the inverted target map 912 can be ANDed in operation 920; the generated map 921 shows the corresponding material deposition (according to the target map) and the actual material deposition (according to the deposition analysis) The pixel of the position. The number of white ("opened") pixels 922 in the map 921 can then be compared to the desired number of "opened" pixels 913; the ratio 923 of the above values is the percentage of the level of completion of the layer. In the embodiment of the present invention, the completion percentage is comparable to a threshold, and when the threshold percentage is reached or exceeded, it means that the layer is completed. The calculations 901, 902, and 920 shown in FIG. 9A are only illustrative; other embodiments can use any transformation or calculation to process the deposition analysis 128 or the target map 900 to determine whether the layer has been manufactured, including but not limited to morphological calculations. For example, operation 901, or Boolean operation, such as operation 902 and operation 920.

圖9A方法之限制在於可能出現一層之整體完成百分比高,但特定子區域完成度卻偏低之情況。在某些情況下,一層之所有子區域皆必須達到高完成度百分比。圖9B顯示一圖9A方法之例示延伸,其係將完成閾值套用於子區域。在本發明實施例中,可利用任何所欲方式定義子區域。例如,可將層體劃分為具有任何解析度之規則晶片塊網格,並將完成標準套用於每一晶片塊。圖9B繪示如何將目標地圖劃分為相連組成部分「島嶼」,並將完成標準分別套用於每一島嶼。目標地圖912(圖9A中反轉而使白色像素對應於所欲沉積)具有四個島嶼912a至912d;每一島嶼為相連組成部分,且不同島嶼彼此不連接。修改後之沉積分析地圖911劃分為此等島嶼區域,產生對應於島嶼912a至912d之四組沉積分析。在每一島嶼沉積分析中,白色 (「開通」)像素之百分比表示相關島嶼上沉積之完成程度。而後個別島嶼完成百分比923a至923d可經分析而判定層體是否完成。例如,可對每一島嶼完成百分比套用一閾值,且僅在所有島嶼均達成或超過此閾值時方能判定該層已經完成。在本發明實施例中,不同完成標準可套用於不同島嶼,且僅當每一島嶼符合其各自完成標準時,方能判定整層完成。The limitation of the method in FIG. 9A is that the overall completion percentage of a layer may be high, but the completion of specific sub-regions is low. In some cases, all sub-areas on the first floor must reach a high completion percentage. Figure 9B shows an exemplary extension of the method of Figure 9A, which applies a completion threshold to a sub-region. In the embodiment of the present invention, any desired method can be used to define the sub-regions. For example, the layer body can be divided into regular wafer block grids with any resolution, and the completion standard can be applied to each wafer block. Figure 9B shows how to divide the target map into connected components "islands", and apply the completion criteria to each island separately. The target map 912 (inverted in FIG. 9A so that the white pixels correspond to the desired deposition) has four islands 912a to 912d; each island is a connected component, and different islands are not connected to each other. The revised sedimentary analysis map 911 is divided into these island areas, and four sets of sedimentary analysis corresponding to islands 912a to 912d are generated. In each island sedimentation analysis, the percentage of white ("open") pixels indicates the degree of completion of sedimentation on the relevant island. Then, the completion percentages of individual islands 923a to 923d can be analyzed to determine whether the layer is completed. For example, a threshold can be applied to the completion percentage of each island, and only when all islands reach or exceed the threshold can it be determined that the layer has been completed. In the embodiment of the present invention, different completion standards can be applied to different islands, and only when each island meets its respective completion standards, the entire layer can be determined to be completed.

在一或多個實施例中,可以其他因素配合或取代所欲沉積像素完成百分比而做為判定層體或個別島嶼完成與否之標準。例如,若一層體或島嶼中所有或特定數量或片段之待沉積像素處於一或多個沉積像素之指定閾值距離內時,可判定該層體或島嶼已經完成。應有材料沉積之像素組及已有材料沉積之像素組(至所欲完成程度)可透過上述方式判定。在某些實施例中,沉積經過時間、用於沉積之物料、整體電流及/或電極間之阻抗可用於判定層體是否完成。In one or more embodiments, other factors can be used in conjunction with or instead of the completion percentage of the desired deposited pixel to be used as the criterion for determining whether the layer or individual island is completed. For example, if all or a specific number or segment of pixels to be deposited in a layer or island are within a specified threshold distance of one or more deposition pixels, it can be determined that the layer or island has been completed. The pixel group that should have material deposition and the pixel group that has material deposition (to the desired degree of completion) can be determined by the above method. In some embodiments, the elapsed time of the deposition, the material used for the deposition, the overall current and/or the impedance between the electrodes can be used to determine whether the layer is completed.

圖10顯示之範例說明如何在建構層體之過程中利用沉積分析128調整程序參數,直到判定層體完成為止。關於完成分析,首先可使用任何種類之過濾或運算對沉積分析128進行轉換。圖10顯示在沉積分析128中運用腐蝕運算1001產生修改後之地圖1002之沉積分析。腐蝕運算1001屬於形態濾波範例,其藉由移除區域邊界之像素而縮小白色像素區域。因此產生之地圖1002可就於已有沉積之處提供較為保守之估計。腐蝕運算1001僅屬說明性質;其他實施例可對沉積分析128運用任何種類之轉換,包括但不限於,形態濾波、線性或非線性濾波或布林運算。修改後之地圖1002可在運算1003中反轉,產生地圖1004,其中黑色像素對應於沉積之腐蝕區域,而白色像素對應於可能缺乏充分沉積之位置。此地圖1004可隨後與反轉之目標地圖912「AND」,產生可用於修改層體後續建構程序參數之地圖1006。於地圖1006中,白色(「開通」)像素對應於應有沉積但尚未充分完成之位置。因而此地圖1006可用於設定陽極陣列201中陽極之輸出1007,俾使對應於地圖1006中「開通」像素之陽極繼續進行沉積。陽極輸出之設定可經由例如設定陽極電流1011、設定陽極電壓1012或設定陽極工作週期1013,或使用此等方法之組合。The example shown in FIG. 10 illustrates how to use the deposition analysis 128 to adjust the program parameters in the process of constructing the layer body until the layer body is determined to be completed. Regarding the completion of the analysis, the sedimentation analysis 128 can be converted first using any kind of filtering or calculation. FIG. 10 shows the deposition analysis of the modified map 1002 generated by the corrosion operation 1001 in the deposition analysis 128. The erosion operation 1001 is an example of morphological filtering, which reduces the white pixel area by removing the pixels at the boundary of the area. Therefore, the generated map 1002 can provide a more conservative estimate of the existing deposits. The corrosion operation 1001 is merely illustrative; other embodiments may apply any type of transformation to the deposition analysis 128, including but not limited to morphological filtering, linear or non-linear filtering, or Bollinger operations. The modified map 1002 can be inverted in operation 1003 to produce a map 1004 in which the black pixels correspond to the corrosion area of the deposition, and the white pixels correspond to the locations that may lack sufficient deposition. This map 1004 can then be "ANDed" with the inverted target map 912 to generate a map 1006 that can be used to modify the parameters of the subsequent construction of the layer. In the map 1006, the white ("opened") pixels correspond to locations where deposits should be made but not yet fully completed. Therefore, this map 1006 can be used to set the output 1007 of the anodes in the anode array 201 so that the anodes corresponding to the "on" pixels in the map 1006 continue to be deposited. The anode output can be set by, for example, setting anode current 1011, setting anode voltage 1012, setting anode duty cycle 1013, or using a combination of these methods.

圖10繪示為陽極產生二元控制訊號之回授控制,例如地圖1006。而後可基於此等控制訊號開通或關斷陽極。在本發明實施例中,陽極控制(或任何其他程序參數之控制)可利用非二元控制訊號;例如,陽極電流可基於回授訊號之分析,自零持續變化至最大值。FIG. 10 illustrates the feedback control of the binary control signal generated by the anode, such as a map 1006. The anode can then be turned on or off based on these control signals. In the embodiment of the present invention, the anode control (or the control of any other program parameters) can utilize non-binary control signals; for example, the anode current can be continuously changed from zero to the maximum value based on the analysis of the feedback signal.

雖然使用高解析度陽極陣列201可提供沉積材料之精細控制,但在某些情況下,陰極上之材料沉積圖案可能並非準確對應於陽極輸出之圖案。因此,一或多個實施例可藉由預先處理目標地圖,處理此種效應,達成調整陽極輸出之作用。為說明之便,圖11A、11B、11C及12A以一維陽極陣列模型解釋上述程序。類似概念可在一或多個實施例中套用於二維陽極陣列;二維範例顯示於圖12B。Although the use of the high-resolution anode array 201 can provide fine control of the deposited material, in some cases, the material deposition pattern on the cathode may not exactly correspond to the pattern of the anode output. Therefore, one or more embodiments can deal with this effect by pre-processing the target map to achieve the effect of adjusting the anode output. For the convenience of explanation, FIGS. 11A, 11B, 11C, and 12A use a one-dimensional anode array model to explain the above procedure. Similar concepts can be applied to a two-dimensional anode array in one or more embodiments; a two-dimensional example is shown in Figure 12B.

圖11A顯示當陽極陣列201中僅有單一陽極1101通電時陰極220上之沉積1111情況。在某些環境中,材料可沉積於陰極上並非正對通電陽極之位置。例如,沉積1111可構成其中心正對通電陽極之約略高斯圖案,並自中心側向朝外擴張。圖11B顯示多個陽極1101、1102及1103通電時之例示沉積圖案1112。在此情境中,沉積圖案可大致為每一個別陽極1101、1102及1103之沉積圖案1112總和。詳言之,於圖11B中,由於來自全部三個陽極1101、1102及1103之積層效應,沉積之中心(正對陽極1101)處高於邊緣。FIG. 11A shows the deposition 1111 on the cathode 220 when only a single anode 1101 in the anode array 201 is energized. In some environments, the material can be deposited on the cathode not directly opposite the energized anode. For example, the deposition 1111 can form an approximately Gaussian pattern whose center is facing the energized anode and expands outward from the center side. FIG. 11B shows an exemplary deposition pattern 1112 when a plurality of anodes 1101, 1102, and 1103 are energized. In this scenario, the deposition pattern may be roughly the sum of the deposition patterns 1112 of each individual anode 1101, 1102, and 1103. In detail, in FIG. 11B, due to the layering effect from all three anodes 1101, 1102, and 1103, the center of the deposition (opposite the anode 1101) is higher than the edge.

若將個別陽極之沉積圖案積層結合,圖11A及11B所示現象之總體效應會經由卷積1141而以描述單一陽極點源之沉積擴散之點擴散函數1140改變陽極輸出之圖案。圖11C顯示陽極電流之例示圖案1130,其於自邊界1121至1122之範圍內維持不變,而在此範圍外為零。由於卷積1141之故,實際沉積厚度並不符合圖案1130之輸入形狀,而是產生中心累積較高且某些沉積延伸超過邊界1121及1122之形狀1150。圖11A及11B所示之效應使陽極電流圖案1130之有效尖稜角平滑化。因此一或多個實施例可修改陽極電流以對應此卷積1141或其他造成沉積圖案變形之效應。圖12A顯示可用於一或多個實施例中之例示方案。基於將層體目標厚度描述為位置函數之目標地圖1201,建造規劃程序可執行一去轉換1210之卷積或其他轉換,以反轉圖11A至11C所示之變形效應。例如,邊界1121與1122間厚度固定之目標地圖1201經去卷積而成為陽極電流圖案1211。為補償沉積點擴散函數1140之分散效應,例示陽極電流邊緣數值1212較高,且某些在規則圖案中央區域之陽極例如1214可完全關斷。此外,某些陽極,例如陽極1213,即便超出邊界1121及1122,仍可能具有非零電流。上述效應僅屬說明性質;其他實施例可產生任何所欲陽極電流圖案1211以達成目標地圖1201所欲層厚度圖案。轉換1210可包括任何去卷積方法或任何其他函數轉換或影像處理方法。此等轉換可基於任何測量或沉積程序模型,包括例如描述陽極電流1011如何映射於沉積圖案之點擴散函數1140。If the deposition patterns of individual anodes are combined in layers, the overall effect of the phenomenon shown in FIGS. 11A and 11B will be changed by the point spread function 1140 describing the deposition diffusion of a single anode point source through convolution 1141 to change the anode output pattern. FIG. 11C shows an exemplary pattern 1130 of anode current, which remains unchanged from the boundary 1121 to 1122, and is zero outside this range. Due to the convolution 1141, the actual deposition thickness does not conform to the input shape of the pattern 1130, but produces a shape 1150 with a higher center accumulation and some depositions extending beyond the boundaries 1121 and 1122. The effect shown in FIGS. 11A and 11B smoothes the effective sharp corners of the anode current pattern 1130. Therefore, one or more embodiments can modify the anode current to correspond to this convolution 1141 or other effects that cause deformation of the deposition pattern. Figure 12A shows an exemplary solution that can be used in one or more embodiments. Based on the target map 1201 that describes the target thickness of the layer as a position function, the construction planning program can perform a convolution or other transformation to transform 1210 to reverse the deformation effect shown in FIGS. 11A to 11C. For example, the target map 1201 with a fixed thickness between the boundaries 1121 and 1122 is deconvoluted to become the anode current pattern 1211. To compensate for the spreading effect of the deposition point spread function 1140, it is illustrated that the anode current edge value 1212 is relatively high, and some anodes in the central area of the regular pattern, such as 1214, can be completely turned off. In addition, some anodes, such as anode 1213, may still have non-zero current even if it exceeds the boundaries 1121 and 1122. The above effects are only illustrative; other embodiments can generate any desired anode current pattern 1211 to achieve the desired layer thickness pattern of the target map 1201. The conversion 1210 may include any deconvolution method or any other function conversion or image processing method. These conversions can be based on any measurement or deposition process model, including, for example, a point spread function 1140 that describes how the anode current 1011 maps to the deposition pattern.

圖12B顯示目標地圖1220轉換為所欲陽極電流圖案之二維範例。目標地圖1220顯示一部件建造中特定層體之所欲沉積區域(黑色)。如上所述,例如包括去卷積或任何其他類型影像處理在內之轉換1210可應用於此目標地圖1220以產生一圖案1230,顯示為達成所欲沉積而產生之陽極電流圖案。在此範例中,係將對應於具有所欲沉積陽極之陽極關斷,並將沉積區域邊緣及稜角周圍之額外陽極(顯示為交叉陰影線區域)開通。例如,每一外緣周圍之邊緣陽極開通,例如沿頂緣延伸之陽極1231,且稜角周圍之額外陽極亦開通,例如右上角周圍之陽極1232。開通上述額外邊緣及角落陽極有助於塑造電流場形狀,以使對應目標地圖1220邊緣及角落處之材料沉積更加均勻。FIG. 12B shows a two-dimensional example of the target map 1220 converted into a desired anode current pattern. The target map 1220 shows the desired deposition area (black) of a specific layer in the construction of a part. As described above, for example, a transformation 1210 including deconvolution or any other type of image processing can be applied to the target map 1220 to generate a pattern 1230 showing the anode current pattern generated to achieve the desired deposition. In this example, the anode corresponding to the anode to be deposited is turned off, and the additional anodes around the edges and corners of the deposition area (shown as cross-hatched areas) are turned on. For example, the edge anodes around each outer edge are opened, such as the anode 1231 extending along the top edge, and the additional anodes around the corners are also opened, such as the anode 1232 around the upper right corner. Opening the above-mentioned extra edge and corner anodes helps to shape the current field, so that the material deposition at the edges and corners of the corresponding target map 1220 is more uniform.

一或多個實施例亦可按照預先設定或適應性模式而隨時間改變陽極電流,如圖13所示。例如,在一或多個實施例中,可在製造一層之過程中先後開通不同小組之陽極。若陽極在建構一層之全程中輸出恆定電流,電解質中之金屬離子容易耗盡,而如此交替則能夠在此時發揮補償作用,且亦可防止電解質中產生氣泡。於圖13所示範例中,係於目標地圖112e之方形中心區域1301內沉積材料。本發明之實施例可自棋盤狀區域1301內之兩個子區域1311及1312交替提供電流,而非自對應於區域1301之所有陽極不斷發出電流。在階段1321中,區域1311內之陽極發出電流1331,區域1312內之陽極關斷;在階段1322中,區域1311內之陽極關斷,區域1312內之陽極發出電流1332。此交替可使電解質中之離子1310擴散入鄰近關斷陽極之區域,避免此等區域內之離子耗盡。區域1311及1312之棋盤圖案僅屬說明性質;其他實施例可將陽極劃分為任何數量且具有任何形狀及尺寸之區域,且可依照任何所欲工作週期以任何模式將此等區域之陽極開通或關斷。One or more embodiments can also change the anode current over time according to a preset or adaptive mode, as shown in FIG. 13. For example, in one or more embodiments, different groups of anodes can be turned on sequentially during the process of manufacturing a layer. If the anode outputs a constant current during the whole process of constructing a layer, the metal ions in the electrolyte are easily depleted, and such alternation can play a compensation role at this time, and can also prevent the formation of bubbles in the electrolyte. In the example shown in FIG. 13, the material is deposited in the square central area 1301 of the target map 112e. The embodiment of the present invention can alternately provide current from the two sub-areas 1311 and 1312 in the checkerboard-shaped area 1301, instead of continuously emitting current from all anodes corresponding to the area 1301. In stage 1321, the anodes in area 1311 emit current 1331, and the anodes in area 1312 are turned off; in stage 1322, the anodes in area 1311 are turned off, and the anodes in area 1312 emit current 1332. This alternation allows the ions 1310 in the electrolyte to diffuse into the area adjacent to the shut-off anode, avoiding the depletion of ions in these areas. The checkerboard patterns of areas 1311 and 1312 are only illustrative; other embodiments can divide the anodes into any number of areas with any shape and size, and the anodes in these areas can be opened or opened in any pattern according to any desired duty cycle. Shut down.

圖14顯示在一或多個實施例中可於製程期間執行之例示維護動作。此等動作可例如與沉積交錯,或可於兩個層體製造之間執行。圖中顯示之動作僅屬說明性質;其他實施例可於製程中之任何時點執行任何所欲維護活動。圖14顯示製造過程中可能需要進行維護活動之三種問題。第一,陽極陣列201中之陽極可能腐蝕,例如陽極1401,因此需要補充或重新處理表面。第二,薄膜1402可能形成於陽極上,減損陽極在陰極220上形成沉積之效率。第三,陽極陣列201與沉積材料230間之電解質中可能產生氣泡1403。Figure 14 shows exemplary maintenance actions that can be performed during the manufacturing process in one or more embodiments. These actions can be interleaved with deposition, for example, or can be performed between the production of two layers. The actions shown in the figure are merely illustrative; other embodiments can perform any desired maintenance activities at any point in the manufacturing process. Figure 14 shows the three problems that may require maintenance activities during the manufacturing process. First, the anodes in the anode array 201 may corrode, such as the anode 1401, so the surface needs to be supplemented or re-treated. Second, the thin film 1402 may be formed on the anode, impairing the efficiency of the formation and deposition of the anode on the cathode 220. Third, bubbles 1403 may be generated in the electrolyte between the anode array 201 and the deposition material 230.

隨使用時間延長,即便是大多以非可溶性材料建構而成,例如陽極1401等陽極仍可能發生腐蝕。本發明之實施例可定期或依需要使用輔助陽極1410反轉腐蝕。此時可暫停沉積程序,並使用開關1411及1412反轉電源供應器221,使得陽極陣列暫時作用為陰極220,而輔助陽極1410作用為陽極。來自輔助陽極1410之電流可使得材料1413自輔助陽極1410流向陽極陣列201中發生腐蝕之陽極。輔助陽極1410可為以例如鉑等惰性材料2112所構成之大塊陽極。輔助陽極1410可由用於電沉積之金屬所構成,例如銅;此金屬可溶解後附著於陽極陣列201之陽極上,而不耗用電解質溶液210中之金屬。當開關1411及1412再次反轉時,覆蓋於陽極陣列201上之金屬轉而覆蓋於陰極220之上。With the prolonged use time, even if most of them are constructed of insoluble materials, anodes such as the anode 1401 may still be corroded. Embodiments of the present invention may use auxiliary anode 1410 to reverse corrosion periodically or as needed. At this time, the deposition process can be suspended, and the switches 1411 and 1412 are used to reverse the power supply 221, so that the anode array temporarily functions as the cathode 220, and the auxiliary anode 1410 functions as the anode. The current from the auxiliary anode 1410 can cause the material 1413 to flow from the auxiliary anode 1410 to the anode in the anode array 201 where corrosion occurs. The auxiliary anode 1410 may be a bulk anode made of an inert material 2112 such as platinum. The auxiliary anode 1410 can be made of a metal used for electrodeposition, such as copper; this metal can be dissolved and attached to the anode of the anode array 201 without consuming the metal in the electrolyte solution 210. When the switches 1411 and 1412 are reversed again, the metal covering the anode array 201 turns to cover the cathode 220.

在某些情況下,目標沉積材料(例如銅電解質槽中之銅)可能在電極陣列表面形成一層薄膜1402,並橋接於多個沉積電極之間,可能影響電極個別定址效果。例如當一群相鄰陽極之電流異常飆高時,自回授訊號中可探知有此薄膜1402存在。透過例如使陰極220遠離陽極陣列201並活化受薄膜1402所覆蓋之陽極等方式可去除所述薄膜1402。此動作可溶解薄膜1402且不會在陰極220上產生意外沉積。In some cases, the target deposition material (for example, copper in a copper electrolyte tank) may form a thin film 1402 on the surface of the electrode array and bridge between multiple deposition electrodes, which may affect the individual addressing effect of the electrodes. For example, when the current of a group of adjacent anodes is abnormally high, the existence of this thin film 1402 can be detected in the self-feedback signal. The film 1402 can be removed by, for example, moving the cathode 220 away from the anode array 201 and activating the anode covered by the film 1402. This action can dissolve the thin film 1402 and will not cause accidental deposition on the cathode 220.

在電解作用期間,陽極陣列201與部件230間之空間內可能形成氣泡1403。去除氣泡之方式包括例如以泵浦或攪拌器等設備操控或改變電解質之流動1420,或於電解質中導入震動1421以消除氣泡1403。所述震動1421之導入方式可為以振盪器接觸電解質,或震動陰極220、陽極陣列201或反應室。流體之流動操控亦可包括刻意增加建造物與陽極陣列201間之距離,以加大流量並/或去除氣泡1403,同時保持陽極通電或斷電直到流動操控完成為止。During the electrolysis, air bubbles 1403 may form in the space between the anode array 201 and the component 230. Ways to remove air bubbles include, for example, using a pump or agitator to control or change the flow of the electrolyte 1420, or introduce vibration 1421 into the electrolyte to eliminate air bubbles 1403. The introduction method of the vibration 1421 can be to contact the electrolyte with an oscillator, or to vibrate the cathode 220, the anode array 201 or the reaction chamber. The fluid flow control can also include deliberately increasing the distance between the structure and the anode array 201 to increase the flow rate and/or remove air bubbles 1403, while keeping the anode energized or de-energized until the flow control is completed.

在一或多個實施例中,可將於建造部件過程中所測得或產生之全部或部分回授訊號、控制參數及沉積分析保留為品質控制紀錄。此資料可用於多種目的,包括例如促進或省略部件檢查、支援部件或製程認證及發生部件故障或部件性能問題時之事後分析。除提供特定製造步驟之細節追蹤及各部件之參數外,上述品質控制資料可跨部件、批次或設施累積,並用於統計程序控制及持續程序改良。例如,可將部件現場性能資料(例如故障率或部件使用壽命)連接於部件品質控制資料,以確認程序參數與部件性能間之關聯;此等關聯可用於改良未來部件建造程序。在本發明實施例中,可運用機器學習技術或其他人工智慧技術確認建造紀錄資訊與部件性能間之關聯。例如,大量部件及其相關品質控制紀錄之分析可能顯示特定類型之層體之較低電流密度或許是部件故障率較高之原因所在;製造商可利用此類資訊調整建造程序,以降低未來故障率。當建造參數與部件性能間之關係確認後,可利用部件建造品質資訊資料庫預測先前製造部件之故障情況,以利召回或提前更換。In one or more embodiments, all or part of the feedback signals, control parameters, and deposition analysis measured or generated during the construction of the component may be retained as a quality control record. This data can be used for a variety of purposes, including, for example, facilitating or omitting component inspections, supporting component or process certification, and post-analysis when component failures or component performance problems occur. In addition to providing detailed tracking of specific manufacturing steps and the parameters of each component, the above-mentioned quality control data can be accumulated across components, batches or facilities, and used for statistical process control and continuous process improvement. For example, component field performance data (such as failure rate or component service life) can be connected to component quality control data to confirm the correlation between process parameters and component performance; these correlations can be used to improve future component construction procedures. In the embodiment of the present invention, machine learning technology or other artificial intelligence technology can be used to confirm the correlation between construction record information and component performance. For example, analysis of a large number of parts and their related quality control records may show that the lower current density of a particular type of layer may be the reason for the higher failure rate of the parts; manufacturers can use this information to adjust the construction process to reduce future failures Rate. When the relationship between construction parameters and component performance is confirmed, the component construction quality information database can be used to predict the failure of previously manufactured components to facilitate recall or early replacement.

圖15顯示使用本發明實施例製造之例示部件1501。使用上述技術之製程回授控制有利於此完成部件1501達成極佳解析度及品質。Figure 15 shows an exemplary component 1501 manufactured using an embodiment of the present invention. The process feedback control using the above-mentioned technology is conducive to achieving excellent resolution and quality of the finished part 1501.

在一或多個實施例中,可利用例如上述製程為例如矽晶圓等晶板添加互連特徵、散熱片或類似結構。所述互連結構可稱為例如「晶圓凸塊」或「柱體」。精準成形之導電互連結構乃是半導體及電子封裝中之關鍵組成部分。由於技術要求增加,各區域互連密度隨之增加,或需要在封裝內設置更多且更細長密集之特徵。電化學積層製造較本技藝中目前已知程序更能夠建構有效之互連結構。In one or more embodiments, the process described above may be used to add interconnect features, heat sinks, or similar structures to wafers such as silicon wafers. The interconnect structure may be called, for example, "wafer bumps" or "pillars." Precisely formed conductive interconnect structures are a key component of semiconductor and electronic packaging. Due to the increase in technical requirements, the interconnection density of each area increases, or more and more slender and dense features need to be placed in the package. Electrochemical build-up manufacturing is more capable of constructing effective interconnection structures than currently known procedures in the art.

傳統晶圓凸塊製程所涉步驟多, 較為複雜。首先要沉積具有傳導性之薄膜,通常為金屬材質,稱為「晶種」層,其次為應用、暴露並建立光阻以定義凸塊設置位置,而後透過電沉積步驟將材料沉積於由光阻所定義之開口中。最後去除光阻及晶種層,在基板上留下獨立電性絕緣結構。The traditional wafer bumping process involves many steps and is relatively complicated. First, a conductive thin film is deposited, usually a metal material, called a "seed" layer. Second, a photoresist is applied, exposed, and established to define the bump placement position. Then, the material is deposited on the photoresist through an electrodeposition step. In the defined opening. Finally, the photoresist and the seed layer are removed, leaving an independent electrical insulating structure on the substrate.

由於光阻定義區域及沉積凸塊材料側壁,凸塊形狀及間隔之主要限制取決於光阻能力,包括光阻能夠分辨之長寬比(垂直特徵維度相對於水平特徵維度)、最小直徑、最大整體高度及相鄰凸塊間隔。光阻式處理之另一問題在於,每新增一種連接圖案便必須製作全新遮罩。因此,無需仰賴或減少仰賴光阻步驟之晶圓凸塊製作程序不僅有助於降低製造成本及提升時間效率,亦有助於達成更佳之互連結構性能。Due to the defined area of the photoresist and the sidewalls of the deposited bump material, the main limitations of the shape and spacing of the bumps depend on the photoresist ability, including the aspect ratio (vertical feature dimension relative to the horizontal feature dimension) that the photoresist can distinguish, minimum diameter, and maximum Overall height and spacing between adjacent bumps. Another problem with photoresist processing is that a new mask must be made every time a new connection pattern is added. Therefore, the wafer bumping process that does not need to rely on or reduce the photoresist step not only helps to reduce manufacturing costs and improve time efficiency, but also helps to achieve better interconnect structure performance.

圖16繪示使用電化學積層製造增設晶圓凸塊之技術,其可提供例如上述優點。一目的係於晶板1601上增設晶圓凸塊或類似結構,所述晶板1601可例如為矽晶圓或任何可供設置電路或組件之基板。晶板1601可為任何大小或形狀,且可由任何材料製成。其可包含一或多個晶片塊,例如例示晶片塊1602;每一晶片塊可例如包含一或多個電路,或絕緣電子或電氣組件。晶板通常係於一或多個表面增設傳導結構。此等結構可為例如具有導電性質、導熱性質或兩者兼具。其功能可為,例如,用於連接其他電路或裝置,作為幫助晶板1601上電路散熱之散熱片或執行例如對齊或附加等機械功能。為建構此類結構,晶板1601可連接如圖2所示裝置中之陰極220。自沉積陽極陣列201中之陽極通過電解質溶液210之電流接觸晶板表面,沉積產生互連結構,例如凸塊1603。來自每一陽極之電流量在受控運作下以精確圖案沉積連接結構材料。完成之晶板1611可在整個晶板上包含多個互連結構。晶板1611上例示之完成晶片塊1612具有五個晶圓凸塊,各連接於在晶片塊內部或鄰近處之電路1613上之對應連接點;例如,凸塊1603係連接於電路1613之連接點1614。FIG. 16 shows a technique of using electrochemical layered manufacturing to add wafer bumps, which can provide, for example, the above-mentioned advantages. One purpose is to add wafer bumps or similar structures on the wafer 1601. The wafer 1601 can be, for example, a silicon wafer or any substrate on which circuits or components can be provided. The crystal plate 1601 can be of any size or shape, and can be made of any material. It may include one or more wafer blocks, such as the exemplified wafer block 1602; each wafer block may, for example, include one or more circuits, or insulated electronic or electrical components. The crystal plate usually adds conductive structures on one or more surfaces. These structures can have electrical conductivity, thermal conductivity, or both, for example. Its function can be, for example, used to connect to other circuits or devices, serve as a heat sink to help the circuit on the wafer 1601 dissipate heat, or perform mechanical functions such as alignment or addition. To construct such a structure, the wafer 1601 can be connected to the cathode 220 in the device shown in FIG. 2. The anodes in the self-deposited anode array 201 contact the surface of the wafer through the current of the electrolyte solution 210, and the interconnection structure, such as bump 1603, is generated by deposition. The amount of current from each anode deposits the connection structure material in a precise pattern under controlled operation. The completed wafer 1611 may include multiple interconnect structures on the entire wafer. The completed chip block 1612 illustrated on the wafer 1611 has five wafer bumps, each of which is connected to a corresponding connection point on the circuit 1613 inside or adjacent to the chip block; for example, the bump 1603 is connected to the connection point of the circuit 1613 1614.

圖17顯示一或多個實施例中可用於在晶板上製作互連結構或類似特徵之例示步驟流程圖。於步驟1701,取得晶板;晶板可包含一或多個晶片塊,各包含一或多個連接點。晶板可具有一導電晶種層,其可例如沉積於晶板之表面。於步驟1702,晶板耦接於一電源供應器(例如經由附加裝置連接於圖16之陰極220);例如,此附加裝置可產生與晶板導電晶種層之電性連接。於步驟1703,晶板表面,例如晶種層表面,置入並接觸電解質溶液210。於步驟1704,晶板準確對齊於陽極陣列201;此對齊可藉由調整晶板及/或陽極陣列201而設定兩者間之相對位置及方向。於步驟1705,電流自陽極陣列201中陽極通過電解質以建構互連特徵。Figure 17 shows a flowchart of exemplary steps that can be used to fabricate interconnect structures or similar features on a wafer in one or more embodiments. In step 1701, a wafer is obtained; the wafer may include one or more wafer blocks, each including one or more connection points. The crystal plate may have a conductive seed layer, which may be deposited on the surface of the crystal plate, for example. In step 1702, the wafer is coupled to a power supply (for example, connected to the cathode 220 in FIG. 16 via an additional device); for example, the additional device can be electrically connected to the conductive seed layer of the wafer. In step 1703, the surface of the crystal plate, such as the surface of the seed layer, is placed in and in contact with the electrolyte solution 210. In step 1704, the crystal plate is accurately aligned with the anode array 201; this alignment can be adjusted by adjusting the crystal plate and/or the anode array 201 to set the relative position and direction between the two. In step 1705, current flows from the anodes in the anode array 201 through the electrolyte to construct interconnection features.

步驟1705可逐層建構特徵,如上所述。層體可為任何高度。本案發明人發現,層體高度較小時沉積品質較佳,且電鍍所需之電壓及電流密度較小。在本發明一或多個實施例中所使用之例示層體高度為5微米以下;其他實施例可利用1微米以下層體高度以提升控制及沉積品質。在某些情況下,於初始之數層加高電流密度或陽極電壓,並/或縮短層體高度有助於形成初始沉積侷域化。在某些情況下,於沉積之最終(頂部)數層採用與其他部分不同之參數有助於提升沉積結構側面及頂部之表面品質,具體而言可例如將工作距離增大至超過建造物之其餘部分並減少電流。例如,若建造物之絕大部分每層工作距離為10微米,則在此可增加至25微米以上。如此可以較低侷域化之高品質材料層覆蓋沉積結構。Step 1705 can construct features layer by layer, as described above. The layer body can be any height. The inventor of this case found that the deposition quality is better when the layer height is smaller, and the voltage and current density required for electroplating are smaller. The exemplary layer height used in one or more embodiments of the present invention is less than 5 micrometers; other embodiments may use a layer height of less than 1 micrometer to improve control and deposition quality. In some cases, adding a higher current density or anode voltage to the initial layers and/or shortening the height of the layer helps to form localization of the initial deposition. In some cases, the use of different parameters in the final (top) layers of the deposition helps to improve the surface quality of the sides and top of the deposition structure. Specifically, the working distance can be increased beyond that of the structure. The rest and reduce the current. For example, if the working distance of each layer of most buildings is 10 microns, it can be increased to more than 25 microns here. In this way, the deposited structure can be covered with a low-localized high-quality material layer.

在步驟1705中,可利用上述回授控制技術對製程進行控制。例示回授控制方法可包括例如測量通過每一陽極之電流。電流測量方式可為在一時間開通一個陽極,並測量通過整個陽極陣列201之電流。或者,在一或多個實施例中,可將電壓感應式數類比至數位轉換器連接於各陽極之表面。當電壓下降時,表示沉積已經接近或接觸到陽極,且陽極處於接地狀態。藉由知悉像素之電阻,可將陽極處之壓降(表面電壓減供應電壓)除以陽極電阻以計算陽極電流。此技術之優點在於無需停止沉積程序即可提供電流映射資料,且能夠提供沉積過程中之實際陽極電流,如此能夠揭露僅於單一時間感應陽極所無法查知之資訊,例如溶液衰減效應。In step 1705, the above feedback control technology can be used to control the manufacturing process. An exemplary feedback control method may include, for example, measuring the current through each anode. The current measurement method can be to turn on one anode at a time and measure the current through the entire anode array 201. Alternatively, in one or more embodiments, a voltage-sensing digital-to-analog-to-digital converter can be connected to the surface of each anode. When the voltage drops, it means that the deposition has approached or touched the anode, and the anode is in a grounded state. By knowing the resistance of the pixel, the voltage drop at the anode (surface voltage minus the supply voltage) can be divided by the anode resistance to calculate the anode current. The advantage of this technology is that it can provide current mapping data without stopping the deposition process, and can provide the actual anode current during the deposition process, so that it can reveal information that cannot be found by sensing the anode at a single time, such as the solution attenuation effect.

基於回授訊號(例如電流或電壓測量值),系統可修改通過個別陽極之電流。可開通或關斷陽極(二元控制),或者改變通過陽極之電流量(連續控制)。於關斷陽極時,可將陽極切換至高阻抗模式(非接地),以停止通過電極之電流。或者,在一或多個實施例中,關斷陽極之方式可為將陽極設為預先指定之電壓,而非進入高阻抗狀態。此電壓可經特別選擇而大於0 V或地端電位,但低於通過陽極電流之電壓。一般而言,電化學系統係由陽極材料、鍍液組成及電極形狀(大小/間隔)之組合所定義而成,並於陽極電壓與系統電流之間產生非線性關係。針對每一電極與鍍液組合,可就上述關係進行特徵分析,以掌握一電極在何種電壓下可維持電位但不致發生顯著電流通過或材料沉積。更具體而言,當用為陽極時,鉑知電壓高於銅。當鉑質電極出現銅膜時,可將電極設置為銅閾值電壓;銅會通過電流並溶入溶液中,但當銅全部去除後,電位將降低至未有顯著電流通過系統之程度。因此可藉由測量陽極或系統電流以分析銅膜之去除何時完成。在某些情況下,即便在陽極上測得短路後,仍可使陽極維持通電一段時間。此方法可能影響沉積頂部表面條件及其所形成之特徵直徑。Based on feedback signals (such as current or voltage measurements), the system can modify the current through individual anodes. The anode can be turned on or off (binary control), or the amount of current passing through the anode can be changed (continuous control). When the anode is turned off, the anode can be switched to high impedance mode (non-grounded) to stop the current passing through the electrode. Alternatively, in one or more embodiments, the way to turn off the anode may be to set the anode to a predetermined voltage instead of entering a high impedance state. This voltage can be specially selected to be greater than 0 V or ground potential, but lower than the voltage through the anode current. Generally speaking, the electrochemical system is defined by the combination of anode material, plating solution composition and electrode shape (size/interval), and a nonlinear relationship is generated between anode voltage and system current. For each electrode and plating solution combination, the above-mentioned relationship can be analyzed with characteristics to grasp the voltage at which an electrode can maintain the potential without significant current flow or material deposition. More specifically, when used as an anode, platinum has a higher voltage than copper. When a copper film appears on the platinum electrode, the electrode can be set to the copper threshold voltage; the copper will pass the current and dissolve into the solution, but when the copper is all removed, the potential will drop to the point where no significant current flows through the system. Therefore, the anode or system current can be measured to analyze when the removal of the copper film is completed. In some cases, even after a short circuit is measured on the anode, the anode can be kept energized for a period of time. This method may affect the top surface conditions of the deposition and the resulting feature diameters.

由於沉積在不同位置可能需要高低不等之電流密度,因此陽極電流可持續變化。例如,在所有陽極均滿足相等電流密度之凸塊陣列中,陣列內部之凸塊建造速度快且較粗,而邊緣處沉積材料較少,角落處更少。基於陽極之位置、大小或其他測量值(若離子在一位置耗盡,甚至可考量即時電流測量),對其賦予不同電壓/電流密度,從而分析並補償上述差異。但在某些實施例中,陽極陣列201中之陽極可能為分批或集體控制。於此等類型之實施例中,每一互連柱體可對應於陽極陣列201中之一陽極。在某些實施例中,對於需要沉積數千個特徵之裝置,對應陽極陣列201包含數千個能夠個別控制之陽極。此設置不同於當陽極數目遠小於特徵數目時之多重陽極應用,例如某些遮罩式系統所採用者。Since the deposition in different locations may require varying current densities, the anode current can continue to vary. For example, in a bump array where all anodes meet the same current density, the bumps inside the array are built faster and thicker, with less deposited material at the edges and less at the corners. Based on the anode's position, size, or other measured values (if ions are exhausted at one location, even real-time current measurement can be considered), different voltage/current densities are assigned to it to analyze and compensate for the above-mentioned differences. However, in some embodiments, the anodes in the anode array 201 may be controlled in batches or collectively. In these types of embodiments, each interconnection pillar may correspond to an anode in the anode array 201. In some embodiments, for devices requiring the deposition of thousands of features, the corresponding anode array 201 includes thousands of anodes that can be individually controlled. This setting is different from multiple anode applications when the number of anodes is much smaller than the number of features, such as those used in some shielded systems.

在某些實施例中,陣列中之數個陽極可經通電而形成連續沉積,例如活化在具有15微米間隔之均勻網格上之3x3 網格陽極,同樣可達成尺寸為45微米 x 45微米之單一方形沉積。或者,可使用各種子像素形狀輔助電場調控,並提升對於沉積成長之控制。例如,可利用中央陽極元件及外部陽極元件補償 沉積自中心至外部直徑之一致性變化。In some embodiments, several anodes in the array can be energized to form continuous deposition. For example, a 3x3 grid anode activated on a uniform grid with 15 micron intervals can also achieve a size of 45 micrometers x 45 micrometers. Single square deposit. Alternatively, various sub-pixel shapes can be used to assist electric field control and improve the control of deposition growth. For example, a central anode element and an external anode element can be used to compensate for the uniform variation of the deposition from the center to the outer diameter.

圖22A、22B及22C繪示三種範例類型之電極配置:圖22A繪示非獨立控制之獨立電極;圖22B繪示非獨立控制之非獨立電極;圖22C繪示獨立控制之獨立電極,其可例如使用一陽極陣列201實施。Figures 22A, 22B and 22C show three example types of electrode configurations: Figure 22A shows a non-independently controlled independent electrode; Figure 22B shows a non-independently controlled non-independent electrode; Figure 22C shows an independently controlled independent electrode, which can For example, an anode array 201 is used for implementation.

在圖22A所示之實施例中,陽極並非電性獨立且亦非獨立控制。三個例示陽極2201、2202及2203,可例如以導體2204製成,並簡單遮蔽開口2205及2206表面。當接近基板時,獨立沉積開始形成,但由於電極並非電性絕緣,當沉積增長至足以在陽極與陰極220間造成短路接觸時,電流優先通過沉積而非通過溶液以形成其餘沉積。藉由在調整陽極/陰極220空隙後仔細注意沉積電流以察知即將發生之接觸,可緩和上述短路效應。In the embodiment shown in FIG. 22A, the anode is not electrically independent and not independently controlled. The three exemplified anodes 2201, 2202, and 2203 can be made of a conductor 2204, for example, and simply cover the surface of the openings 2205 and 2206. When approaching the substrate, independent deposition begins to form, but since the electrode is not electrically insulated, when the deposition grows enough to cause a short-circuit contact between the anode and the cathode 220, the current flows preferentially through the deposition rather than through the solution to form the remaining deposition. By carefully paying attention to the deposition current after adjusting the anode/cathode 220 gap to detect the impending contact, the above-mentioned short-circuit effect can be alleviated.

在圖22B所示實施例中,範例陽極2211、2212及2213為電性獨立,但非獨立控制。電極可利用例如電阻器達成電性獨立,因而與其他陽極隔離。例如,陽極2211、2212及2213係分別經由電阻器2214、2215及2216隔離。當一組陽極活化時,其沉積增長,而當沉積增長並接觸到對應陽極時,絕緣電阻器可限制短路電流通過該陽極,而使電流通過其餘陽極並持續增長其個別沉積。In the embodiment shown in FIG. 22B, the exemplary anodes 2211, 2212, and 2213 are electrically independent, but not independently controlled. The electrodes can be electrically independent using, for example, resistors, so they are isolated from other anodes. For example, the anodes 2211, 2212, and 2213 are separated by resistors 2214, 2215, and 2216, respectively. When a group of anodes is activated, its deposition grows, and when the deposition grows and touches the corresponding anode, the insulating resistor can limit the short-circuit current through the anode, and allow current to pass through the remaining anodes and continue to increase their individual deposition.

於圖22C所示實施例中,範例陽極2221、2222及2223係分別經由對應開關2224、2225及2226而可個別且獨立控制。應知雖然圖中係以刀鋒符號代表開關,但開關實可為不同種類,且可對陽極提供獨立受控之非二元(類比)控制訊號。In the embodiment shown in FIG. 22C, the example anodes 2221, 2222, and 2223 can be individually and independently controlled via corresponding switches 2224, 2225, and 2226, respectively. It should be noted that although the blade symbol is used to represent the switch in the figure, the switch can be of different types and can provide an independently controlled non-binary (analogous) control signal to the anode.

圖18顯示圖16裝置之變化,其可用於一或多個實施例中以建構互連特徵或其他結構。在此例示裝置中,陽極陣列201垂直位於晶板1601及陰極上方。晶板1601定位可採用半導體製造領域已知之方式,包括機械式夾固、真空夾頭等等。在某些情況下,電性連接係通往基板表面。此電性連接可經由夾固組體,或為分離晶片。晶板可事先覆有供電性連接之傳導性「晶種」 層1601a。於圖18所示之範例中,晶板1601係由夾鉗1801a與1802a,及1801b與1802b或夾頭保持定位。任何數量之夾固點可用於一或多個實施例中。夾鉗1801a及1801b之連接器實線與晶板1601導電晶種層1601a之電性接觸,使晶種層耦接於電源供應電路地端,而可做為電沉積之陰極。Figure 18 shows a variation of the device of Figure 16 that can be used in one or more embodiments to construct interconnect features or other structures. In this exemplary device, the anode array 201 is vertically located above the crystal plate 1601 and the cathode. The positioning of the wafer 1601 can be done in a manner known in the semiconductor manufacturing field, including mechanical clamping, vacuum chuck, and so on. In some cases, the electrical connection leads to the surface of the substrate. The electrical connection can be through a clamping assembly or a separate chip. The wafer can be pre-covered with a conductive "seed" layer 1601a for power connection. In the example shown in FIG. 18, the wafer 1601 is held in position by clamps 1801a and 1802a, and 1801b and 1802b or clamps. Any number of clamping points can be used in one or more embodiments. The solid lines of the connectors of the clamps 1801a and 1801b are in electrical contact with the conductive seed layer 1601a of the crystal plate 1601, so that the seed layer is coupled to the ground of the power supply circuit and can be used as a cathode for electrodeposition.

機械式定位系統可用於設定、修改並維持陽極陣列201與晶板1601間之相對位置及方向。在某些實施例中,其可用於在沉積形成之過程中,維持沉積材料表面與陽極陣列201間之固定空隙。其亦可對齊陽極陣列201與晶板1601以確保結構沉積發生於設定位置。可就陽極陣列201相對於晶板1601之方向進行控制,以確保陽極陣列201與晶板1601實質上共平面。機械式定位系統亦可包括感測器223,用以判定陽極陣列201與晶板1601間之相對位置,包括但不限於線性電位計、線性可變差動變壓器(LVDT)、霍爾效應電容式雷射測距儀、雷射及其他類似線性編碼器類型。感測器223可例如利用光學或電性方法檢驗晶板1601相對於陽極陣列201之位置或方向。例如,在某些實施例中,可利用高放大倍率光學系統觀看陽極陣列201與晶板1601上對齊標誌之位置,並判定其相對偏移。在一或多個實施例中,可利用晶板1601上之凹槽或平直段落將裝置對齊於晶板1601,並大致定位晶板1601上之特徵。在某些實施例中,可利用陽極陣列201本身進行測量,以判定陽極與基板之共面性。此等測量可包括例如,利用基板晶種層之電容讀數,或電壓或電流,或陽極與基板間在空氣中或電鍍槽中之A/C阻抗測量值,以判定建造支撐柱在不同位置上與表面之距離。陽極陣列201相對於基板之共面對齊亦極為重要。為確保對齊,可例如利用多個感測器223以分析陽極與陰極220間各處之空隙,例如使用電容感測器或雷射感測器。參考此等空隙測量值,可移動陽極陣列201或基板(或兩者),使各自平面對齊。標準基板大小為300 mm晶圓,若待製造之特徵為直徑30微米且高度小於100微米之柱體,則沉積前對齊可要求空隙測量值及對齊準確度達到約一微米以下。The mechanical positioning system can be used to set, modify and maintain the relative position and direction between the anode array 201 and the wafer 1601. In some embodiments, it can be used to maintain a fixed gap between the surface of the deposition material and the anode array 201 during the deposition process. It can also align the anode array 201 and the crystal plate 1601 to ensure that the structure deposition occurs at a set position. The direction of the anode array 201 relative to the crystal plate 1601 can be controlled to ensure that the anode array 201 and the crystal plate 1601 are substantially coplanar. The mechanical positioning system may also include a sensor 223 to determine the relative position between the anode array 201 and the crystal plate 1601, including but not limited to linear potentiometer, linear variable differential transformer (LVDT), Hall effect capacitive Laser rangefinders, lasers and other similar linear encoder types. The sensor 223 can inspect the position or direction of the crystal plate 1601 relative to the anode array 201 by optical or electrical methods, for example. For example, in some embodiments, a high-magnification optical system can be used to observe the positions of the alignment marks on the anode array 201 and the wafer 1601, and determine their relative offset. In one or more embodiments, the grooves or straight sections on the wafer 1601 can be used to align the device to the wafer 1601 and roughly locate the features on the wafer 1601. In some embodiments, the anode array 201 itself can be used for measurement to determine the coplanarity of the anode and the substrate. These measurements can include, for example, using the capacitance readings of the substrate seed layer, or voltage or current, or the A/C impedance measurement value between the anode and the substrate in the air or in the electroplating bath to determine the different positions of the construction support column The distance from the surface. The coplanar alignment of the anode array 201 with respect to the substrate is also extremely important. To ensure alignment, multiple sensors 223 can be used to analyze the gaps between the anode and cathode 220, for example, capacitive sensors or laser sensors. With reference to these gap measurements, the anode array 201 or the substrate (or both) can be moved to align the respective planes. The standard substrate size is a 300 mm wafer. If the feature to be manufactured is a column with a diameter of 30 μm and a height of less than 100 μm, the pre-deposition alignment may require the gap measurement value and the alignment accuracy to be less than about one micron.

根據本發明實施例,在開始將材料沉積於晶板1601時,可透過初始歸零程序將陽極陣列201與晶板1601放置於適當之開始位置。例如,在一或多個實施例中,所述歸零可利用位置感測器感應陽極與陰極220間之空隙。而後啟動機械式定位系統,將陽極陣列201移近陰極220;當位置感測器開始感應到位移小於指令距離時,系統即判定晶板1601與陽極陣列201已經開始彼此接觸。此測量亦可透過光學方式實現,例如使用雷射、磁性或電性感測器。陽極陣列201與陰極220之共面性亦對沉積之品質及一至性具有絕對影響。類似之歸零技術可於陰極平面上之多個位置實施,配合陽極固定器、陰極固定器或兩者之調整,以確保共面性。According to the embodiment of the present invention, when the material is deposited on the crystal plate 1601, the anode array 201 and the crystal plate 1601 can be placed in appropriate starting positions through the initial zeroing procedure. For example, in one or more embodiments, the zeroing can use a position sensor to sense the gap between the anode and the cathode 220. Then the mechanical positioning system is activated to move the anode array 201 closer to the cathode 220; when the position sensor starts to sense that the displacement is less than the instruction distance, the system determines that the wafer 1601 and the anode array 201 have begun to contact each other. This measurement can also be achieved through optical methods, such as using lasers, magnetic or electrical sensors. The coplanarity of the anode array 201 and the cathode 220 also has an absolute influence on the quality and consistency of the deposition. A similar zero-return technique can be implemented at multiple positions on the cathode plane, with the adjustment of the anode holder, the cathode holder, or both to ensure coplanarity.

機械式定位系統可移動陽極陣列201、晶板1601或兩者。於圖18之例示裝置中,致動器224a可移動陽極陣列201,且致動器224b可移動晶板1601。例如,致動器224b可影響夾鉗1801a/1802a及1801b/1802b之定位,以調整晶板1601之位置或方向。本發明之實施例可僅使用致動器224a及224b中之一者;其他實施例可兼具兩者。陽極陣列201之動作可具有最大六自由度225a,以利將陽極陣列201放置於任何所欲位置及方向。同理,晶板1601之動作亦可具有最大六自由度225b,以利將晶板1601放置於任何所欲位置及方向。致動器224a及224b可受控於處理器222,處理器222取得之感測器223資料可顯示陽極陣列201與晶板1601之相對位置及方向,且可控制致動器224a及224b以將此相對位置及方向設為所欲數值。The mechanical positioning system can move the anode array 201, the crystal plate 1601, or both. In the illustrated device of FIG. 18, the actuator 224a can move the anode array 201, and the actuator 224b can move the wafer 1601. For example, the actuator 224b can affect the positioning of the clamps 1801a/1802a and 1801b/1802b to adjust the position or direction of the wafer 1601. The embodiment of the present invention may use only one of the actuators 224a and 224b; other embodiments may have both. The movement of the anode array 201 can have a maximum of six degrees of freedom 225a, so that the anode array 201 can be placed in any desired position and direction. In the same way, the movement of the crystal plate 1601 can also have the maximum six degrees of freedom 225b, so that the crystal plate 1601 can be placed in any desired position and direction. The actuators 224a and 224b can be controlled by the processor 222. The sensor 223 data obtained by the processor 222 can display the relative position and direction of the anode array 201 and the wafer 1601, and can control the actuators 224a and 224b to Set the relative position and direction to the desired value.

在一或多個實施例中,晶板1601可具有超過陽極陣列201大小之水平延伸。於此等狀況下,所述陽極陣列201可相對於晶板1601水平移動,以於晶板1601之不同子區域中成功建構互連結構。例如,於圖18中,陽極陣列201之水平移位1810可於晶片塊1602特徵建構在晶板1601右側後執行。In one or more embodiments, the crystal plate 1601 may have a horizontal extension that exceeds the size of the anode array 201. Under these conditions, the anode array 201 can move horizontally relative to the wafer 1601 to successfully construct interconnection structures in different sub-regions of the wafer 1601. For example, in FIG. 18, the horizontal shift 1810 of the anode array 201 can be performed after the feature of the wafer block 1602 is constructed on the right side of the wafer 1601.

一或多個實施例亦可包括一流體系統,用以管理電解質溶液210之流動及狀態。例如,於圖18中,流體系統跨陽極陣列201與晶板1601間之空隙自右側抽汲流體1803,且流體於位置1804流出以進行再循環。流體系統可具有例如以下之任一或全部:泵浦、過濾器、溫度控制系統(溫度計、加熱器、冷卻器)、管路、例如酸鹼度及離子濃度感測器(導電率、分光光度計、質譜儀、電感耦合等離子體質譜法、其他)等分析設備、用以吸收不利副產物之淋溶系統以及用於添加電解質槽消耗成分之補充系統。所有系統組成部分可設計為耐受腐蝕性電沉積環境。亦可利用液流或系統組件之動作防止或減少電沉積時之氣泡1403產生。氣泡1403清潔週期可定期啟動,或在測得沉積效率降低時執行,例如全部或個別陽極之測得電流降低,表示缺乏傳導路徑或氣泡1403隔絕陽極。本發明之實施例可利用流體之超音波作用沖走氣泡1403,提供脈衝式液流而非恆定流速。例如,可使超音波換能器接觸流體、陽極及陰極220中之任何組合;其可對容易注入超音波能量,使溶液中之氣泡1403從基板釋出並破碎成較小氣泡,此二態樣有助於促使氣泡1403隨流動溶液離開當前建造區域。一或多個實施例亦可包括震動整個組體以清除氣泡1403。One or more embodiments may also include a fluid system to manage the flow and state of the electrolyte solution 210. For example, in FIG. 18, the fluid system draws fluid 1803 from the right side across the gap between the anode array 201 and the wafer 1601, and the fluid flows out at a position 1804 for recirculation. The fluid system can have, for example, any or all of the following: pumps, filters, temperature control systems (thermometers, heaters, coolers), pipelines, such as pH and ion concentration sensors (conductivity, spectrophotometer, Analysis equipment such as mass spectrometer, inductively coupled plasma mass spectrometry, etc., leaching system used to absorb unfavorable by-products, and supplementary system used to add consumable components in the electrolyte tank. All system components can be designed to withstand corrosive electrodeposition environments. The action of liquid flow or system components can also be used to prevent or reduce the generation of bubbles 1403 during electrodeposition. The bubble 1403 cleaning cycle can be started regularly, or executed when the deposition efficiency is measured to be reduced. For example, the measured current of all or individual anodes is reduced, which means that there is a lack of conduction path or the bubble 1403 isolates the anode. The embodiment of the present invention can use the ultrasonic effect of the fluid to wash away the bubbles 1403, providing a pulsed liquid flow instead of a constant flow rate. For example, the ultrasonic transducer can be contacted with any combination of fluid, anode and cathode 220; it can easily inject ultrasonic energy, so that bubbles 1403 in the solution are released from the substrate and broken into smaller bubbles. This two-state This helps to encourage bubbles 1403 to leave the current build area with the flowing solution. One or more embodiments may also include shaking the entire assembly to remove air bubbles 1403.

圖18所示之液流自流體1803流至位置1804係與晶板1601及陽極陣列201之平面平行。在本發明實施例中,液流可垂直於此等平面,例如經由陽極陣列201及/或陰極220中之流體供應孔;此垂直液流在某些情況下更為有效,且可改善氣泡1403移除。本發明之實施例可包含特徵,例如陽極陣列201表面上與液流對齊之凸脊,用以改善液流並去除氣泡1403。The liquid flow shown in FIG. 18 from the fluid 1803 to the position 1804 is parallel to the plane of the wafer 1601 and the anode array 201. In the embodiment of the present invention, the liquid flow can be perpendicular to these planes, for example, through the fluid supply holes in the anode array 201 and/or the cathode 220; this vertical liquid flow is more effective in some cases and can improve air bubbles 1403 Remove. Embodiments of the present invention may include features such as ridges on the surface of the anode array 201 that are aligned with the liquid flow to improve liquid flow and remove bubbles 1403.

在某些實施例中,可於晶板1601上沉積多種材料。例如,可於一種材料之柱體頂部沉積另一材料,以延伸柱體。一種範例可為銅質沉積上覆銲料(例如錫或錫合金)。當因材料不相容而無法於不同材料使用共用組件時,可藉由將基板移動至配備不同材料之不同機器而達成不同材料之沉積,或使用對每一類型材料具有獨立組件之平行流體處理系統來達成上述目的。例如,每一材料可裝入獨立料槽,且具有獨立溫度控制、過濾、酸鹼值管理等等。此外,可利用流體沖洗系統沖洗共用組件(建造艙、電極陣列),並在替換材料時進行沖洗。此系統可例如為潔淨水供應,沖洗系統後流入集液槽或排水管。在某些實施例中,可使用多個建造艙,例如使晶板1601在建造艙之間移動。In some embodiments, multiple materials can be deposited on the wafer 1601. For example, one material can be deposited on top of a column of another material to extend the column. One example can be copper depositing solder (such as tin or tin alloy). When the common components cannot be used for different materials due to material incompatibility, the deposition of different materials can be achieved by moving the substrate to different machines equipped with different materials, or using parallel fluid processing with independent components for each type of material System to achieve the above purpose. For example, each material can be loaded into an independent trough, with independent temperature control, filtration, pH management, and so on. In addition, a fluid flushing system can be used to flush common components (building chambers, electrode arrays), and flushing when replacing materials. This system can be, for example, a clean water supply, which flows into a sump or drain pipe after flushing the system. In some embodiments, multiple building cabins may be used, for example, the crystal plate 1601 is moved between the building cabins.

包括處理器222之控制系統可收集感測器223資訊,並按照沉積前事先輸入之建造計畫103實施結構沉積。控制系統可接收來自電解質槽監控設備、機械式定位感測器及電鍍電力系統之資料。例如,可於系統層級(整塊)及/或於每一個別陽極,或於某些陽極小組,測量電壓及電流。The control system including the processor 222 can collect the sensor 223 information, and implement the structure deposition according to the construction plan 103 input in advance before deposition. The control system can receive data from the electrolyte tank monitoring equipment, mechanical positioning sensors and electroplating power system. For example, voltage and current can be measured at the system level (monolithic) and/or at each individual anode, or at certain anode groups.

收集而得之資訊可用於自動化建造品質判定程序中。例如,此資訊可用於判定一特徵是否破裂或未能在建造程序中正確形成,並通報製造產量,從而省略後續檢查步驟。The collected information can be used in automated construction quality determination procedures. For example, this information can be used to determine whether a feature is broken or not correctly formed during the construction process, and to report manufacturing output, thereby omitting subsequent inspection steps.

在標準沉積週期中,控制系統可按照建造計畫103設定每一陽極元件之電流及/或電壓,相對於晶板1601定位陽極陣列201,啟用泵浦以推動液流並在個別陽極極系統整體層面測量電流、電壓及沉積時間。當符合特定閾值時,例如計算而得之電荷(隨時間變化之陽極電流),或電流/電壓尖峰顯示短路時,系統可停用特定陽極及/或相對於晶板1601移動陽極陣列201以繼續程序。在建造程序之特定位置,可利用機械性系統刻意增加空隙,以提升流體速度,藉此例如清除產生之氣泡及/或刷新電解質失活建造區域。In a standard deposition cycle, the control system can set the current and/or voltage of each anode element according to the construction plan 103, position the anode array 201 relative to the wafer 1601, activate the pump to drive the liquid flow, and perform the overall operation of the individual anode system. Layer measurement current, voltage and deposition time. When a specific threshold is met, such as the calculated charge (anode current that varies with time), or current/voltage spikes indicating a short circuit, the system can deactivate the specific anode and/or move the anode array 201 relative to the crystal plate 1601 to continue program. At a specific location in the construction process, a mechanical system can be used to deliberately increase the gap to increase the fluid velocity, for example, to clear the generated bubbles and/or refresh the electrolyte inactivation construction area.

在另一實施例中,可加設一陽極,使其與可電鍍槽為流體接觸,用於後續將液槽材料沉積於陽極陣列201上。如此可使陽極陣列201表面自不溶電極材料變為可溶,且有助於減少二次氣體形成、減少不利二次反應並/或延長陽極本身之使用壽命。In another embodiment, an anode may be added to make fluid contact with the electroplatable tank for subsequent deposition of the tank material on the anode array 201. In this way, the surface of the anode array 201 can become soluble from the insoluble electrode material, and can help reduce secondary gas formation, reduce unfavorable secondary reactions, and/or extend the life of the anode itself.

於某些狀況下,若晶板1601停留於電解質溶液210中,電鍍液可能緩慢侵蝕沉積物,造成沉積之破壞。為抵銷上述效應,在一或多個實施例中可使用任何技術維持陰極220上之電位,避免材料損失。第一種技術可利用電行接合於陰極且設置於槽內之犧牲鋅陽極。鋅成分較銅沉積更易溶入溶液,因此可保護沉積物。此電極可與輔助槽及鹽橋/離子膜並用,以避免鋅離子污染液槽。另一技術可利用活性陰極220電流保護,將陰極220電位維持於略低於陽極及電解質之水準,以確保恆定但極小之前向電流始終作用於陰極220。Under certain conditions, if the wafer 1601 stays in the electrolyte solution 210, the electroplating solution may slowly erode the deposits, causing damage to the deposits. In order to offset the above effects, in one or more embodiments, any technique can be used to maintain the potential on the cathode 220 to avoid material loss. The first technique can use a sacrificial zinc anode that is electrically connected to the cathode and placed in the tank. Zinc is easier to dissolve into the solution than copper deposits, so it can protect deposits. This electrode can be used with auxiliary tank and salt bridge/ion membrane to avoid zinc ion contamination of the liquid tank. Another technique can use active cathode 220 current protection to maintain the potential of the cathode 220 slightly lower than that of the anode and the electrolyte to ensure a constant but very small forward current always acts on the cathode 220.

為沉積所鎖定之例示材料為In、Cu、Sn、Ni、Co、Ag、Au、Pb及上述材料之合金,例如SnAg、NiCo。可於電解質化學藥劑中使用添加劑,以改善沉積品質,例如表面質感、密度、殘餘應力等等。例如,在一或多個實施例中,可在電解質中加入具有抑制作用之添加劑。此等添加劑之作用為減慢或停止陰極220上較低電流密度區域之沉積,其優點在於能夠使沉積物基底產生更明確之邊緣。若無抑制添加劑,每一沉積之基底處可能呈現擴散狀之邊緣。Exemplary materials locked for deposition are In, Cu, Sn, Ni, Co, Ag, Au, Pb, and alloys of the foregoing materials, such as SnAg, NiCo. Additives can be used in electrolyte chemicals to improve the deposition quality, such as surface texture, density, residual stress, and so on. For example, in one or more embodiments, additives with inhibitory effects may be added to the electrolyte. The effect of these additives is to slow down or stop the deposition of the lower current density area on the cathode 220, and their advantage is that they can produce a more defined edge of the deposit substrate. Without inhibitory additives, there may be a diffused edge at each deposited substrate.

儘管此程序可免除晶板上之光罩處理,但在一或多個實施例中亦可使用光罩幫助改善解析度及結構初始形成。Although this procedure can eliminate the mask processing on the wafer, in one or more embodiments, the mask can also be used to help improve the resolution and the initial formation of the structure.

一或多個實施例可在設置於晶板1601上之導電晶種層1601a上沉積互連特徵。使用晶種層1601a之範例步驟示於圖19。步驟1901將初始導電晶種層1601a設置於晶板1601。此步驟1901可例如使用物理氣相沉積(「PVD」)執行。在本發明實施例中,此初始晶種層1601a可較晶圓電鍍應用中之一般沉積晶種層更薄。而後可於步驟1902使用電化學沉積增厚層體,具體而言是將晶板1601及晶種層1601a置入電解質溶液210中,並以材料鍍於整個晶種層1601a之以將其加厚,產生增厚導電晶種層1601b。初始使用較薄晶種層1601a並隨後經由電沉積加厚之優點為可減少晶種層沉積時之PVD工具使用,提高對於晶種層厚度之控制度,能夠改變基板上不同部位之晶種層厚度,能夠達成較PVD程序沉積更厚之晶種層,並建構多重材料晶種層。隨後步驟1903在加厚導電晶種層1601b上沉積互連特徵,例如凸塊1603,如上所述。最後,步驟1904移除互連結構間之晶種層1601b,使個別互連電性隔絕。One or more embodiments may deposit interconnect features on the conductive seed layer 1601a disposed on the wafer 1601. An exemplary procedure for using the seed layer 1601a is shown in FIG. 19. In step 1901, the initial conductive seed layer 1601a is disposed on the crystal plate 1601. This step 1901 can be performed using physical vapor deposition ("PVD"), for example. In the embodiment of the present invention, the initial seed layer 1601a can be thinner than the generally deposited seed layer in wafer electroplating applications. Then in step 1902, electrochemical deposition can be used to thicken the layer body. Specifically, the crystal plate 1601 and the seed layer 1601a are placed in the electrolyte solution 210, and the material is plated on the entire seed layer 1601a to thicken it. , Resulting in a thickened conductive seed layer 1601b. The advantage of initially using a thinner seed layer 1601a and then thickening by electrodeposition is that it can reduce the use of PVD tools when the seed layer is deposited, improve the control of the thickness of the seed layer, and can change the seed layer at different locations on the substrate. Thickness can achieve a thicker seed layer than the PVD process and build a multi-material seed layer. Subsequent step 1903 deposits interconnect features, such as bumps 1603, on the thickened conductive seed layer 1601b, as described above. Finally, step 1904 removes the seed layer 1601b between the interconnection structures to electrically isolate the individual interconnections.

圖20A、20B及20C說明使用電沉積建構互連結構優於現有技藝之處。圖20A顯示例示晶圓凸塊1603或柱體,例如柱體1603a,其可使用電沉積或現有技藝建構,例如光阻式程序。三項重要維度包括柱體直徑2001、柱體高度2002及柱體間隔2003(中心之間)。就使用光阻之最新技術處理而言,柱體直徑2001為約50 µm,柱體高度2002為約50 µm至100 µm,且柱體間隔2003為約100 µm。圖20B顯示使用本發明之實施例沉積例如柱體1603b之互連結構而可達成之例示尺寸:柱體直徑2011可小於10 µm,柱體高度2012於10 µm 直徑時可為200 µm或以上,且柱體間隔2013可小至10 µm至20 µm。此等數值顯示對於現有技藝之顯著改善,可製成更高更細且間隔更小之柱體。使用本發明之一或多個實施例可達成之柱體長寬比(高度比直徑)大於10:1,此為光阻式程序陰光阻在應用及接觸上之厚度限制而無法達成者。Figures 20A, 20B, and 20C illustrate the advantages of using electrodeposition to construct interconnect structures over existing techniques. FIG. 20A shows an exemplary wafer bump 1603 or pillar, such as pillar 1603a, which can be constructed using electrodeposition or existing techniques, such as a photoresist process. Three important dimensions include column diameter 2001, column height 2002 and column interval 2003 (between centers). In terms of the latest technology processing using photoresist, the column diameter 2001 is about 50 µm, the column height 2002 is about 50 µm to 100 µm, and the column spacing 2003 is about 100 µm. FIG. 20B shows an exemplary size that can be achieved by depositing an interconnect structure such as a pillar 1603b using an embodiment of the present invention: the pillar diameter 2011 can be less than 10 µm, and the pillar height 2012 can be 200 µm or more at a diameter of 10 µm. And the column spacing 2013 can be as small as 10 µm to 20 µm. These numerical values show a significant improvement to the existing technology, and can be made into taller, thinner, and smaller-spaced cylinders. The aspect ratio (height to diameter) of the column achievable by using one or more embodiments of the present invention is greater than 10:1, which is the limit of the thickness of the photoresist process photoresist in application and contact and cannot be achieved.

圖20C顯示本發明實施例之另一例示優點:互連結構可包括具有對角、傾斜或水平段落之形狀。此技藝中通常使用之晶圓凸塊1603係自半導體晶粒表面垂直凸起。此等垂直結構可供晶粒墊直接跨越對應晶粒墊位置而連接至連接點。然而,在某些情況下可能需要製作非垂直互連特徵。由於電化學積層製程之靈活性,晶粒墊連接結構並不以簡單之垂直柱體為限。在某些實施例中,可製造水平結構以連接分散訊號,原因包括基於相同晶粒之客製化晶片、不適於晶粒上互連之分散訊號互連等等。例如,此等技術可用於將晶粒訊號帶出至封裝邊緣以便連接。在某些實施例中,一或多個柱體可傾斜而非垂直於晶粒表面。例如,部分或全部柱體可同方向傾斜,使晶粒水平偏離連接點。在某些實施例中,某些柱體之傾斜方向可與其他柱體相反(展開)以創造較晶粒上墊片更為分散之連接點。於圖20C所示之說明範例中,柱體1603c之垂直段落2021連接於一大致水平段落2020;此形狀將連接點移動至晶板邊緣。非垂直形狀亦為適合之散熱片結構,其可配合或取代互連結構而建構於晶板上。在某些實施例中,散熱片可經電沉積方式,連同互連結構沉積或獨立形成於積體電路晶粒之單或雙側。FIG. 20C shows another exemplary advantage of the embodiment of the present invention: the interconnection structure may include a shape with diagonal, inclined or horizontal segments. The wafer bumps 1603 commonly used in this art are vertically raised from the surface of the semiconductor die. These vertical structures allow the die pad to directly connect to the connection point across the corresponding die pad position. However, in some cases it may be necessary to make non-vertical interconnect features. Due to the flexibility of the electrochemical build-up process, the die pad connection structure is not limited to simple vertical pillars. In some embodiments, horizontal structures can be fabricated to connect discrete signals for reasons including customized chips based on the same die, discrete signal interconnection that is not suitable for on-die interconnection, and so on. For example, these techniques can be used to bring the die signal out to the edge of the package for connection. In some embodiments, one or more pillars may be inclined rather than perpendicular to the surface of the die. For example, part or all of the pillars can be inclined in the same direction, so that the crystal grains deviate from the connection point horizontally. In some embodiments, the inclination direction of some pillars can be opposite (expanded) to other pillars to create more scattered connection points than the spacers on the die. In the illustrative example shown in FIG. 20C, the vertical segment 2021 of the pillar 1603c is connected to a substantially horizontal segment 2020; this shape moves the connection point to the edge of the wafer. The non-vertical shape is also a suitable heat sink structure, which can be constructed on the wafer with or in place of the interconnect structure. In some embodiments, the heat sink can be deposited on one or both sides of the integrated circuit die by electrodeposition, together with the interconnect structure, or independently.

圖21顯示可用於一或多個實施例中以建構水平(或傾斜,非垂直)互連特徵或散熱片特徵段落之例示技術,例如圖20C所示者。首先於步驟2101在晶板1601上沉積特徵之垂直段落2021,例如段落2110a及2111a,晶板1601可具有一導電晶種層1601a。而後可依次活化步驟2103選定之陽極,以沉積建造水平平行於陽極陣列201之水平段落2110b及2111b。此程序如上文參照圖6所述者。在某些實施例中,活化活性陽極,直到發現電流短路為止。此時停用當前之活性陽極,並活化後續陽極以繼續建構。FIG. 21 shows an exemplary technique that can be used in one or more embodiments to construct horizontal (or inclined, non-vertical) interconnection features or heat sink feature sections, such as the one shown in FIG. 20C. First, in step 2101, the vertical segments 2021 of features are deposited on the wafer 1601, such as segments 2110a and 2111a, the wafer 1601 may have a conductive seed layer 1601a. Then, the anodes selected in step 2103 can be sequentially activated to deposit and build horizontal sections 2110b and 2111b parallel to the anode array 201. This procedure is as described above with reference to FIG. 6. In certain embodiments, the active anode is activated until a current short circuit is found. At this time, the current active anode is disabled, and subsequent anodes are activated to continue construction.

建構水平結構可導入懸伸效應,細長結構尤甚。當製造此類三維互連結構時,可利用多種技術改善懸伸效應,例如,降低懸伸結構所承受之應力。在微重力環境中執行沉積亦為可避免因重力作用而產生應力之方式。亦可採用其他技術。The construction of a horizontal structure can introduce an overhanging effect, especially for a slender structure. When manufacturing such a three-dimensional interconnect structure, various techniques can be used to improve the overhang effect, for example, to reduce the stress on the overhang structure. Performing deposition in a microgravity environment is also a way to avoid stress due to gravity. Other techniques can also be used.

在某些實施例中,為降低懸伸應力,可執行多重材料建造,在步驟之間移除或不移除材料。例如,在一或多個實施例中,製程可建造支撐柱、支撐柱頂部之承槽(例如環氧化物或類似物等惰性材料2112填充),而後建造水平結構及更多支撐柱、承槽,建造直角水平結構等等。此技術如圖21之步驟2102所示,其中惰性材料2112係沉積於直柱之段落2110a及2111a周圍。此惰性材料2112可為步驟2103所建造之水平結構段落2110b及2111b提供支撐。In some embodiments, in order to reduce the overhang stress, a multi-material construction may be performed, with or without material removal between steps. For example, in one or more embodiments, the process can build support columns, supporting troughs at the top of the support columns (filled with inert materials such as epoxy or the like 2112), and then build horizontal structures and more support columns and troughs , Build right-angle horizontal structures and so on. This technique is shown in step 2102 of FIG. 21, in which the inert material 2112 is deposited around the sections 2110a and 2111a of the straight column. This inert material 2112 can provide support for the horizontal structure sections 2110b and 2111b constructed in step 2103.

雖然本發明係藉由特定實施例及應用加以陳明,但熟悉此技藝人士應可據以實現各種修改及變化而不脫離本發明如以下請求項所界定之範疇。Although the present invention is illustrated by specific embodiments and applications, those skilled in the art should be able to implement various modifications and changes without departing from the scope of the present invention as defined by the following claims.

100:規劃階段 1001:腐蝕運算 1002:地圖 1003:運算 1004:地圖 1006:地圖 1007:輸出 101:模型 1011:陽極電流 101a:模型 1012:陽極電壓 1013:陽極工作週期 102:規劃步驟 103:建造計畫 1101:陽極 1102:陽極 1103:陽極 111:層體描述 1111:沉積 1112:沉積圖案 112:目標地圖 1121:邊界 1122:邊界 112a:目標地圖 112b:目標地圖 112c:目標地圖 112d:目標地圖 112e:目標地圖 113:程序參數 1130:圖案 113a:程序參數 113b:程序參數 113c:程序參數 113d:程序參數 1140:點擴散函數 1141:卷積 115:程序參數 1150:形狀 120:建造階段 1201:目標地圖 121:步驟 1210:轉換 1211:圖案 1212:數值 1213:陽極 1214:陽極 122:步驟 123:步驟 1230:圖案 1231:陽極 1232:陽極 124:控制訊號 125:步驟 126:步驟 127:步驟 128:沉積分析 129:判定 130:判定 1301:區域 131:程序參數 1310:離子 1311:子區域 1312:子區域 132:測試 1331:電流 1332:電流 140:迴圈 1401:陽極 1402:薄膜 1403:氣泡 1410:輔助陽極 1411:開關 1412:開關 1413:材料 1420:流動 1421:震動 1501:部件 1601:晶板 1601a:晶種層 1601b:晶種層 1602:晶片塊 1603:凸塊 1603a:柱體 1603b:柱體 1603c:柱體 1611:晶板 1612:晶片塊 1613:電路 1614:連接點 1701:步驟 1702:步驟 1703:步驟 1704:步驟 1705:步驟 1801a:夾鉗 1801b:夾鉗 1802a:夾鉗 1802b:夾鉗 1803:流體 1804:位置 1810:水平移位 1901:步驟 1902:步驟 200:列印頭 2001:柱體直徑 2002:柱體高度 2003:柱體間隔 201:陽極陣列 2011:柱體直徑 2012:柱體高度 2013:柱體間隔 202:控制電路 2020:水平段落 2021:垂直段落 203:網格控制電路 204:配電電路 210:電解質溶液 2101:步驟 2102:步驟 2103:步驟 211:陽極 2110a:段落 2110b:段落 2111a:段落 2111b:段落 2112:惰性材料 212:陽極 220:陰極 2201:陽極 2202:陽極 2203:陽極 2204:導體 2205:開口 2206:開口 221:電源供應器 2211:陽極 2212:陽極 2213:陽極 2214:電阻器 2215:電阻器 2216:電阻器 222:處理器 2221:陽極 2222:陽極 2223:陽極 2224:開關 2225:開關 2226:開關 223:感測器 223a:電流感測器 224:位置致動器 224a:致動器 224b:致動器 225:垂直移動 225a:最大六自由度 230:部件 230a:部件 301:程序參數 302:程序參數 303:程序參數 401:密度 402:目標地圖 403:基底層 404:額外層體 405:部件 501:差分運算 502:異動資料比對地圖 503:區域 504:判定 601b:部分 601c:區域 610:支撐柱 611:材料 613:材料 614:結構 621:子集 622:子集 623:子集 701:陽極 702:陽極 703:陽極 704:陽極 705:陽極 706:陽極 710:電流 711:電流 713:電流 714:電流 801:地圖 802:閾值運算 900:目標地圖 901:運算 902:運算 911:地圖 912:目標地圖 912a:島嶼 912b:島嶼 912c:島嶼 912d:島嶼 913:像素數 920:運算 921:地圖 922:像素數 923:比率 923a:完成百分比 923b:完成百分比 923c:完成百分比 923d:完成百分比100: Planning stage 1001: Corrosion calculation 1002: Map 1003: Operation 1004: Map 1006: map 1007: output 101: Model 1011: anode current 101a: model 1012: anode voltage 1013: anode duty cycle 102: Planning steps 103: Construction Plan 1101: anode 1102: anode 1103: anode 111: layer description 1111: deposition 1112: deposition pattern 112: Target Map 1121: boundary 1122: boundary 112a: target map 112b: target map 112c: target map 112d: target map 112e: target map 113: Program Parameters 1130: pattern 113a: Program parameters 113b: Program parameters 113c: program parameters 113d: Program parameters 1140: Point spread function 1141: Convolution 115: program parameters 1150: shape 120: Construction phase 1201: Target Map 121: Step 1210: Conversion 1211: pattern 1212: Numerical value 1213: anode 1214: anode 122: Step 123: Steps 1230: pattern 1231: anode 1232: anode 124: Control signal 125: step 126: Step 127: Step 128: Sedimentation analysis 129: Judgment 130: Judgment 1301: area 131: Program parameters 1310: ion 1311: sub-area 1312: sub-area 132: test 1331: current 1332: current 140: loop 1401: anode 1402: Film 1403: Bubble 1410: auxiliary anode 1411: switch 1412: switch 1413: material 1420: flow 1421: Vibration 1501: parts 1601: crystal board 1601a: seed layer 1601b: seed layer 1602: wafer block 1603: bump 1603a: cylinder 1603b: cylinder 1603c: cylinder 1611: crystal board 1612: wafer block 1613: circuit 1614: connection point 1701: Step 1702: Step 1703: step 1704: step 1705: step 1801a: clamp 1801b: clamp 1802a: clamp 1802b: clamp 1803: fluid 1804: location 1810: Horizontal shift 1901: steps 1902: steps 200: print head 2001: cylinder diameter 2002: column height 2003: Cylinder spacing 201: Anode Array 2011: cylinder diameter 2012: column height 2013: column interval 202: control circuit 2020: horizontal paragraphs 2021: vertical paragraph 203: Grid Control Circuit 204: Power Distribution Circuit 210: Electrolyte solution 2101: Step 2102: step 2103: step 211: Anode 2110a: Paragraph 2110b: Paragraph 2111a: Paragraph 2111b: Paragraph 2112: inert materials 212: Anode 220: cathode 2201: anode 2202: anode 2203: anode 2204: Conductor 2205: opening 2206: opening 221: power supply 2211: anode 2212: anode 2213: anode 2214: resistor 2215: resistor 2216: resistor 222: processor 2221: anode 2222: anode 2223: anode 2224: switch 2225: switch 2226: switch 223: Sensor 223a: Current sensor 224: Position Actuator 224a: Actuator 224b: Actuator 225: Vertical movement 225a: Maximum six degrees of freedom 230: parts 230a: Parts 301: program parameters 302: program parameters 303: Program Parameters 401: Density 402: Target Map 403: basal layer 404: Extra layer body 405: Parts 501: Difference Operation 502: Change data comparison map 503: area 504: Judgment 601b: Partial 601c: area 610: Support Column 611: Material 613: Material 614: structure 621: Subset 622: Subset 623: Subset 701: anode 702: anode 703: anode 704: Anode 705: anode 706: anode 710: Current 711: current 713: current 714: current 801: Map 802: Threshold Operation 900: target map 901: Operation 902: calculation 911: Map 912: Target Map 912a: island 912b: island 912c: island 912d: island 913: Number of pixels 920: Operation 921: Map 922: Number of pixels 923: ratio 923a: Percent complete 923b: Percent complete 923c: Percent complete 923d: Percent complete

本發明之上述及其他態樣、特徵及優點將藉由下文詳細敘述配合下列附圖加以陳明: 圖1為本發明實施例之流程圖,其係使用回授控制評估層體完成並在製造過程中調整參數,以先後製造多個層體。 圖2顯示可用於實施本發明一或多個實施例之例示電沉積設備之架構方塊圖。 圖3顯示一物體之分層例示建造計畫,其中每一層體之目標地圖標明所欲之材料沉積區域以及描述層體製造方式之程序參數。 圖4繪示如何利用密度控制產生便於進行後續移除之多孔基底層。 圖5繪示層體懸伸部位之偵測。 圖6繪示圖5所示懸伸之製造步驟。 圖7顯示陽極陣列上以電流感測器所獲得之回授例示實施例。 圖8顯示例示電流地圖感測器回授訊號,及此等訊號經處理而形成層體內沉積區域地圖之情形。 圖9A顯示基於圖8電流感測器資料之層體完成測試例示方法。 圖9B為圖9A層體完成測試之延伸,其分別測試該層體中所有相連組成部分之完成。 圖10繪示基於圖8電流感測器回授訊號之陽極輸出更新。 圖11A、11B及11C繪示陽極電流與沉積材料間之可能複雜關係,可能需要預處理以取得所欲之沉積圖案。 圖12A繪示透過陽極電流計算取得所欲沉積圖案之過程。 圖12B之二維範例說明計算陽極電流圖案以取得所欲沉積圖案之過程。 圖13顯示在不同區域進行交替陽極輸出之例示實施例。 圖14顯示可於層體製造時可對陽極陣列或電解質執行之例示維護動作。 圖15顯示利用本發明實施例所製造之例示部件。 圖16顯示本發明實施例之例示應用,其係使用電化學積層製造在晶圓上沉積形成晶圓凸塊。 圖17顯示使用電化學積層製造在晶板上增設晶圓凸塊或類似特徵之方法例示流程圖。 圖18顯示可用於實施圖17所示方法之例示設備。 圖19顯示在晶板上增設互連特徵之程序例示步驟,其是在晶種層頂部建立特徵後再移除晶種層。 圖20A為晶圓凸塊之例示輪廓圖。 圖20B顯示可利用本發明實施例增設之加高加密特徵。 圖20C顯示可利用本發明實施例產生之具水平段落之例示特徵。 圖21顯示可用於一或多個實施例中以建構如圖20C所示水平特徵之例示步驟。 圖22A、22B及22C繪示可用於一或多個實施例中之不同類型電極配置 圖22A繪示非獨立控制之獨立電極。 圖22B繪示非獨立控制之非獨立電極。 圖22C繪示獨立控制之獨立電極。The above and other aspects, features and advantages of the present invention will be illustrated by the following detailed description with the following drawings: FIG. 1 is a flowchart of an embodiment of the present invention, which uses feedback control to evaluate the completion of the layer body and adjust the parameters during the manufacturing process to sequentially manufacture multiple layer bodies. FIG. 2 shows a block diagram of an exemplary electrodeposition apparatus that can be used to implement one or more embodiments of the present invention. Fig. 3 shows a layered example construction plan of an object, in which the target area of each layer is indicated by the desired material deposition area and the process parameters describing the method of manufacturing the layer. Figure 4 shows how to use density control to create a porous base layer that facilitates subsequent removal. Figure 5 shows the detection of the overhanging part of the layer body. FIG. 6 shows the manufacturing steps of the overhang shown in FIG. 5. FIG. Fig. 7 shows an exemplary embodiment of feedback obtained by a current sensor on the anode array. FIG. 8 shows an example of the feedback signals from the current map sensor, and the situation where these signals are processed to form a map of the deposition area in the layer. FIG. 9A shows an example method for testing the layer body based on the current sensor data of FIG. 8. Fig. 9B is an extension of the completion test of the layer body of Fig. 9A, which respectively tests the completion of all connected components in the layer body. FIG. 10 shows the anode output update based on the feedback signal of the current sensor of FIG. 8. FIG. 11A, 11B, and 11C illustrate the possible complicated relationship between anode current and deposition material, and pretreatment may be required to obtain the desired deposition pattern. FIG. 12A shows the process of obtaining the desired deposition pattern through anode current calculation. The two-dimensional example of FIG. 12B illustrates the process of calculating the anode current pattern to obtain the desired deposition pattern. Figure 13 shows an exemplary embodiment of alternate anode output in different areas. Figure 14 shows exemplary maintenance actions that can be performed on the anode array or electrolyte during the manufacture of the layered body. Figure 15 shows an exemplary component manufactured using an embodiment of the present invention. FIG. 16 shows an exemplary application of an embodiment of the present invention, which uses electrochemical build-up manufacturing to deposit and form wafer bumps on a wafer. FIG. 17 shows an exemplary flow chart of a method of adding wafer bumps or similar features on a wafer using electrochemical build-up manufacturing. Figure 18 shows an exemplary device that can be used to implement the method shown in Figure 17. FIG. 19 shows an exemplary procedure for adding interconnect features on a wafer, which is to remove the seed layer after the features are created on top of the seed layer. FIG. 20A is an exemplary outline view of a wafer bump. FIG. 20B shows the enhanced encryption feature that can be added by the embodiment of the present invention. Figure 20C shows exemplary features of horizontal paragraphs that can be generated using embodiments of the present invention. Figure 21 shows exemplary steps that can be used in one or more embodiments to construct the horizontal features shown in Figure 20C. 22A, 22B, and 22C illustrate different types of electrode configurations that can be used in one or more embodiments Figure 22A shows independent electrodes that are not independently controlled. Figure 22B shows a non-independent electrode that is not independently controlled. Figure 22C shows an independent electrode controlled independently.

100:規劃階段 100: Planning stage

101:模型 101: Model

102:規劃步驟 102: Planning steps

103:建造計畫 103: Construction Plan

111:層體描述 111: layer description

112:目標地圖 112: Target Map

113:程序參數 113: Program Parameters

115:程序參數 115: program parameters

121:步驟 121: Step

122:步驟 122: Step

123:步驟 123: Steps

124:控制訊號 124: Control signal

125:步驟 125: step

126:步驟 126: Step

127:步驟 127: Step

128:沉積分析 128: Sedimentation analysis

129:判定 129: Judgment

130:判定 130: Judgment

131:程序參數 131: Program parameters

132:測試 132: test

140:迴圈 140: loop

Claims (23)

一種用以製造互連特徵之電化學積層製造方法,其係包含: 取得一包含一或多個晶片塊之晶板,所述一或多個晶片塊中之每一晶片塊包含一或多個連接點,其中,所述晶板又包含一導電晶種層; 將所述導電晶種層電性耦接至一電源供應器; 使所述導電晶種層之一表面接觸一電解質溶液; 使一陽極陣列接觸所述電解質溶液,其中, 所述陽極陣列包含複數個沉積陽極;且 所述複數個沉積陽極中之每一沉積陽極,其係配置為獨立提供電流,該電流經由所述電解質溶液自所述電源供應器取道所述沉積陽極流至所述晶板,在所述晶板上產生材料之沉積; 將所述晶板與所述陽極陣列對齊;及 製造一或多個互連特徵,各自電性耦接於所述每一晶片塊上所述一或多個連接點中之一對應連接點,其中製造所述一或多個互連特徵之步驟包含 控制自所述每一沉積陽極流出之所述電流之量,以將所述材料沉積於所述晶板上,形成所述一或多個互連特徵。An electrochemical layered manufacturing method for manufacturing interconnection features, which includes: Obtain a wafer board including one or more wafer blocks, each of the one or more wafer blocks includes one or more connection points, wherein the wafer board further includes a conductive seed layer; Electrically coupling the conductive seed layer to a power supply; Contacting one surface of the conductive seed layer with an electrolyte solution; An anode array is brought into contact with the electrolyte solution, wherein The anode array includes a plurality of deposition anodes; and Each deposition anode of the plurality of deposition anodes is configured to independently provide a current, and the current flows from the power supply through the electrolyte solution to the crystal plate through the deposition anode, Deposition of materials produced on the board; Aligning the crystal plate with the anode array; and Manufacturing one or more interconnection features, each electrically coupled to a corresponding connection point among the one or more connection points on each wafer block, wherein the step of manufacturing the one or more interconnection features Include The amount of the current flowing from each deposition anode is controlled to deposit the material on the wafer to form the one or more interconnect features. 如請求項1所述之方法,其中,所述一或多個互連特徵包含一或多個晶圓凸塊。The method of claim 1, wherein the one or more interconnect features include one or more wafer bumps. 如請求項1所述之方法,其中,所述一或多個互連特徵包含一或多個柱體。The method of claim 1, wherein the one or more interconnection features include one or more pillars. 如請求項1所述之方法,其中將所述晶板與所述陽極陣列對齊之步驟包含 使用一或多個感測器,以判定所述晶板相對於所述陽極陣列之一三維位置及一三維方向;及 使用一或多個致動器,以設定或修改所述晶板相對於所述陽極陣列之所述三維位置及所述三維方向。The method according to claim 1, wherein the step of aligning the crystal plate with the anode array comprises Using one or more sensors to determine a three-dimensional position and a three-dimensional direction of the crystal plate relative to the anode array; and One or more actuators are used to set or modify the three-dimensional position and the three-dimensional direction of the crystal plate relative to the anode array. 如請求項1所述之方法,又包含 移除所述一或多個互連特徵覆蓋之部分。The method described in claim 1, which also includes Remove the portion covered by the one or more interconnected features. 如請求項1所述之方法,又包含 控制自所述每一沉積陽極流出之所述電流量,以增加所述晶板之一或多個區域中所述導電晶種層之一厚度。The method described in claim 1, which also includes The amount of the current flowing from each deposition anode is controlled to increase the thickness of one of the conductive seed layers in one or more regions of the crystal plate. 如請求項1所述之方法,其中,所述一或多個互連特徵中之一或多者包含不實質垂直於所述晶板之部分。The method of claim 1, wherein one or more of the one or more interconnection features includes a portion that is not substantially perpendicular to the wafer. 如請求項7所述之方法,又包含 依序活化所述複數個沉積陽極中之水平偏移陽極,以建構實質垂直於所述晶板之所述部分。The method described in claim 7, which also includes The horizontally offset anodes of the plurality of deposition anodes are sequentially activated to construct the part substantially perpendicular to the crystal plate. 如請求項8所述之方法,又包含 建構所述一或多個互連特徵中所述一或多者之垂直部分,所述垂直部分係實質垂直於所述晶板; 在所述垂直部分間之所述晶板上沉積一惰性材料;及 在沉積所述惰性材料後活化所述水平偏移陽極。The method described in claim 8, which also includes Constructing vertical portions of the one or more of the one or more interconnection features, the vertical portions being substantially perpendicular to the wafer; Depositing an inert material on the wafer between the vertical portions; and The horizontal offset anode is activated after depositing the inert material. 如請求項1所述之方法,其中 所述材料包含一第一材料及一第二材料;且 將所述材料沉積於所述晶板上以形成所述一或多個互連特徵之步驟包含 將所述第一材料沉積於所述晶板上;及 將所述第二材料沉積於所述第一材料頂部。The method described in claim 1, wherein The material includes a first material and a second material; and The step of depositing the material on the wafer to form the one or more interconnect features includes Depositing the first material on the crystal plate; and The second material is deposited on top of the first material. 如請求項10所述之方法,其中, 所述第一材料包含銅;及 所述第二材料包含錫、銀及鉛中之一或多者。The method according to claim 10, wherein: The first material includes copper; and The second material includes one or more of tin, silver, and lead. 如請求項1所述之方法,其中, 所述晶板包含二或多個晶片塊;且 製造所述一或多個互連特徵之步驟又包含 使用一或多個致動器以定位最接近所述二或多個晶片塊中之每一晶片塊之所述陽極陣列,以製造與所述每一晶片塊關聯之互連特徵。The method according to claim 1, wherein: The wafer includes two or more wafer blocks; and The step of manufacturing the one or more interconnect features further includes One or more actuators are used to position the anode array closest to each of the two or more wafers to produce interconnect features associated with each of the wafers. 如請求項1所述之方法,其中,製造所述一或多個互連特徵之步驟包含 取得一建造計畫,其係包含所述一或多個互連特徵之複數個層體中每一層之一層體描述,其中,該層體描述包含 一目標地圖,其係包含該材料在一關聯層體內複數個位置之所欲存在或不存在;及 一或多個程序參數值,其影響該關聯層體之一製程; 製造該複數個層體中之每一層體,其中製造該複數個層體中一層體之步驟包含 設定或確認該晶板相對於該陽極陣列之一位置,以開始該層體之製造; 基於該層體之該層體描述,傳送控制訊號至該陽極陣列; 測量該陽極陣列上之一或多個回授訊號; 分析該一或多個回授訊號,以產生一沉積分析,該沉積分析包含該層體內該複數個位置上之沉積進展程度; 基於該沉積分析,判定該層體之沉積是否完成; 當該層體之沉積未完成時, 判定是否修改該一或多個程序參數值中與該層體關聯之一或多個程序參數值;及 當該層體之沉積完成且當該複數個層體中之一後續層體尚未製造時,製造該後續層體。The method of claim 1, wherein the step of manufacturing the one or more interconnection features comprises Obtain a construction plan that includes a layer description of each of the plurality of layers of the one or more interconnected features, wherein the layer description includes A target map, which contains the desired existence or non-existence of a plurality of positions of the material in an associated layer; and One or more program parameter values, which affect a process of the associated layer; Manufacturing each of the plurality of layer bodies, wherein the step of manufacturing one of the plurality of layer bodies includes Setting or confirming a position of the crystal plate relative to the anode array to start the manufacture of the layer body; Based on the layer description of the layer body, transmit a control signal to the anode array; Measuring one or more feedback signals on the anode array; Analyzing the one or more feedback signals to generate a deposition analysis, the deposition analysis including the degree of deposition progress at the plurality of locations in the layer; Based on the deposition analysis, determine whether the deposition of the layer body is completed; When the deposition of the layer is not completed, Determine whether to modify one or more program parameter values associated with the layer among the one or more program parameter values; and When the deposition of the layer body is completed and when one of the subsequent layer bodies of the plurality of layer bodies has not been manufactured, the subsequent layer body is manufactured. 如請求項13所述之方法,其中,該一或多個回授訊號包含該陽極陣列上電流之一地圖。The method according to claim 13, wherein the one or more feedback signals include a map of the current on the anode array. 如請求項13所述之方法,其中製造該複數個層體中之一層體之步驟又包含 計算自該陽極陣列中每一沉積陽極之所欲電流輸出地圖,所述電流將產生對應於與該層體關聯之該目標地圖之沉積。The method according to claim 13, wherein the step of manufacturing one of the plurality of layer bodies further comprises Calculate the desired current output map from each deposition anode in the anode array, and the current will generate a deposition corresponding to the target map associated with the layer. 如請求項15所述之方法,其中,計算自每一沉積陽極之所欲電流輸出地圖之步驟包含對與該層體關聯之該目標地圖施加一或多種轉換。The method of claim 15, wherein the step of calculating the desired current output map from each deposition anode includes applying one or more transformations to the target map associated with the layer. 如請求項13所述之方法,其中,製造該複數個層體中之該層體之步驟又包含 執行一或多個維護動作,以維護該陽極陣列與該電解質溶液中一或多者之條件。The method according to claim 13, wherein the step of manufacturing the layer body of the plurality of layer bodies further comprises Perform one or more maintenance actions to maintain the condition of one or more of the anode array and the electrolyte solution. 如請求項17所述之方法,其中該一或多個維護動作包含將材料放回一或多個已經腐蝕之沉積陽極。The method of claim 17, wherein the one or more maintenance actions include returning the material to the one or more corroded deposition anodes. 如請求項17所述之方法,其中該一或多個維護動作包含活化一或多個其上已形成有一薄膜之沉積陽極,以移除該薄膜。The method according to claim 17, wherein the one or more maintenance actions include activating one or more deposition anodes on which a thin film has been formed to remove the thin film. 如請求項17所述之方法,其中該一或多個維護動作包含去除該電解質溶液中之氣泡。The method of claim 17, wherein the one or more maintenance actions include removing bubbles in the electrolyte solution. 一種互連特徵電化學積層製造系統,其係包含: 一反應室,配置為容納一可經電解作用沉積之離子溶液; 一陽極陣列,設置於該反應室中,且配置為浸入該離子溶液中; 一基板,設置於該反應室中; 一導電晶種層,設置於該基板之一表面上,且配置為接觸該離子溶液; 一機械式定位系統,配置為修改一或多個該陽極陣列與該基板之一位置及方向中之一或多者;及 一微控制器,其係編程為 傳送控制訊號至該機械式定位系統,以修改該陽極陣列與該基板之該相對位置及方向,俾使 該陽極陣列與該基板為實質上共平面;且 該陽極陣列係與該基板之一或多個特徵對齊; 接受一互連特徵三維模型添加於該基板; 基於該互連特徵三維模型,控制通過由該陽極陣列中之每一陽極之電流,以在該基板上建構該互連特徵。An interconnected characteristic electrochemical layered manufacturing system, which includes: A reaction chamber, configured to contain an ionic solution that can be deposited by electrolysis; An anode array arranged in the reaction chamber and configured to be immersed in the ionic solution; A substrate arranged in the reaction chamber; A conductive seed layer disposed on a surface of the substrate and configured to contact the ionic solution; A mechanical positioning system configured to modify one or more of one or more of the position and orientation of the anode array and the substrate; and A microcontroller, which is programmed as Send a control signal to the mechanical positioning system to modify the relative position and direction of the anode array and the substrate, so that The anode array and the substrate are substantially coplanar; and The anode array is aligned with one or more features of the substrate; Accept a three-dimensional model of interconnection features to be added to the substrate; Based on the three-dimensional model of the interconnection feature, the current passing through each anode in the anode array is controlled to construct the interconnection feature on the substrate. 如請求項21所述之系統,又包含一或多個附加裝置,其係配置為對該導電晶種層提供一電性連接。The system according to claim 21 further includes one or more additional devices configured to provide an electrical connection to the conductive seed layer. 如請求項21所述之系統,其中, 該基板包含二或多個晶片塊;且 該微控制器更編程為 傳送一第一組控制訊號至該機械式定位系統,以將該陽極陣列與該二或多個晶片塊中一第一晶片塊對齊; 控制該通過該陽極陣列中每一陽極之電流,以在該第一晶片塊上建構該互連特徵; 傳送一第二組控制訊號至該機械式定位系統,以將該陽極陣列與該二或多個晶片塊中之一第二晶片塊對齊;及 控制該通過該陽極陣列中每一陽極之電流,以在該第二晶片塊上建構該互連特徵。The system according to claim 21, wherein: The substrate includes two or more wafer blocks; and The microcontroller is more programmed as Transmitting a first set of control signals to the mechanical positioning system to align the anode array with a first die block of the two or more die blocks; Controlling the current through each anode in the anode array to construct the interconnection feature on the first wafer block; Transmitting a second set of control signals to the mechanical positioning system to align the anode array with the second chip block of one of the two or more chip blocks; and The current through each anode in the anode array is controlled to construct the interconnection feature on the second wafer block.
TW110104696A 2020-02-28 2021-02-08 Electrochemical additive manufacturing of interconnection features TW202141593A (en)

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