TW202137555A - Semiconductor device - Google Patents

Abstract

A semiconductor device including a substrate having a first conductive type and a gate structure located on the substrate is provided. The substrate includes a first well, a second well, and at least one third well. The first well having a second conductive type is in the substrate. The second well having the second conductive type is in the first well below the gate structure. The third well is in the first well and located at the least one side of the second well. The third well includes a first and a second doped region having the first and the second conductive types respectively and a source and a drain region having the second conductive type respectively The first doped region is between the second well and the second doped region. The source region is in the first doped region. The drain region is in the second doped region.

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a metal oxide semiconductor.

High-voltage semiconductor components are widely used in various fields, such as high-voltage AC-DC converters (AC-DC converters), LED drivers and other fields. With the gradual advancement of semiconductor technology, high-voltage semiconductor components with high conversion efficiency and low standby power consumption have also received increasing attention. For example, high-voltage startup circuits (commonly used transistors such as HV JFET and DMOS) and pulse width modulation (PWM) circuits are integrated into a single chip. The pulse width circuit is then closed to reduce energy consumption. However, in order to withstand voltages as high as hundreds of volts or more, the size of the high-voltage junction field-effect transistor is usually large, which limits the saturation current of the high-voltage junction field-effect transistor.

The present invention provides a semiconductor device that can provide good withstand voltage characteristics.

The present invention provides a semiconductor device, which includes a substrate having a first conductivity type and a gate structure on the substrate. The base includes a first well area, a second well area and at least one third well area. The first well region is in the substrate and has a second conductivity type. The second well region is in the first well region under the gate structure and has a second conductivity type. The third well region is in the first well region and located on at least one side of the second well region, wherein the third well region includes a first doped region, a second doped region, a source region and a drain region. The first doped region has a first conductivity type. The second doped region has a second conductivity type, wherein the first doped region is between the second well region and the second doped region. The source region is in the first doped region and has a second conductivity type. The drain region is in the second doped region and has a second conductivity type.

In an embodiment of the present invention, the aforementioned at least one third well area includes a plurality of third well areas, which are respectively located on opposite sides of the second well area.

In an embodiment of the present invention, the doping concentration of the above-mentioned second doping region is greater than the doping concentration of the first well region.

In an embodiment of the present invention, the doping concentration of the second well region is greater than the doping concentration of the first well region.

In an embodiment of the present invention, the aforementioned semiconductor device further includes an isolation structure disposed between the source region and the drain region.

In an embodiment of the present invention, the above-mentioned first well region includes a first drift region and a second drift region, wherein the first drift region is located in the first well region adjacent to the bottom of the first doped region, and the second drift region is The region is located in the first well region adjacent to the second doped region.

In an embodiment of the present invention, the aforementioned third well region includes at least one sub-doped region having the first conductivity type, and the sub-doped region is in the first doped region and is spaced apart from the source region.

In an embodiment of the present invention, the aforementioned at least one sub-doped region includes a plurality of sub-doped regions spaced apart from each other.

In an embodiment of the present invention, the above-mentioned first doped region is in contact with the second doped region and the second well region respectively.

The present invention also provides a semiconductor device, which includes a substrate with a first conductivity type and a gate structure on the substrate, wherein the substrate includes a first well region, a plurality of first doped regions, a plurality of source regions, and a plurality of Drain region. The first well region is in the substrate and has a second conductivity type, wherein the first well region includes a first part, a second part, and a third part located under the first part and the second part. The plurality of first doped regions are in the first well region and have a first conductivity type, wherein each of the plurality of first doped regions is between the first part and the second part, and the first part is in the plurality of second Between a doped region and under the gate structure. The source regions are respectively in the corresponding first doped regions and have the second conductivity type. The drain regions are respectively in the second part of the first well region and have the second conductivity type.

In an embodiment of the present invention, the above-mentioned substrate includes a second well region having a second conductivity type, which is located in the first part of the first well region.

In an embodiment of the present invention, the aforementioned second well region is in contact with the adjacent first doped region.

In an embodiment of the present invention, the above-mentioned substrate includes a plurality of second doped regions having a second conductivity type, which are respectively located in the second part of the first well region, and the multiple drain regions are respectively located in the phase In the corresponding second doped region.

In an embodiment of the present invention, the doping concentration of the above-mentioned second doping region is greater than the doping concentration of the first well region.

In an embodiment of the present invention, the aforementioned second doped region is in contact with the adjacent first doped region.

In an embodiment of the present invention, the aforementioned semiconductor device further includes an isolation structure disposed between the source region and the drain region adjacent to each other.

In an embodiment of the present invention, the above-mentioned first well region includes a first drift region and a second drift region, wherein the first drift region is in the third part of the first well region, and the second drift region is in the first drift region. In the second part of the well area.

In an embodiment of the present invention, the above-mentioned substrate includes a plurality of sub-doped regions having a first conductivity type, and the plurality of sub-doped regions are respectively in the corresponding first doped regions and correspond to the source regions. Separate.

Based on the above, since the first doped region with the first conductivity type is in the first well region with the second conductivity type and is located between the second well region with the second conductivity type and the second doped region, therefore, In the case where the source region and the drain region with the second conductivity type are located in the first doped region and the second doped region, respectively, the first well region will form an additional buried region adjacent to the bottom of the first doped region. Embedded drift region (buried drift region), so that the length of the drift region can be increased and the semiconductor device can have good withstand voltage characteristics.

The present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawing will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

It should be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or intervening elements may also be present. If an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" can refer to physical and/or electrical connection, and "electrical connection" or "coupling" can mean that there are other elements between two elements. "Electrical connection" as used herein may include physical connection (for example, wired connection) and physical disconnection (for example, wireless connection).

As used herein, "about", "approximately" or "substantially" includes the mentioned value and the average value within the acceptable deviation range of the specific value that can be determined by a person with ordinary knowledge in the technical field. The measurement in question and the specific number of errors associated with the measurement (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximate" or "substantially" used herein can select a more acceptable deviation range or standard deviation based on optical properties, etching properties or other properties, and not one standard deviation can be applied to all properties .

The terms used herein are only used to illustrate exemplary embodiments, but not to limit the present disclosure. In this case, unless otherwise explained in the context, the singular form includes the majority form.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. 2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. 4 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the invention. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention.

1, the semiconductor device 10 may include a substrate 100 having a first conductivity type and a gate structure 200 on the substrate 100. In this embodiment, the substrate 100 may include a first well area 110, a second well area 120 and at least one third well area 130. The first well region 110 may be located in the substrate 100 and have the second conductivity type. The second well region 120 may be located in the first well region 110 under the gate structure 200 and have the second conductivity type. The third well area 130 may be in the first well area 110 and located on at least one side of the second well area 120. The third well region 130 may include a first doped region 132 having a first conductivity type, a second doped region 134 having a second conductivity type, a source region 136 having a second conductivity type, and a source region 136 having a second conductivity type. Drain region 138. The first doped region 132 may be located between the second well region 120 and the second doped region 134. The source region 136 may be located in the first doped region 132; and the drain region 138 may be located in the second doped region 134. In this way, since the first doped region 132 with the first conductivity type is located in the first well region 110 with the second conductivity type and between the second well region 120 and the second doped region 134 with the second conductivity type Therefore, when the source region 136 and the drain region 138 having the second conductivity type are located in the first doped region 132 and the second doped region 134, respectively, the first well region 110 is adjacent to the first doped region. An additional buried drift region is formed at the bottom of the region 132, so that the length of the drift region can be increased and the semiconductor device can have good withstand voltage characteristics. On the other hand, the buried drift region can have a double reduction of surface field (RESURF) effect, so it can improve the withstand voltage of the drain terminal. In this embodiment, the first doped region 132 may be in contact with the second doped region 134 and the second well region 120 respectively. In this embodiment, the semiconductor device 10 can be fabricated by, for example, a CMOS process, but the invention is not limited to this.

In the following, the first conductivity type is N-type and the second conductivity type is P-type as exemplary embodiments for description, but the present invention is not limited thereto. In other embodiments, the first conductivity type can also be P type; and the second conductivity type can also be N type.

In the case where the first conductivity type is N-type and the second conductivity type is P-type, the conduction current path of the semiconductor device 10 may be as shown by the dashed line in FIG. 1, and its internal resistance may include the sum of the following resistances: source contact resistance R _SC , source region resistance R _S , channel region resistance R _CH , accumulation region resistance R _A , JFET region resistance R _JFET , buried drift region resistance R _burieddrift , drift region resistance R _drift , well region resistance R _well , drain The electrode resistance R _D and the drain contact resistance R _DC . _{In other words, the conductor device 10 may have a first drift region (the region shown by R burieddrift} in FIG. 1) in the first well region 110 adjacent to the bottom of the first doped region 132, and is adjacent to the second doped region. The first well region 110 of the miscellaneous region 134 may have a second drift region (a region shown by _{R drift in FIG. 1 ).} Therefore, the semiconductor device 10 can increase the length of the drift region while maintaining the element size, so that the semiconductor device 10 has good withstand voltage characteristics. On the other hand, it can be seen from FIG. 1 that the conduction current path of the semiconductor device 10 may include a horizontal current path and a vertical current path. That is to say, from the perspective of the structure of the semiconductor device 10, the semiconductor device 10 includes a JFET region similar to VDMOS ( _{the region shown by R JFET} in FIG. 1, the vertical current path) and the drift region of LDMOS (FIG. 1 In addition to _{the region shown by R drift} , the horizontal current path, it also includes a first drift region located between the first doped region 132 and the first well region 110 (the region shown by _{R burieddrift in FIG. 1} , The horizontal current path), as the current connection path between the JFET region and the drift region. In other words, the semiconductor device 10 integrates the features of VDMOS and LDMOS to form a DMOS with a folded buried drift region.

In this embodiment, the gate structure 200 may include a spacer 202, a gate dielectric layer 204 and a gate electrode 206. The gate dielectric layer 204 may include silicon dioxide or a high-k gate dielectric material, and the gate electrode 206 may include polysilicon or a metal gate material. The spacer 202 may include nitride-based sidewall spacers (for example, including SiN) or oxide-based sidewall spacers (for example, SiO ₂ , SiOC, etc.).

In this embodiment, as shown in FIG. 1, at least one third well area 130 may include a plurality of third well areas 130, which are respectively located on opposite sides of the second well area 120. In other words, the semiconductor device 10 may have two channel regions (that is, the part of the first doped region 132 under the gate structure 200), a single JFET region (that is, the second well region 120), and two buried drift regions. _{Area (the area shown by R burieddrift} in FIG. 1), two drift areas ( _{the area shown by R drift} in FIG. 1), two source areas 136 and two drain areas 138.

In this embodiment, the doping concentration of the second doping region 134 can be greater than the doping concentration of the first well region 110, so that the separation distance between the source region 136 and the drain region 138 can be shortened, so that the semiconductor device 10 The component size can be further reduced. In this embodiment, the doping concentration of the second well region 120 may be greater than the doping concentration of the first well region 110, so that the separation distance between two adjacent first doping regions 132 can be shortened, so that the semiconductor device The component size of 10 can be further reduced.

In this embodiment, the semiconductor device 10 may include an isolation structure 140 for defining a device region. The first well area 110, the second well area 120 and the third well area 130 may be located between two adjacent isolation structures 140. In this embodiment, the semiconductor device 10 may include a dielectric layer 170 and a plurality of contact windows 180 formed in the dielectric layer 170. The dielectric layer 170 may be formed on the substrate 100 and cover the gate structure 200. The contact window 180 can be electrically connected to the corresponding source 136, drain 138, and gate electrode 206, respectively. In this embodiment, the semiconductor device 10 may optionally include a silicide layer 150 and a salicide barrier layer 160. The silicide layer 150 may be formed on the source region 136 and the drain region 138 respectively, and electrically connect the source region 136 and the drain region 138 to the corresponding contact window 180. The self-aligned metal silicide barrier layer 160 may be formed between two adjacent silicide layers 150. In other embodiments, as shown in FIG. 2, the semiconductor device 20 may not include the silicide layer 150 and the salicide barrier layer 160, and the source electrode 136 and the drain electrode 138 may be directly electrically connected to the corresponding contact window 180.

In some embodiments, as shown in FIG. 3, the semiconductor device 30 may further include an isolation structure 142 disposed between the source region 136 and the drain region 138, so as to increase the voltage applied to the drain.

In some embodiments, as shown in FIG. 4, the third well region 230 of the semiconductor device 40 may include at least one sub-doped region 233 having the first conductivity type, wherein the sub-doped region 233 may be located in the first doped region 232 and spaced apart from the source region 136, so that the body effect can be improved by voltage modulation on the first doped region 232. In other embodiments, as shown in FIG. 5, the at least one sub-doped region 233 may include a plurality of sub-doped regions 233 spaced apart from each other.

6 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. FIG. 7 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present invention.

The semiconductor device 50 shown in FIG. 6 is similar to the semiconductor device 10 shown in FIG. 1, the difference is only that the substrate 100a of FIG. Identical or similar component numbers are not described in further detail below. The semiconductor device 60 shown in FIG. 7 is similar to the semiconductor device 50 shown in FIG. 6, the difference is only that the substrate 100a of FIG. No further details will be given below. The semiconductor device 70 shown in FIG. 8 is similar to the semiconductor device 50 shown in FIG. 6 except that the substrate 100a of FIG. 8 further includes a plurality of second doped regions 134, and other same or similar components are the same or similar. The component number will not be described in further detail below.

Referring to FIG. 6, the semiconductor device 50 may include a substrate 100a having a first conductivity type and a gate structure 200 on the substrate 100a. In this embodiment, the substrate 100a may include a first well region 110a, a plurality of first doped regions 132, a plurality of source regions 136, and a plurality of drain regions 138. The first well region 110a may be located in the substrate 100a and have the second conductivity type. The first well region 110a may include a first portion 110a1, a second portion 110a2, and a third portion 110a3 located under the first portion 110a1 and the second portion 110a2. The first doped region 132 may be located in the first well region 110a and have the first conductivity type. Each of the first doped regions 132 may be located between the first portion 110a1 and the second portion 110a2, and the first portion 110a1 may be located between the first doped regions 132 and under the gate structure 200. The source regions 136 may be respectively in the corresponding first doped regions 132 and have the second conductivity type. The drain regions 138 may be respectively in the second portion 110a2 of the first well region 110a and have the second conductivity type. In this way, since the first doped region 132 having the first conductivity type is located between the first portion 110a1 and the second portion 110a2 having the second conductivity type and on the third portion 110a3 having the second conductivity type, In the case where the source region 136 and the drain region 138 having the second conductivity type are respectively located in the first doped region 132 and the second portion 110a2 of the first well region 110a, the first well region 110a is adjacent to the first doped region 110a. The third part 110a3 of the region 132 will form a first drift region (ie, buried drift region), and a second drift region will be formed in the second part 110a2 of the first well region 110a, so that the length of the drift region can be increased And it can make the semiconductor device have good withstand voltage characteristics. On the other hand, the buried drift region can have a double reduction of surface field (RESURF) effect, so it can improve the withstand voltage of the drain terminal.

In some embodiments, as shown in FIG. 7, the substrate 100 b in the semiconductor device 60 may include a second well region 120 having a second conductivity type. The second well area 120 may be located in the first part 110a1 of the first well area 110a (please refer to FIGS. 6 and 7 at the same time). In this embodiment, the doping concentration of the second well region 120 can be greater than the doping concentration of the first well region 110a, so that the separation distance between two adjacent first doping regions 132 can be shortened, so that the semiconductor device The component size of 60 can be further reduced. In this embodiment, the second well region 120 may be in contact with the adjacent first doped region 132.

In some embodiments, as shown in FIG. 8, the substrate 100 a of the semiconductor device 70 may include a plurality of second doped regions 134 having the second conductivity type. The second doped regions 134 can be respectively located in the second portion 110a2 of the first well region 110a (please refer to FIGS. 6 and 8 at the same time), wherein the drain regions 138 can be respectively located in the corresponding second doped regions 134 . In this embodiment, the doping concentration of the second doping region 134 may be greater than the doping concentration of the first well region 110a, so that the separation distance between the source region 136 and the drain region 138 can be shortened, so that the semiconductor device 70 The component size can be further reduced. In this embodiment, the second doped region 134 may be in contact with the adjacent first doped region 132.

In summary, in the semiconductor device of the above embodiment, since the first doped region having the first conductivity type is in the first well region having the second conductivity type and is located in the second well region having the second conductivity type And the second doped region (or between the first part and the second part with the second conductivity type), therefore, the source region and the drain region with the second conductivity type are respectively located in the first doped region In the case of the second doped region (or the second part), the first well region will form an additional buried drift region near the bottom of the first doped region, which can increase the length of the drift region and can Make the semiconductor device have good withstand voltage characteristics.

10, 20, 30, 40, 50, 60, 70: semiconductor device 100, 100a: substrate 110, 110a: first well area 110a1: first part 110a2: second part 110a3: third part 120: second well area 130 , 230: third well region 132, 232: first doped region 134: second doped region 136: source region 138: drain region 140, 142: isolation structure 150: silicide layer 160: self-aligned metal Silicide barrier layer 170: dielectric layer 180: contact window 200: gate structure 202: gap wall 204: gate dielectric layer 206: gate electrode 233: sub-doped region R _SC : source contact resistance R _S : source resistance of R _CH: channel region resistor R _A: accumulation region resistance R _{JFET: JFET} region resistance _R burieddrift: buried drift region resistance R _drift: drift region resistance R _well: the well region resistor R _D: drain region resistance R _DC : Drain contact resistance

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. 2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. 4 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the invention. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. 6 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. FIG. 7 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present invention.

10: Semiconductor device

100: base

110: The first well area

120: The second well area

130: The third well area

132: The first doped region

134: second doped region

136: Source Region

138: Drain Area

140: Isolation structure

150: Silicide layer

160: Self-aligned metal silicide barrier

170: Dielectric layer

180: contact window

200: gate structure

202: Gap Bi

204: gate dielectric layer

206: gate electrode

R _SC : Source contact resistance

R _S : source region resistance

R _CH : Channel zone resistance

R _A : accumulation zone resistance

R _JFET : JFET area resistance

R _burieddrift : buried drift region resistance

R _drift : drift zone resistance

R _well : well area resistance

R _D : Drain resistance

R _DC : Drain contact resistance

Claims (19)

A semiconductor device includes a substrate with a first conductivity type and a gate structure on the substrate, wherein the substrate includes: The first well area is in the substrate and has a second conductivity type; A second well area in the first well area under the gate structure and having the second conductivity type; and At least one third well area in the first well area and located on at least one side of the second well area, wherein the at least one third well area includes: A first doped region having the first conductivity type; A second doped region having the second conductivity type, wherein the first doped region is between the second well region and the second doped region; A source region in the first doped region and having the second conductivity type; and The drain region is in the second doped region and has the second conductivity type. The semiconductor device according to claim 1, wherein the at least one third well region includes a plurality of third well regions, and the plurality of third well regions are respectively located on opposite sides of the second well region. The semiconductor device according to claim 1, wherein the doping concentration of the second doping region is greater than the doping concentration of the first well region. The semiconductor device according to claim 1, wherein the doping concentration of the second well region is greater than the doping concentration of the first well region. The semiconductor device according to claim 1, further comprising: The isolation structure is arranged between the source region and the drain region. The semiconductor device according to claim 1, wherein the first well region includes a first drift region and a second drift region, and the first drift region is located in the first well adjacent to the bottom of the first doped region In the region, the second drift region is located in the first well region adjacent to the second doped region. The semiconductor device according to claim 1, wherein the at least one third well region includes at least one sub-doped region having the first conductivity type, and the at least one sub-doped region is in the first doped region. In the miscellaneous region and spaced apart from the source region. The semiconductor device according to claim 7, wherein the at least one sub-doped region includes a plurality of sub-doped regions spaced apart from each other. The semiconductor device according to claim 1, wherein the first doped region is in contact with the second doped region and the second well region, respectively. A semiconductor device includes a substrate with a first conductivity type and a gate structure on the substrate, wherein the substrate includes: A first well region in the substrate and having a second conductivity type, wherein the first well region includes a first part, a second part, and a third part located under the first part and the second part; A plurality of first doped regions are in the first well region and have the first conductivity type, wherein each of the plurality of first doped regions is in the first part and the second Between parts, and the first part is between the plurality of first doped regions and under the gate structure; A plurality of source regions are respectively in the corresponding first doped regions and have the second conductivity type; and A plurality of drain regions are respectively in the second part of the first well region and have the second conductivity type. The semiconductor device according to claim 10, wherein the substrate includes a second well region having a second conductivity type, and the second well region is located in the first portion of the first well region. The semiconductor device according to claim 11, wherein the doping concentration of the second well region is greater than the doping concentration of the first well region. The semiconductor device according to claim 11, wherein the second well region is in contact with an adjacent first doped region. The semiconductor device according to claim 10, wherein the substrate includes a plurality of second doped regions having a second conductivity type, and the plurality of second doped regions are respectively located in the first well region. In the second part, the plurality of drain regions are respectively located in the corresponding second doped regions. The semiconductor device according to claim 14, wherein the doping concentration of the second doping region is greater than the doping concentration of the first well region. The semiconductor device according to claim 14, wherein the second doped region is in contact with an adjacent first doped region. The semiconductor device according to claim 10, further comprising: The isolation structure is arranged between the source region and the drain region adjacent to each other. The semiconductor device according to claim 10, wherein the first well region includes a first drift region and a second drift region, and the first drift region is in the third portion of the first well region, so The second drift zone is in the second part of the first well zone. The semiconductor device according to claim 10, wherein the substrate includes a plurality of sub-doped regions having the first conductivity type, and the plurality of sub-doped regions are respectively in the corresponding first doped regions and are in contact with The corresponding source regions are spaced apart.

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