TW202137411A - Via formation for a memory device - Google Patents

Abstract

Methods, systems, and devices for via formation in a memory device are described. A memory cell stack for a memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A via may also be formed in an area outside of the memory array, and the via may protrude from a material that surrounds the via. A material may then be formed above the memory cell stack and also above the via, and the top surface of the barrier material may be planarized until at least a portion of the via is exposed. A subsequently formed material may thereby be in direct contact with the top of the via, while a portion of the initially formed material may remain above the memory cell stack.

Description

Used for through hole formation of memory devices

The technical field relates to the formation of through holes for memory devices.

The following content generally relates to the fabrication of memory cell stacks in cross-point memory arrays and more specifically to the methods of access line granularity modulation and via formation used in memory devices.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming the different states of the memory device. For example, a binary device has two states, which are usually represented as logic "1" or logic "0". In other systems, more than two states can be stored. In order to access the stored information, a component of the electronic device can read or sense the stored state in the memory device. In order to store information, a component of an electronic device can write or program the state in the memory device.

There are various types of memory devices, including magnetic hard drives, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM) , Magnetic RAM (MRAM), Resistive RAM (RRAM), flash memory, phase change memory (PCM) and others. The memory device can be volatile or non-volatile. Even in the absence of an external power supply, a non-volatile memory (such as FeRAM) can maintain its stored logic state for an extended period of time. Volatile memory devices (for example, DRAM) may lose their storage state over time, unless they are periodically renewed by an external power source. There are also various types of memory architectures. For example, an array of PCM memory cells can be arranged in a cross-point structure to form a cross-point memory array.

This patent application claims priority to the U.S. Patent Application No. 16/746,645 named "VIA FORMATION FOR A MEMORY DEVICE" by Economy et al., filed on January 17, 2020. The U.S. Patent Application No. 16/746,645 Part of the continuation of the U.S. Patent Application No. 16/102,494 filed by Economy et al., filed on August 13, 2018, entitled "ACCESS LINE GRAIN MODULATION IN A MEMORY DEVICE", and claimed U.S. Patent Application No. 16 The priority of No. /102,494, each of these cases is assigned to its assignee, and each of them is expressly incorporated herein by reference in its entirety. Some memory devices can be formed at least in part by forming a stack of various materials (for example, a stack of materials can be formed and additional processing steps can be applied to the stack). In some cases, different stacked layers may be formed sequentially, and thus the formation of the stack may involve forming an additional layer on top of the first stacked layer. The structure of the top surface of the first layer (e.g., the surface morphology of the top surface) can result in an additional layer having a similar structure (e.g., surface morphology). For example, if an additional layer of the stack is formed in contact with the top surface of the uneven (e.g., wavy) layer of the first layer, the unevenness or wavy pattern of the first layer can propagate upward to the additional layer, thereby also causing the additional layer The top surface is not flat or wavy.

The corrugated top surface can affect the performance of components that include one or two layers and/or components that include other layers above or on top of the corrugated top surface of additional layers. For example, the material in a given layer or the performance of the entire memory device (e.g., the resistance associated with the components of the memory device, current delivery, or both) may depend on the presence of the top surface of the waveform of the additional layer ( For example, affected by this existence). Therefore, minimizing the waveform of one or more layers can improve the performance of some implemented memory devices.

According to the teachings herein, fabricating a memory cell may include planarizing (e.g., polishing or otherwise smoothing) one layer before forming the next layer. For example, a barrier material can be manufactured using a technique that initially produces a wave-shaped top surface of the barrier material (for example, a top surface that is wavy in thickness or surface morphology or is otherwise uneven). In some cases, the barrier material may be planarized before the metal layer is formed over the barrier material. Planarizing the barrier material before the formation of the metal layer allows the resulting metal layer to have no or at least reduced corrugations (as opposed to corrugations that may already be present in the metal layer formed without the intermediate planarization step of the barrier material). Therefore, the metal layer may have more predictable and uniform performance or otherwise more desirable performance.

For example, the grain size of the metal layer can be increased, resulting in a decrease in resistivity in the access line formed by the metal layer and an increase in current delivery throughout the memory device. Increasing the grain size of the metal layer by planarizing the top surface of the barrier material can also reduce the complexity of the formation of the memory device (for example, the complexity of the etching step is due to the reduced amount of metal used to form the access line) . These and other manufacturing techniques described herein can therefore improve the performance and performance of memory cells and have other benefits that can be appreciated by those who are generally familiar with the technology.

In some cases, through holes may also be formed in the memory device. For example, vias can be formed of conductive materials and can couple components at one layer of the memory device (for example, the access lines of the memory cell array) to the upper or lower layer of the memory device. Components (for example, to access line drives that may be located underneath the memory cell). In some cases, through holes may be formed over the first area of the substrate. The first area may be referred to as a through hole area, a through hole area or a socket area, and the memory array may be formed over the second area of the substrate. The second area may be referred to as an array area or an array area. The via area and the array area may not overlap in some cases.

In some cases, the state in which the memory device is formed (such as the state in which the wavy top surface of the barrier material is initially generated) can create a through hole at least temporarily from one or more materials surrounding the through hole (for example, (At least at one manufacturing level) protruding such that the top surface of the through hole is at least temporarily above the top surface of one or more surrounding materials, wherein one or more of the side walls of the through hole are exposed. For example, the through hole may be surrounded by a dielectric material (for example, formed in the dielectric material), and the through hole may at least temporarily protrude above the top surface of the dielectric material.

A material such as the barrier material described above may be deposited or otherwise formed so as to be over one or more memory cells of the array and over one or more through holes. The material may have benefits when included in the array area (for example, the barrier material may have a beneficial effect on the current characteristics of the memory cell, such as improved reset current characteristics), and for any number of reasons (for example, cost , Complexity), just forming the material over the array area may be impractical or otherwise undesirable. For example, the barrier material may be formed as a blanket layer (sheet) over the area including both the via area and the array area, and possibly over the entire surface of the die or wafer.

In the case where the material is formed so that it initially covers the top surface of the through hole (eg, the protruding portion of the through hole), the planarization material can beneficially remove the material from above the through hole and allow the additional layer before forming the additional layer Direct contact with the through hole. For example, in the case where the barrier material is formed above the protruding part of the through hole, the planarized barrier material can beneficially expose at least a part of the through hole (for example, the top surface of the through hole), so that the subsequently formed access line can be Direct contact with the through hole. In this example, with respect to implementations in which the barrier material remains above the via and therefore between the via and the access line, planarization can therefore reduce the impedance between the via and the access line. In addition, the planarization material can remain above the array area (for example, a portion of the planarized removable material is sufficient to expose the upper surface of the through hole while leaving the remaining lower or less exposed portion of the material), which can provide as described herein Describes or as may otherwise be understood by those skilled in the art one or more associated benefits.

The features of the present invention described above are further described below in the context of the example manufacturing techniques shown in FIGS. 1 to 4 and FIGS. 8 to 11. These and other features of the present invention are additionally illustrated by the example memory array of FIG. 5 and the flowcharts of FIGS. 6 and 7 and FIGS. 12 to 14 regarding the manufacture of memory cells and devices, with reference to the example memory array and Flow chart to describe.

Various techniques can be used to form the materials or components shown in 1 to 5 below. These techniques may include, for example, chemical vapor deposition (CVD), metal organic vapor deposition (MOCVD), physical vapor deposition (PVD), sputter deposition, atomic layer deposition (ALD) or molecular beam epitaxy (MBE) , And other thin film growth technologies. Several techniques may be used to remove material, and these techniques may include, for example, chemical etching (also known as "wet etching"), plasma etching (also known as "dry etching"), or chemical mechanical planarization (CMP).

FIG. 1A and FIG. 1B are schematic descriptions of an intermediate memory array structure illustrating a method of manufacturing a memory cell stack at each manufacturing level.

Referring to Figure 1A, in accordance with some examples, the intermediate array structure 100-a may include a first processed to finally form a memory cell stack 105-a, the second memory cell stack 105-b and the third memory cell stack 105- The state of cell stacking of c is described in further detail below. In some cases, the regions including the first memory cell stack 105-a, the second memory cell stack 105-b, and the third memory cell stack 105-c may be finally configured (eg, manufactured) to include Three distinct memory cells (for example, the storage components in the memory cell stack 105). Therefore, the data stored in the first memory unit can be independent of the data stored in the second and third memory units, and the data stored in the second memory unit can be independent of the data stored in the first and third memory. The data in the volume unit, and the data stored in the third memory unit can be independent of the data stored in the first and second memory units.

Although three memory cell stacks 105-a, 105-b, and 105-c are shown, those skilled in the art should understand that any number of memory cell stacks 105 can be formed in practice. In some cases, manufacturing the memory cell stack 105 may include forming a metal layer 110 over a substrate (not shown). The metal layer 110 can be used to form one or more access lines, such as word lines or bit lines for memory cells included in the memory cell stack 105.

In some cases, manufacturing the memory cell stack 105 may include forming the first electrode material 115 over the metal layer 110. The first electrode material 115 can be used to form one or more bottom electrode components, such as the bottom electrodes corresponding to the memory cell stacks 105-a, 105-b, and 105-c, respectively.

The method may include forming a selector material 120 over the first electrode material 115. The selector material 120 can be used to form one or more selection components, such as selector components corresponding to the memory cell stacks 105-a, 105-b, and 105-c, respectively. In some cases, the selector material 120 may include a chalcogenide material.

The method may include forming a second electrode material 125 over the selector material 120. The second electrode material 125 can be used to form one or more intermediate electrode assemblies, such as the intermediate electrodes corresponding to the memory cell stacks 105-a, 105-b, and 105-c, respectively.

The method may include forming a storage material 130 over the second electrode material 125. The storage material 130 can be used to form one or more storage components, such as storage components corresponding to the memory cell stacks 105-a, 105-b, and 105-c, respectively. In some cases, the storage material 130 may include a chalcogenide material. The storage material 130 may be the same as or different from the selector material 120. In addition, although the example of the intermediate array structure 100-a illustrates the storage material 130 as being above the selector material 120, the positions of the storage material 130 and the selector material 120 are interchangeable in some examples. In addition, in some examples, the memory cell stack 105 and the corresponding memory cell stack may not have the individual selector material 120 and the second electrode material 125, and the storage material 130 may be self-selectable.

The method may include forming a third electrode material 135 over the storage material 130. The third electrode material 135 can be used to form one or more top electrode components, for example, corresponding to the top electrodes of the memory cell stacks 105-a, 105-b, and 105-c, respectively.

The electrode materials 115, 125, and 135 may each include carbon. In some cases, one or more of the electrode materials 115, 125, and 135 may be composed of two sub-layers (not shown in the figure), and thus the electrode formed therefrom may be referred to as a double-layer electrode. In this case, at least one sub-layer may include carbon and may be referred to as a carbon-based material. The electrode materials 115, 125, and 135 may be formed, for example, by deposition techniques such as PVD, CVD or ALD and other deposition techniques.

Each layer of the intermediate array structure 100-a may be initially formed as a blanket layer on the surface area of the entire die or substrate (such as a wafer).

Referring now to the intermediate array structure 100-b of FIG. 1B , isolation regions 140-a and 140-b can be formed between the memory cell stacks 105-a and 105-b and/or 105-b and 105-c in order to The memory cell stack 105 is separated and isolated from each other. The isolation regions 140-a and 140-b can be formed using various etching or other removal techniques (which can use photomasks and photolithography to define features as needed).

FIG. 1B illustrates the cross-section of the intermediate array structure 100-b in one plane (for example, the xy plane) and thus shows the isolation regions 140-a and 140-b as separating memories in one dimension (for example, the x dimension) Body unit stacks 105-a, 105-b, and 105-c, but those who are generally familiar with this technology should understand that similar technology can be applied in another plane (for example, yz plane) to be in another dimension (for example, y dimension) The middle partition memory cell stacks 105-a, 105-b, and 105-c and the corresponding memory cell stacks, so that the memory cell stacks corresponding to the memory cell stacks 105-a, 105-b, and 105-c can each include One column. In addition, those who are generally familiar with the technology should understand that, in some cases, what appears to be separating the isolation regions 140-a and 140-b in FIG. 1B may be combined in different planes and therefore in some alternatives. A continuous isolation area 140 may be included.

2A and 2B illustrate additional intermediate is a memory array of the stacked structure producing method of the memory cell 200. schematically described.

Manufacturing the intermediate array structure 200-a of FIG. 2A may include depositing a dielectric material 205. For example, the isolation regions 140-a and 140-b can be filled with a dielectric material 205. Therefore, the dielectric material 205 can be deposited and inserted between the stacks of separate memory cells. In that case, the dielectric material 205 may surround one or more memory cell stacks 105.

Fabricating the intermediate array structure 200-b of FIG. 2B may include forming a wavy surface 210. In some examples, the undulating surface 210 may be referred to as a “wrapped” surface morphology and may be formed over the third electrode material 135 and the dielectric material 205. For example, the undulating surface 210 may extend across at least some (if not all) of the memory cell stacks 105-a, 105-b, and 105-c and the isolation regions 140-a and 140-b. The cladding surface morphology (which can be replicated in one or more layers above the wavy surface 210) can in some cases improve the structural stability of the memory cell stack 105 and other aspects of the memory array.

In some cases, the waved surface 210 may be formed by polishing or etching the top surface of the third electrode material 135 and the top surface of the dielectric material 205. In some examples, polishing or etching the top surface of the third electrode material 135 and the top surface of the dielectric material 205 can remove the third electrode material 135 and the dielectric material 205 at different rates. For example, the dielectric material 205 can be removed at a greater (faster) rate than the third electrode material 135, which can produce a waved surface 210. Therefore, in some examples, the waved surface 210 may be formed by removing the third electrode material 135 at a first rate and/or removing the dielectric material 205 at a second rate different from the first rate.

In some examples, the waved surface 210 can be formed by applying a CMP process to the top surface of the third electrode material 135 and the dielectric material 205. In some cases, polishing the top surface of the third electrode material 135 may include breaking the vacuum seal associated with the deposition method. In this case, the third electrode material 135 may include carbon oxide, because the polishing of the intermediate array structure 200-b outside the vacuum environment can expose the top of the third electrode material 135 and the dielectric material 205 to oxygen and/or The polishing procedure itself can introduce oxidation. In some other cases, manufacturing the memory cell stack may not include polishing of the third electrode material 135 and the dielectric material 205, and the third electrode material 135 may not include carbon oxide.

3A and 3B barrier material having a method of memory cell stack 305 is a schematic depiction of a structure 300 with additional intermediate memory array for explaining manufacturing. In some cases, the barrier material 305 may be formed over the third electrode material 135 and the dielectric material 205 of the intermediate array structure 300-a.

The intermediate array structure 300-a of FIG. 3A illustrates the deposition of the barrier material 305 on the upper surface of the third electrode material 135 and the upper surface of the dielectric material 205, that is, the barrier material 305 is on the wavy surface described with reference to FIG. 2B 210 deposition above. In some cases, the barrier material 305 may directly contact the third electrode material 135 and the dielectric material 205. Various techniques can be used to deposit the barrier material 305. These techniques may include (but are not limited to) PVD, CVD, MOCVD, sputter deposition, ALD or MBE, and other thin film growth techniques. In some cases, the barrier material 305 may include a metal nitride such as tungsten nitride (WN), a metal silicide such as tungsten silicide (WSix), or a metal silicon nitride such as tungsten silicon nitride (WSiN). In some examples, the barrier material 305 may be an example of a thermal barrier between the carbon of the third electrode material 135 and a layer deposited on top of the barrier material 305 (eg, a metal layer as discussed in more detail below).

When initially formed, the barrier material 305 may include a top surface 310 that is wavy. For example, the barrier material 305 can be deposited on top of the waved surface 210. In some examples, when initially formed, the barrier material 305 may include the uniform thicknesses of the memory cell stacks 105-a, 105-b, and 105-c and the isolation regions 140-a and 140-b and thus may include uniform thicknesses similar to those of The top surface 310 of the wave pattern of the bottom wave surface (for example, wave surface 210) of the barrier material 305.

Although not shown for the sake of clarity and simplicity, it should be understood that in some cases the illustrated array structure may also include the lining material deposited under the barrier material 305. For example, the lining material may be inserted between the bottom surface of the barrier material 305 and the top surface of the third electrode material 135 and the top surface of the dielectric material 205 (for example, between the bottom surface of the barrier material 305 and the waved surface 210).

As Figure 3B of intermediate array structure 300-b as described, in some examples, the top surface 310 barrier material 305 may be planarized or otherwise smoothed. Various techniques can be used to planarize the top surface 310 of the barrier material 305. These techniques may include, but are not limited to, chemical etching, plasma etching, or polishing (e.g., CMP).

In some examples, treating the top surface 310 can change the barrier material 305 from having a uniform thickness to having a varying thickness. For example, the thickness of the barrier material 305 in the region (eg, the second region or the second type region) disposed above the memory cell stack 105-a (for example, overlaps the memory cell stack 105-a) The thickness (for example, the second thickness) may be smaller than the thickness (for example, the first thickness) of the barrier material 305 in the region (for example, the first region) disposed above (for example, overlapping with the isolation region) of the isolation region 140-a. In some examples, as long as the interface corresponding to the wavy surface 210 is maintained, the thickness of the barrier material 305 may not affect the performance of the memory device. For example, the lack of thickness requirements or constraints may allow flexibility in the planarization procedure, as discussed with reference to FIG. 3B.

FIG. 4 may be a schematic depiction of an additional intermediate array structure 400 illustrating a method of manufacturing a memory cell stack with a metal layer 405. In some cases, the metal layer 405 may be formed on the barrier material 305 of the intermediate array structure 400. In some cases, the metal layer 405 may be in direct contact with the top surface 310 of the barrier material 305 (which may have been planarized or otherwise smoothed, as described herein).

The middle array structure 400 of FIG. 4 illustrates the deposition of the metal layer 405 on the top surface 310 of the barrier material 305. Various techniques can be used to deposit the metal layer 405. These techniques may include (but are not limited to) PVD, CVD, MOCVD, sputter deposition, ALD or MBE, and other thin film growth techniques. In some cases, the metal layer 405 may be an example of access lines (eg, word lines, bit lines, etc.). For example, the metal layer 405 may include a high melting point metal such as tungsten, tantalum, or molybdenum. In some cases, the barrier material 305 (for example, including WN, WSix, or WSiN) may be deposited between the third electrode material 135 (for example, including carbon) and the metal layer 405 (for example, including tungsten, tantalum, or molybdenum). Provide reset current benefits or other benefits.

In some cases, memory cell stack 105-a may include center point 410-a and memory cell stack 105-b may include center point 410-b. The center point 410-a and the center point 410-b may be examples of the center of the memory cell stack. The distance 415 may be an example of the distance between the center point 410-a and the center point 410-b. For example, the distance 415 may be an example of a cell pitch distance.

In some cases, where there is no planarization or other smoothing of the metal layer 405, the metal layer 405 may have an average grain size substantially corresponding to (eg, substantially equal to) the distance 415. For example, in the absence of planarization or other smoothing of the metal layer 405, the average crystal grain size of the metal layer 405 may substantially correspond to the surface morphology of the corrugated surface 210, which may in turn substantially correspond to the distance 415.

However, where the top surface 310 of the barrier material 305 is planarized or otherwise smoothed as described herein, the metal layer 405 may have an average grain size greater than the distance 415 (eg, greater than twice the distance 415). For example, in the case where the top surface 310 of the barrier material 305 is planarized or otherwise smoothed as described herein, the grain size of the metal layer 405 may be close to or substantially equal to the metal included in the metal layer 405 The observed grain size of the blanket film deposition of the material (for example, approximately 250 nm or in some cases up to 300 nm or 350 nm, where the metal layer 405 includes tungsten, tantalum, or molybdenum). In some cases, increasing the average grain size of the metal layer 405 can result in reduced resistance of access lines in the memory device, increased current delivery, and opportunities for reducing the thickness of the metal layer 405. In some cases, planarizing the top surface 310 of the barrier material 305 can reduce the etching complexity of the memory device (for example, because the metal layer 405 can be formed using a reduced amount of metal) and increase the structural yield of the memory device.

Although not shown for the sake of clarity and simplicity, it should be understood that the illustrated array structure may be formed above or below other layers (for example, above the substrate), and other layers may further include various peripheral and supporting circuits. For example, complementary metal oxide semiconductor (CMOS) transistors can be incorporated into row and column driver circuits and sense amplifier circuits, and such circuits can be connected to the sockets of the memory array via the rows and columns described above And wiring. In addition, other layers may include one or more memory arrays, or the "platform" of the array (the structure illustrated in the examples of FIGS. 1 to 4) may correspond to a platform of the memory array and may be in the memory array. Any number of additional platforms above or below.

Although not shown for clarity and simplicity of illustration, it should be understood that the illustrated array structure may also include a conformal liner deposited adjacent to the dielectric material 205 (for example, in contact with the dielectric material 205). For example, a conformal liner may be inserted between the side surface of the dielectric material 205 and the side surface of the memory cell stack.

Although the processing in the x-y plane is described with reference to FIGS. 1 to 4, those skilled in the art should understand that similar processing can continue similar procedures in the other direction (for example, as will be shown by a cross-section in the y-z plane). For example, the memory array formation can continue to stack definitions in the orthogonal (eg, y) direction to form access lines from the metal layer 405 and generate pillars for each memory cell stack 105 and thereby transfer from adjacent The electrodes, selector components, and storage components of the memory cell stack 105 are isolated (insulated) from each other. In addition, such processing steps as described with reference to FIGS. 1 to 4 can be repeated to form any number of memory device levels.

FIG. 5 illustrates an example memory array 500 that supports granular modulation of access lines in a memory device according to various examples of the present invention. The memory array 500 can also be referred to as an electronic memory device. The memory array 500 includes a memory cell stack 505 that can be programmed to store different states. Each memory cell stack 505 may include one or more memory cells. In some cases, the memory cell stack 505 can be programmed to store one of two states, representing a logical "0" and a logical "1". In some cases, the memory cell stack 505 can be configured to store one of more than two logic states. The memory cell stack 505 may be an example of the memory cell stack 105 as described with reference to FIGS. 1 to 4.

The memory array 500 may be a three-dimensional (3D) memory array, where two-dimensional (2D) memory arrays are formed on top of each other. Compared with a 2D array, this can increase the number of memory cells that can be formed on a single die or substrate, which can reduce production costs or increase the performance of the memory array, or both. According to the example depicted in FIG. 5, the memory array 500 includes two levels of the memory cell stack 505, and therefore can be regarded as a three-dimensional memory array; however, the number of levels is not limited to two. The levels can be aligned or positioned so that the memory cell stack 505 can be substantially aligned with each other across the levels.

Each row of the memory cell stack 505 is connected to the access line 510 and the access line 515. The access line 510 and the access line 515 may be examples of the corresponding metal layer 110 or the metal layer 405 or formed by the corresponding metal layer 110 or the metal layer 405, as described with reference to FIGS. 1 to 4. The access line 510 and the access line 515 may also be referred to as a word line 510 and a bit line 515, respectively. The bit line 515 can also be referred to as a digit line 515. The reference systems for word lines and bit lines, or the like are interchangeable without loss of understanding or manipulation.

The word line 510 and the bit line 515 may be substantially perpendicular to each other to create an array. Two memory cell stacks 505 can share a common conductive line such as digit line 515. That is, the digit line 515 can electronically communicate with the bottom electrode of the upper memory cell stack 505 and the top electrode of the lower memory cell stack 505. Therefore, in some cases, a single access line 510, 515 can serve as the first group for one or more memory cell stacks 505 (e.g., one or more memory cells below the access lines 510, 515). The character line 510 of the group of cell stacks 505) and can serve as the second group for one or more memory cell stacks 505 (for example, one or more memory cells above the access lines 510, 515) Stack the bit line 515 of the group 505). Other configurations may be possible; for example, the memory cell stack 505 may include an asymmetric electrode interface with the memory storage device. In some examples, the die size of the access lines 510 and 515 can be increased by planarizing the top surface of the barrier material in the memory cell stack 505, as described herein, including referring to FIGS. 1 to 4.

Generally speaking, a memory cell stack 505 can be located at the intersection of two conductive lines (such as the word line 510 and the digit line 515). This intersection point can be called the address of the memory cell. The target memory cell stack 505 can be the memory cell stack 505 located at the intersection of the energized word line 510 and the digit line 515; that is, both the word line 510 and the digit line 515 can be energized so as to be at their intersection point The memory cells included in the memory cell stack 505 are read or written. Other memory cell stacks 505 that are in electronic communication with the same word line 510 or digit line 515 (eg, connected to the same word line 510 or digit line 515) may be referred to as non-target memory cell stacks 505.

As discussed above, electrodes (eg, the third electrode material 135 and the first electrode material 115) may be coupled to the memory cell stack 505 and the word line 510 or the digit line 515, respectively. The term electrode may refer to an electrical conductor, and in some cases, may be used as an electrical contact to the memory cell stack 505. The electrodes may include traces, wires, conductive lines, conductive layers, or the like that provide conductive paths between elements or components of the memory array 500.

Operations such as reading and writing can be performed on the memory cell stack 505 by activating or selecting the word line 510 and digit line 515. Activating or selecting the word line and digit line can include applying voltage or current to each Don't line it. The word line 510 and the digit line 515 may be made of conductive materials such as metals (for example, copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti), etc.), metal alloys , Carbon, conductive doped semiconductors or other conductive materials, alloys, and compounds.

The access memory cell stack 505 can be controlled by the column decoder 520 and the row decoder 530. For example, the column decoder 520 may receive the column address from the memory controller 540, and activate the appropriate word line 510 based on the received column address. Similarly, the row decoder 530 receives the row address from the memory controller 540 and activates the appropriate digit line 515. Therefore, by activating the word line 510 and the digit line 515, the memory cell stack 505 can be accessed.

After being accessed, the memory cell stack 505 can be read or sensed by the sensing component 525. For example, the sensing component 525 can be configured to determine the stored logic state of the memory cell stack 505 based on a signal generated by accessing the memory cell stack 505. The signal may include voltage or current, and the sensing component 525 may include a voltage sense amplifier, a current sense amplifier, or both. For example, a voltage can be applied to the memory cell stack 505 (using the corresponding word line 510 and digit line 515) and the magnitude of the resulting current can depend on the resistance of the memory cell stack 505, which can reflect the resistance of the memory cell stack 505 Stack 505 the stored logic state. Likewise, current can be applied to the memory cell stack 505 and the magnitude of the voltage used to generate the current can depend on the resistance of the memory cell stack 505, which can reflect the logic state stored by the memory cell stack 505. The sensing component 525 may include various transistors or amplifiers to detect and amplify the signal, which may be called a latch. The detected logic state of the memory cell stack 505 can then be output as an output 535. In some cases, the sensing component 525 may be part of the row decoder 530 or the column decoder 520. Alternatively, the sensing component 525 may be connected to, or electronically communicate with, the row decoder 530 or the column decoder 520.

The memory controller 540 can control the operation of the memory cell stack 505 (reading, writing, rewriting, renewing, discharging, etc.) through various components (such as the column decoder 520, the row decoder 530, and the sensing component 525) ). In some cases, one or more of the column decoder 520, the row decoder 530, and the sensing component 525 may be co-located with the memory controller 540. The memory controller 540 can generate a column address signal and a row address signal to activate the desired word line 510 and digit line 515. The memory controller 540 can also generate and control various voltages or currents used during the operation of the memory array 500. For example, it can apply a discharge voltage to the word line 510 or the digit line 515 after accessing one or more memory cell stacks 505.

In general, the amplitude, shape, or duration of the applied voltage or current discussed herein can be adjusted or changed and can be different for the various operations discussed in operating the memory array 500. In addition, one, multiple, or all memory cell stacks 505 in the memory array 500 can be accessed at the same time; for example, multiple or all cells of the memory array structure 100 can be accessed during a reset operation. It is assumed that all memory cell stacks 505 or a group of memory cell stacks 505 are set to a single logic state in operation.

FIG. 6 shows a flowchart illustrating a method 600 for adjusting the granularity of access lines in a memory device according to an embodiment of the present invention. The operations of method 600 may be implemented according to various manufacturing techniques as described herein. For example, the operations of the method 600 can be implemented by manufacturing techniques as discussed with reference to FIGS. 1 to 5.

At 605, a stack of memory cells in a cross-point memory array can be formed. The memory cell stack may include a storage element. The operation of 605 can be performed according to the method described herein. In some instances, the aspect of operation of 605 can be performed using the manufacturing techniques discussed with reference to FIGS. 1 to 5.

At 610, barrier material may be formed over the stack of memory cells. The operation of 610 can be performed according to the method described herein. In some instances, the aspect of operation of 610 can be performed using the manufacturing techniques discussed with reference to FIGS. 1 to 5.

At 615, the top surface of the barrier material may be planarized. The operation of 615 can be performed according to the method described herein. In some instances, the aspect of operation of 615 can be performed using the manufacturing techniques discussed with reference to FIGS. 1 to 5.

At 620, the metal layer of the access line of the cross-point memory array can be formed. In some cases, the metal layer may be formed on the top surface of the barrier material after planarization. In some instances, the aspect of operation of 620 can be performed using the manufacturing techniques discussed with reference to FIGS. 1 to 5.

In some instances, the device can perform the manufacturing aspects described above using general-purpose or special-purpose hardware. The device may include features, components, or instructions for forming a stack of memory cells in a cross-point memory array, the stack of memory cells including storage elements. The device may further include features, members, or instructions for forming barrier material over the stack of memory cells. The device may also include features, components, or instructions for flattening the top surface of the barrier material. The device may additionally include features, components, or instructions for forming the metal layer of the access lines of the cross-point memory array on the top surface of the barrier material.

In some examples of the methods and devices described above, planarizing the top surface of the barrier material may include applying a CMP process to the top surface of the barrier material. In some examples of the method and apparatus, forming the barrier material may include depositing the barrier material via a PVD process, a CVD process, an ALD process, or any combination thereof. In some cases, forming the memory cell stack may include forming an electrode layer, where the electrode layer includes carbon. In some cases, forming the electrode layer may include depositing the electrode layer via a PVD process, a CVD process, an ALD process, or any combination thereof.

Some examples of the methods and devices described above may further include procedures, features, components, or instructions for removing at least a portion of the electrode layer. In some examples of the methods and devices described above, the metal layer is in contact with the top surface of the barrier material. In some cases, forming the memory cell stack may include depositing a dielectric material, where the dielectric material is inserted between the memory cell stack and the second memory cell stack. Some examples of the methods and devices described above may further include procedures, features, components, or instructions for removing a portion of the dielectric material and a portion of the electrode layer of the memory cell stack.

In some examples of the methods and devices described above, the removal of the electrode layer occurs at a first rate and the removal of the dielectric material occurs at a second rate different from the first rate, wherein the removal of the dielectric material A part and a part of the electrode layer are formed on the corrugated surface under the barrier material. In some examples of the methods and devices described above, the barrier material includes WN, WSix, or WSiN, and the metal layer of the access line includes tungsten, tantalum, or molybdenum.

FIG. 7 shows a flowchart illustrating a method 700 for adjusting the granularity of access lines in a memory device according to an embodiment of the present invention. The operations of method 700 may be implemented according to various manufacturing techniques as described herein. For example, the operations of the method 700 can be implemented by manufacturing techniques as discussed with reference to FIGS. 1 to 5.

At 705, a stack of memory cells can be formed. The operation of 705 can be performed according to the method described herein. In some instances, the aspect of operation of 705 can be performed using the manufacturing techniques discussed with reference to FIGS. 1 to 5.

At 710, a barrier material with a top surface and a bottom surface can be formed above the memory cell stack. The operation of 710 can be performed according to the method described herein. In some instances, the aspect of operation of 710 can be performed using the manufacturing techniques discussed with reference to FIGS. 1 to 5.

At 715, the top surface of the barrier material can be reduced by polishing the top surface of the barrier material. The operation of 715 can be performed according to the method described herein. In some instances, the aspect of operation of 715 can be performed using the manufacturing techniques discussed with reference to FIGS. 1 to 5.

At 720, a metal layer for the access line can be formed over the top surface of the barrier material. The operation of 720 can be performed according to the method described herein. In some instances, the aspect of operation of 720 can be performed using the manufacturing techniques discussed with reference to FIGS. 1 to 5.

In some instances, the device can perform the manufacturing described using general-purpose or special-purpose hardware. The device may include features, components, or instructions for forming a stack of memory cells. The device may additionally include features, members, or instructions for forming barrier materials with top and bottom surfaces above the stack of memory cells. The device may further include features, members, or instructions for reducing the top surface of the barrier material by polishing the top surface of the barrier material. The device may further include features, components, or instructions for forming the metal layer of the access wire above the top surface of the barrier material.

Some examples of the methods and devices described above may further include procedures, features, components, or instructions for etching the top surface of the electrode layer of the memory cell stack. Some examples of the methods and devices described above may further include procedures, features, components, or instructions for etching the top surface of the dielectric material inserted between the electrode layer and the second memory cell stack. Some examples of the methods and devices described above may further include procedures, features, components, or instructions for forming a wave surface based at least in part on etching the electrode layer on the top surface and etching the top surface of the dielectric material.

Some examples of the methods and devices described above may further include procedures, features, components, or instructions for forming barrier material on top of the wavy surface. In some examples of the methods and devices described above, forming the barrier material may include forming an interface between the electrode layer of the memory cell stack and the bottom surface of the barrier material, wherein the interface has a wave pattern. In some examples of the method and apparatus, reducing the top surface of the barrier material may include changing the barrier material from a uniform thickness to a variable thickness by applying a CMP process to the top surface of the barrier material.

It should be noted that the method described above describes possible implementations, and the operations and steps can be reconfigured or modified in other ways, and other implementations are possible. In addition, two or more embodiments of these methods can be combined.

In some cases, devices, systems, or devices manufactured according to various manufacturing techniques as described herein may include a stack of memory cells in a cross-point memory array, a stack of memory cells containing storage elements, and a stack of memory cells arranged in a memory cell stack. The upper barrier material, the barrier material including the planarized top surface, and the metal layer of the access line contacting the planarized top surface of the barrier material.

In some examples of the devices, systems, or devices described above, the barrier material may include a wavy bottom surface. In some cases, the barrier material may have a first thickness in the first area above the memory cell stack and the barrier material may have a second thickness in the second area, where the second area is inserted in the first area and in the second area. Between the third area above the memory cell stack.

In some examples, the device, system, or apparatus may further include a dielectric material stacked around the memory cell, wherein the dielectric material has a top surface in contact with the barrier material, and the second region is above the dielectric material. In some cases of the devices, systems, or devices described above, the second thickness may be less than the first thickness.

In some examples, the barrier material may include a metal nitride such as WN, a metal silicide such as WSix, or a metal silicon nitride such as WSiN, and the metal layer may include a high melting point metal such as tungsten, tantalum, or molybdenum. The device, system or device may also include an electrode layer in the memory cell stack, wherein the electrode layer has a top surface in contact with the bottom surface of the barrier material, and the interface between the top surface of the electrode layer and the bottom surface of the barrier material and the metal layer Separate a varying distance. In some other examples, the electrode layer may include carbon.

In some examples, the center of the memory cell stack may be separated from the center of the immediately adjacent memory cell stack by a cell pitch distance. In some cases, the metal layer may have an average grain size greater than twice the cell pitch distance.

8A and 8B used for explaining a schematic depiction of an additional intermediate memory array structure manufacturing method of the memory device.

The intermediate array structure 800-a of FIG. 8A may include the aspect of the intermediate array structure 200-a as described herein with reference to FIG. 2A. The middle array structure 800-a may further include a dielectric material 805 and a through hole 810. The dielectric material 805 may be formed in an area beside (eg, adjacent to) any number of memory cell stacks 105. For example, the dielectric material 805 can be formed in the via area, which can be over the first area of the substrate, and the memory cell stack 105 can be formed in the array area, which can be over the second area of the substrate. In some cases, the first area and the second area of the substrate may not overlap.

The space (area) in the memory device occupied by the dielectric material 805 may have previously included any number of other materials or structures, such as some or all of the materials included in the memory cell stack 105. For example, the layer of the intermediate array structure 100-a as described herein with reference to FIG. 1A may be formed as a blanket layer or otherwise may have previously occupied the space occupied by the dielectric material 805. In some cases, the additional memory cell stack 105 may be previously formed in the space occupied by the dielectric material 805.

The materials or structures previously in the space occupied by the dielectric material 805 may have been etched away or otherwise removed using any suitable technique (such as the various removal techniques described herein). In some cases, the material or structure previously in the space occupied by the dielectric material 805 may have been removed based on a masking step that can be called a cut-off mask, which can be used to define the array area (and therefore the memory Volume array) and the boundary between the array areas or the via areas outside the array areas in other ways. Removal of the material or structure previously in the space occupied by the dielectric material 805 can create pores (eg, trenches) that can then be filled with the dielectric material 805. The dielectric material 805 may have been deposited or otherwise formed using any suitable technique, such as the various formation techniques described herein. In some examples, the dielectric material 805 may be the same material as the dielectric material 205 formed between the memory cell stacks 105. In other examples, the dielectric material 805 may be a different material from the dielectric material 205 formed between the memory cell stacks 105. For example, the dielectric material 805 may include an oxide, and the dielectric material 205 may include the same or different oxides.

The through hole 810 may be formed by etching the dielectric material 805 to remove a portion of the dielectric material 805. Portions of the dielectric material 805 may be etched or otherwise removed using any suitable technique (such as the various removal techniques described herein). Spaces (eg, holes, pores) can thereby be formed in the dielectric material 805, and the via material can then be deposited or otherwise formed in the space to form the vias 810. The through hole 810 can therefore be surrounded by the dielectric material 805. In addition, a dielectric material 805 (possibly and any number of other materials) may be between the via 810 and the memory cell stack 105. As an example, the via material may be tungsten (W). The space and therefore the through hole 810 may extend through the dielectric material 805. In some cases, the top surface of the through hole 810 that is initially formed may have the same (or at least substantially the same) height as the top surface of the dielectric material 805.

In some cases, the through holes 810 may be formed over any number of other through holes (not shown for clarity), and these other through holes may be aligned with the through holes 810 (for example, coaxial) but included in the In other layers below those layers shown in Figure 8A (e.g., extending through other layers). Therefore, any number of vias 810 can be connected to collectively form interconnects through any number of layers within the memory device.

In addition, although only one through hole 810 is shown for clarity of illustration, it should be understood that any number of similar or similar through holes can be formed in the dielectric material 805 at the same time. For example, a group of through holes may be located in the same through hole area as the through holes 810 and at the same layer or level of the memory device (for example, also formed in the dielectric material 805). In addition, although the through hole 810 is described and illustrated as being formed in the dielectric material 805 and surrounded by the dielectric material 805, it should be understood that the through hole 810 may alternatively be formed in any other type of material (including a collection of multiple materials). ) Or surrounded by any other type of material.

Referring now to FIG. 8B , manufacturing the intermediate array structure 800-b can cause a portion of the through hole 810 to protrude from the surrounding dielectric material 805. In some cases, the protruding portion may be derived from polishing or etching (for example, applying a first planarization process to) the top surface of the intermediate array structure 800-a (and therefore the top surface of the dielectric material 805 and the top surface of the via 810). ) Until the through hole 810 protrudes from the surface of the dielectric material 805. In some examples, the protruding portion of the through hole 810 can be formed by applying a CMP process to the dielectric material 805 and the top surface of the through hole 810.

For example, polishing or etching the top surface of the dielectric material 805 and the top surface of the material included in the through hole 810 can remove the dielectric material 805 and the material included in the through hole 810 at different rates. For example, the dielectric material 805 can be removed at a greater (faster) rate than the material included in the through hole 810, which can create the protrusion of the through hole 810. Therefore, in some examples, the protruding portion of the through hole 810 may be removed by removing the dielectric material 805 at a first rate and/or removing the material included in the through hole 810 at a second rate different from the first rate. form. In this case, the height of the top surface of the through hole 810 (e.g., the protruding portion) can be made greater than the height of the top surface of the dielectric material 805 (e.g., this is because the top surface of the dielectric material 805 can lie above the substrate The height reduction is relatively large). Therefore, in some cases, one or more of the sidewalls of the through hole 810 may be exposed and extend above the top surface of the dielectric material 805.

In some examples, the protruding portion of the through hole 810 can be formed due to one or more of the same procedures that can produce the waved surface 210 and the intermediate array structure 200-b described above with reference to FIG. 2B. For example, the same CMP process that produces the wavy surface 210 can also cause the via 810 to protrude from the surrounding dielectric material 805.

Although the example of FIG. 8B illustrates the upper surface of the through hole 810 as being above the uppermost part of the memory cell stack 105 (higher than the uppermost parts), it should be understood that in other examples, the upper surface of the through hole 810 is The uppermost parts of the memory cell stack 105 are at the same height or below the uppermost parts (lower than the uppermost parts). For example, in some cases, the upper surface of the dielectric material 805 in the through hole region including the through hole 810 may be recessed (depressed) than the upper surface of the dielectric material 205 in the isolation region 140 (for example, due to The polishing or etching process such as the polishing or etching process described with reference to FIG. 2B) to a wider range, and therefore the through hole 810 can protrude from the dielectric material 805, and the upper surface of the through hole 810 is not necessarily the largest than the memory cell stack 105. The upper part is at a greater height. In some cases, the through hole 810 may protrude from the dielectric material 805 even though the upper surface through hole 810 is at a lower height than the lowest part of the isolation region 140.

FIG. 9 is a schematic depiction of an additional intermediate array structure 900-b used in the method of manufacturing a memory device. In some cases, the barrier material 305 may be formed over the through holes 810 of the intermediate array structure 900-b, and may also be formed on the third electrode material 135, the dielectric material as described in the example of the intermediate array structure 900-b Some or all of the electrical material 205 and the dielectric material 805 are above. Therefore, in some cases, the barrier material 305 may be deposited over the waved surface 210 described with reference to FIGS. 2B and 8B and over the dielectric material 805 and the via 810. The barrier material 305 may be deposited or otherwise formed as, for example, a blanket layer, and thus may directly contact the top surfaces of the third electrode material 135, the dielectric material 205, the dielectric material 805, and the through hole 810.

Various techniques can be used to deposit the barrier material 305. These techniques may include (but are not limited to) PVD, CVD, MOCVD, sputter deposition, ALD or MBE, and other thin film growth techniques. In some cases, the barrier material 305 may include nitride. For example, the barrier material 305 may include a metal nitride such as tungsten nitride (WN), a metal silicide such as tungsten silicide (WSix), or a metal silicon nitride such as tungsten silicon nitride (WSiN). However, it should be understood that the barrier material 305 may alternatively include any other suitable barrier material. In some examples, the barrier material 305 may be an example of a thermal barrier between the carbon of the third electrode material 135 and a layer deposited on top of the barrier material 305 (eg, a metal layer as discussed in more detail below).

When initially formed, the barrier material 305 may include a top surface 310 that is wavy. For example, the barrier material 305 can be deposited on top of the waved surface 210. In some examples, when initially formed, the barrier material 305 may be included in the memory cell stacks 105-a, 105-b, and 105-c, the isolation regions 140-a and 140-b, the dielectric material 805, and the through holes 810. The uniform thickness above. Therefore, when initially formed, the barrier material 305 may include a top surface 310 that includes a wave pattern similar to the bottom wave surface of the barrier material 305 (eg, wave surface 210). Additionally or alternatively, the top surface 310 of the barrier material 305 may be a mirror surface or otherwise have a surface morphology similar to the cross section of the top surface of the dielectric material 805 and the through hole 810 (including the protruding portion of the through hole 810). For example, the barrier material 305 may be in contact with both the top surface of the through hole 810 and one or more (for example, all) sidewalls of the through hole, or in other ways with all surfaces of the protruding portion of the through hole 810).

The presence of the barrier material 305 above the array area (for example, above the memory cell stack 105 and the isolation region 140) may have one or more as described elsewhere herein or as otherwise understood by those skilled in the art. benefit. As an example, the presence of the barrier material 305 above the array area may provide a reset current benefit or other electrical benefit associated with programming the memory material 130 or otherwise operating the memory array including the memory cell stack 105. As another example, the presence of barrier material 305 above the array area can provide structural benefits related to the use of the lower wave surface 210 and the cladding surface morphology. However, the presence of the barrier material 305 above the via 810 (e.g., above the via region) may have one or more disadvantages, such as the via 810 and any structure subsequently formed over the via 810 (e.g., subsequently formed The increased impedance between access lines or other vias 810 at higher levels of the memory device (meaning directly or indirectly coupled to vias 810).

FIG. 10 is a schematic depiction of an additional intermediate array structure 1000 used in the method of manufacturing a memory device. As illustrated in the intermediate array structure 1000, in some examples, after the barrier material 305 is formed, the top surface 310 of the barrier material 305 may be planarized or otherwise smoothed. Various techniques can be used to planarize the top surface 310 of the barrier material 305. These may include (but are not limited to) CMP. In some examples, the top surface 310 of the barrier material 305 may be planarized using one or more of the same procedures described above with reference to FIG. 3B and the intermediate array structure 300-b. For example, the same CMP process can be used to planarize or otherwise smooth over the memory cell stack 105 and the dielectric material 205 (e.g., over the array area) and over the via 810 and the dielectric material 805 (e.g., Above the through hole area) the surface 310 of the barrier material 305.

In some cases, the top surface of the barrier material 305 may be polished or otherwise processed (eg, removed) until at least one top surface of the protruding through hole 810 is exposed. The barrier material 305 may remain above the memory cell stack 105 and the isolation region 140 (eg, above the array area) after the planarization process, and in some cases also above the dielectric material 805. For example, the barrier material 305 may remain above other aspects of the intermediate array structure 1000-b after the planarization process, because the thickness of the barrier material 305 (for example, as described with reference to FIG. 9) formed initially is greater than The amount of the through hole 810 protruding from the dielectric material 805 (for example, greater than the height of one or more sidewalls of the protruding portion of the through hole 810).

Although the example of FIG. 10 illustrates the upper surface of the through hole 810 as being above the uppermost part of the memory cell stack 105 (higher than the uppermost part), it should be understood that in other examples, the upper surface of the through hole 810 is on the memory The uppermost part of the bulk cell stack 105 or even the lowermost part of the isolation region 140 is at the same height or below (below), for example, as explained above with reference to FIG. 8. In at least some such examples, the polished (smoothed) upper surface 310 of the barrier material 305 may not be completely above the array area and at the same height above the via area.

In some cases, after planarization, the barrier material 305 may remain in contact with at least a portion of one or more sidewalls of the through hole 810. For example, the sidewall of the protruding part of the through hole 810 can be kept in contact with the barrier material 305. The barrier material 305 can also be held above the dielectric material 805. In this case, a part of the through hole 810 may be at least partially surrounded by the barrier material. Although the example of FIG. 10 shows the top surface of the through hole 810 as being flush with the top surface of the barrier material 305, it should be understood that in some cases the through hole 810 may pass through a through hole protruding from the dielectric material 805 in reference to FIG. 8B. The similar mechanism described by the hole 810 protrudes from the top surface of the barrier material 305.

Removing (or at least reducing) the corrugations in the upper surface 310 of the barrier material 305 may have one or more benefits as described elsewhere herein or as otherwise understood by those skilled in the art, such as removing (or at least reducing ) The corrugations subsequently formed in the layer above the barrier material and thereby promote larger grain sizes in the subsequently formed access lines. In addition, removing the barrier material 305 from above the through hole 810 can reduce the direct or indirect coupling between the through hole 810 and the through hole 810 (for example, an access line or other through hole 810 formed subsequently) that is directly or indirectly coupled to the through hole 810. The impedance between any structures of, while avoiding additional cost, complexity, or other shortcomings that can be associated with forming the barrier material 305 so as not to initially cover the via 810.

Although not shown for the sake of clarity and simplicity, it should be understood that in some cases the illustrated array structure may also include an inner lining or other additional materials formed under the barrier material 305 (for example, formed as a blanket layer) . For example, the lining material may be inserted between the bottom surface of the barrier material 305 and the top surface of the third electrode material 135 and the top surface of the dielectric material 205 (for example, between the bottom surface of the barrier material 305 and the waved surface 210). In some examples, when initially formed, the lining material may be inserted between the bottom surface of the barrier material 305 and the top surface of the through hole 810 and the top surface of the dielectric material 805. The lining material can be removed from the top surface of the through hole 810 using the same or similar processing operation as that described for removing the barrier material 305 from above the top surface of the through hole.

FIG. 11 is a schematic depiction of an additional intermediate array structure 1100 used in the method of manufacturing a memory device. In some cases, the metal layer 405 may be formed over the barrier material 305. For example, the metal layer 405 may be in direct contact with the top surface 310 of the barrier material 305 (which may have been planarized or otherwise smoothed, as described herein). In some examples, the metal layer 405 may directly contact the via 810. For example, the metal layer 405 may extend from above the memory cell stack to above the through holes (for example, the metal layer 405 may be deposited or otherwise formed as a blanket layer).

In some such cases, since the barrier material 305 has been previously removed from the top surface of the through hole 810, the metal layer 405 may be in contact with the top surface of the through hole 810. The direct contact between the metal layer 405 and the via 810 can support reduced contact resistance, thereby improving overall memory device performance. For example, access lines (e.g., bit lines or word lines of memory cells corresponding to the memory cell stacks 105-a, 105-b, and 105-c) can be subsequently formed by the metal layer 405, and The access line can be in direct contact with the through hole 810, thereby reducing the gap between the access line and the through hole 810 and therefore between the access line and any other structure that can be coupled with the through hole 810 (for example, for access line The impedance between the driver). These and other manufacturing techniques described herein can therefore improve the performance and performance of memory cells and other benefits that can be appreciated by those who are generally familiar with the technology.

Various techniques can be used to form the metal layer 405. These techniques may include (but are not limited to) PVD, CVD, MOCVD, sputter deposition, ALD or MBE, and other thin film growth techniques. In some cases, the metal layer 405 may include a high melting point metal, such as tungsten, tantalum, or molybdenum. In some cases, the barrier material 305 (for example, including WN, WSix, or WSiN) may be deposited between the third electrode material 135 (for example, including carbon) and the metal layer 405 (for example, including tungsten, tantalum, or molybdenum). Provide reset current benefits or other benefits.

Although not shown for the sake of clarity and simplicity, it should be understood that the illustrated array structure may be formed above or below other layers (for example, above the substrate), and it may also include various peripherals and supporting circuits; and The hole 810 may couple the metal layer 405 or a structure formed therein with a structure at a higher or lower layer. For example, complementary metal oxide semiconductor (CMOS) transistors can be incorporated into row and column driver circuits and sense amplifier circuits, and vias 810 can couple the access lines formed in the metal layer 405 to the corresponding driver. In addition, other layers may include one or more memory arrays, or the "platform" of the array (the structure illustrated in the examples of FIGS. 8 to 11) may correspond to a platform of the memory array and may be located on the memory array. Any number of additional platforms above or below.

FIG. 12 shows a flowchart illustrating one or more methods 1200 for manufacturing a memory device according to aspects of the invention. The operations of method 1200 can be used to form a memory device or component thereof, as described herein. For example, the operation of the method 1200 can be implemented by the manufacturing technique as described with reference to FIG. 8 to FIG. 11.

At 1205, a stack of memory cells including storage elements may be formed over the first area of the substrate. The operation of 1205 can be performed according to the method described herein. In some examples, the operation aspect of 1205 can be performed using manufacturing techniques as described with reference to FIGS. 8 to 11.

At 1210, a through hole extending through the dielectric material may be formed over the second area of the substrate. The operation of 1210 can be performed according to the method described herein. In some examples, the operation aspect of 1210 can be performed using manufacturing techniques as described with reference to FIGS. 8-11.

At 1215, barrier material can be formed over the memory cell stack and vias. The operation of 1215 can be performed according to the method described herein. In some examples, the operation aspect of 1215 can be performed using manufacturing techniques as described with reference to FIGS. 8-11.

At 1220, the top surface of the barrier material can be planarized. The operation of 1220 can be performed according to the method described herein. In some examples, the aspect of operation of 1220 can be performed using the manufacturing techniques described with reference to FIGS. 1 to 6.

At 1225, the metal used for the access lines of the memory array can be formed over the barrier material. The operation of 1225 can be performed according to the method described herein. In some examples, the operation aspect of 1225 can be performed using manufacturing techniques as described with reference to FIGS. 8-11.

In some examples, a device as described herein may perform one or more methods, such as method 1200. The device may include features, components, or instructions for performing the following operations (for example, a non-transitory computer-readable medium storing instructions executable by a processor): a stack of memory cells including storage elements is formed over the first area of the substrate ; Forming a through hole extending through the dielectric material above the second area of the substrate; forming a barrier material above the memory cell stack and through holes; planarizing the top surface of the barrier material; and forming a memory above the barrier material The metal of the access line of the array.

Some examples of the methods 1200 and devices described herein may further include operations, features, components, or instructions for removing barrier material from above the via based at least in part on planarization. In some examples of the method 1200 and apparatus described herein, the barrier material may remain above the stack of memory cells after planarization. In some examples of the method 1200 and the apparatus described herein, the barrier material may remain on the sidewall of the via after planarization. In some examples of the methods 1200 and devices described herein, the barrier material may remain above the dielectric material after planarization.

Some examples of the methods 1200 and devices described herein may further include operations, features, components, or instructions for removing barrier material from above the through holes based on planarization. In some examples of the method 1200 and apparatus described herein, the barrier material remains above the stack of memory cells after planarization. In some examples of the method 1200 and apparatus described herein, the barrier material remains on the sidewall of the via after planarization. In some examples of the methods 1200 and devices described herein, the barrier material remains above the dielectric material after planarization.

Some examples of the method 1200 and the apparatus described herein may further include operations, features, components, or instructions for applying a first planarization process to the top surface of the dielectric material and the top surface of the via before forming the barrier material , Wherein the top surface of the through hole can protrude above the top surface of the dielectric material after the first planarization process. In some examples of the method 1200 and devices described herein, the first planarization process removes the dielectric material at a faster rate than the material included in the via.

Some examples of the method 1200 and the apparatus described herein may further include operations, features, components, or instructions for forming an insulating region between the memory cell stack and the second memory cell stack, wherein the insulating region includes the second The dielectric material, the memory cell stack includes electrodes, the first planarization process is applied to the top surface of the electrode and the top surface of the insulating region, and the first planarization process removes the first planarization process at a faster rate than the material included in the electrode Two dielectric materials.

In some examples of the methods 1200 and devices described herein, the dielectric material and the second dielectric material may be different materials. In some examples of the methods 1200 and devices described herein, the metal may be in contact with the top surface of the via. In some examples of the method 1200 and apparatus described herein, after planarization, the barrier material may have a waved lower surface and a flat top surface. In some examples of the methods 1200 and devices described herein, the waveform lower surface may conform to one or more materials under the barrier material.

In some examples of the method 1200 and the apparatus described herein, planarizing the top surface of the barrier material may include operations, features, components, or instructions for applying a CMP process to the top surface of the barrier material.

FIG. 13 shows a flowchart illustrating one or more methods 1300 for manufacturing a memory device according to aspects of the invention. The operations of method 1300 may be used to form a memory device or component thereof, as described herein. For example, the operation of the method 1300 can be implemented by the manufacturing technique as described with reference to FIGS. 8 to 11.

At 1305, a stack of memory cells including storage elements may be formed over the first area of the substrate. The operation of 1305 can be performed according to the method described herein. In some examples, the operation aspect of 1305 can be performed using manufacturing techniques as described with reference to FIGS. 8-11.

At 1310, a through hole extending through the dielectric material may be formed over the second area of the substrate. The operation of 1310 can be performed according to the method described herein. In some examples, the state of operation of 1310 can be performed using manufacturing techniques as described with reference to FIGS. 8-11.

At 1315, barrier material can be formed over the memory cell stack and vias. The operation of 1315 can be performed according to the method described herein. In some examples, the operation aspect of 1315 can be performed using manufacturing techniques as described with reference to FIGS. 8-11.

At 1320, the top surface of the barrier material may be planarized. The operation of 1320 can be performed according to the method described herein. In some examples, the state of operation of 1320 can be performed using manufacturing techniques as described with reference to FIGS. 8 to 11.

At 1325, the barrier material can be removed from above the via based on planarization. The operation of 1325 can be performed according to the method described herein. In some examples, the state of operation of 1325 can be performed using manufacturing techniques as described with reference to FIGS. 8-11.

At 1330, the metal used for the access lines of the memory array may be formed over the barrier material. The operation of 1330 can be performed according to the method described herein. In some examples, the state of operation of 1330 can be performed using manufacturing techniques as described with reference to FIGS. 8 to 11.

FIG. 14 shows a flowchart illustrating one or more methods 1400 for manufacturing a memory device according to aspects of the invention. The operations of method 1400 can be used to form a memory device or component thereof, as described herein. For example, the operation of the method 1400 can be implemented by manufacturing techniques as described with reference to FIGS. 8-11.

At 1405, a collection of memory cell stacks can be formed, each of the memory cell stacks including a respective storage element and a respective electrode above the respective storage element. The operation of 1405 can be performed according to the method described herein. In some examples, the operation aspect of 1405 can be performed using manufacturing techniques as described with reference to FIGS. 8-11.

At 1410, a dielectric material can be formed. The operation of 1410 can be performed according to the method described herein. In some examples, the aspect of operation of 1410 can be performed using manufacturing techniques as described with reference to FIGS. 8-11.

At 1415, a through hole in contact with a dielectric material can be formed, wherein the dielectric material is between the through hole and the stack of memory cells. The operation of 1415 can be performed according to the method described herein. In some examples, the operation aspect of 1415 can be performed using manufacturing techniques as described with reference to FIGS. 8-11.

At 1420, barrier material can be formed over the collection of memory cell stacks and the through holes. The operation of 1420 can be performed according to the method described herein. In some examples, the aspect of operation of 1420 can be performed using manufacturing techniques as described with reference to FIGS. 8 to 11.

At 1425, a portion of the barrier material can be removed to expose the top surface of the through hole. The operation of 1425 can be performed according to the method described herein. In some examples, the mode of operation of 1425 can be performed using manufacturing techniques as described with reference to FIGS. 8-11.

At 1430, a metal that contacts the top surface of the through hole and the barrier material can be formed. The operation of 1430 can be performed according to the method described herein. In some examples, the aspect of operation of 1430 can be performed using manufacturing techniques as described with reference to FIGS. 8 to 11.

In some instances, a device as described herein may perform one or more methods, such as method 1400. The device may include features, components, or instructions (for example, a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: forming a collection of memory cell stacks, each of which includes a separate A storage element and a respective electrode above the respective storage element; forming a dielectric material; forming a through hole in contact with the dielectric material, wherein the dielectric material is between the through hole and the stack of memory cells; forming The barrier material above the assembly of the memory cell stack and the through hole; removing a part of the barrier material to expose the top surface of the through hole; and forming the metal that is in contact with the top surface of the through hole and the barrier material.

In some examples of the methods 1400 and devices described herein, removing the portion of the barrier material may include operations, features, components, or instructions for polishing the top surface of the barrier material until the top surface of the through hole is exposed.

Some examples of the methods 1400 and devices described herein may further include operations, features, components, or instructions for polishing the top surface of the dielectric material before forming the barrier material until the vias protrude from the dielectric material.

It should be noted that the method described herein is a possible implementation, and the operations and steps can be reconfigured or modified in other ways, and other implementations are possible. In addition, two or more of these methods can be combined.

Describe a device. The device may include: a set of memory cell stacks, each of which includes a respective storage element; a dielectric material disposed on the set of memory cell stacks and through holes extending through the dielectric material Between; a barrier material, which is arranged above the set of memory cell stacks and the dielectric material; and an access line, which extends from the set of memory cell stacks to above the through hole, wherein the storage The wire is in contact with a top surface of the barrier material and a top surface of the through hole.

In some examples, the barrier material may be in contact with the sidewall of the through hole. In some examples, the sidewalls of the vias extend above the top surface of the dielectric material. In some examples, a part of the through hole may be surrounded by a barrier material. In some examples, the top surface of the barrier material may be flat and at least a portion of the bottom surface of the barrier material may be conformal and wavy. In some examples, the bottom surface of the barrier material may also conform to one or more materials below the barrier material.

In some examples, the collective memory cell stack includes electrodes, and a portion of the electrode may be over a portion of the barrier material. Some examples of devices may include a second dielectric material disposed between a stack of assembled memory cells, where the barrier material may be in contact with the second dielectric material.

In some examples, the individual storage elements include chalcogenide materials. In some examples, the barrier material includes nitride. In some examples, the barrier material includes tungsten silicon nitride, and the access line includes tungsten.

The term "layer" as used herein refers to a layer or sheet of a geometric structure. Each layer can have three dimensions (e.g., height, width, and depth), and can cover some or all of the surface. For example, the layer may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a film. Layers can include different elements, components, and/or materials. In some cases, a layer may be composed of two or more sub-layers. In some accompanying figures, the two dimensions of the three-dimensional layer are depicted for illustrative purposes. However, those skilled in the art will recognize that the layers are actually three-dimensional.

As used herein, the term "electrode" can refer to an electrical conductor, and in some cases can be used as an electrical contact to a memory cell or other components of a memory array. The electrodes may include traces, wires, conductive lines, conductive layers, or the like that provide conductive paths between elements or components of the memory array.

The terms "electronic communication", "conductive contact", "connection" and "coupling" can refer to the relationship between components that support the flow of signals between components. If there are any conductive paths between the components that can support the flow of signals between the components at any time, the components are considered to be in electronic communication with each other (or in conductive contact with each other or connected to or coupled to each other). At any given time, the conductive paths between components that are in electronic communication with each other (or are in conductive contact with each other or connected to each other or coupled to each other) may be open or closed based on the operation of the device including the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some instances, one or more intermediate components such as switches or transistors may be used to interrupt the signal flow between connected components for a period of time, for example.

As used herein, the term "substantially" means that the modified characteristic (for example, a verb or adjective substantially modified by the term) need not be an absolute value but close enough to achieve the advantage of the characteristic.

The switching elements or transistors discussed herein may refer to field effect transistors (FETs) and include three terminal devices including source, drain, and gate. The terminals may be connected to other electronic components via conductive materials (for example, metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by lightly doped semiconductor regions or channels. If the channel is n-type (that is, most of the carrier is electrons), the FET can be referred to as an n-type FET. If the channel is p-type (that is, most of the carriers are holes), the FET can be called a p-type FET. The channel can be covered by an insulating gate oxide. The channel conductivity can be controlled by applying voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor, the transistor can be "turned on" or "started". When a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor, the transistor can be "disconnected" or "deactivated".

The term "exemplary" as used herein means "serving as an example, example, or illustration" and does not mean "better" or "better than other examples."

The chalcogenide material may be a material or alloy including at least one of the elements S, Se, and Te. The phase change materials discussed herein can be chalcogenide materials. Chalcogenide materials may include alloys of the following: S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium ( Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni) or platinum (Pt). Example chalcogenide materials and alloys may include (but are not limited to): Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te -Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge -Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te -Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd Or Ge-Te-Sn-Pt. As used herein, a hyphenated chemical composition label indicates an element included in a particular compound or alloy and is intended to indicate all stoichiometry related to the indicated element. For example, Ge-Te can include Ge _x Te _y , where x and y can be any positive integers. Other examples of variable resistance materials may include binary metal oxide materials or mixed valence oxides including two or more metals (for example, transition metals, alkaline earth metals, and/or rare earth metals). The embodiments are not limited to specific variable resistance materials or materials associated with the memory elements of the memory cell. For example, other examples of variable resistance materials can be used to form memory devices and can include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials plus others.

The devices discussed herein can be formed on semiconductor substrates (such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping with various chemical substances including but not limited to phosphorus, boron or arsenic. The doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

The description set forth herein in conjunction with the accompanying drawings describes example configurations, and does not mean all examples that can be implemented or are within the scope of the patent application. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, these techniques can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form so as not to obscure the concepts of the described examples.

In the drawings, similar components or features may have the same reference label. In addition, various components of the same type can be distinguished by adding a dash after the reference mark and a second mark that distinguishes between similar components. If only the first reference sign is used in the specification, the description is applicable to any one of the similar components having the same first reference sign regardless of the second reference sign.

As used herein (including in the scope of the patent application), "or" is used in a list of items (for example, items ending with phrases such as "at least one of" or "one or more of" List) indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (ie, A and B and C) . In addition, as used in this article, the phrase "based on" should not be considered as a reference to a closed set of conditions. For example, without departing from the scope of the present invention, the exemplary steps described as "based on condition A" can be based on both condition A and condition B. In other words, as used in this article, the phrase "based on" should be interpreted in the same way as the phrase "based on".

The description herein is provided to enable those skilled in the art to make or use the present invention. Various modifications to the present invention will be obvious to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the examples and designs described in this article, but should conform to the broadest scope consistent with the principles and novel features disclosed in this article.

100-a: Intermediate array structure 100-b: Intermediate array structure 105-a: first memory cell stack 105-b: second memory cell stack 105-c: third memory cell stack 110: Metal layer 115: first electrode material 120: Selector material 125: second electrode material 130: storage materials 135: Third electrode material 140-a: Quarantine 140-b: Quarantine 200: Memory array structure 200-a: Intermediate array structure 200-b: Intermediate array structure 205: Depositing dielectric materials 210: Wave surface 300: Memory array structure 300-a: Intermediate array structure 300-b: Intermediate array structure 305: Barrier Material 310: top surface 400: Additional intermediate array structure 405: Metal layer 410-a: center point 410-b: center point 415: distance 500: memory array 505: Memory cell stacking 510: Access Line 515: Access Line 520: column decoder 525: Sensing component 530: Line decoder 535: output 540: Memory Controller 600: method 605: step 610: Step 615: step 620: step 700: method 705: step 710: step 715: step 720: step 800-a: Intermediate array structure 800-b: Intermediate array structure 805: Dielectric material 810: Through hole 900-b: Intermediate array structure 1000: Additional intermediate array structure 1100: Additional intermediate array structure 1200: method 1205: Step 1210: Step 1215: step 1220: step 1225: step 1300: method 1305: step 1310: step 1315: step 1320: step 1325: step 1330: step 1400: method 1405: step 1410: step 1415: step 1420: step 1425: step 1430: step

FIG. 1A and FIG. 1B illustrate an example of a manufacturing technique according to an embodiment of the present invention.

2A and 2B illustrate an example of manufacturing technology according to an embodiment of the present invention.

3A and 3B illustrate an example of manufacturing technology according to an embodiment of the present invention.

Figure 4 illustrates an example of a manufacturing technique according to an embodiment of the present invention.

FIG. 5 illustrates an example memory array that supports granularity modulation of access lines in a memory device according to an example of the present invention.

6 and 7 illustrate one or more methods for adjusting the granularity of access lines in a memory device according to an embodiment of the present invention.

8A and 8B illustrate an example of a manufacturing technique according to an embodiment of the present invention.

Fig. 9 illustrates an example of a manufacturing technique according to an embodiment of the present invention.

Fig. 10 illustrates an example of a manufacturing technique according to an embodiment of the present invention.

FIG. 11 illustrates an example of a manufacturing technique according to an embodiment of the present invention.

12 to 14 show flowcharts illustrating one or more methods for accessing line-granularity modulation in a memory device according to examples as disclosed herein.

105-a: first memory cell stack

105-b: second memory cell stack

105-c: third memory cell stack

115: first electrode material

120: Selector material

125: second electrode material

130: storage materials

135: Third electrode material

140-a: Quarantine

140-b: Quarantine

205: Depositing dielectric materials

210: Wave surface

305: Barrier Material

310: top surface

405: Metal layer

805: Dielectric material

810: Through hole

1100: Additional intermediate array structure

Claims (25)

A method that includes: Forming a memory cell stack including a storage element over a first area of a substrate; Forming a through hole extending through a dielectric material above a second area of the substrate; Forming a barrier material above the memory cell stack and the through hole; Flattening one of the top surfaces of the barrier material; and A metal for an access line of a memory array is formed above the barrier material. Such as the method of claim 1, which further includes: The barrier material is removed from above the through hole based at least in part on the planarization. The method of claim 2, wherein the barrier material remains above the memory cell stack after the planarization. The method of claim 2, wherein the barrier material remains on one of the sidewalls of the through hole after the planarization. The method of claim 2, wherein the barrier material remains above the dielectric material after the planarization. Such as the method of claim 1, which further includes: Before forming the barrier material, a first planarization process is applied to a top surface of the dielectric material and a top surface of the through hole, wherein the top surface of the through hole is after the first planarization process The dielectric material protrudes above the top surface. The method of claim 6, wherein the first planarization process removes the dielectric material at a faster rate than a material included in the through hole. Such as the method of claim 6, which further includes: An insulating region is formed between the memory cell stack and a second memory cell stack, wherein; The insulating region includes a second dielectric material; The memory cell stack includes an electrode; The first planarization process is applied to a top surface of the electrode and a top surface of the insulating region; and The first planarization process removes the second dielectric material at a rate faster than a material included in the electrode. The method of claim 8, wherein the dielectric material and the second dielectric material are different materials. The method of claim 1, wherein the metal is in contact with a top surface of the through hole. The method of claim 1, wherein after the planarization, the barrier material has a wave-shaped lower surface and a flat top surface. The method of claim 1, wherein flattening the top surface of the barrier material includes: A chemical mechanical planarization (CMP) process is applied to the top surface of the barrier material. A device comprising: A plurality of memory cells are stacked, each of which includes a separate storage element; A dielectric material disposed between the plurality of memory cell stacks and a through hole extending through the dielectric material; A barrier material arranged on the plurality of memory cell stacks and the dielectric material; and An access line extends from above the plurality of memory cell stacks to above the through hole, wherein the access line is in contact with a top surface of the barrier material and a top surface of the through hole. The device of claim 13, wherein the barrier material is in contact with a side wall of the through hole. The device of claim 14, wherein the sidewall of the through hole extends above a top surface of the dielectric material. Such as the device of claim 13, wherein a part of the through hole is surrounded by the barrier material. The device of claim 13, wherein the top surface of the barrier material is flat and at least a part of a bottom surface of the barrier material is conformal and wavy. Such as the device of claim 13, where: One of the memory cell stacks in the plurality of memory cell stacks includes an electrode; and A part of the electrode is over a part of the barrier material. Such as the device of claim 13, which further includes: A second dielectric material is arranged between the plurality of memory cell stacks, wherein the barrier material is in contact with the second dielectric material. Such as the device of claim 13, wherein the respective storage element includes a chalcogenide material. The device of claim 13, wherein the barrier material includes nitride. Such as the device of claim 21, where: The barrier material includes tungsten silicon nitride; and The access line contains tungsten. A method that includes: Forming a plurality of memory cell stacks, each of the plurality of memory cell stacks including a respective storage element and a respective electrode above the respective storage element; Forming a dielectric material; Forming a through hole in contact with the dielectric material, wherein the dielectric material is between the through hole and the plurality of memory cell stacks; Forming a barrier material above the plurality of memory cell stacks and the through hole; Removing a part of the barrier material to expose a top surface of the through hole; and A metal contacting the top surface of the through hole and the barrier material is formed. Such as the method of claim 23, wherein removing the part of the barrier material includes: Polishing a top surface of the barrier material until the top surface of the through hole is exposed. Such as the method of claim 23, which further includes: Before forming the barrier material, a top surface of the dielectric material is polished until the through hole protrudes from the dielectric material.

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