TW202136995A - Memory apparatus and memory management method for safe power-up - Google Patents

Abstract

A memory apparatus and a memory management method for safe power-up are provided. The memory management method includes: dividing a memory cell array into a first block and a second block ; storing a boot code in the first block and storing a backup boot code in the second block by backing up the boot code; in a power up sequence, setting a fail-safe flag , and reading the boot code from the first block to obtain a fist read-out boot code according to a reset command; judging whether the first read-out boot code is normal or not to generate a judging result, and setting a prequalify flag according to the judging result or the fail-safe flag, and determining whether to read the backup boot code to obtain a second read-out boot code or not.

Description

Memory device and memory management method for safe booting

The present invention relates to a memory device and a memory management method for safe booting, and more particularly to a memory device that can increase the success rate of booting and a memory management method for safe booting.

In today's electronic devices, the boot code of the host is often stored in a non-volatile memory, such as a flash memory. The boot code stored in the flash memory is often damaged due to various reasons. Once the boot code content is damaged, the host will boot up correctly without code and cannot operate normally. Moreover, in the conventional technology, when the host side fails to boot and crashes, the system can only be sent back to the supplier side for maintenance, which is extremely inconvenient to use.

The invention provides a memory device and a memory management method for safe booting, which can improve the chance of successful booting of a host.

The memory management method for safe boot of the present invention includes: distinguishing the first block and the second block in the memory cell array; storing the boot code in the first block, and backing up the boot code to be in the second area Block storage backup boot code; in the boot process, set the fail-safe flag, and read the boot code in the first block according to the host-side programmable software command to obtain the first read boot code; determine the first read Whether the startup code is correct to generate a judgment result, and based on the judgment result or the failure-safe flag to set a pre-audit flag, and based on the pre-audit flag, determine whether to read the backup startup code as the second read startup code.

The memory device of the present invention includes a memory cell array and a control circuit. The memory cell array has a first block and a second block, and the first block and the second block respectively store the boot code and the backup boot code. The control circuit is coupled between the memory cell array and the host terminal for executing the above-mentioned safe boot management method.

Based on the above, the present invention stores the activation code and the backup activation code in the first block and the second block in the memory cell array, respectively. In the boot process, the pre-audit flag is set according to the judgment result of the failure-safe flag or whether the first read boot code is correct, and based on the pre-check flag, it is determined whether to read the backup boot code to execute the host-side startup maneuver. . The normal operation of the host can be maintained.

Please refer to FIG. 1. FIG. 1 is a flowchart of a memory management method for secure boot according to an embodiment of the present invention. Wherein, in step S110, the memory cell array in the memory can distinguish the first block and the second block. The first block and the second block can be two different blocks with consecutive or discontinuous addresses in the memory cell array. In the embodiment of the present invention, the first block may be arranged in the memory cell array with a relatively low address range, and the second block may be arranged in the memory cell array with a relatively high address range. In this embodiment, the memory may be a non-volatile memory, such as a flash memory.

Then, in step S120, the activation code is stored in the first block, and the activation code is backed up to store the backup activation code in the second block. The startup code is used to provide the host side for reading and provide the host side to execute the startup action.

In step S130, the boot process is entered, and in the boot process, the failure-safe flag is set, and the boot code in the first block is read according to the reset command to obtain the first read boot code. Among them, a failure-safe flag can be set in the flash memory. In addition, in step S130, the failure-safe flag may be set to the first logic level (for example, logic level 1). Then, the host side can execute a reset command through the host side programmable software, and based on the trigger of the reset command, the host side can read the boot code of the first block in the memory cell array and read it out First read the boot code.

Here, when reading the boot code of the first block of the memory, the access address can be set as the first initial access address, and the first initial access address of the memory cell array can be set Perform a reading action to obtain the first read boot code.

Then, in step S140, a judgment can be made as to whether the first read boot code is correct, and thereby a judgment result can be generated. In this embodiment, the judgment result can be obtained by performing a cyclic redundancy check (CRC) on the first read boot code. Alternatively, in other embodiments of the present invention, after the host side executes the boot action according to the first read boot code, the judgment result can be obtained by performing a specific function check, and thereby know the first area in the memory cell array Whether the boot code stored in the block is correct.

Incidentally, when the judgment result obtained in step S140 indicates that the first read boot code is correct, the failure-safe flag can be cleared to the second logic level (for example, logic level 0). If the judgment result obtained in step S140 indicates that the first read boot code is wrong, the failure-safe flag may be maintained at the first logic level (for example, logic level 1).

In step S150, a pre-audit flag can be set according to the judgment result or the failure-safe flag. Among them, the pre-review flag is a volatile memory flag configured in the memory. In addition, in the boot process, when the failure-safe flag is set (equal to the first logic level), or the judgment result in step S140 indicates that the first read boot code is wrong, the pre-audit flag can be Is set equal to the first logic level. In addition, in the state where the pre-review flag is equal to the first logic level, the host can read the backup activation code of the second block in the memory cell array, and thereby obtain the second read activation code. The host terminal can perform a restart action according to the second read-out boot code.

On the other hand, in the above step S150, when the read operation is to be performed on the backup boot code of the second block of the memory cell array, the host can rely on the pre-audit flag equal to the first logic level. Under the condition of changing the initial access address, a read operation is performed on the memory cell array to obtain the second read boot code.

It is not difficult to know from the above description that in the memory management method for secure boot of the embodiment of the present invention, when an error occurs in the boot code stored in the memory cell array, the memory cell array can provide the backup stored in the second block Boot code, and through the backup boot code to enable the host to successfully boot, effectively improve the probability of successful boot of the host.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a configuration of a memory cell array according to an embodiment of the present invention. In FIG. 2, the memory cell array 200 of the memory can be divided into a first block Z1 and a second block Z2. In this embodiment, the first block Z1 is arranged between the address ADD1 and the address ADD2, and the second block Z2 is arranged between the address ADD2 and the address ADD3. In addition, the activation code BC1 is stored in the first block Z1, and the backup activation code BC2 is stored in the second block Z2. When the startup code BC1 in the first block Z1 is to be read, the start address ADD1 can be set as the access address, and the startup code BC1 is read. In contrast, when the pre-audit flag Peugeot is to read the backup boot code BC2 in the second block Z2, the host side maintains the original start address (ADD1) as the access address, and Read the backup boot code BC2.

Here, the memory capacity of the first block Z1 and the second block Z2 is larger than the size of the startup code BC1 and the backup startup code BC2. In addition, the address configuration of the first block Z1 and the second block Z2 may be continuous, but may also be discontinuous, and there is no certain limit.

Please refer to FIG. 3, which is a flowchart of a memory management method according to another embodiment of the present invention. In Fig. 3, step S310 starts the boot procedure. Step S320 judges whether the error safety flag has been set. When the error safety flag is set, step S3100 is executed. On the other hand, when the error safety flag is not set, it is executed. Step S330. Here, step S320 can be judged according to the logic level of the false safety flag. For example, when the error safety flag is the first logic level, the visible error safety flag is in a set state. Conversely, when the error safety flag is the second logic level, the error safety flag can be viewed as a non-set state. The first logic level is complementary to the second logic level.

It is worth noting that when it is determined in step S320 that the error safety flag has been set, it means that the conditions for error safety booting already exist, and the error safety booting mechanism needs to be activated. In this case, it means that the previous boot (read the boot code BC1) failed, and the error security flag has not been cleared. Then, step S3100 is executed to set the pre-audit flag to be enabled.

Incidentally, the error safety flag can be set in a non-volatile memory (such as flash memory). Therefore, the logic level of the error safety flag will not be changed through the reboot action on the host side. In addition, in the embodiment of the present invention, the error security flag may be stored in the same flash memory as the boot code. In other embodiments of the present invention, the error security flag and the boot code can also be stored in different flash memories.

In step S330, the error safety flag is set to the first logic level, and then in step S340, the host can send a memory reset command, and in step S350, download the boot code of the first block in the memory cell array. Next, in step S360, a function check or a CRC check is performed on the first read boot code, so as to confirm whether the first read boot code is correct. Wherein, when the check result of step S360 is passed, it indicates that the first read-out power-on code is correct, and step S370 can be executed. In contrast, when the check result of step S360 is not passed, it means that the first read-out power-on code is wrong and step S390 is executed correspondingly.

In step S370, based on the fact that the first read-out power-on code is correct, the error safety flag can be cleared to the second logic level to indicate that the conditions for performing an error-safe startup do not exist. And in step S380, the host can perform normal actions.

On the other hand, in step S390, the host side executes a reset command again or initiates a hardware reset (Hardware Reset) action. Then, through step S3100, the pre-audit flag is set to enable in the memory. Here, you can set the pre-review flag to enable by setting the pre-review flag to the high logic level. Correspondingly, when the pre-review flag is at the second logic level, the pre-review flag can be viewed as disabled .

In step S3110, the backup activation code in the second block of the memory is downloaded according to the pre-audit flag set to enable, and the second read activation code is obtained thereby. Next, step S3120 performs a function check or a CRC check for the second read-out startup code. If the second read-out power-on check action of step S3120 is passed, step S3130 is executed. Conversely, if the second read power-on check operation of step S3120 fails, an error report operation is performed (step S3140).

In step S3130, the host side can perform a clearing action of the error security flag (clearing to the second logic level), and can perform a repairing action of the boot code of the first block in the memory. It is worth mentioning that regarding the details of the boot code restoration action, the first block in the memory can be erased first. Then, it is completed by writing the backup boot code in the second block (that is, the second read boot code) back to the first block of the memory.

Please note here that in this embodiment, the error security flag is set in the memory. Therefore, the memory management process of FIG. 3 can be completed through the memory and the corresponding control circuit.

Please refer to FIG. 4 below. FIG. 4 is a flowchart of a memory management method for secure boot according to another embodiment of the present invention. Different from the previous embodiment, the embodiment of FIG. 4 uses a user (external electronic device) outside of the memory and its controller to set the logic criterion of the forced exchange flag (equivalent to the error safety flag of the previous embodiment). Bit.

In terms of action details, the booting procedure is started in step S410. Then, in step S430, the activation code can be downloaded from the first block of the memory, and the first read activation code can be obtained.

In step S440, a CRC or function check is performed on the first read-out power-on code to determine whether the first read-out power-on code is correct. If the result of the determination in step S440 indicates that the first read-out boot code is correct, the forced exchange flag can be disabled in step S450, and normal actions can be performed (step S460). On the contrary, if the judgment result of step S440 indicates that the first read-out boot code is wrong, the system side can set an external signal connected to the memory (forcibly swapped pins) (step S445) to a high logic level, and A warm reboot (warm reboot) restart action is performed, and at the same time, the memory sets the pre-review flag as an enabled action (step S470). After the waiting of the warm boot action in step S480 is over, in step S490, the action of downloading the backup boot code of the second block in the memory is performed.

Please note that in this embodiment, the logic level of the forced exchange flag can be set by an external electronic device. Under the condition that the forced exchange flag is enabled and the forced exchange flag is the first logic level, step S490 can perform the action of downloading the backup boot code of the second block in the memory, and thereby obtain the second Read the startup code.

Next, in step S4100, a function check or a CRC check is performed for the second read-out startup code, and step S4120 is performed when the check is passed, or step S4110 is performed when the check fails to report an error.

In step S4120, the startup code of the first block in the memory can be repaired, and the forced exchange flag can be cleared after the startup code of the first block is repaired (cleared to the second logic level).

Please refer to FIGS. 5A and 5B below. FIGS. 5A and 5B respectively illustrate schematic diagrams of different implementations of the memory device according to an embodiment of the present invention. In FIG. 5A, the memory device 501 includes a memory cell array 510 and a control circuit 520. The memory cell array 510 is divided into a first block and a second block, and stores the activation code BC1 and the backup activation code BC2, respectively.

The control circuit 520 can be used to execute the memory management process of the foregoing embodiment, so as to improve the probability of successful booting of the host.

On the other hand, the control circuit 520 includes a flip-flop FF1, a logic circuit 522, and an address decoder 521. The data terminal of the flip-flop FF1 receives the boot address setting value BA-DEF, the clock terminal of the flip-flop FF1 receives the boot trigger signal PUT, and the output terminal of the flip-flop FF1 receives the boot trigger signal PUT generated by the restart action. Generate the boot address setting value BA-DEF.

On the other hand, the logic circuit 522 can be used as a glue logic circuit between the host and the memory cell array 510. The logic circuit 522 receives the output of the startup code setting value BC-DEF, the highest bit address HMSB, and the flip-flop FF1, and performs logic operations to generate the switching address MMSAD. In addition, the address decoder 521 receives the low-order address HLSB and the switching address MMSAD, and generates an access address according to the low-order address HLSB and the switching address MMSAD by performing a value row address decoding operation. According to the access address, the startup code BC1 or the backup startup code BC2 in the memory cell array 510 can be read.

In terms of operation details, when the startup code setting value BC-DEF is disabled, the address decoder 521 can only provide an access address to read the startup code BC1 of the first block of the memory cell array 510. When the startup code setting value BC-DEF is enabled, the logic circuit 522 can generate the switching address MMSAD according to the highest bit address HMSB and the output of the flip-flop FF1.

To further explain, under this condition, when the output of the flip-flop FF1 is, for example, the logic level 0, the logic circuit 522 can output the high bit address HMSB as the switching address MMSAD. The address decoder 521 generates an access address according to the switching address MMSAD and the lower address HLSB. The switch address MMSAD can be a single bit, can be used as the highest bit of the address, and used to integrate with the low bit address HLSB. Under the condition that the low bit address HLSB is 0 and the switching address MMSAD is also 0, the address decoder 521 can generate an access address equal to 000000h (hexadecimal value) to read the boot code BC1.

When the output of the flip-flop FF1 is, for example, the logic level 1, the logic circuit 522 can reverse the switching address MMSAD and make the switching address MMSAD become the logic level 1. The address decoder 521 can generate an access address equal to 800000h (hexadecimal value) to read the backup boot code BC2.

Please note here that the output of the flip-flop FF1 can be generated based on the boot address setting value BA-DEF, and when the boot address setting value BA-DEF is changed, the flip-flop FF1 needs to be restarted after the restart action occurs. The output generated can be changed according to the power-on trigger signal PUT.

Next, please refer to FIG. 5B. Unlike the embodiment of FIG. 5A, the control circuit 520 in the memory device 502 of FIG. 5B further includes a mutual exclusion or gate XOR. The exclusive OR gate XOR is coupled between the output terminal of the flip-flop FF1 and the logic circuit 522. The exclusive or gate XOR receives the pre-audit flag PREQ and the output of the flip-flop FF1. When the pre-audit flag PREQ is enabled, the output of the flip-flop FF1 can be inverted (or not inverted) according to the pre-audit flag PREQ, thereby changing the switching address MMSAD generated by the logic circuit 522, and selecting read Output the startup code BC1 or backup startup code BC2.

Here, the pre-audit flag PREQ can be provided by a random access memory. That is to say, the external electronic device can change the pre-audit flag PREQ by writing data to the random access memory, and perform the switching action of reading the boot code BC1 or the backup boot code BC2 accordingly.

In summary, the present invention stores the activation code and the backup activation code in different blocks in the memory cell array. And when the startup code is judged to have an error state, switch to read the backup startup code to perform the startup action. In this way, the host ensures that it can successfully boot and maintain the normal operation of the system.

S110~S150, S310~S3130, S410~S4120: Memory management steps 200: Memory cell array 501: memory device 510: Memory Cell Array 520: control circuit 521: Address Decoder 522: Logic Circuit ADD1~ADD3: address BA-DEF: Boot address setting value BC1: startup code BC2: Backup boot code BC-DEF: Boot code setting value FF1: Flip-Flop HLSB: Low bit address HMSB: Most significant bit address MMSAD: switch address PREQ: Pre-audit flag PUT: Power-on trigger signal XOR: Mutually exclusive or gate Z1: first block Z2: second block

FIG. 1 shows a flowchart of a memory management method for secure boot according to an embodiment of the present invention. FIG. 2 is a schematic diagram of the configuration of the memory cell array according to the embodiment of the present invention. FIG. 3 shows a flowchart of a memory management method according to another embodiment of the present invention. FIG. 4 shows a flowchart of a memory management method for secure boot according to another embodiment of the present invention. 5A and 5B respectively show schematic diagrams of different implementations of the memory device according to an embodiment of the present invention.

S110~S150: Memory management steps

Claims (10)

A memory management method for safe booting includes: Distinguish a first block and a second block in a memory cell array; Storing a boot code in the first block, and backing up the boot code to store a backup boot code in the second block; In a boot process, set a failure-safe flag, and read the boot code in the first block according to a host-side programmable software command to obtain a first read boot code; Judging whether the first read-out boot code is correct to generate a judgment result; and According to the judgment result or the failure-safe flag, a pre-audit flag is set, and according to the pre-audit flag, it is determined whether to read the backup startup code as a second read startup code. For the memory management method described in item 1 of the scope of patent application, when the judgment result indicates that the first read-out boot code is correct, it further includes clearing the failure-safe flag. For example, in the memory management method described in item 1 of the scope of patent application, the pre-examination flag is set when the judgment result indicates that the first read-out boot code is wrong. As described in item 3 of the scope of patent application, the memory management method further includes reading the backup boot code as the second read boot code according to the pre-review flag. For the memory management method described in item 1 of the scope of patent application, the step of judging whether the first read-out boot code is correct to generate the judgment result includes: Perform a cyclic redundancy check on the first read boot code to obtain the judgment result; or Perform a boot action on a host terminal according to the first read boot code, and make the host terminal perform a function check to obtain the judgment result. The memory management method described in item 1 of the scope of patent application further includes: Perform a cyclic redundancy check on the second boot code, or perform a boot action on a host terminal according to the second read boot code, and make the host perform a function check to verify whether the second read boot code Is correct; and When the second read power-on code is verified as correct, the failure-safe flag is cleared. The memory management method described in item 6 of the scope of patent application further includes: Perform a repair operation on the boot code in the first block. The memory management method described in item 7 of the scope of patent application, wherein the repairing action includes: Perform an erase operation on the first block; and Copy the second read boot code to write to the first block. As described in the first item of the patent application, the first block and the second block respectively correspond to a first initial access address and a second initial access address, wherein the read The step of obtaining the activation code in the first block to obtain the first read activation code includes: Setting an access address as the first initial access address, and performing a read operation on the memory cell array according to the access address to obtain the first read boot code, Wherein, the step of determining whether to read the backup boot code as the second read boot code according to the pre-review flag includes: According to the pre-review flag and the initial access address, a read operation is performed on the memory cell array to obtain the second read-out startup code. A memory device includes: A memory cell array having a first block and a second block, the first block and the second block respectively storing an activation code and a backup activation code; A control circuit, coupled between the memory cell array and a host terminal, is used to execute: In a boot process, set a failure-safe flag, and read the boot code in the first block according to a host-side programmable software command to obtain a first read boot code; Judging whether the first read-out boot code is correct to generate a judgment result; and A pre-audit flag is set according to the judgment result or the failure-safe flag, and whether to read the backup startup code is determined according to the pre-audit flag as a second read startup code.

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