TW202135178A - Packaging substrate and manufacturing method thereof - Google Patents

Abstract

The embodiment of the invention relates to a packaging substrate and a manufacturing method thereof. According to the packaging substrate in one embodiment, the packaging substrate comprises a circuittop layer, a circuit bottom layer, a first insulating layer and at least one stepped inclined side surface, wherein the first insulating layer is located between the circuit top layer and the circuit bottom layer; and the stepped inclined side surface is provided with a first stepped inclined side surface extending from the circuit top layer to the first insulating layer and a second stepped inclined side surface extending from the first insulating layer to the circuit bottom layer. According to the packaging substrate and the manufacturing method thereof provided by the embodiment of the invention, the soldering tin performance of the packaging substrate can be effectively evaluated from the appearance.

Description

Package substrate and manufacturing method thereof

The embodiments of the present application generally relate to the semiconductor field, and more specifically, relate to a package substrate and a manufacturing method thereof.

Land grid array (LGA) packaging technology is a "leapfrog technological revolution" in the field of semiconductor packaging technology, mainly because it uses metal contact packaging to replace the previous pin-shaped pins. However, it is generally difficult to judge the performance of the solder joints, especially the solder joints at the bottom, from the appearance of the platform grid array package. In addition, the solder pin on the side of the LGA package is only cut off at the junction of the package unit during the production process to expose the cut surface of the solder pin. Correspondingly, due to the small cut surface of the solder leg, it is difficult to adhere enough solder during soldering. Moreover, the cut surface of the exposed solder foot is prone to oxidation after a period of time, which will further cause the difficulty of tin on the cut surface of the solder foot, which will affect the operability and stability of the packaged product during application.

Therefore, the existing platform grid array package type package substrate needs to be further improved.

One of the objectives of the embodiments of the present application is to provide a package substrate and a manufacturing method thereof, which can effectively evaluate the soldering performance of the package substrate from its appearance.

An embodiment of the present application provides a package substrate, which includes: a top layer of a circuit; a bottom layer of a circuit; a first insulating layer located between the top layer of the circuit and the bottom layer of the circuit; and at least one stepped oblique side surface, the The stepped oblique side surface has a first stepped oblique side surface extending from the top layer of the circuit to the first insulating layer and a second stepped oblique side surface extending from the first insulating layer to the bottom layer of the circuit.

According to another embodiment of the present application, the first insulating layer has a core layer. The circuit top layer further includes a conductive top layer, and an anti-oxidation top layer is arranged on the conductive top layer. The packaging substrate further includes: a side conductive layer extending from the conductive top layer along the at least one stepped oblique side to the bottom line of the circuit; and a side anti-oxidation layer located above the side conductive layer and extending from the The oxidation top layer extends. The packaging substrate further includes an anti-oxidation bottom layer covering the bottom layer of the circuit, and the anti-oxidation bottom layer extends from the side anti-oxidation layer.

According to another embodiment of the present application, the circuit bottom layer further includes a conductive bottom layer, and an anti-oxidation bottom layer is provided under the conductive bottom layer. The conductive top layer, the side conductive layer and the conductive bottom layer are copper layers, and the anti-oxidation top layer, the side anti-oxidation layer and the anti-oxidation bottom layer are nickel-gold layers. The side surface of the anti-oxidation top layer is also inclined and stepped.

Another embodiment of the application also provides a package substrate strip, which includes the above-mentioned package substrate.

Another embodiment of the present application also provides a method for manufacturing a package substrate, which includes: providing a package substrate strip having a plurality of package substrate units, each of the package substrate units includes a circuit top layer, a circuit bottom layer, And a first insulating layer. The first insulating layer has a core layer and is located between the top layer of the circuit and the bottom layer of the circuit; and a portion of the first insulating layer is drilled down from an upper surface of the top layer of the circuit A first groove is formed, and the first groove has a first stepped oblique side surface extending from the top layer of the circuit to the first insulating layer; and is formed by drilling a hole from a bottom of the first groove to the bottom layer of the circuit A second groove, the second groove having a second stepped oblique side surface extending from the first insulating layer to the bottom layer of the circuit; and a plurality of package substrate units are divided to form a single package substrate.

According to another embodiment of the present application, the top layer of the circuit has a conductive top layer. The method includes forming an anti-oxidation top layer above the conductive top layer, and further includes forming a side conductive layer along with the conductive top layer. Extending from the first step oblique side surface and the second step oblique side surface to the bottom layer of the circuit; and forming a side anti-oxidation layer, which is located above the side conductive layer and extends from the anti-oxidation top layer.

According to another embodiment of the present application, the method further includes forming an anti-oxidation underlayer covering the circuit underlayer, the anti-oxidation underlayer extending from the side anti-oxidation layer.

According to another embodiment of the present application, the circuit bottom layer includes a conductive bottom layer, and the method further includes forming an anti-oxidation bottom layer under the conductive bottom layer.

Compared with the prior art, the package substrate provided by the embodiment of the present application has solder visibility, so that it can effectively determine whether the solderability of the package substrate is good, and at the same time, the cut surface of the package substrate is not easily oxidized.

In order to better understand the spirit of the embodiments of the present application, the following further describes them in conjunction with some preferred embodiments of the present application.

The embodiments of this application will be described in detail below. In the full text of the specification of this application, the same or similar components and components with the same or similar functions are denoted by similar reference numerals. The embodiments related to the drawings described herein are illustrative, diagrammatic and used to provide a basic understanding of the application. The embodiments of this application should not be construed as limitations on this application.

As used herein, the terms "approximately", "generally", "basic" and "about" are used to describe and illustrate small changes. When used in conjunction with an event or situation, the term can refer to an instance in which the event or situation occurs precisely and an instance in which the event or situation occurs in close proximity. For example, when used in conjunction with a value, the term can refer to a range of variation less than or equal to ±10% of the value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or Equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values is less than or equal to ±10% of the average value of the value (for example, less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than Or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), the two values can be considered "substantially" the same.

In this manual, unless otherwise specified or limited, relative terms such as: "central", "vertical", "lateral", "front", "rear", "right" "," "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below "", "above", "below", "top", "bottom" and their derivative terms (such as "horizontal", "downward", "upward", etc.) should be interpreted as Reference is made to the directions described in the discussion or depicted in the drawings. These relative terms are only used for the convenience of description, and do not require the construction or operation of this application in a specific direction.

In addition, sometimes amounts, ratios, and other numerical values are presented in range format in this article. It should be understood that this type of range format is used for convenience and brevity, and should be understood flexibly. It includes not only the values explicitly designated as range limits, but also all individual values or sub-ranges covered within the range, as if clearly Specify each value and sub-range in general.

Furthermore, for ease of description, "first", "second", "third", etc. may be used herein to distinguish different components of a graph or a series of graphs. "First", "Second", "Third", etc. are not intended to describe corresponding components.

FIG. 1 is a cross-sectional view of a package substrate 100 according to some embodiments of the present application. The package substrate 100 includes a top circuit layer 10, a circuit bottom layer 12, and an insulating layer 14 between the circuit top layer 10 and the circuit bottom layer 12. The insulating layer 14 may be a core layer. In addition, the package substrate 100 also includes at least one stepped oblique side surface 102 to facilitate side tinning of the package substrate 100, and at the same time, the soldering condition of the package substrate 100 can be well judged according to the solder points. In actual production, several packaging substrates 100 can be processed and transported on a packaging substrate strip (not shown) in a centralized manner, thereby improving production efficiency.

According to some embodiments of the present application, the stepped oblique side 102 can be divided into two sections, as shown in FIG. It is the second stepped oblique side 102b extending from the insulating layer 14 to the circuit bottom layer 12. The two-stage slope design side of the package substrate 100 makes the packaging tin better, and the smaller the angle between the first stepped oblique side 102a and the second stepped oblique side 102b and the surface of the circuit bottom layer 12, the side surface of the package substrate 100 The better the tinning effect.

According to some embodiments of the present application, as shown in FIG. 1, the circuit top layer 10 may include a conductive top layer 10a, which can be used for circuit connection between devices on the package substrate. For example, the conductive top layer 10a may be located on the resin layer 210b of the circuit top layer 10, such as a prepreg (prepreg) layer. The thickness of the conductive top layer 10a is about 10 to 20 microns. The packaging substrate 100 may also include an anti-oxidation top layer 10b on the conductive top layer 10a. The anti-oxidation top layer 20b can be used to protect the electronic circuits on the conductive top layer 10a.

The conductive top layer 10a and the anti-oxidation top layer 10b on it can respectively extend along the stepped oblique side surface 102 to the circuit bottom layer 12 to form a side conductive layer 112 and a side anti-oxidation layer 114 located above the side conductive layer 112. According to some embodiments of the present application, the thickness of the side conductive layer 112 may be about 10-20 microns.

According to some embodiments of the present application, the circuit bottom layer 12 may include a conductive bottom layer 12a, which can also be used for circuit connection between devices on the package substrate 100. Similarly, the conductive bottom layer 12a may be located under the resin layer 220b. According to some embodiments of the present application, the package substrate 100 may also include an anti-oxidation underlayer 115 covering the circuit underlayer 12. The anti-oxidation underlayer 115 may extend from the side anti-oxidation layer 114.

According to some embodiments of the present application, the package substrate 100 may also include another anti-oxidation underlayer 12b under the conductive underlayer.

According to some embodiments of the present application, the conductive top layer 10a, the side conductive layer 112, and the conductive bottom layer 12a are metal layers, such as a copper layer, the anti-oxidation top layer 10b, the side anti-oxidation layer 114, the anti-oxidation bottom layer 12b, and another anti-oxidation bottom layer 115 is also a metal layer, such as a nickel-gold layer.

According to some embodiments of the present application, the side surface 102c of the antioxidant top layer 10b is also stepped.

2A to 2F are methods of manufacturing the package substrate 100 according to some embodiments of the present application.

2A, a package substrate (for example, LBGA package substrate) strip is provided with a number of package substrate units. Each package substrate unit 200 includes: a circuit top layer 210, a circuit bottom layer 220, and a substrate between the circuit top layer 210 and the circuit bottom layer 220 Insulation layer 214. The thickness of the circuit top layer 210 and the circuit bottom layer 220 is about 35 to 55 microns, the thickness of the insulating layer 214 is about 55 to 65 microns, and the insulating layer may be a BT resin substrate material. The top line 210 may include a top conductive layer 210a, and the bottom line 220 may include a conductive bottom layer 220a. The conductive top layer 210a and the conductive bottom layer 220a may be made of metal materials, such as copper. The thickness and shape of the conductive top layer 210a and the conductive bottom layer 220a will vary with the manufacturing process during the production process. For example, the initial thickness can be about 12 microns, and the thickness can be reduced to about 3 microns through an etching process. Similarly, those familiar with this technology should understand that during the semiconductor manufacturing process, other layer structures may also be similarly affected, and the existence of the structure and the relationship between them cannot be denied.

Referring to FIG. 2B, at one of the openings on the conductive top layer 210a, the top line 210 at the opening and a part of the insulating layer under the top line 210 are removed downward to expose part of the surface of the insulating layer 214, and a first groove 201 is formed at the same time . The size of the first groove 201 can be controlled by controlling the thickness and the manufacturing process of the conductive top layer 210a. For example, according to some embodiments of the present application, the width of the upper opening of the first groove 201 can be about 550 microns. The number and position of the first grooves 201 can be determined according to needs, and will not be described in detail here. In some embodiments, other grooves may also be formed on the package substrate 100, such as grooves for forming through holes.

According to some embodiments of the present application, the first groove 201 can be formed by processes such as laser drilling and mechanical drilling, so that the first groove 201 has a first oblique side surface extending from the top layer 210 of the circuit to the insulating layer 214 201a. Stepped (or multi-section) side design can have better soldering effect. For example, in the embodiment shown in FIG. 2B, the first oblique side surface 201a may be composed of two sections of oblique side surfaces. Similarly, the shape and size of the first oblique side surface 201a can also be controlled by controlling the thickness and manufacturing process of the conductive top layer 210a.

2C, from the bottom of the first groove 201, the insulating layer at the bottom of the first groove 201 and a portion of the circuit bottom layer under the insulating layer 214 are removed downwards to form the second groove 202.

According to some embodiments of the present application, the second groove 202 may be formed into an inverted trapezoid structure by laser drilling and other processes, wherein the conductive bottom layer 220a may be used as an etch stop layer. This can expose part of the conductive bottom layer of the circuit bottom layer 220, so as to achieve precise control of the depth of the second groove 202. The second groove 202 has a second inclined side surface 201 b extending from the insulating layer 214 to the bottom of the second groove 202. According to some embodiments of the present application, the width of the bottom of the second groove 202 is about 240 to 260 microns.

According to some embodiments of the present application, the total depth of the first groove 201 and the second groove 202 may be about 110 to 130 microns, such as 120 microns. The total depth can be further improved by structural design and manufacturing process, such as using a laser method to make the design space larger. On the other hand, the bottom copper in the circuit bottom layer 220 can help control the total depth, thereby achieving depth consistency control. One or more conductive layers can be formed in separate positions on the package substrate where the grooves have been formed.

For example, referring to FIG. 2D, a first conductive layer 212 may be formed, which may extend along the first side surface 201a of the first groove 201 and the second oblique side surface 201b of the second groove 202 to the bottom of the second groove 202 , So that the first conductive layer 212 has a stepped oblique side surface, thereby forming the side conductive layer 112 of the substrate unit 200. The first conductive layer 212 may be a copper layer with a thickness of about 1 μm, and may be formed by, for example, but not limited to, a chemical method. The first conductive layer 212 can also be formed on the upper surface of the conductive top layer 210a and the lower surface of the conductive bottom layer 220a to further thicken the conductive top layer 210a and the conductive bottom layer 220a, or cover the bottom of the second groove 202. The first conductive layer 212 can be prepared for the subsequent formation of a circuit layer.

Referring to FIG. 2E, the upper and lower surfaces of the substrate 200 may be laminated with a polymer layer, the patterned polymer layer is exposed and developed, and then the polymer layer is removed to obtain separate circuits. In some embodiments, individual grooves can also be filled as needed, for example, a groove used to fill a through hole to form a through hole. In some embodiments, the thickness of the copper layer in the first groove 201 and/or the second groove 202 can also be adjusted as needed. For example, in one example, the second conductive layer 216 may be formed on the upper and lower surfaces of the substrate 200 and the oblique sides of the first groove 201 and the second groove 202 by, for example, but not limited to, an electroplating method. The second conductive layer 216 can cover the first conductive layer 212 and its stepped oblique side surface, and can fill individual grooves as needed. The second conductive layer 216 can be about 22-28 microns thick, for example, can be formed as a copper layer of about 25 microns.

Subsequently, the thickness of the second conductive layer 216 on the stepped oblique side of the first conductive layer 212 can be appropriately adjusted as needed. For example, the polymer layer is laminated, exposed and developed again to pattern the polymer. Layer to etch the exposed second conductive layer to reduce the thickness of the second conductive layer 216 on the oblique sidewalls and bottom of the first groove 201 and the second groove 202 to about 10 microns, and then remove the polymer物层。 The material layer. The thickness of the conductive top layer 210a and the conductive bottom layer 220a of the substrate unit 200 can be further increased by the second conductive layer 216.

After the above exemplary processing, such as forming the first conductive layer 212 and the second conductive layer 216, and based on the operations of the first conductive layer 212 and the second conductive layer 216, the required appropriate conductive top layer, side conductive layer, and The conductive bottom layer, such as the conductive top layer 10a, the side conductive layer 112, and the conductive bottom layer 12a in FIG. 1.

According to some embodiments of the present application, during the etching of the second conductive layer 216, the conductive top layer 210a located above the circuit top layer can be formed with an inclined side surface with an inclined step shape, such as the conductive top layer 210a in FIG. 2F. The side 201c.

An anti-oxidation layer can be formed on the circuit layer to prevent oxidation of the circuit layer and provide good conductivity.

For example, referring to FIG. 2G, an anti-oxidation layer 218 is formed on the second conductive layer 216 of the substrate unit 200 according to location requirements to protect the conductive layer underneath from being oxidized and at the same time enhance the electrical transmission performance of the circuit. For example, the anti-oxidation top layer 10b, the side anti-oxidation layer 114, and the anti-oxidation bottom layer 12b may be formed above the conductive top layer 210, the side conductive layer 112, and below the conductive bottom layer 220a of the substrate unit 200, respectively. In some embodiments, the anti-oxidation underlayer 218 may cover the conductive layer at the bottom of the second groove 202, for example, another anti-oxidation underlayer 115 as shown in FIG. 1. The anti-oxidation layer may be, for example, but not limited to, a nickel-gold layer. As shown in FIG. 2G, since the conductive top layer 210a above the top layer of the circuit forms a stepped side surface, for example, the side surface 201c of the conductive top layer 210a in FIG. 2F (as shown in FIG. 2F), the anti-oxidation layer on it , It is also possible to form an inclined stepped inclined side surface 102c. Finally, the package substrate strip obtained by the processing method can be cut to obtain a top view of the package substrate strip 110 composed of an array of package substrates 100 as shown in FIG. 3 and the respective saw regions (A and A). ') cross-sectional view.

Referring to FIG. 3, the stepped oblique side structure of the package substrate 100 allows the saw area (A and A') to be designed as a stepped half-hole structure. When soldering, the whole product can be observed by the side creeping tin. The soldering condition includes the soldering condition on the bottom and the sides, so as to effectively determine whether the side creeping condition of the package substrate 100 is good, and at the same time, the soldering area can be increased, thereby improving the firmness and stability of the product.

The structure design of the package substrate proposed in the present invention enables the quality of the package solder on the substrate to be confirmed by observing the solder climbing on the side, and at the same time increases the solder contact area of the finished substrate during the packaging process and improves the soldering yield. And the multi-stage climbing design effectively improves the soldering effect, and the size of the oblique side of the substrate can be effectively controlled by proper process selection, and uniform control can be achieved at the same time.

The technical content and technical features of this application have been disclosed above, but those who are familiar with this technology may still make various substitutions and modifications without departing from the spirit of this application based on the teachings and disclosures of this application. Therefore, the scope of protection of this application should not be limited to the content disclosed in the embodiments, but should include various substitutions and modifications that do not deviate from this application, and should be covered by the patent application scope of this patent application.

10: Top of the line 10a: conductive top layer 10b: Antioxidant top layer 12: Bottom of the line 12a: Conductive bottom layer 12b: Antioxidant bottom layer 14: Insulation layer 100: Package substrate 102: Stepped oblique side 102a: Oblique side of the first step 102b: Oblique side of the second step 102c: Inclined stepped oblique side 110: Package substrate strip 112: side conductive layer 114: side anti-oxidation layer 115: Antioxidant bottom layer 200: Package substrate unit/substrate 201: The first groove 201a: first oblique side 201b: second oblique side 201c: side 202: second groove 210: Top of the line 210a: conductive top layer 210b: resin layer 212: first conductive layer 214: Insulation layer 216: second conductive layer 218: Antioxidant bottom layer 220: bottom line 220a: conductive bottom layer 220b: resin layer A: Sawing area A': sawing area

In the following, the drawings necessary to describe the embodiments of the present application or the prior art will be briefly described in order to describe the embodiments of the present application. Obviously, the drawings in the following description are only part of the embodiments in this application. For those who are familiar with the technology, it is still possible to obtain drawings of other embodiments based on the structures illustrated in these drawings without requiring creative work. FIG. 1 is a cross-sectional view of a package substrate 100 according to some embodiments of the present application 2A to 2G are methods of manufacturing the package substrate 100 according to some embodiments of the present application FIG. 3 is a top view and a cross-sectional view of a cutting part of a packaging substrate strip 110 composed of an array of packaging substrates 100 according to some implementations of the present application

10: Top of the line

10a: conductive top layer

10b: Antioxidant top layer

12: Bottom of the line

12a: Conductive bottom layer

12b: Antioxidant bottom layer

14: Insulation layer

100: Package substrate

102: Stepped oblique side

102a: Oblique side of the first step

102b: Oblique side of the second step

102c: Inclined stepped oblique side

112: side conductive layer

114: side anti-oxidation layer

115: Antioxidant bottom layer

210b: resin layer

220b: resin layer

Claims (19)

A packaging substrate, which includes: The top layer of a line; One line bottom layer; A first insulating layer located between the top layer of the circuit and the bottom layer of the circuit; and At least one stepped oblique side surface having a first stepped oblique side surface extending from the top layer of the circuit to the first insulating layer and a second stepped oblique side surface extending from the first insulating layer to the bottom layer of the circuit . The package substrate of claim 1, wherein the first insulating layer has a core layer. Such as the packaging substrate of claim 1, wherein the circuit top layer further includes a conductive top layer, and an anti-oxidation top layer is provided on the conductive top layer. Such as the packaging substrate of claim 3, wherein the packaging substrate further includes: One side conductive layer extends from the conductive top layer along the at least one stepped oblique side to the bottom line of the circuit; and one side anti-oxidation layer is located above the side conductive layer and extends from the anti-oxidation top layer. Such as the package substrate of claim 4, which further comprises an anti-oxidation underlayer covering the bottom layer of the circuit, and the anti-oxidation underlayer extends from the side anti-oxidation layer. Such as the packaging substrate of claim 1, wherein the circuit bottom layer further includes a conductive bottom layer, and an anti-oxidation bottom layer is provided under the conductive bottom layer. Such as the package substrate of claim 4 or 6, wherein the conductive top layer, the side conductive layer, and the conductive bottom layer are copper layers. The package substrate according to any one of claims 4 to 6, wherein the anti-oxidation top layer, the side anti-oxidation layer and the anti-oxidation bottom layer are nickel-gold layers. Such as the package substrate of claim 3, wherein the side surface of the anti-oxidation top layer is also inclined and stepped. A packaging substrate strip, which includes the packaging substrate according to any one of claims 1 to 9. A method of manufacturing a package substrate, which includes: A packaging substrate strip with a plurality of packaging substrate units is provided, each of the packaging substrate units includes: The top layer of a line; The bottom layer of a line; and A first insulating layer located between the top layer of the circuit and the bottom layer of the circuit; A first groove is formed by drilling down from an upper surface of the top layer of the circuit to a portion of the first insulating layer, and the first groove has a first step extending from the top layer of the circuit to the first insulating layer Oblique side; and Drilling a hole from a bottom of the first groove to the circuit bottom layer to form a second groove, the second groove having a second stepped oblique side surface extending from the first insulating layer to the circuit bottom layer; and Several packaging substrate units are divided to form a single packaging substrate. The method for manufacturing a package substrate according to claim 11, wherein the top layer of the circuit has a conductive top layer, and the method includes forming an anti-oxidation top layer on the conductive top layer. According to claim 12, the method for manufacturing a package substrate, further comprising: forming a conductive layer on one side, and the conductive layer on the side extends from the conductive top layer along the first stepped oblique side and the second stepped oblique side to the circuit bottom layer; And forming a side anti-oxidation layer, which is located above the side conductive layer and extends from the anti-oxidation top layer. The method for manufacturing a package substrate according to claim 13, further comprising forming an anti-oxidation underlayer covering the bottom layer of the circuit, the anti-oxidation underlayer extending from the side anti-oxidation layer. According to claim 11, the method of manufacturing a package substrate, wherein the circuit bottom layer includes a conductive bottom layer, and the method further includes forming an anti-oxidation bottom layer under the conductive bottom layer. Such as the method of manufacturing a package substrate of claim 12, wherein the side surface of the anti-oxidation top layer is also inclined and stepped. The method of manufacturing a package substrate of claim 11, wherein the first insulating layer has a core layer. According to claim 13 or 15, the method of manufacturing a package substrate, wherein the conductive top layer, the side conductive layer, and the conductive bottom layer are copper layers. The method for manufacturing a package substrate according to any one of claims 13 to 15, wherein the anti-oxidation top layer, the side anti-oxidation layer and the anti-oxidation bottom layer are nickel-gold layers.

Images