TW202133396A - Memory structure and method of manufacturing the same - Google Patents

Abstract

A memory structure and its manufacturing method are provided. The memory structure includes a substrate having active regions, wherein adjacent active regions are separated by an isolation structure. The memory structure includes several stacked structures disposed on the active regions, respectively. Each of the stacked structures includes a tunnel dielectric layer on the substrate and a floating gate on the tunnel dielectric layer. The floating gate includes a lower silicon layer and an upper silicon layer, wherein the lower silicon layer includes one or more implants selected from nitrogen gas, carbon or a combination thereof.

Description

Memory structure and manufacturing method thereof

The present invention relates to a memory structure and a manufacturing method thereof, and particularly relates to a non-volatile memory structure and a manufacturing method thereof.

In the non-volatile memory, according to whether the data in the memory can be rewritten at any time while using the computer, it can be divided into two categories: read-only memory (ROM) and flash memory (flash). memory). Among them, flash memory has gradually become the mainstream technology of non-volatile memory due to its low cost.

Generally speaking, a flash memory contains two gates, the first gate is a floating gate for storing data, and the second gate is a control gate for data input and output. The floating gate is located below the control gate and is in a "floating" state. The so-called floating refers to the use of insulating materials to surround and isolate the floating gate to prevent charge loss. The control gate is connected to the word line to control the device. One of the advantages of flash memory is that it can block-by-block erasing. Flash memory is widely used in corporate servers, storage and network technology, as well as a wide range of consumer electronics products, such as flash drives for flash drives, mobile phones, digital cameras, tablets, and personal computer cards for notebook computers And embedded controllers and so on.

Although the existing formation methods of non-volatile memory are sufficient for their original intended use, they have not fully met the requirements in all aspects. Therefore, the technology of non-volatile memory still has problems to be overcome.

The present invention discloses a memory structure including a substrate, wherein the substrate includes a plurality of active regions, and the active regions are separated by an isolation structure. The memory structure further includes a plurality of stacked structures respectively located above each active area, and each stacked structure includes a tunneling dielectric layer on the substrate and a floating gate located on the tunneling dielectric layer. The floating gate includes a lower silicon layer and an upper silicon layer on the tunnel dielectric layer, wherein the lower silicon layer contains nitrogen, carbon, or a combination of dopants.

The present invention discloses a manufacturing method of a memory structure, which includes providing a substrate including a plurality of active regions. The manufacturing method of the memory structure also includes forming a plurality of stacked structures respectively located above each active area, wherein each stacked structure includes a tunneling dielectric layer on the substrate and a floating gate located on the tunneling dielectric layer . The floating gate includes a lower silicon layer and an upper silicon layer on the tunnel dielectric layer, wherein the lower silicon layer contains nitrogen, carbon, or a combination of dopants. The manufacturing method of the memory structure further includes forming a plurality of trenches respectively located between the active regions, and forming an isolation structure in the trenches.

The present invention will be explained more fully with reference to the drawings of the embodiments of the present invention. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawing will be exaggerated for clarity. The same or similar element numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one. In order to simplify the description, the drawings used in the embodiment draw four stacked structures including floating gates on the substrate and the control gates extending above the floating gates to illustrate the memory structure.

FIGS. 1A-10 are schematic cross-sectional views corresponding to different intermediate stages of manufacturing a memory structure according to an embodiment of the present invention. Referring to FIG. 1A, a substrate 10 is provided. The substrate 10 includes a source region and a drain region (not shown). The material of the substrate 10 may include silicon, gallium arsenide, gallium nitride, germanium silicide, silicon on an insulating layer, other suitable materials, or a combination of the foregoing.

Next, a tunneling dielectric material layer 11 is formed on the substrate 10. The tunneling dielectric material layer 11 is, for example, silicon oxide or a high dielectric constant material (for example, the dielectric constant is greater than 4). The high dielectric constant material may include, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, or hafnium tantalum oxide. In an embodiment, the thickness of the tunneling dielectric material layer 11 may range from 3 nm to 10 nm.

Referring to FIG. 1B, a silicon layer 12 is formed on the tunneling dielectric material layer 11. The silicon layer 12 is, for example, amorphous silicon, and can be formed by a deposition process. In an embodiment, the thickness of the silicon layer 12 may range from 10 nm to about 30 nm, for example, about 20 nm.

Then, referring to FIG. 1C, an implantation process 12M is performed to implant dopants in the silicon layer 12. For example, dopants containing nitrogen (N ₂ ), carbon, or a combination of the foregoing are implanted in the silicon layer 12. In one embodiment, nitrogen is implanted in the silicon layer 12, and the implantation dose of nitrogen is, for example, in the range of ^{1×10 15} atoms/cm ² to 4×10 ¹⁵ atoms/cm ^2. In one embodiment, the implantation energy of nitrogen is, for example, in the range of 2 KJ to 5 KJ, such as 3 KJ. In addition, in other embodiments, N-type dopants, such as phosphorus (P), may be implanted in the silicon layer 12, so that the floating gate produced later has an N-type conductivity.

Then, referring to FIG. 1D, a silicon layer 13 is formed on the silicon layer 12. The silicon layer 13 includes polysilicon, and can be formed using a deposition process. In one embodiment, the silicon layer 13 is, for example, an undoped polysilicon layer. In an embodiment, the thickness of the silicon layer 13 may range from 40 nm to 100 nm, such as 60 nm.

Then, referring to FIG. 1E, an oxide layer 14, a mask layer 16, a mask layer 17, and a patterned photoresist 18 are sequentially formed on the silicon layer 13. The material of the oxide layer 14 may include silicon oxide or silicon oxynitride, and may be formed by thermal oxidation, chemical vapor deposition, or a combination of the foregoing methods. In an embodiment, the thickness of the oxide layer 14 may range from 5 nm to 15 nm. The material of the mask layer 16 may include silicon nitride or silicon oxynitride, the material of the mask layer 17 may include silicon oxide, and the mask layers 16 and 17 may be formed by chemical vapor deposition.

Referring to FIG. 1F, the exposed portion of the mask layer 17 is removed according to the patterned photoresist 18 to form a patterned mask layer 170. Anisotropic etching, such as dry etching, can be used to remove the exposed part of the mask layer 17.

Referring to Figure 1G, next, use the patterned photoresist 18 and the patterned mask layer 170 as a mask to remove the exposed mask layer 16 and the oxide layer 14 to form a patterned mask layer 160 and a patterned oxide layer 140. Anisotropic etching, such as dry etching, can be used to perform the aforementioned removal. So far, the stacked structure 19 is formed on the silicon layer 13. In addition, when part of the oxide layer 14 is removed, the silicon layer 13 can be used as an etching stop layer. Although in this example, the patterned mask layers 170 and 160 constitute a patterned mask stack (multi-layer structure) HM. But in other examples, the patterned mask stack may be a single-layer structure.

Referring to Figure 1H, after the stacked structure 19 is formed, in the same etching step, the silicon layers 13 and 12 are patterned to form the upper silicon layer 130 and the lower silicon layer 120 of the floating gate FG, respectively. An opening 210 is formed between adjacent stacked structures 19 and between adjacent floating gates FG. The opening 210 exposes part of the tunneling dielectric material layer 11. In one embodiment, the silicon layers 13 and 12 are patterned by dry etching, such as reactive ion etching and/or self-aligned double patterning.

It is worth mentioning that since the silicon layer 12 contains nitrogen, carbon, phosphorus and other dopants, the etching rate of the silicon layer 12 is lower than that of the silicon layer 13, so that the width W1 of the lower silicon layer 120 formed after etching is greater than The width W2 of the upper silicon layer 130.

In one embodiment, the width W1 of the lower silicon layer 120 has a ratio (W1/W2) to the width W2 of the upper silicon layer 130, and the ratio is in the range of greater than 1 to 1.5, for example, about 1.1. The content of dopants containing nitrogen, carbon, or the foregoing combination in the silicon layer 12 can be adjusted according to actual application requirements to obtain a desired ratio. For example, when the content of the aforementioned dopants is increased, the etching rate of the silicon layer 12 will be slower, and the width W1 of the lower silicon layer 120 formed will be larger, and the ratio of the width W1/width W2 can be changed.

Next, referring to Figure 11, the patterned photoresist 18 is removed, and the patterned mask stack HM, the patterned oxide layer 140, and the floating gate FG are used as a mask for the exposed tunneling dielectric material layer 11 and The underlying substrate 10 is etched, and a trench 220 is formed in the substrate 10. As shown in FIG. 11, the area between adjacent trenches 220 may be the active area A _A of the memory structure. Furthermore, the tunneling dielectric material layer 11 can form a dielectric pattern after etching to serve as a tunnel oxide layer 110 of the memory structure. In one embodiment, the sidewall 120c of the lower silicon layer 120 and the sidewall 110c of the tunneling dielectric layer 110 are substantially coplanar. The floating gate FG and the tunnel oxide layer 110 above the substrate 10 constitute the stacked structure 20.

It is worth mentioning that since the lower silicon layer 120 contains implants, its etching rate will be lower than that of the underlying substrate 10. Thus, the width W1 and below the lower silicon layer 120 corresponding to the active region width W _A A _A are substantially equal, and the upper silicon layer is smaller than the width W2 130.

Referring to FIG. 1J, afterwards, an isolation material layer 24 is deposited on the patterned mask stack HM, the patterned oxide layer 140 and the stacked structure 20, and the isolation material layer 24 is filled in the trench 220 and the opening 210. In an embodiment, the isolation material layer 24 may be formed to both sides of the patterned mask stack HM, or beyond the top surface of the patterned mask stack HM (as shown in FIG. 1J). The material of the isolation material layer 24 includes an insulating material, such as silicon oxide, silicon nitride, or a combination thereof, and the isolation material layer 24 can be formed by a chemical vapor deposition method.

Referring to FIG. 1K, then, part of the isolation material layer 24 and the patterned mask layer 170 are removed. The remaining isolation material layer 240 is formed, for example, to both sides of the patterned mask layer 160, and the top surface of the isolation material layer 240 and the top surface of the patterned mask layer 160 are substantially coplanar. In one embodiment, this removal step can be performed by a method such as chemical mechanical polishing (CMP).

After that, referring to FIG. 1L, a first etching step is performed to remove part of the isolation material layer 240, so that the isolation material layer 240 is recessed. The remaining isolation material layer forms an isolation structure 242 in the opening 210 and the trench 220. In addition, during the first etching step, part of the patterned mask layer 160 is also removed. The method of removing part of the isolation material layer 240 includes anisotropic etching, such as dry etching. In one embodiment, the top surface 242a of the controllable isolation structure 242 is lower than the top surface 130a of the upper silicon layer 130, so that the gate coupling between the floating gate FG and the conductive layer that is subsequently formed as a control gate can be improved. Rate (Gate-Coupling Ratio; GCR). In addition, the top surface 242a of the isolation structure 242 can be controlled to be higher than the top surface 110a of the tunneling dielectric layer 110, so as to avoid damage to the tunneling dielectric layer 110 during the process of forming the isolation structure 242.

After that, referring to Figure 1M, the patterned mask layer 160' left after the foregoing first etching step is performed is removed.

Referring to FIG. 1N, a second etching step is then performed to further etch the isolation structure 242 and remove the patterned oxide layer 140 to form the isolation structure 242-2. A dry etching process can be used to etch the isolation structure 242 and remove the patterned oxide layer 140.

It is worth mentioning that by controlling the deposition thickness of the silicon layer 12, the lower silicon layer 120 of different floating gates FG can be made to have a uniform height, thereby controlling the position between the floating gates FG as shown in Figure 1L. between depth uniformity (uniformity) recessed insulating material layer 240, thereby enabling the isolation structure between the active region _a a (e.g. isolation structure 242, or isolation structures 242-2) having a top surface height consistency.

Referring to Figure 10, afterwards, an inter-gate dielectric layer 27 is conformably formed on the floating gate FG, and a conductive layer 28 is deposited on the inter-gate dielectric layer 27 to serve as a memory structure Control the gate. In one embodiment, the inter-gate dielectric layer 27 may be a single-layer structure or a multi-layer structure, and the material of the inter-gate dielectric layer 27 may include silicon oxide, silicon nitride, or a combination thereof. For example, the inter-gate dielectric layer 27 can be a silicon oxide/silicon nitride/silicon oxide structure (ONO structure), or a NONON structure. Furthermore, the conductive layer 28 may have a single-layer or multi-layer structure. The material of the conductive layer 28 includes polysilicon, metal, metal silicide or other conductive materials. For example, the metal may include titanium, tantalum, tungsten, aluminum, or zirconium. The metal silicide may include nickel silicide, titanium silicide, or tungsten silicide. So far, the fabrication of the memory structure of this embodiment is completed.

10²⁰ /cm³ 至­­­1

10²² /cm³ 的範圍之間。It is worth mentioning that in an embodiment where nitrogen is implanted on the silicon layer 12 (as shown in FIG. 1C), the lower silicon layer 120 of the floating gate FG that is finally produced contains the doping concentration of dopant nitrogen, for example, 1

10 ²⁰ /cm ³ to 1

10 ²² /cm ³ between the range.

In one embodiment, the silicon layer 12 originally formed of an amorphous silicon material is converted into polysilicon after a thermal process during the manufacturing of the memory structure. Therefore, in the memory structure produced as shown in FIG. 10, the lower silicon layer 120 and the upper silicon layer 130 of the floating gate FG both include polysilicon. The dopants of nitrogen, carbon, or a combination of the foregoing in the silicon layer 12 also make the grain size of the polysilicon to be formed later than that of the polysilicon of the upper silicon layer 130 that does not contain the aforementioned dopants.

Referring to FIG. 2, it shows a schematic cross-sectional view of a memory structure according to another embodiment of the present invention. As shown in the figure, the lower silicon layer 120 of the floating gate FG has a first average crystal grain size, the upper silicon layer 130 has a second average crystal grain size, and the first average crystal grain size is smaller than the second average crystal grain size. In one embodiment, the first average crystal grain size is, for example, 5 nm to 20 nm, and the second average crystal grain size is, for example, 50 nm to 80 nm. It is worth mentioning that the smaller the grain size and the more grain boundaries, the more paths for electrons to flow. Therefore, the current generated during the write operation in the memory structure is more effective. The more stable the channel from the active area A _A jumps over the tunneling dielectric layer 110 to inject the floating gate FG, and the path of current flowing through the tunneling dielectric layer 110 can be dispersed. Therefore, after multiple write operations, damage to the tunneling dielectric layer 110 can be reduced, thereby making the data stored in the floating gate more difficult to lose data.

According to the above embodiments, the present invention can stably control the topology of the manufactured floating gate FG. In detail, by additionally implanting dopants such as nitrogen, carbon, and phosphorus in the silicon layer 12, the lower silicon layer 120 of the floating gate FG can be made to have a larger width than that of the upper silicon layer 130. and the width of the floating gate FG is located below the active region a _a width of the lower silicon layer 120 is substantially equal. For adjacent floating gates FG, the distance between adjacent upper silicon layers 130 is greater than the distance between adjacent lower silicon layers 120, so the upper silicon layer of adjacent floating gates FG can be reduced The coupling between 130 (FG-FG coupling). At the same time, because the floating gate FG has a lower silicon layer 120 wider than the upper silicon layer 130 and an active area A _A , the channel area of the active area A _A is also increased, so that more operating current can flow through the channel and be injected into the floating Gate FG, thereby reducing the operating voltage. Furthermore, since the lower silicon layer 120 of the present invention has a smaller average grain size and more grain boundaries, the current can be more stably injected into the floating gate FG, so that the electrical performance is more stable.

In summary, the memory structure and manufacturing method proposed by the present invention is to implant dopants containing nitrogen, carbon, or a combination of the foregoing into the lower silicon layer of the floating gate on the tunnel dielectric layer. The lower silicon layer forms the lower part of the floating gate in the subsequent process. The manufacturing method of the memory structure proposed according to the present invention can stably control the topology of the manufactured floating gate FG, including controlling the width of the lower silicon layer, the width of the active area, and the gap between the floating gates. The height of the isolation structure. The memory structure prepared according to the present invention has at least many benefits such as speeding up the writing speed, lowering the writing operation voltage, having good data retention and stable electrical performance, thereby improving the yield and the final product. Reliability.

Although the present invention has been disclosed in several preferred embodiments as described above, it is not intended to limit the present invention. Anyone with ordinary knowledge in the art can make any changes and modifications without departing from the spirit and scope of the present invention. Retouching, therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

10: Substrate 11: Tunneling dielectric material layer 110: Tunneling dielectric layer 12, 13: Silicon layer 120: Lower silicon layer 130: Upper silicon layer 12M: Planting process 14: Oxide layer 140: Patterned oxide layer 16 , 17: mask layer 160, 160', 170: patterned mask layer 18: patterned photoresist 19, 20: stacked structure 210: opening 130b: bottom surface 110a, 120a, 130a, 242a: top surface 110c, 120c, 130c: sidewall 220: trench 24, 240: isolation material layer 242, 242-2: isolation structure 27: inter-gate dielectric layer 28: conductive layer HM: patterned mask stack FG: floating gate W1, W2 : Width A _A ~: active area

FIGS. 1A-10 are schematic cross-sectional views corresponding to different intermediate stages of manufacturing a memory structure according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a memory structure according to another embodiment of the present invention.

10: Base

110a, 120a, 130a, 242a: top surface

110: Tunneling dielectric layer

120: Lower silicon layer

120c, 130c: side wall

130: upper silicon layer

242-2: Isolation structure

20: Stacked structure

FG: floating gate

210: opening

A _A : Active area

Claims (10)

A memory structure including: A substrate includes a plurality of active regions, and adjacent active regions are separated by an isolation structure; A plurality of stacked structures are respectively located above the active regions, and each of the foregoing stacked structures includes a tunneling dielectric layer on the substrate and a floating gate on the tunneling dielectric layer, the floating gate Extremely contains: A lower silicon layer on the tunneling dielectric layer, wherein the lower silicon layer contains nitrogen, carbon, or a combination of dopants; and An upper silicon layer is located on the lower silicon layer. The memory structure described in the first item of the scope of patent application, wherein the lower silicon layer contains dopant nitrogen with a doping concentration of 1

10 ²⁰ /cm ³ to 1

Between 10 ²² /cm ³ range. The memory structure described in claim 1, wherein the lower silicon layer of the floating gate has a first average crystal grain size, the upper silicon layer has a second average crystal grain size, and the first average crystal grain size The grain size is smaller than the second average grain size. A method for manufacturing a memory structure includes: Providing a substrate, the substrate including a plurality of active regions; A plurality of stacked structures are formed respectively above the active regions, wherein each of the foregoing stacked structures includes a tunneling dielectric layer on the substrate and a floating gate on the tunneling dielectric layer, the floating gate Extremely contains: A lower silicon layer on the tunneling dielectric layer, wherein the lower silicon layer contains nitrogen, carbon, or a combination of dopants; and An upper silicon layer located on the lower silicon layer; Forming a plurality of trenches respectively located between the active regions; and An isolation structure is formed in the trenches. According to the manufacturing method of the memory structure described in claim 4, wherein the lower silicon layer contains dopant nitrogen with a doping concentration of 1

10 ²⁰ /cm ³ to 1

Between 10 ²² /cm ³ range. According to the manufacturing method of the memory structure described in claim 4, the lower silicon layer of the floating gate has a first average grain size, the upper silicon layer has a second average grain size, and the first An average crystal grain size is smaller than the second average crystal grain size. According to the method of manufacturing the memory structure described in claim 4, wherein forming the floating gate includes: depositing a first silicon layer on the tunneling dielectric layer; and implanting includes nitrogen (N ₂ ) Doping with carbon, or a combination of the foregoing, in the first silicon layer; and depositing a second silicon layer on the first silicon layer. According to the manufacturing method of the memory structure described in claim 7, wherein nitrogen is implanted in the first silicon layer, and the implantation dose of nitrogen is about 1 ^{×10 15} atoms/cm ² to about 4×10 ¹⁵ atoms/cm Within the range of ^2. According to the manufacturing method of the memory structure described in claim 7, wherein after the second silicon layer is deposited, the second silicon layer and the first silicon layer are patterned in the same etching step, To form the upper silicon layer and the lower silicon layer respectively. According to the manufacturing method of the memory structure described in the scope of patent application, the etching rate of the first silicon layer is lower than the etching rate of the second silicon layer.

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