TW202133251A - Etching method, substrate processing apparatus, and substrate processing system - Google Patents
Etching method, substrate processing apparatus, and substrate processing system Download PDFInfo
- Publication number
- TW202133251A TW202133251A TW110101577A TW110101577A TW202133251A TW 202133251 A TW202133251 A TW 202133251A TW 110101577 A TW110101577 A TW 110101577A TW 110101577 A TW110101577 A TW 110101577A TW 202133251 A TW202133251 A TW 202133251A
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- film
- gas
- area
- etching method
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 220
- 238000005530 etching Methods 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 78
- 239000000463 material Substances 0.000 claims abstract description 37
- 239000002243 precursor Substances 0.000 claims description 47
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 239000013626 chemical specie Substances 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 239000011368 organic material Substances 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 2
- 230000003213 activating effect Effects 0.000 claims 1
- 239000007789 gas Substances 0.000 description 185
- 239000000126 substance Substances 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 16
- 239000011261 inert gas Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 7
- 229910052799 carbon Inorganic materials 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000005046 Chlorosilane Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 4
- IJOOHPMOJXWVHK-UHFFFAOYSA-N chlorotrimethylsilane Chemical compound C[Si](C)(C)Cl IJOOHPMOJXWVHK-UHFFFAOYSA-N 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000010790 dilution Methods 0.000 description 4
- 239000012895 dilution Substances 0.000 description 4
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910003902 SiCl 4 Inorganic materials 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- -1 for example Chemical compound 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 239000004215 Carbon black (E152) Substances 0.000 description 2
- 101001139126 Homo sapiens Krueppel-like factor 6 Proteins 0.000 description 2
- 101000661807 Homo sapiens Suppressor of tumorigenicity 14 protein Proteins 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- KCWYOFZQRFCIIE-UHFFFAOYSA-N ethylsilane Chemical compound CC[SiH3] KCWYOFZQRFCIIE-UHFFFAOYSA-N 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- FZHAPNGMFPVSLP-UHFFFAOYSA-N silanamine Chemical compound [SiH3]N FZHAPNGMFPVSLP-UHFFFAOYSA-N 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000005049 silicon tetrachloride Substances 0.000 description 2
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 2
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 2
- 239000005052 trichlorosilane Substances 0.000 description 2
- 239000005051 trimethylchlorosilane Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 101000710013 Homo sapiens Reversion-inducing cysteine-rich protein with Kazal motifs Proteins 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 150000001244 carboxylic acid anhydrides Chemical class 0.000 description 1
- 150000001732 carboxylic acid derivatives Chemical class 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012948 isocyanate Substances 0.000 description 1
- 150000002513 isocyanates Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000003507 refrigerant Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 1
- 239000006200 vaporizer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3244—Gas supply means
- H01J37/32449—Gas control, e.g. control of the gas flow
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
- H01J2237/3341—Reactive etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
- Plasma Technology (AREA)
Abstract
Description
本發明之例示性實施形態,係關於一種蝕刻方法、基板處理裝置、及基板處理系統。An exemplary embodiment of the present invention relates to an etching method, a substrate processing apparatus, and a substrate processing system.
為了於基板內的膜形成開口,利用電漿蝕刻。專利文獻1揭露一種技術,於界定藉由有機膜之電漿蝕刻而形成的開口之側壁上,形成含矽的保護膜,進一步施行有機膜之電漿蝕刻。 [習知技術文獻] [專利文獻]In order to form an opening in the film in the substrate, plasma etching is used. Patent Document 1 discloses a technique of forming a protective film containing silicon on the sidewalls defining the opening formed by the plasma etching of the organic film, and further performing the plasma etching of the organic film. [Literature Technical Literature] [Patent Literature]
專利文獻1:日本特開第2012-204668號公報Patent Document 1: Japanese Patent Laid-Open No. 2012-204668
[本發明所欲解決的問題][Problems to be solved by the present invention]
本發明提供一種在基板內的區域之蝕刻中抑制遮罩的開口之阻塞的技術。 [解決問題之技術手段]The present invention provides a technique for suppressing the clogging of the opening of the mask during the etching of the area in the substrate. [Technical means to solve the problem]
於一例示性實施形態中,提供一種蝕刻方法。該蝕刻方法,包含膜形成步驟,於基板之表面上形成膜。基板,具備被蝕刻之區域、及遮罩。遮罩,設置於基板之區域上,提供使該區域部分地露出的開口。膜,由與基板之區域的材料相同種類的材料形成。蝕刻方法,更包含區域蝕刻步驟,蝕刻基板之區域。 [本發明之效果]In an exemplary embodiment, an etching method is provided. The etching method includes a film forming step to form a film on the surface of the substrate. The substrate has an area to be etched and a mask. The mask is arranged on the area of the substrate to provide an opening for partially exposing the area. The film is formed of the same type of material as the material of the area of the substrate. The etching method further includes an area etching step, etching the area of the substrate. [Effects of the invention]
依一例示性實施形態,則可在基板內的區域之蝕刻中抑制遮罩的開口之阻塞。According to an exemplary embodiment, the blocking of the opening of the mask can be suppressed during the etching of the area in the substrate.
以下,針對各種例示性實施形態予以說明。Hereinafter, various exemplary embodiments will be described.
於一例示性實施形態中,提供一種蝕刻方法。該蝕刻方法,包含:a)膜形成步驟,於基板之表面上形成膜。基板,具備被蝕刻之區域及遮罩。遮罩,設置於基板之區域上,提供使該區域部分地露出的開口。膜,由與基板之區域的材料相同種類的材料形成。蝕刻方法,更包含b)區域蝕刻步驟,蝕刻基板之區域。在b),可藉由電漿蝕刻而蝕刻區域。In an exemplary embodiment, an etching method is provided. The etching method includes: a) a film forming step, forming a film on the surface of the substrate. The substrate has an area to be etched and a mask. The mask is arranged on the area of the substrate to provide an opening for partially exposing the area. The film is formed of the same type of material as the material of the area of the substrate. The etching method further includes b) area etching step, etching the area of the substrate. In b), the area can be etched by plasma etching.
在上述實施形態,形成於基板上的膜,在區域的蝕刻開始時保護遮罩。因此,可抑制因遮罩受到蝕刻而從遮罩釋出的物質阻塞開口而再度附著於遮罩之情形。抑或,在作為用於蝕刻之氣體,使用為了保護遮罩而於遮罩上形成沉積物之氣體的情況,可抑制過剩的沉積物阻塞開口之情形。In the above-mentioned embodiment, the film formed on the substrate protects the mask at the start of etching of the area. Therefore, it is possible to prevent the substance released from the mask due to the etching of the mask from clogging the opening and attaching to the mask again. Or, when the gas used for etching is used to protect the mask and deposits are formed on the mask, it is possible to prevent excessive deposits from blocking the opening.
在一例示性實施形態,於b)中,亦可使膜的蝕刻率,為基板之區域的蝕刻率以上或該區域的蝕刻率以下。In an exemplary embodiment, in b), the etching rate of the film may be greater than or equal to the etching rate of the area of the substrate or less than the etching rate of the area.
基板之區域,亦可由有機材料形成。基板之區域,亦可由氧化矽或氮化矽形成。基板之區域,亦可具備由氧化矽、氮化矽、及多晶矽中之兩種以上的材料分別形成之複數層。基板之區域,亦可由矽及/或鍺形成。在基板之區域係由矽及/或鍺形成的情況,膜,亦可由非晶矽形成。The area of the substrate can also be formed of organic materials. The area of the substrate may also be formed of silicon oxide or silicon nitride. The area of the substrate may also have a plurality of layers respectively formed of two or more materials among silicon oxide, silicon nitride, and polysilicon. The area of the substrate may also be formed of silicon and/or germanium. When the area of the substrate is formed of silicon and/or germanium, the film may also be formed of amorphous silicon.
一例示性實施形態中,蝕刻方法,亦可更包含c)部分蝕刻步驟,部分地蝕刻區域。膜,形成在於c)中形成的側壁面上;於c)中形成在區域的開口之深度,於b)中增大。In an exemplary embodiment, the etching method may further include c) a partial etching step to partially etch the area. The film is formed on the sidewall surface formed in c); the depth of the opening in the area formed in c) is increased in b).
一例示性實施形態中,a),亦可包含:前驅物層形成步驟:藉由將第1氣體供給至基板,而於基板上形成前驅物層;以及由前驅物層形成膜步驟,藉由將第2氣體供給至前驅物層或使前驅物層活性化,而由前驅物層形成膜。一例示性實施形態中,膜,亦可使用來自由第2氣體產生之電漿的化學物種而形成。另一例示性實施形態中,膜,亦可藉由CVD形成。CVD,可為利用電漿、熱、或光等之CVD。於各種例示性實施形態中,膜,亦可形成為使其厚度與基板內之從基板的上端算起之深度相應而減少。In an exemplary embodiment, a) may also include: a precursor layer forming step: forming a precursor layer on the substrate by supplying the first gas to the substrate; and forming a film from the precursor layer by The second gas is supplied to the precursor layer or is activated to form a film from the precursor layer. In an exemplary embodiment, the film may also be formed using chemical species derived from plasma generated from the second gas. In another exemplary embodiment, the film may also be formed by CVD. CVD can be CVD using plasma, heat, or light. In various exemplary embodiments, the film may also be formed such that its thickness is reduced corresponding to the depth in the substrate from the upper end of the substrate.
一例示性實施形態中,蝕刻方法,亦可於基板之區域,形成具有10以上之寬高比的開口。一例示性實施形態中,遮罩所提供的開口之寬度,亦可為100nm以下。In an exemplary embodiment, the etching method may also form an opening with an aspect ratio of 10 or more in the area of the substrate. In an exemplary embodiment, the width of the opening provided by the mask may also be 100 nm or less.
一例示性實施形態中,亦可交互地重複膜形成步驟與區域蝕刻步驟。In an exemplary embodiment, the film forming step and the area etching step may be repeated alternately.
另一例示性實施形態中,提供一種基板處理裝置。基板處理裝置,具備腔室、氣體供給部、及控制部。氣體供給部,構成為往腔室內供給氣體。控制部,為了於基板上形成膜,控制氣體供給部俾往腔室內供給氣體。基板,具備被蝕刻之區域、及遮罩。遮罩,設置於基板之區域上,提供開口。膜,由與基板之區域的材料相同種類的材料形成。控制部,為了蝕刻基板之區域,控制氣體供給部俾往腔室內供給氣體。In another exemplary embodiment, a substrate processing apparatus is provided. The substrate processing apparatus includes a chamber, a gas supply unit, and a control unit. The gas supply unit is configured to supply gas into the chamber. The control unit controls the gas supply unit to supply gas into the chamber in order to form a film on the substrate. The substrate has an area to be etched and a mask. The mask is set on the area of the substrate to provide an opening. The film is formed of the same type of material as the material of the area of the substrate. The control unit controls the gas supply unit to supply gas into the chamber in order to etch the area of the substrate.
再另一例示性實施形態中,提供一種基板處理系統。基板處理系統,具備成膜裝置及基板處理裝置。成膜裝置,構成為於基板上形成膜。基板,具備被蝕刻之區域、及遮罩。遮罩,設置於基板之區域上,提供開口。膜,由與基板之區域的材料相同種類的材料形成。基板處理裝置,構成為蝕刻基板之區域。In still another exemplary embodiment, a substrate processing system is provided. The substrate processing system includes a film forming device and a substrate processing device. The film forming apparatus is configured to form a film on a substrate. The substrate has an area to be etched and a mask. The mask is set on the area of the substrate to provide an opening. The film is formed of the same type of material as the material of the area of the substrate. The substrate processing device is configured to etch the area of the substrate.
以下,參考圖式,針對各種例示性實施形態詳細地予以說明。另,對於各圖式中相同或相當的部分,給予相同符號。Hereinafter, various exemplary embodiments will be described in detail with reference to the drawings. In addition, the same or equivalent parts in the drawings are given the same symbols.
圖1係一例示性實施形態之蝕刻方法的流程圖。圖1所示之蝕刻方法(下稱「方法MT」),係為了蝕刻基板內之區域而實行。圖2係一例之基板的部分放大剖面圖。圖2所示之基板W,具備區域RE及遮罩MK。基板W,亦可進一步具備基底區域UR。FIG. 1 is a flowchart of an etching method in an exemplary embodiment. The etching method shown in Figure 1 (hereinafter referred to as "method MT") is implemented to etch areas within the substrate. Fig. 2 is a partial enlarged cross-sectional view of an example of a substrate. The substrate W shown in FIG. 2 has an area RE and a mask MK. The substrate W may further include a base region UR.
區域RE,係方法MT中蝕刻之區域。於圖2所示之基板W中,區域RE,設置於基底區域UR上。遮罩MK,設置於區域RE上。使遮罩MK圖案化。亦即,遮罩MK,提供使區域RE部分地露出之一個以上的開口OP。遮罩MK所提供的開口OP之寬度,例如可為100nm以下。區域RE,可由任意材料形成。遮罩MK,只要於後述步驟ST2中對遮罩MK選擇性地蝕刻區域RE,則可由任意材料形成。The area RE is the area etched in the method MT. In the substrate W shown in FIG. 2, the area RE is disposed on the base area UR. The mask MK is set on the area RE. Pattern the mask MK. That is, the mask MK provides more than one opening OP through which the region RE is partially exposed. The width of the opening OP provided by the mask MK can be, for example, 100 nm or less. The area RE can be formed of any material. The mask MK can be formed of any material as long as the region RE is selectively etched for the mask MK in step ST2 described later.
於基板W的第1例中,區域RE,由有機材料形成。於基板W的第2例中,區域RE,由氧化矽形成。於基板W的第3例中,區域RE,由氮化矽形成。於基板W的第4例中,區域RE,由矽(例如多晶矽)及/或鍺形成。於基板W的第5例中,區域RE,包含交互疊層的一層以上之氧化矽膜與一層以上的氮化矽膜。於基板W的第5例中,區域RE,亦可包含單一氧化矽膜與單一氮化矽膜。於基板W的第5例中,單一氮化矽膜,可設置於單一氧化矽膜與遮罩MK之間。於基板W的第6例中,區域RE,包含交互疊層的一層以上之氧化矽膜與一層以上之多晶矽膜。於基板W的第7例中,區域RE,由包含一層以上之氧化矽膜、一層以上之氮化矽膜、及一層以上之多晶矽膜的疊層體形成。於基板W的第8例中,區域RE,由低介電常數材料形成。於基板W的第8例中,區域RE,包含矽、碳、氧、及氫。亦即,於基板W的第8例中,膜PF,可為SiCOH膜。In the first example of the substrate W, the region RE is formed of an organic material. In the second example of the substrate W, the region RE is formed of silicon oxide. In the third example of the substrate W, the region RE is formed of silicon nitride. In the fourth example of the substrate W, the region RE is formed of silicon (for example, polysilicon) and/or germanium. In the fifth example of the substrate W, the region RE includes one or more silicon oxide films and one or more silicon nitride films that are alternately laminated. In the fifth example of the substrate W, the region RE may also include a single silicon oxide film and a single silicon nitride film. In the fifth example of the substrate W, a single silicon nitride film may be provided between the single silicon oxide film and the mask MK. In the sixth example of the substrate W, the region RE includes one or more silicon oxide films and one or more polysilicon films that are alternately stacked. In the seventh example of the substrate W, the region RE is formed of a laminate including one or more silicon oxide films, one or more silicon nitride films, and one or more polysilicon films. In the eighth example of the substrate W, the region RE is formed of a low dielectric constant material. In the eighth example of the substrate W, the region RE includes silicon, carbon, oxygen, and hydrogen. That is, in the eighth example of the substrate W, the film PF may be a SiCOH film.
於基板W的第1例中,遮罩MK,由SiON、含金屬材料、或含矽材料形成。由含矽材料形成之遮罩MK,例如可由含矽反射防止膜形成。於基板W的第2例、第3例、第5例、第6例、及第7例中,遮罩MK,分別由矽、含碳材料、或含金屬材料形成。於基板W的第4例中,遮罩MK,由氧化矽形成。於基板W的第8例中,遮罩MK,由含鎢材料、含鈦材料等含金屬材料形成。於基板W的第8例中,遮罩MK,亦可由光阻劑等有機材料、氮化矽、或多晶矽形成。遮罩MK所含的矽,例如為多晶矽或非晶矽。遮罩MK所含的含碳材料,例如為非晶碳或旋塗碳材料。遮罩MK所含的含金屬材料,例如為鎢、碳化鎢、或氮化鈦。In the first example of the substrate W, the mask MK is formed of SiON, a metal-containing material, or a silicon-containing material. The mask MK formed of a silicon-containing material may be formed of, for example, a silicon-containing anti-reflection film. In the second example, the third example, the fifth example, the sixth example, and the seventh example of the substrate W, the mask MK is formed of silicon, a carbon-containing material, or a metal-containing material, respectively. In the fourth example of the substrate W, the mask MK is formed of silicon oxide. In the eighth example of the substrate W, the mask MK is formed of a metal-containing material such as a tungsten-containing material and a titanium-containing material. In the eighth example of the substrate W, the mask MK may also be formed of organic materials such as photoresist, silicon nitride, or polysilicon. The silicon contained in the mask MK is, for example, polycrystalline silicon or amorphous silicon. The carbon-containing material contained in the mask MK is, for example, amorphous carbon or spin-coated carbon material. The metal-containing material contained in the mask MK is, for example, tungsten, tungsten carbide, or titanium nitride.
一實施形態中,方法MT,係利用基板處理裝置實行。圖3係概略顯示一例示性實施形態之基板處理裝置的圖。圖3所示之基板處理裝置,為電容耦合型之電漿處理裝置1。In one embodiment, the method MT is implemented using a substrate processing apparatus. Fig. 3 is a diagram schematically showing a substrate processing apparatus according to an exemplary embodiment. The substrate processing apparatus shown in FIG. 3 is a capacitive coupling type plasma processing apparatus 1.
電漿處理裝置1,具備腔室10。腔室10,於其中提供內部空間10s。腔室10之中心軸線,為沿著鉛直方向延伸之軸線AX。一實施形態中,腔室10,包含腔室本體12。腔室本體12,具有略圓筒形狀。於腔室本體12之中,提供內部空間10s。腔室本體12,例如由鋁構成。腔室本體12電性接地。於腔室本體12之內壁面上,設置具有耐腐蝕性的膜。具有耐腐蝕性的膜,可為由氧化鋁、氧化釔等陶瓷形成的膜。The plasma processing apparatus 1 includes a
於腔室本體12之側壁,形成通路12p。基板W,在內部空間10s與腔室10的外部之間搬運時,通過通路12p。通路12p,成為可藉由閘閥12g開啟關閉。閘閥12g,沿著腔室本體12之側壁而設置。On the side wall of the
電漿處理裝置1,進一步具備基板支持器16。基板支持器16,構成為在腔室10內支持基板W。基板W,可具有略圓盤形狀。基板支持器16,藉由支持體15支持。支持體15,從腔室本體12之底部往上方延伸。支持體15,具有略圓筒形狀。支持體15,由石英等絕緣材料形成。The plasma processing apparatus 1 further includes a
基板支持器16,包含下部電極18及靜電吸盤20。基板支持器16,亦可更包含電極板19。電極板19,由鋁等導電性材料形成。電極板19,具有略圓盤形狀,其中心軸線為軸線AX。下部電極18,設置於電極板19上。下部電極18,由鋁等導電性材料形成。下部電極18,具有略圓盤形狀,其中心軸線為軸線AX。下部電極18,與電極板19電性連接。The
於下部電極18內,形成流路18f。流路18f,為熱交換媒體(例如冷媒)用的流路。於流路18f,連接熱交換媒體之供給裝置(例如急冷器單元)。該供給裝置,設置於腔室10之外部。從供給裝置,經由配管23a將熱交換媒體往流路18f供給。供給至流路18f的熱交換媒體,經由配管23b而返回供給裝置。熱交換媒體之供給裝置,構成電漿處理裝置1之溫度調整機構。In the
圖4係一例示性實施形態之基板處理裝置中的靜電吸盤之放大剖面圖。以下,參考圖3及圖4。靜電吸盤20,設置於下部電極18上。於靜電吸盤20的頂面上,載置基板W。靜電吸盤20,具備本體20m及電極20e。本體20m,由介電材料形成。靜電吸盤20及本體20m,各自具有略圓盤形狀,其中心軸線為軸線AX。電極20e,為膜狀之電極,設置於本體20m內。電極20e,經由開關20s而與直流電源20p連接。若對電極20e施加來自直流電源20p的電壓,則在靜電吸盤20與基板W之間產生靜電引力。藉由產生的靜電引力,將基板W吸引至靜電吸盤20,藉由靜電吸盤20保持。4 is an enlarged cross-sectional view of an electrostatic chuck in a substrate processing apparatus according to an exemplary embodiment. Hereinafter, refer to FIG. 3 and FIG. 4. The
基板支持器16,亦可具備一個以上之加熱器HT。一個以上之加熱器HT,可各自為電阻加熱元件。電漿處理裝置1,可進一步具備加熱器控制器HC。一個以上之加熱器HT,各自因應從加熱器控制器HC單獨給予的電力而發熱。此一結果,調整基板支持器16上之基板W的溫度。一個以上之加熱器HT,構成電漿處理裝置1之溫度調整機構。一實施形態中,基板支持器16,具備複數個加熱器HT。複數個加熱器HT,亦可設置於靜電吸盤20之中。The
於基板支持器16之周緣部上,以包圍基板W之邊緣的方式,配置邊緣環ER。基板W,配置於靜電吸盤20上且為由邊緣環ER包圍之區域內。邊緣環ER,係為了改善電漿處理之對於基板W的面內均一性而利用。邊緣環ER,可由矽、碳化矽、或石英形成。On the peripheral edge of the
電漿處理裝置1,可進一步具備氣體供給管線25。氣體供給管線25,將來自氣體供給機構之傳熱氣體(例如He氣體),往靜電吸盤20的頂面與基板W的背面(底面)之間的間隙供給。The plasma processing device 1 may further include a
電漿處理裝置1,可進一步具備筒狀部28及絕緣部29。筒狀部28,由腔室本體12之底部往上方延伸。筒狀部28,沿著支持體15之外周延伸。筒狀部28,由導電性材料形成,具有略圓筒形狀。筒狀部28電性接地。絕緣部29,設置於筒狀部28上。絕緣部29,由具有絕緣性的材料形成。絕緣部29,例如由石英等陶瓷形成。絕緣部29,具有略圓筒形狀。絕緣部29,沿著電極板19之外周、下部電極18之外周、及靜電吸盤20之外周而延伸。The plasma processing device 1 may further include a
電漿處理裝置1,進一步具備上部電極30。上部電極30,設置於基板支持器16之上方。上部電極30,經由構件32,支持於腔室本體12之上部。構件32,由具有絕緣性的材料形成。上部電極30與構件32,將腔室本體12之上部開口關閉。The plasma processing apparatus 1 further includes an
上部電極30,可包含頂板34及支持體36。頂板34的底面,為內部空間10s之側的底面,界定內部空間10s。頂板34,可由焦耳熱少之低電阻的導電體或半導體形成。一實施形態中,頂板34,由矽形成。於頂板34,形成複數個氣體噴吐孔34a。複數個氣體噴吐孔34a,將頂板34於其板厚方向貫通。The
支持體36,以可任意裝卸的方式支持頂板34。支持體36,由鋁等導電性材料形成。於支持體36之內部,設置氣體擴散室36a。於支持體36,形成複數個氣體孔36b。複數個氣體孔36b,從氣體擴散室36a往下方延伸。複數個氣體孔36b,各自與複數個氣體噴吐孔34a連通。於支持體36,形成氣體導入口36c。氣體導入口36c,連接至氣體擴散室36a。於氣體導入口36c,連接氣體供給管38。The
於氣體供給管38,經由閥群41、流量控制器群42、及閥群43而連接氣體源群40。氣體源群40、閥群41、流量控制器群42、及閥群43,構成氣體供給部GS。氣體源群40,包含複數個氣體源。氣體源群40的複數個氣體源,包含在方法MT利用之複數種氣體的氣體源。在方法MT利用的一種以上之氣體係由液體形成的情況,複數個氣體源,各自包含具有液體源及氣化器之一個以上的氣體源。閥群41及閥群43,各自包含複數個開閉閥。流量控制器群42,包含複數個流量控制器。流量控制器群42之複數個流量控制器,各自為質量流量控制器或壓力控制式之流量控制器。氣體源群40的複數個氣體源,各自經由閥群41之對應的開閉閥、流量控制器群42之對應的流量控制器、及閥群43之對應的開閉閥,而連接至氣體供給管38。The
電漿處理裝置1,亦可進一步具備遮擋構件48。遮擋構件48,設置於筒狀部28與腔室本體12的側壁之間。遮擋構件48,可為板狀的構件。遮擋構件48,例如,藉由在由鋁形成的構件之表面上形成具有耐腐蝕性的膜而構成。具有耐腐蝕性的膜,可為由氧化釔等陶瓷形成之膜。於遮擋構件48,形成複數個貫通孔。於遮擋構件48之下方,且為腔室本體12之底部,設置排氣口12e。於排氣口12e,經由排氣管52而連接排氣裝置50。排氣裝置50,具備壓力調整閥及渦輪分子泵等真空泵。The plasma processing device 1 may further include a shielding
電漿處理裝置1,進一步具備高頻電源61。高頻電源61,為產生電漿產生用之高頻電力HF的電源。高頻電力HF,具有第1頻率。第1頻率,例如為27~100MHz之範圍內的頻率。為了將高頻電力HF供給至下部電極18,使高頻電源61,經由匹配器61m及電極板19而與下部電極18連接。匹配器61m,具備匹配電路。匹配器61m之匹配電路,具有可變阻抗。調整匹配器61m之匹配電路的阻抗,俾減少來自高頻電源61之負載的反射。另,高頻電源61,亦可不與下部電極18電性連接,可經由匹配器61m而與上部電極30連接。高頻電源61,構成一例之電漿產生部。The plasma processing device 1 further includes a high-
電漿處理裝置1,進一步具備偏壓電源62。偏壓電源62,產生用於將離子引入基板W之偏壓電力BP。偏壓電源62,經由電極板19而與下部電極18連接。The plasma processing apparatus 1 further includes a
一實施形態中,偏壓電源62,亦可為產生高頻電力LF作為偏壓電力BP的高頻電源。高頻電力LF,具有適合將電漿中的離子引入基板W之第2頻率。第2頻率,可為較第1頻率更低之頻率。第2頻率,例如為400kHz~13.56MHz之範圍內的頻率。此實施形態中,偏壓電源62,經由匹配器62m及電極板19而與下部電極18連接。匹配器62m,具備匹配電路。匹配器62m之匹配電路,具有可變阻抗。調整匹配器62m之匹配電路的阻抗,俾減少來自偏壓電源62之負載的反射。In one embodiment, the
另,亦可僅使用高頻電源61及偏壓電源62中之一個電源產生電漿。此一情況中,一個電源,構成一例之電漿產生部。此一情況中,從一個電源供給的高頻電力之頻率,可為較13.56MHz更大之頻率,例如為40MHz。此一情況中,電漿處理裝置,亦可不具備高頻電源61及偏壓電源62中之另一電源。In addition, only one of the high-
另一實施形態中,偏壓電源62,亦可為不連續地或周期性地對下部電極18施加負極性的直流電壓之脈波以作為偏壓電力BP的直流電源裝置。例如,偏壓電源62,亦可藉由1kHz~1MHz之範圍內的頻率,以規定之周期,周期性地對下部電極18施加負極性的直流電壓之脈波。In another embodiment, the
一實施形態中,電漿處理裝置1,亦可進一步具備直流電源裝置64。直流電源裝置64,連接至上部電極30。直流電源裝置64,構成為對上部電極30施加直流電壓,例如負極性的直流電壓。直流電源裝置64,亦可不連續地或周期性地對上部電極30施加直流電壓之脈波。In one embodiment, the plasma processing device 1 may further include a DC
於電漿處理裝置1中產生電漿的情況,將氣體,從氣體供給部GS往內部空間10s供給。此外,藉由供給高頻電力,而在上部電極30與下部電極18之間產生高頻電場。藉由產生的高頻電場,激發氣體。此一結果,於腔室10內產生電漿。When plasma is generated in the plasma processing apparatus 1, gas is supplied from the gas supply part GS to the
電漿處理裝置1,進一步具備控制部80。控制部80,係具備處理器、記憶裝置、輸入裝置、顯示裝置等之電腦,控制電漿處理裝置1的各部。具體而言,控制部80,實行記憶在記憶裝置的控制程式,依據記憶在該記憶裝置的配方資料而控制電漿處理裝置1的各部。藉由控制部80所進行之控制,於電漿處理裝置1中實行由配方資料指定的製程。可藉由控制部80所進行之電漿處理裝置1的各部之控制,於電漿處理裝置1中實行方法MT。The plasma processing apparatus 1 further includes a
再度參考圖1,針對方法MT詳細地說明。以下說明中,以利用電漿處理裝置1處理圖2所示之基板W的情況為例,說明方法MT。另,方法MT,亦可利用其他基板處理裝置。方法MT,亦可處理其他基板。Referring again to FIG. 1, the method MT will be described in detail. In the following description, a case where the substrate W shown in FIG. 2 is processed by the plasma processing apparatus 1 is taken as an example to describe the method MT. In addition, the method MT can also use other substrate processing equipment. Method MT can also process other substrates.
方法MT,在將基板W載置於基板支持器16上之狀態下實行。方法MT,可維持腔室10之內部空間10s的減壓之環境,且不將基板W從內部空間10s取出地實行。一實施形態中,方法MT,亦可在步驟STa開始。在步驟STa,部分地蝕刻區域RE。區域RE,可使用電漿予以蝕刻。The method MT is performed in a state where the substrate W is placed on the
在步驟STa,於腔室10內由處理氣體產生電漿Pa。處理上述基板W的第1例之情況,在步驟STa使用之處理氣體,可包含含氧氣體。含氧氣體,可包含O2
氣體、COS氣體、SO2
氣體、CO2
氣體、及CO氣體中的一種以上之氣體。處理上述基板W的第2例及第8例之情況,在步驟STa使用之處理氣體,可包含氟碳化物氣體。處理上述基板W的第3例之情況,在步驟STa使用之處理氣體,可包含氫氟碳化物氣體。處理上述基板W的第4例之情況,在步驟STa使用之處理氣體,可包含含鹵素氣體。含鹵素氣體,例如可包含CF4
氣體、Cl2
氣體、HBr氣體、HI氣體中的一種以上之氣體。處理上述基板W的第5例、第6例、及第7例之情況,在步驟STa使用之處理氣體,各自可包含上述氟碳化物氣體及氫氟碳化物氣體中的一種以上之氣體。另,處理任一例的基板W之情況中,在步驟STa使用之處理氣體,皆可更包含惰性氣體(例如稀有氣體)。In step STa, plasma Pa is generated from the processing gas in the
圖5(a)係用於說明圖1所示之蝕刻方法的步驟STa之例子的圖,圖5(b)係步驟STa之實行後的狀態之一例的基板之部分放大剖面圖。在步驟STa,如圖5(a)所示,將來自電漿Pa的化學物種對基板W供給,藉由該化學物種部分地蝕刻區域RE。在步驟STa,將區域RE,蝕刻至區域RE的頂面與區域RE的底面之間的位置。另,區域RE的底面,係與基底區域UR接觸之區域RE的面。區域RE的頂面,係從遮罩MK的開口露出之區域RE的表面。若實行步驟STa,則如圖5(b)所示,將開口OP,形成為從遮罩MK延伸至區域RE之中。FIG. 5(a) is a diagram for explaining an example of step STa of the etching method shown in FIG. 1, and FIG. 5(b) is a partially enlarged cross-sectional view of a substrate in an example of a state after step STa is performed. In step STa, as shown in FIG. 5(a), a chemical species from the plasma Pa is supplied to the substrate W, and the region RE is partially etched by the chemical species. In step STa, the region RE is etched to a position between the top surface of the region RE and the bottom surface of the region RE. In addition, the bottom surface of the region RE is the surface of the region RE that is in contact with the base region UR. The top surface of the area RE is the surface of the area RE exposed from the opening of the mask MK. If step STa is performed, as shown in FIG. 5(b), the opening OP is formed to extend from the mask MK to the area RE.
於步驟STa中,控制部80,控制排氣裝置50俾將腔室10內之氣體的壓力設定為指定的壓力。於步驟STa中,控制部80,控制氣體供給部GS俾將處理氣體往腔室10內供給。於步驟STa中,控制部80,為了由處理氣體產生電漿而控制電漿產生部。在一實施形態之步驟STa,控制部80,控制高頻電源61及偏壓電源62,俾供給高頻電力HF及偏壓電力BP。於步驟STa中,亦可為了產生電漿,僅供給高頻電力HF及高頻電力LF中之一方。In step STa, the
另,方法MT,亦可不包含步驟STa。此一情況,在應用方法MT的基板之區域RE,預先設置開口OP。抑或,在方法MT未包含步驟STa的情況,對圖2所示之基板W應用步驟ST1及步驟ST2。In addition, the method MT may not include step STa. In this case, the opening OP is preset in the area RE of the substrate to which the method MT is applied. Or, when the method MT does not include the step STa, the steps ST1 and ST2 are applied to the substrate W shown in FIG. 2.
在步驟ST1,將膜PF形成於基板W之表面上(參考圖7(b))。在步驟ST2,蝕刻區域RE。膜PF,由與區域RE的材料相同種類的材料形成。膜PF,在步驟ST2中之區域RE的蝕刻之際同時蝕刻。一實施形態中,步驟ST2中之膜PF的蝕刻率,可為區域RE的蝕刻率以上或該區域RE的蝕刻率以下。抑或,膜PF的蝕刻率除以區域RE的蝕刻率之值,亦可為0.7以上、1.2以下。膜PF的蝕刻率除以區域RE的蝕刻率之值,亦可為0.8以上、1.1以下。In step ST1, the film PF is formed on the surface of the substrate W (refer to FIG. 7(b)). In step ST2, the region RE is etched. The film PF is formed of the same kind of material as the material of the region RE. The film PF is simultaneously etched during the etching of the region RE in step ST2. In one embodiment, the etching rate of the film PF in step ST2 may be greater than or equal to the etching rate of the region RE or less than the etching rate of the region RE. Alternatively, the value obtained by dividing the etching rate of the film PF by the etching rate of the region RE may be 0.7 or more and 1.2 or less. The value obtained by dividing the etching rate of the film PF by the etching rate of the region RE may be 0.8 or more and 1.1 or less.
處理基板W的第1例之情況,膜PF,由含碳材料形成。處理基板W的第1例之情況,膜PF,例如可由氟碳化物、氫氟碳化物、碳化氫、碳、或摻雜硼的碳形成。在將區域RE由非晶碳或光阻劑形成的情況,膜PF,可由摻雜硼的碳形成。處理基板W的第2例~第7例之情況,膜PF,各自由含矽材料形成。處理基板W的第2例或第5例之情況,膜PF,例如各自由氧化矽(例如TEOS等)、SiOC、SiON、或氮化矽形成。處理基板W的第3例之情況,膜PF,例如由氮化矽、SiON、或氧化矽形成。處理基板W的第4例之情況,膜PF,例如由多晶矽或非晶矽形成。處理基板W的第6例之情況,膜PF,例如由氧化矽(例如TEOS等)、SiOC、SiON、氮化矽、多晶矽、或非晶矽形成。處理基板W的第6例及第7例之情況,膜PF,例如由氧化矽(例如TEOS等)、SiOC、SiON、氮化矽、多晶矽、或非晶矽形成。在將區域RE由使用TEOS形成之氧化矽形成的情況,抑或,如同基板W的第8例地將基板W由低介電常數材料(例如多孔質SiOCH)形成的情況,膜PF,可由氧化矽形成。In the case of the first example of processing the substrate W, the film PF is formed of a carbon-containing material. In the case of the first example of processing the substrate W, the film PF may be formed of, for example, fluorocarbon, hydrofluorocarbon, hydrocarbon, carbon, or carbon doped with boron. When the region RE is formed of amorphous carbon or photoresist, the film PF may be formed of carbon doped with boron. In the case of the second to seventh examples of processing the substrate W, the film PF is each formed of a silicon-containing material. In the case of the second or fifth example of processing the substrate W, the film PF is each formed of, for example, silicon oxide (for example, TEOS, etc.), SiOC, SiON, or silicon nitride. In the case of the third example of processing the substrate W, the film PF is formed of, for example, silicon nitride, SiON, or silicon oxide. In the fourth example of processing the substrate W, the film PF is formed of, for example, polycrystalline silicon or amorphous silicon. In the case of the sixth example of processing the substrate W, the film PF is formed of, for example, silicon oxide (for example, TEOS, etc.), SiOC, SiON, silicon nitride, polysilicon, or amorphous silicon. In the case of the sixth and seventh examples of processing the substrate W, the film PF is formed of, for example, silicon oxide (for example, TEOS, etc.), SiOC, SiON, silicon nitride, polysilicon, or amorphous silicon. In the case where the region RE is formed of silicon oxide formed using TEOS, or, as in the eighth example of the substrate W, the substrate W is formed of a low-dielectric constant material (for example, porous SiOCH), the film PF may be formed of silicon oxide form.
處理基板W的第1例~第8例之情況,在步驟ST1,亦可藉由CVD法各自形成膜PF。CVD法,可為電漿(Plasma Enhanced)CVD法,亦可為利用熱或光等之CVD法。在由CVD法進行的步驟ST1,往腔室10內供給成膜氣體。在由CVD法進行的步驟ST1,亦可於腔室10內由成膜氣體產生電漿。抑或,在步驟ST13,亦可藉由熱或光等將形成膜PF之成膜氣體中的前驅物活性化。In the case of processing the first example to the eighth example of the substrate W, in step ST1, the film PF may be formed separately by the CVD method. The CVD method can be a plasma (Plasma Enhanced) CVD method, or a CVD method using heat or light. In step ST1 performed by the CVD method, a film forming gas is supplied into the
在由CVD法進行的步驟ST1,控制部80,控制氣體供給部GS,俾往腔室10內供給成膜氣體。此外,控制部80,控制排氣裝置50,俾將腔室10內的壓力設定為指定的壓力。在由CVD法進行的步驟ST1,控制部80,亦可為了由成膜氣體產生電漿而控制電漿產生部。具體而言,控制部80,可控制高頻電源61及/或偏壓電源62,俾供給高頻電力HF及/或高頻電力LF。抑或,在由CVD法進行的步驟ST1,亦可往腔室10內供給成膜氣體,並為了活性化而控制加熱器HT俾將基板W加熱。抑或,於步驟ST13中,控制部80,亦可為了活性化而控制光源俾對基板W照射光線。In step ST1 performed by the CVD method, the
處理基板W的第1例之情況,於由CVD法進行的步驟ST1中使用之成膜氣體,例如包含氟碳化物氣體、氫氟碳化物氣體、CO氣體、或碳化氫氣體(例如CH4 氣體、C3 H6 氣體、或C2 H4 氣體)。在步驟ST1,成膜氣體,亦可更包含Ar氣體等稀有氣體及/或N2 氣體。In the first example of processing the substrate W, the film forming gas used in step ST1 performed by the CVD method includes, for example, fluorocarbon gas, hydrofluorocarbon gas, CO gas, or hydrocarbon gas (such as CH 4 gas). , C 3 H 6 gas, or C 2 H 4 gas). In step ST1, the film forming gas may further include a rare gas such as Ar gas and/or N 2 gas.
處理基板W的第2例及第3例之情況,於由CVD法進行的步驟ST1中使用之成膜氣體,包含含矽氣體。成膜氣體,更包含含氧氣體及/或含氮氣體。成膜氣體,例如可包含SiCl4 氣體及O2 氣體。抑或,成膜氣體,例如可包含Si2 Cl6 氣體及NH3 氣體。In the case of the second example and the third example of processing the substrate W, the film forming gas used in step ST1 by the CVD method includes a silicon-containing gas. The film-forming gas further includes oxygen-containing gas and/or nitrogen-containing gas. The film forming gas may include SiCl 4 gas and O 2 gas, for example. Alternatively, the film forming gas may include Si 2 Cl 6 gas and NH 3 gas, for example.
處理基板W的第4例之情況,於由CVD法進行的步驟ST1中使用之成膜氣體,包含甲矽烷(SiH4 )、乙矽烷(Si2 H6 )、氯化矽、氯矽烷、或氟化矽。氯化矽,例如為四氯化矽(SiCl4 )、六氯二矽烷(Si2 Cl6 )等。氯矽烷,例如為三氯矽烷(HSiCl3 )、二氯矽烷(H2 SiCl2 )、三甲基氯矽烷((CH3 )3 SiCl)等。氟化矽,例如為四氟化矽(SiF4 )等。成膜氣體,亦可包含氫(例如H2 )及/或稀有氣體(例如Ar、He)。In the fourth example of processing the substrate W, the film forming gas used in the step ST1 performed by the CVD method includes silane (SiH 4 ), ethyl silane (Si 2 H 6 ), silicon chloride, chlorosilane, or Silicon fluoride. Silicon chloride, for example, silicon tetrachloride (SiCl 4 ), hexachlorodisilane (Si 2 Cl 6 ), etc. The chlorosilanes are, for example, trichlorosilane (HSiCl 3 ), dichlorosilane (H 2 SiCl 2 ), trimethylchlorosilane ((CH 3 ) 3 SiCl), etc. Silicon fluoride, for example, silicon tetrafluoride (SiF 4 ), etc. The film-forming gas may also include hydrogen (for example, H 2 ) and/or rare gas (for example, Ar, He).
處理基板W的第5例之情況,於由CVD法進行的步驟ST1中使用之成膜氣體,為與對於基板W的第2例或第3例在步驟ST1中使用之成膜氣體相同的成膜氣體。處理基板W的第6例及第8例之情況,於由CVD法進行的步驟ST1中使用之成膜氣體,為與對於基板W的第2例或第4例在步驟ST1中使用之成膜氣體相同的成膜氣體。處理基板W的第7例之情況,於由CVD法進行的步驟ST1中使用之成膜氣體,為與對於基板W的第2例、第3例、或第4例在步驟ST1中使用之成膜氣體相同的成膜氣體。In the fifth example of processing the substrate W, the film forming gas used in step ST1 by the CVD method is the same as the film forming gas used in step ST1 for the second or third example of the substrate W Membrane gas. In the case of processing the substrate W in the sixth example and the eighth example, the film forming gas used in step ST1 by the CVD method is the same as the film forming gas used in the second or fourth example of the substrate W in step ST1 The same film-forming gas as the gas. In the case of the seventh example of processing the substrate W, the film-forming gas used in the step ST1 performed by the CVD method is the same as that used in the second, third, or fourth example of the substrate W in the step ST1. The film forming gas is the same as the film gas.
處理基板W的第4例之情況,在步驟ST1,亦可藉由物理氣相沉積(PVD)法形成膜PF。此一情況,往腔室10內供給惰性氣體。惰性氣體,例如為稀有氣體。此外,於腔室10內由惰性氣體產生電漿。此外,對上部電極30施加負極性的直流電壓。此一結果,來自電漿的陽離子碰撞頂板34,從頂板34釋出矽。從頂板34釋出的矽,於基板W之表面上沉積而形成區域RE。In the fourth example of processing the substrate W, in step ST1, the film PF may be formed by a physical vapor deposition (PVD) method. In this case, an inert gas is supplied into the
在由PVD法進行的步驟ST1,控制部80,控制氣體供給部GS,俾往腔室10內供給惰性氣體。此外,控制部80,控制排氣裝置50,俾將腔室10內的壓力設定為指定的壓力。在由PVD法進行的步驟ST1,控制部80,為了由惰性氣體產生電漿而控制電漿產生部。具體而言,控制部80,可控制高頻電源61及/或偏壓電源62,俾供給高頻電力HF及/或高頻電力LF。在由PVD法進行的步驟ST1,控制部80,控制直流電源裝置64,俾對上部電極30施加負極性的直流電壓。In step ST1 performed by the PVD method, the
處理基板W的第1例~第8例之情況,在步驟ST1,亦可藉由圖6所示之成膜法各自形成膜PF。圖6係可於一例示性實施形態之蝕刻方法中使用的成膜方法之流程圖。以下,參考圖6暨圖7(a)及圖7(b)。圖7(a)係前驅物層形成後的狀態之一例的基板之部分放大剖面圖。圖7(b)係膜PF形成後的狀態之一例的基板之部分放大剖面圖。In the case of processing the first example to the eighth example of the substrate W, in step ST1, the film PF may be formed separately by the film forming method shown in FIG. 6. FIG. 6 is a flowchart of a film forming method that can be used in the etching method of an exemplary embodiment. Hereinafter, refer to Fig. 6 and Fig. 7(a) and Fig. 7(b). Fig. 7(a) is a partial enlarged cross-sectional view of the substrate in an example of the state after the precursor layer is formed. Fig. 7(b) is a partially enlarged cross-sectional view of a substrate of an example of the state after the film PF is formed.
如圖6所示,一實施形態中,步驟ST1,包含步驟ST11及步驟ST13。步驟ST1,亦可更包含步驟ST12及步驟ST14。步驟ST12,於步驟ST11與步驟ST13之間實行。步驟ST14,於步驟ST13與步驟ST11之間實行。As shown in FIG. 6, in one embodiment, step ST1 includes step ST11 and step ST13. Step ST1 may further include step ST12 and step ST14. Step ST12 is executed between step ST11 and step ST13. Step ST14 is executed between step ST13 and step ST11.
在步驟ST11,如圖7(a)所示,將前驅物層PC形成於基板W之表面上。在步驟ST11,為了形成前驅物層PC,使用第1氣體。第1氣體,包含構成前驅物層PC的物質。在步驟ST11,可不由第1氣體產生電漿地形成前驅物層PC。抑或,在步驟ST11,前驅物層PC,亦可使用來自由第1氣體產生之電漿的化學物種而形成。In step ST11, as shown in FIG. 7(a), a precursor layer PC is formed on the surface of the substrate W. In step ST11, in order to form the precursor layer PC, the first gas is used. The first gas includes the substance constituting the precursor layer PC. In step ST11, the precursor layer PC can be formed without generating plasma from the first gas. Alternatively, in step ST11, the precursor layer PC can also be formed using chemical species derived from the plasma generated by the first gas.
處理基板W的第1例之情況,第1氣體,例如包含羧酸、羧酸鹵化物、羧酸酐、或異氰酸酯。處理基板W的第2例、第3例、第5例、第6例、第7例、及第8例之情況,第1氣體,例如各自包含胺基矽烷。第1氣體,亦可包含Si2 Cl6 ,而非胺基矽烷。處理基板W的第4例之情況,第1氣體,包含甲矽烷(SiH4 )、乙矽烷(Si2 H6 )、氯化矽、氯矽烷、或氟化矽。氯化矽,例如為四氯化矽(SiCl4 )、六氯二矽烷(Si2 Cl6 )等。氯矽烷,例如為三氯矽烷(HSiCl3 )、二氯矽烷(H2 SiCl2 )、三甲基氯矽烷((CH3 )3 SiCl)等。氟化矽,例如為四氟化矽(SiF4 )等。In the case of the first example of processing the substrate W, the first gas includes, for example, carboxylic acid, carboxylic acid halide, carboxylic anhydride, or isocyanate. In the case of processing the second example, the third example, the fifth example, the sixth example, the seventh example, and the eighth example of the substrate W, the first gas includes, for example, aminosilane. The first gas may also contain Si 2 Cl 6 instead of aminosilane. In the fourth example of processing the substrate W, the first gas includes silane (SiH 4 ), ethyl silane (Si 2 H 6 ), silicon chloride, chlorosilane, or silicon fluoride. Silicon chloride, for example, silicon tetrachloride (SiCl 4 ), hexachlorodisilane (Si 2 Cl 6 ), etc. The chlorosilanes are, for example, trichlorosilane (HSiCl 3 ), dichlorosilane (H 2 SiCl 2 ), trimethylchlorosilane ((CH 3 ) 3 SiCl), etc. Silicon fluoride, for example, silicon tetrafluoride (SiF 4 ), etc.
於步驟ST11中,控制部80,控制氣體供給部GS俾將第1氣體往腔室10內供給。於步驟ST11中,控制部80,控制排氣裝置50俾將腔室10內之氣體的壓力設定為指定的壓力。於步驟ST11中產生電漿之情況,控制部80,控制電漿產生部俾於腔室10內由第1氣體產生電漿。在一實施形態,為了由第1氣體產生電漿,控制部80,控制高頻電源61及/或偏壓電源62俾供給高頻電力HF及/或高頻電力LF。In step ST11, the
在步驟ST12,實行內部空間10s之吹掃。在步驟ST12,控制部80,控制排氣裝置50俾實行內部空間10s之排氣。在步驟ST12,控制部80,亦可控制氣體供給部GS俾往腔室10內供給惰性氣體。藉由步驟ST12的實行,可將腔室10內之第1氣體置換為惰性氣體。藉由步驟ST12的實行,亦可將吸附於基板W上之過剩物質除去。藉由步驟ST11與步驟ST12的實行,亦可將前驅物層PC作為單分子層形成在基板W上。In step ST12, purging of the
在步驟ST13,如圖7(b)所示,由前驅物層PC形成膜PF。在步驟ST13,亦可為了膜PF的形成,使用第2氣體。第2氣體,包含藉由與構成前驅物層PC的物質反應而由前驅物層PC形成膜PF的反應物種。在步驟ST13,可不由第2氣體產生電漿地形成膜PF。抑或,在步驟ST13,亦可使用來自由第2氣體產生之電漿的化學物種而形成膜PF。抑或,在步驟ST13,亦可藉由熱或光等將前驅物層PC活性化。In step ST13, as shown in FIG. 7(b), a film PF is formed from the precursor layer PC. In step ST13, the second gas may be used for the formation of the film PF. The second gas includes a reactive species that forms the film PF from the precursor layer PC by reacting with the substance constituting the precursor layer PC. In step ST13, the film PF can be formed without generating plasma from the second gas. Alternatively, in step ST13, a chemical species derived from the plasma generated by the second gas may be used to form the film PF. Alternatively, in step ST13, the precursor layer PC may be activated by heat, light, or the like.
處理基板W的第1例之情況,第2氣體,例如包含具有NH基的化合物或具有羥基的化合物。具有NH基的化合物,例如包含胺、NH3 、N2 H2 、或N2 H4 。處理基板W的第2例、第3例、第5例、第6例、第7例、及第8例之情況,第2氣體,各自包含含氧氣體或含氮氣體。含氧氣體,例如為O2 氣體。含氮氣體,例如為NH3 氣體。處理基板W的第4例之情況,第2氣體,包含含氫氣體(例如H2 氣體)。In the case of the first example of processing the substrate W, the second gas includes, for example, a compound having an NH group or a compound having a hydroxyl group. The compound having an NH group includes, for example, amine, NH 3 , N 2 H 2 , or N 2 H 4 . In the case of processing the second example, the third example, the fifth example, the sixth example, the seventh example, and the eighth example of the substrate W, the second gas each includes an oxygen-containing gas or a nitrogen-containing gas. The oxygen-containing gas is, for example, O 2 gas. The nitrogen-containing gas is, for example, NH 3 gas. In the fourth example of processing the substrate W, the second gas includes a hydrogen-containing gas (for example, H 2 gas).
於步驟ST13中,控制部80,控制氣體供給部GS俾將第2氣體往腔室10內供給。於步驟ST13中,控制部80,控制排氣裝置50俾將腔室10內之氣體的壓力設定為指定的壓力。於步驟ST13中產生電漿之情況,控制部80,控制電漿產生部俾於腔室10內由第2氣體產生電漿。在一實施形態,為了由第2氣體產生電漿,控制部80,控制高頻電源61及/或偏壓電源62,俾供給高頻電力HF及/或高頻電力LF。抑或,於步驟ST13中,控制部80,亦可為了前驅物層PC的活性化而控制加熱器HT俾將基板W加熱。抑或,於步驟ST13中,控制部80,亦可為了前驅物層PC之活性化而控制光源俾對基板W照射光線。In step ST13, the
在步驟ST14,實行內部空間10s之吹掃。步驟ST14,係與步驟ST12相同的步驟。藉由步驟ST14的實行,可將腔室10內之第2氣體置換為惰性氣體。In step ST14, purging of the
在步驟ST1,亦可依序重複各自包含步驟ST11及步驟ST13的複數個成膜周期CY1。複數個成膜周期CY1,亦可各自更包含步驟ST12及步驟ST14。膜PF的厚度,可藉由調整成膜周期CY1之重複次數而調整。重複成膜周期CY1之情況,於步驟ST15中判定是否滿足停止條件。停止條件,在成膜周期CY1之實行次數達到既定次數的情況滿足。於步驟ST15中判定為未滿足停止條件之情況,再度實行成膜周期CY1。於步驟ST15中判定為滿足停止條件之情況,結束步驟ST1的實行,如圖1所示,使處理前往步驟ST2。In step ST1, a plurality of film forming cycles CY1 each including step ST11 and step ST13 may be repeated sequentially. A plurality of film forming cycles CY1 may each further include step ST12 and step ST14. The thickness of the film PF can be adjusted by adjusting the number of repetitions of the film forming cycle CY1. When the film forming cycle CY1 is repeated, it is determined in step ST15 whether the stop condition is satisfied. The stop condition is satisfied when the number of executions of the film forming cycle CY1 reaches the predetermined number. If it is determined in step ST15 that the stop condition is not satisfied, the film formation cycle CY1 is executed again. If it is determined in step ST15 that the stop condition is satisfied, the execution of step ST1 is ended, and the process proceeds to step ST2 as shown in FIG. 1.
步驟ST2,於步驟ST1中在基板W上形成膜PF後實行。在步驟ST2,蝕刻區域RE。在一實施形態,藉由來自電漿的化學物種蝕刻區域RE。在步驟ST2,於腔室10內由處理氣體產生電漿P2。在步驟ST2使用之處理氣體,可與在步驟STa使用之處理氣體相同。Step ST2 is performed after the film PF is formed on the substrate W in step ST1. In step ST2, the region RE is etched. In one embodiment, the region RE is etched by chemical species from plasma. In step ST2, plasma P2 is generated from the processing gas in the
圖8(a)係用於說明圖1所示之蝕刻方法的步驟ST2之例子的圖,圖8(b)係步驟ST2之實行後的狀態之一例的基板之部分放大剖面圖。在步驟ST2,如圖8(a)所示,對區域RE照射來自電漿P2的化學物種,藉由該化學物種蝕刻區域RE。步驟ST2之實行的結果,如圖8(b)所示,使開口OP之深度增加。於區域RE形成的開口OP,亦可具有10以上之寬高比。FIG. 8(a) is a diagram for explaining an example of step ST2 of the etching method shown in FIG. 1, and FIG. 8(b) is a partially enlarged cross-sectional view of a substrate in an example of a state after step ST2 is performed. In step ST2, as shown in FIG. 8(a), the region RE is irradiated with a chemical species from the plasma P2, and the region RE is etched by the chemical species. As a result of the execution of step ST2, as shown in FIG. 8(b), the depth of the opening OP is increased. The opening OP formed in the region RE may also have an aspect ratio of 10 or more.
於步驟ST2中,控制部80,控制排氣裝置50俾將腔室10內之氣體的壓力設定為指定的壓力。於步驟ST2中,控制部80,控制氣體供給部GS俾將處理氣體往腔室10內供給。於步驟ST2中,控制部80,為了由處理氣體產生電漿而控制電漿產生部。在一實施形態中的步驟ST2,控制部80,控制高頻電源61及偏壓電源62,俾供給高頻電力HF及偏壓電力BP。於步驟ST2中,亦可為了產生電漿,僅供給高頻電力HF及高頻電力LF中之一方。In step ST2, the
在方法MT,亦可依序實行各自包含步驟ST1及步驟ST2的複數個周期CY。依序實行複數個周期CY之情況,於步驟ST3中判定是否滿足停止條件。停止條件,在周期CY之實行次數達到既定次數的情況滿足。於步驟ST3中判定為未滿足停止條件之情況,再度實行周期CY。於步驟ST3中判定為滿足停止條件之情況,結束方法MT的實行。In the method MT, a plurality of cycles CY including step ST1 and step ST2 can also be executed sequentially. When a plurality of cycles CY are executed in sequence, it is determined in step ST3 whether the stop condition is satisfied. The stop condition is met when the number of executions in the cycle CY reaches the predetermined number. If it is determined in step ST3 that the stop condition is not satisfied, the cycle CY is executed again. When it is determined in step ST3 that the stop condition is satisfied, the execution of the method MT is ended.
形成於基板W上的膜PF,在步驟ST2中之區域RE的蝕刻開始時保護遮罩MK。因此,可抑制因遮罩MK受到蝕刻而從遮罩MK釋出的物質阻塞開口OP而再度附著於遮罩MK之情形。抑或,在作為用於蝕刻之氣體,使用為了保護遮罩MK而於遮罩MK上形成沉積物之氣體的情況,可抑制過剩的沉積物阻塞開口OP之情形。此外,膜PF,保護形成於區域RE的側壁面,故可抑制形成在區域RE內的開口OP因步驟ST2中之蝕刻而往橫向擴大的情形。The film PF formed on the substrate W protects the mask MK when the etching of the region RE in step ST2 starts. Therefore, it is possible to prevent the substance released from the mask MK due to the etching of the mask MK from blocking the opening OP and attaching to the mask MK again. Or, in the case of using a gas for forming deposits on the mask MK to protect the mask MK as a gas for etching, it is possible to prevent the excess deposits from blocking the opening OP. In addition, the film PF protects the sidewall surface formed in the region RE, so that the opening OP formed in the region RE can be prevented from expanding laterally due to the etching in step ST2.
此外,在膜PF形成後,於步驟ST2中蝕刻區域RE,故於步驟ST2中遮罩MK的蝕刻之開始延遲。因此,於方法MT中,區域RE之蝕刻的相對於遮罩MK之蝕刻的選擇比變高。In addition, after the film PF is formed, the region RE is etched in step ST2, so the start of etching of the mask MK in step ST2 is delayed. Therefore, in the method MT, the selective ratio of the etching of the region RE to the etching of the mask MK becomes higher.
另,亦可使用於在複數個周期CY裡之至少一個周期中形成膜PF的步驟ST1之條件,與用於在複數個周期CY裡之至少另一個周期中形成膜PF的步驟ST1之條件成為不同。亦可使全部周期CY的步驟ST1之條件,彼此成為不同。此一情況,於各周期中,可將膜PF,以其厚度或覆蓋範圍與在其他周期中形成之膜PF的厚度或覆蓋範圍不同之方式形成。In addition, the conditions of the step ST1 for forming the film PF in at least one of the cycles CY may be used as the conditions of the step ST1 for forming the film PF in at least another of the cycles CY different. The conditions of step ST1 in all cycles CY may be different from each other. In this case, in each cycle, the film PF can be formed in a way that its thickness or coverage is different from the thickness or coverage of the film PF formed in other cycles.
亦可使用於在複數個周期CY裡之至少一個周期中蝕刻區域RE的步驟ST2之條件,與用於在複數個周期CY裡之至少另一個周期中蝕刻區域RE的步驟ST2之條件成為不同。亦可使全部周期CY的步驟ST2之條件,彼此成為不同。此一情況,於各周期中,將區域RE,以其蝕刻量與在其他周期之區域RE的蝕刻量成為不同之方式蝕刻。The condition of step ST2 for etching the area RE in at least one of the cycles CY may also be different from the condition of step ST2 for etching the area RE in at least another cycle of the plurality of cycles CY. The conditions of step ST2 in all cycles CY may be different from each other. In this case, in each period, the area RE is etched in such a way that its etching amount is different from the etching amount of the area RE in other periods.
在各複數個周期CY,亦可使在複數個成膜周期CY1裡之一個成膜周期形成膜PF之條件,與用於在複數個成膜周期CY1裡之至少另一個成膜周期形成膜PF之條件成為不同。亦即,在各複數個周期CY,亦可使一個成膜周期中的步驟ST11之條件及/或步驟ST13之條件,與至少另一個成膜周期中的步驟ST11之條件及/或步驟ST13之條件成為不同。在各複數個周期CY,亦可使在全部成膜周期CY1形成膜PF之條件,彼此成為不同。此一情況,可於各複數個周期CY所包含的各複數個成膜周期CY1,控制膜PF的厚度之分布。In each of the plurality of cycles CY, the conditions for forming the film PF in one of the plurality of film forming cycles CY1 may be the same as the conditions for forming the film PF in at least another of the plurality of film forming cycles CY1 The conditions become different. That is, in each of the plural cycles CY, the conditions of step ST11 and/or the conditions of step ST13 in one film formation cycle may be different from the conditions of step ST11 and/or step ST13 in at least another film formation cycle. The conditions become different. In each of the plural cycles CY, the conditions for forming the film PF in all the film forming cycles CY1 may be different from each other. In this case, the thickness distribution of the film PF can be controlled in each of the plurality of film forming periods CY1 included in each of the plurality of periods CY.
以下,參考圖9(a)及圖9(b)。圖9(a)係前驅物層形成後的狀態之一例的基板之部分放大剖面圖,圖9(b)係膜形成後的狀態之一例的基板之部分放大剖面圖。一實施形態中,如圖9(b)所示,膜PF,覆蓋基板W內之上部的表面即可。基板W內之上部的表面,包含遮罩MK的表面。基板W內之上部的表面,未包含界定開口OP的底面BS。基板W內之上部的表面,亦可進一步未包含界定開口OP的側面SS中之底面BS的附近之區域。抑或,一實施形態中,膜PF的厚度,亦可具有因應位置而改變之分布。例如,膜PF,亦可形成為使其厚度與基板W內之從基板W的上端算起之深度相應而減少。更具體而言,膜PF的厚度,亦可為在開口OP之上端附近大,在開口OP之深部附近小或為零。藉由使用具有此等厚度之分布的膜PF,而抑制開口OP之寬度在其底部側變窄的情形。具有此等厚度之分布的膜PF,可藉由下述說明的膜PF之形成方法或上述CVD法而形成。Hereinafter, refer to Fig. 9(a) and Fig. 9(b). FIG. 9(a) is a partially enlarged cross-sectional view of a substrate of an example of a state after the precursor layer is formed, and FIG. 9(b) is a partially enlarged cross-sectional view of a substrate of an example of a state after film formation. In one embodiment, as shown in FIG. 9(b), the film PF may cover the upper surface of the substrate W. The upper surface of the substrate W includes the surface of the mask MK. The upper surface of the substrate W does not include the bottom surface BS defining the opening OP. The upper surface of the substrate W may further not include an area near the bottom surface BS in the side surface SS defining the opening OP. Or, in one embodiment, the thickness of the film PF may also have a distribution that changes according to the position. For example, the film PF may be formed so that its thickness decreases in accordance with the depth of the substrate W from the upper end of the substrate W. More specifically, the thickness of the film PF may be large near the upper end of the opening OP, small or zero near the deep portion of the opening OP. By using the film PF having such a thickness distribution, the width of the opening OP is suppressed from narrowing on the bottom side. The film PF having such a thickness distribution can be formed by the method of forming the film PF described below or the above-mentioned CVD method.
為了形成圖9(b)所示之膜PF,於步驟ST11中,將前驅物層PC,如圖9(a)所示地形成為覆蓋遮罩MK之表面,但亦可形成為未覆蓋基板W之全表面。如此地,為了形成前驅物層PC,於步驟ST11中,滿足(1)~(5)之條件裡的至少一個條件。在(1)之條件,將步驟ST11之實行中的腔室10中之氣體的壓力,設定為在其他處理條件相同之情況,較使形成前驅物層PC的物質吸附於基板W之全表面的壓力更低的壓力。在(2)之條件,將步驟ST11的處理時間,設定為在其他處理條件相同之情況,較使形成前驅物層PC的物質吸附於基板W之全表面的處理時間更短的時間。在(3)之條件,將形成前驅物層PC的物質之第1氣體的稀釋度,設定為在其他處理條件相同之情況,較使形成前驅物層PC的物質吸附於基板W之全表面的稀釋度更高之值。在(4)之條件,將步驟ST11的實行中之基板支持器16的溫度,設定為在其他處理條件相同之情況,較使形成前驅物層PC的物質吸附於基板W之全表面的溫度更低的溫度。(5)之條件,可應用在於步驟ST11中產生電漿的情況。在(5)之條件,將高頻電力(高頻電力HF及/或高頻電力LF)的絕對值,設定為在其他處理條件相同之情況,較使形成前驅物層PC的物質吸附於基板W之全表面的絕對值更小的值。In order to form the film PF shown in FIG. 9(b), in step ST11, the precursor layer PC, as shown in FIG. 9(a), is formed to cover the surface of the mask MK, but it can also be formed without covering the substrate W The whole surface. In this way, in order to form the precursor layer PC, in step ST11, at least one of the conditions (1) to (5) is satisfied. Under the condition of (1), the pressure of the gas in the
為了形成圖9(b)所示之膜PF,亦可於步驟ST13中,滿足(1)~(5)之條件裡的至少一個條件。在(1)之條件,將步驟ST13之實行中的腔室10中之氣體的壓力,設定為在其他處理條件相同之情況,較使第2氣體中的物質與形成前驅物層PC的物質之反應於前驅物層PC全體中完成的壓力更低的壓力。在(2)之條件,將步驟ST13的處理時間,設定為在其他處理條件相同之情況,較使第2氣體中的物質與形成前驅物層PC的物質之反應於前驅物層PC全體中完成的處理時間更短的時間。在(3)之條件,將形成膜PF的物質之第2氣體的稀釋度,設定為在其他處理條件相同之情況,較使第2氣體中的物質與形成前驅物層PC的物質之反應於前驅物層PC全體中完成的稀釋度更高的值。在(4)之條件,將步驟ST13之實行中的基板支持器16之溫度,設定為在其他處理條件相同之情況,較使第2氣體中的物質與形成前驅物層PC的物質之反應於前驅物層PC全體中完成的溫度更低的溫度。(5)之條件,可應用在於步驟ST13中產生電漿的情況。在(5)之條件,將高頻電力(高頻電力HF及/或高頻電力LF)的絕對值,設定為在其他處理條件相同之情況,較使第2氣體中的物質與形成前驅物層PC的物質之反應於前驅物層PC全體中完成的絕對值更小的值。In order to form the film PF shown in FIG. 9(b), at least one of the conditions (1) to (5) may be satisfied in step ST13. Under the condition of (1), the pressure of the gas in the
以下,參考圖10。方法MT,亦可利用包含成膜裝置及基板處理裝置之基板處理系統而實行。圖10係顯示一例示性實施形態之基板處理系統的圖。圖10所示之基板處理系統PS,可使用在方法MT的實行。Hereinafter, refer to FIG. 10. The method MT can also be implemented using a substrate processing system including a film forming device and a substrate processing device. Fig. 10 is a diagram showing a substrate processing system according to an exemplary embodiment. The substrate processing system PS shown in FIG. 10 can be used in the implementation of the method MT.
基板處理系統PS,具備:載台2a~2d、容器4a~4d、裝載模組LM、對準器AN、裝載鎖定模組LL1和LL2、處理模組PM1~PM6、搬運模組TF、及控制部MC。另,基板處理系統PS中之載台的個數、容器的個數、裝載鎖定模組的個數,可為一以上的任意個數。此外,基板處理系統PS中之處理模組的個數,可為二以上的任意個數。The substrate processing system PS includes:
載台2a~2d,沿著裝載模組LM之一緣而配列。容器4a~4d,分別搭載於載台2a~2d上。容器4a~4d,例如分別為被稱作FOUP(Front Opening Unified Pod,前開式晶圓盒)之容器。容器4a~4d,分別構成為於其內部收納基板W。The
裝載模組LM,具備腔室。將裝載模組LM之腔室內的壓力,設定為大氣壓。裝載模組LM,具備搬運裝置TU1。搬運裝置TU1,例如為多關節機械臂,藉由控制部MC而控制。搬運裝置TU1,構成為經由裝載模組LM之腔室而搬運基板W。搬運裝置TU1,可於各容器4a~4d與對準器AN之間、對準器AN與各裝載鎖定模組LL1和LL2之間、各裝載鎖定模組LL1和LL2與各容器4a~4d之間,搬運基板W。對準器AN,與裝載模組LM連接。對準器AN,構成為施行基板W之位置的調整(位置的校正)。The loading module LM has a cavity. Set the pressure in the chamber of the loading module LM to atmospheric pressure. The loading module LM is equipped with a transport device TU1. The transport device TU1 is, for example, a multi-joint robot arm, and is controlled by the control unit MC. The transfer device TU1 is configured to transfer the substrate W through the chamber of the loading module LM. The transport device TU1 can be used between each
裝載鎖定模組LL1及裝載鎖定模組LL2,各自設置於裝載模組LM與搬運模組TF之間。裝載鎖定模組LL1及裝載鎖定模組LL2,各自提供預備減壓室。The load lock module LL1 and the load lock module LL2 are respectively arranged between the load module LM and the transport module TF. The load lock module LL1 and the load lock module LL2 each provide a preliminary decompression chamber.
搬運模組TF,經由閘閥而與裝載鎖定模組LL1及裝載鎖定模組LL2各自連接。搬運模組TF,具備可減壓之搬運腔室TC。搬運模組TF,具備搬運裝置TU2。搬運裝置TU2,例如為多關節機械臂,藉由控制部MC控制。搬運裝置TU2,構成為經由搬運腔室TC搬運基板W。搬運裝置TU2,可於各裝載鎖定模組LL1和LL2與各處理模組PM1~PM6之間、及處理模組PM1~PM6裡的任意二個處理模組之間中搬運基板W。The transport module TF is connected to the load lock module LL1 and the load lock module LL2 via gate valves. The transport module TF has a transport chamber TC that can be decompressed. The transport module TF has a transport device TU2. The transport device TU2 is, for example, a multi-joint robot arm, and is controlled by the control unit MC. The transfer device TU2 is configured to transfer the substrate W via the transfer chamber TC. The transport device TU2 can transport the substrate W between each load lock module LL1 and LL2 and each processing module PM1~PM6, and between any two processing modules of the processing modules PM1~PM6.
處理模組PM1~PM6,各自構成為施行專用的基板處理之裝置。處理模組PM1~PM6裡的一個處理模組為成膜裝置。此成膜裝置,係為了於步驟ST1中形成膜PF而使用。因此,此成膜裝置,係構成為實行由上述成膜法進行的步驟ST1之裝置。此成膜裝置,於步驟ST1中產生電漿的情況,可為電漿處理裝置1或其他電漿處理裝置等電漿處理裝置。此成膜裝置,於步驟ST1中形成膜PF而非產生電漿的情況,亦可不具有用於產生電漿之構成。The processing modules PM1~PM6 are each constituted as a device for performing dedicated substrate processing. One of the processing modules PM1~PM6 is a film forming device. This film forming apparatus is used for forming the film PF in step ST1. Therefore, this film forming apparatus is configured to execute step ST1 by the above-mentioned film forming method. This film forming device, when generating plasma in step ST1, may be a plasma processing device such as a plasma processing device 1 or other plasma processing devices. In this film forming apparatus, when the film PF is formed in step ST1 instead of generating plasma, it may not have a configuration for generating plasma.
處理模組PM1~PM6裡之另一個處理模組,為電漿處理裝置1或其他電漿處理裝置等基板處理裝置。此基板處理裝置,係為了於步驟ST2中蝕刻區域RE而使用。此基板處理裝置,亦可使用在步驟STa之蝕刻。抑或,步驟STa之蝕刻,亦可使用處理模組PM1~PM6裡之係再另一處理模組之基板處理裝置實行。The other processing module among processing modules PM1~PM6 is a substrate processing device such as plasma processing device 1 or other plasma processing devices. This substrate processing apparatus is used to etch the region RE in step ST2. This substrate processing apparatus can also be used for etching in step STa. Or, the etching of step STa can also be performed using a substrate processing device of another processing module among the processing modules PM1 to PM6.
於基板處理系統PS中,控制部MC,構成為控制基板處理系統PS的各部。控制部MC,控制成膜裝置俾於步驟ST1中形成膜PF。控制部MC,控制基板處理裝置,俾於形成膜PF後,蝕刻區域RE。此基板處理系統PS,可在處理模組間以不接觸大氣的方式搬運基板W。In the substrate processing system PS, the control section MC is configured to control each section of the substrate processing system PS. The control unit MC controls the film forming apparatus so that the film PF is formed in step ST1. The control part MC controls the substrate processing apparatus so that the region RE is etched after the film PF is formed. This substrate processing system PS can transport the substrate W between the processing modules without contacting the atmosphere.
以上,雖針對各種例示性實施形態予以說明,但並未限定於上述例示性實施形態,亦可進行各式各樣的追加、省略、置換、及變更。此外,可組合不同實施形態之要素而形成另一實施形態。Although various exemplary embodiments have been described above, they are not limited to the above-mentioned exemplary embodiments, and various additions, omissions, replacements, and changes may be made. In addition, elements of different embodiments can be combined to form another embodiment.
例如,方法MT的實行所使用之基板處理裝置,亦可為任意類型之電漿處理裝置。例如,方法MT的實行所使用之基板處理裝置,亦可為電漿處理裝置1以外的電容耦合型之電漿處理裝置。方法MT的實行所使用之基板處理裝置,亦可為電感耦合型之電漿處理裝置、ECR(電子迴旋共振)電漿處理裝置、或將微波等表面波使用在電漿的產生之電漿處理裝置。此外,於方法MT中,在未利用電漿的情況,基板處理裝置,亦可不具備電漿產生部。For example, the substrate processing device used in the implementation of the method MT can also be any type of plasma processing device. For example, the substrate processing apparatus used for the execution of the method MT may also be a capacitive coupling type plasma processing apparatus other than the plasma processing apparatus 1. The substrate processing device used for the implementation of method MT can also be an inductively coupled plasma processing device, an ECR (electron cyclotron resonance) plasma processing device, or a plasma processing that uses surface waves such as microwaves to generate plasma Device. In addition, in the method MT, when plasma is not used, the substrate processing apparatus may not include the plasma generating unit.
由上述說明來看,在說明之目的下,藉由本說明書闡述本發明之各種實施形態,應理解可不脫離本發明之範圍及主旨地進行各種變更。因此,本說明書所揭露之各種實施形態,其意旨不在於限定本發明,而本發明之真正的範圍與主旨,依添附之發明申請專利範圍所示。Judging from the above description, for the purpose of description, this specification explains various embodiments of the present invention, and it should be understood that various changes can be made without departing from the scope and spirit of the present invention. Therefore, the various embodiments disclosed in this specification are not intended to limit the present invention, but the true scope and gist of the present invention are shown by the appended invention patent scope.
1:電漿處理裝置 2a~2d:載台 4a~4d:容器 10:腔室 10s:內部空間 12:腔室本體 12e:排氣口 12g:閘閥 12p:通路 15:支持體 16:基板支持器 18:下部電極 18f:流路 19:電極板 20:靜電吸盤 20e:電極 20m:本體 20p:直流電源 20s:開關 23a,23b:配管 25:氣體供給管線 28:筒狀部 29:絕緣部 30:上部電極 32:構件 34:頂板 34a:氣體噴吐孔 36:支持體 36a:氣體擴散室 36b:氣體孔 36c:氣體導入口 38:氣體供給管 40:氣體源群 41,43:閥群 42:流量控制器群 48:遮擋構件 50:排氣裝置 52:排氣管 61:高頻電源 61m,62m:匹配器 62:偏壓電源 64:直流電源裝置 80:控制部 AN:對準器 AX:軸線 BS:底面 BP:偏壓電力 CY:周期 CY1:成膜周期 PF:膜 ER:邊緣環 GS:氣體供給部 HC:加熱器控制器 HF,LF:高頻電力 HT:加熱器 LL1,LL2:裝載鎖定模組 LM:裝載模組 MC:控制部 MK:遮罩 MT:方法 OP:開口 P2,Pa:電漿 PC:前驅物層 PM1~PM6:處理模組 PS:基板處理系統 RE:區域 STa,ST1~ST3,ST11~ST15:步驟 SS:側面 TC:搬運腔室 TF:搬運模組 TU1,TU2:搬運裝置 UR:基底區域 W:基板1: Plasma processing device 2a~2d: carrier 4a~4d: container 10: Chamber 10s: internal space 12: Chamber body 12e: exhaust port 12g: gate valve 12p: access 15: Support 16: substrate supporter 18: Lower electrode 18f: flow path 19: Electrode plate 20: Electrostatic chuck 20e: Electrode 20m: body 20p: DC power supply 20s: switch 23a, 23b: Piping 25: Gas supply line 28: cylindrical part 29: Insulation 30: Upper electrode 32: component 34: top plate 34a: Gas vent hole 36: support body 36a: Gas diffusion chamber 36b: Gas hole 36c: Gas inlet 38: Gas supply pipe 40: Gas source group 41, 43: valve group 42: Flow Controller Group 48: occlusion component 50: Exhaust device 52: Exhaust pipe 61: High frequency power supply 61m, 62m: matcher 62: Bias power supply 64: DC power supply unit 80: Control Department AN: Aligner AX: axis BS: bottom surface BP: Bias power CY: cycle CY1: Film formation cycle PF: Membrane ER: Edge ring GS: Gas Supply Department HC: heater controller HF, LF: high frequency power HT: heater LL1, LL2: Load lock module LM: Load module MC: Control Department MK: Mask MT: method OP: opening P2, Pa: Plasma PC: Precursor layer PM1~PM6: Processing module PS: Substrate processing system RE: area STa, ST1~ST3, ST11~ST15: steps SS: side TC: Handling chamber TF: Handling module TU1, TU2: handling device UR: basal area W: substrate
圖1係一例示性實施形態之蝕刻方法的流程圖。 圖2係一例之基板的部分放大剖面圖。 圖3係概略顯示一例示性實施形態之基板處理裝置的圖。 圖4係一例示性實施形態之基板處理裝置中的靜電吸盤之放大剖面圖。 圖5中,圖5(a)係用於說明圖1所示之蝕刻方法的步驟STa之例子的圖;圖5(b)係步驟STa之實行後的狀態之一例的基板之部分放大剖面圖。 圖6係可於一例示性實施形態之蝕刻方法中使用的成膜方法之流程圖。 圖7中,圖7(a)係前驅物層形成後的狀態之一例的基板之部分放大剖面圖;圖7(b)係膜PF形成後的狀態之一例的基板之部分放大剖面圖。 圖8中,圖8(a)係用於說明圖1所示之蝕刻方法的步驟ST2之例子的圖;圖8(b)係步驟ST2之實行後的狀態之一例的基板之部分放大剖面圖。 圖9中,圖9(a)係前驅物層形成後的狀態之一例的基板之部分放大剖面圖;圖9(b)係膜形成後的狀態之一例的基板之部分放大剖面圖。 圖10係顯示一例示性實施形態之基板處理系統的圖。FIG. 1 is a flowchart of an etching method in an exemplary embodiment. Fig. 2 is a partial enlarged cross-sectional view of an example of a substrate. Fig. 3 is a diagram schematically showing a substrate processing apparatus according to an exemplary embodiment. 4 is an enlarged cross-sectional view of an electrostatic chuck in a substrate processing apparatus according to an exemplary embodiment. In FIG. 5, FIG. 5(a) is a diagram for explaining an example of step STa of the etching method shown in FIG. 1; FIG. 5(b) is a partially enlarged cross-sectional view of a substrate of an example of a state after step STa is performed . FIG. 6 is a flowchart of a film forming method that can be used in the etching method of an exemplary embodiment. In FIG. 7, FIG. 7(a) is a partially enlarged cross-sectional view of the substrate of an example of the state after the precursor layer is formed; FIG. 7(b) is a partially enlarged cross-sectional view of the substrate of an example of the state after the film PF is formed. In FIG. 8, FIG. 8(a) is a diagram for explaining an example of step ST2 of the etching method shown in FIG. 1; FIG. 8(b) is a partially enlarged cross-sectional view of a substrate of an example of a state after the execution of step ST2 . In FIG. 9, FIG. 9(a) is a partially enlarged cross-sectional view of the substrate in an example of the state after the precursor layer is formed; FIG. 9(b) is a partially enlarged cross-sectional view of the substrate in an example of the state after the film is formed. Fig. 10 is a diagram showing a substrate processing system according to an exemplary embodiment.
CY:周期 CY: cycle
MT:方法 MT: method
STa,ST1~ST3:步驟 STa, ST1~ST3: steps
Claims (18)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020012240 | 2020-01-29 | ||
JP2020-012240 | 2020-01-29 | ||
JP2020101012A JP2021118347A (en) | 2020-01-29 | 2020-06-10 | Etching method, substrate processing apparatus and substrate processing system |
JP2020-101012 | 2020-06-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW202133251A true TW202133251A (en) | 2021-09-01 |
Family
ID=77175235
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110101577A TW202133251A (en) | 2020-01-29 | 2021-01-15 | Etching method, substrate processing apparatus, and substrate processing system |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP2021118347A (en) |
KR (1) | KR20210097044A (en) |
CN (1) | CN113270315A (en) |
TW (1) | TW202133251A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2023120622A (en) * | 2022-02-18 | 2023-08-30 | 東京エレクトロン株式会社 | Film deposition method and film deposition apparatus |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3976703B2 (en) * | 2003-04-30 | 2007-09-19 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor device |
JP5642001B2 (en) | 2011-03-25 | 2014-12-17 | 東京エレクトロン株式会社 | Plasma etching method |
JP2014225501A (en) * | 2013-05-15 | 2014-12-04 | 東京エレクトロン株式会社 | Plasma etching method and plasma etching apparatus |
JP6235974B2 (en) * | 2014-09-24 | 2017-11-22 | 東京エレクトロン株式会社 | Substrate processing method, program, computer storage medium, and substrate processing system |
JP7008474B2 (en) * | 2016-11-30 | 2022-01-25 | 東京エレクトロン株式会社 | Plasma etching method |
JP7022651B2 (en) * | 2018-05-28 | 2022-02-18 | 東京エレクトロン株式会社 | Film etching method and plasma processing equipment |
-
2020
- 2020-06-10 JP JP2020101012A patent/JP2021118347A/en active Pending
-
2021
- 2021-01-15 TW TW110101577A patent/TW202133251A/en unknown
- 2021-01-19 CN CN202110067048.4A patent/CN113270315A/en active Pending
- 2021-01-27 KR KR1020210011640A patent/KR20210097044A/en active Search and Examination
Also Published As
Publication number | Publication date |
---|---|
CN113270315A (en) | 2021-08-17 |
KR20210097044A (en) | 2021-08-06 |
JP2021118347A (en) | 2021-08-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107799390B (en) | High dry etch rate materials for semiconductor patterning applications | |
CN111247269B (en) | Geometrically selective deposition of dielectric films | |
US20220415661A1 (en) | Plasma processing apparatus and plasma processing method | |
TWI641022B (en) | Method and apparatus for precleaning a substrate surface prior to epitaxial growth | |
TWI834679B (en) | Selective growth of metal-containing hardmask thin films | |
CN107017162B (en) | Ultra-high selectivity polysilicon etch with high throughput | |
TW202147431A (en) | Atomic layer etching of molybdenum | |
CN114078683A (en) | Etching method and plasma processing apparatus | |
TW202133251A (en) | Etching method, substrate processing apparatus, and substrate processing system | |
US20210233778A1 (en) | Etching method, substrate processing apparatus, and substrate processing system | |
TW202133252A (en) | Etching method, substrate processing apparatus, and substrate processing system | |
US20230307290A1 (en) | Reducing intralevel capacitance in semiconductor devices | |
JP7412257B2 (en) | Etching method, substrate processing equipment, and substrate processing system | |
TWI745559B (en) | Method for processing target object | |
TWI797739B (en) | Etching method, plasma processing device and substrate processing system | |
US12009219B2 (en) | Substrate processing method | |
TWI840524B (en) | Method of etching film of substrate and plasma processing apparatus | |
CN111725062B (en) | Film etching method and plasma processing apparatus | |
TW202213517A (en) | Substrate processing method and plasma processing apparatus | |
WO2023178273A1 (en) | Reducing capacitance in semiconductor devices | |
TW202315000A (en) | Substrate processing device, plasma generation device, method for manufacturing semiconductor device, and program | |
TW202123334A (en) | Plasma processing method and plasma processing apparatus |