TW202131405A - Semiconductor device and method for forming the same - Google Patents

Abstract

An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

Description

Semiconductor device and its forming method

The embodiment of the present invention relates to a semiconductor structure, and particularly relates to a semiconductor device with dummy fins, a semiconductor structure and a method of forming the same.

Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are usually manufactured by the following methods, including sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and patterning the above-mentioned material layers using a lithography process to form circuit components on the semiconductor substrate And components.

The semiconductor industry continues to increase the integration density of various electronic components (for example, transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, which allows more components to be accumulated in a specific area. However, as the size of the smallest component decreases, other problems that should be resolved arise.

An embodiment of the disclosure discloses a semiconductor device, including: a first source/drain region is located on a semiconductor substrate; a dummy fin is adjacent to the first source/drain region, and the dummy fin includes: One part includes the first film layer; and the second part is located on the first part, the width of the second part is smaller than the width of the first part, wherein the second part includes: the second film layer; and the third film layer is located between the first film layer and the Between the second film layers, the third film layer is made of a material different from the first film layer and the second film layer; and the gate stack is arranged along the sidewall of the dummy fin.

An embodiment of the disclosure discloses a semiconductor device, including: a first transistor is located on the top surface of the semiconductor substrate, the first transistor includes: a first channel region; and a first gate stack located on the sidewall of the first channel region Above and along the sidewall of the first channel region; a second transistor located on the top surface of the semiconductor substrate; the second transistor includes: a second channel region; and a second gate stack located in the second channel region Above the sidewalls of and along the sidewalls of the second channel region; and dummy fins, which physically isolate the first gate stack from the second gate stack, wherein the dummy fins include: a first film layer And the second film layer, located above the first film layer, wherein the width of the dummy fin measured at the height position of the second film layer is smaller than the dummy fin measured at the height position of the first film layer The width of the slice.

An embodiment of the disclosure discloses a method for forming a semiconductor device, including: defining an opening between a first semiconductor fin and a second semiconductor fin; forming a dummy fin between the first semiconductor fin and the second semiconductor fin In between, forming the dummy fin includes: depositing the first film layer in the opening; recessing the first film layer in the opening; depositing the second film layer in the opening above the first film layer; depositing the first film layer The three films are in the opening above the second film, the second film is disposed on the sidewall and bottom surface of the third film; and the second film is etched to move at least partially from the sidewall of the third film Removing the second film layer; and forming a gate structure along the sidewall and top surface of the first semiconductor fin, the sidewall and top surface of the second semiconductor fin, and the sidewall and top surface of the dummy fin.

The following disclosure provides many embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. , So that they do not directly touch the embodiment. In addition, the embodiment of the present invention may repeat reference values and/or letters in various examples. Such repetition is for the purpose of conciseness and clarity, rather than to show the relationship between the different embodiments and/or configurations discussed.

Furthermore, words that are relative to space may be used, such as "below", "below", "lower", "above", "higher" and other similar words to facilitate the description of the picture The relationship between one part(s) or feature and another part(s) or feature in the formula. Spatial relative terms are used to include the different orientations of the device in use or operation, as well as the orientation described in the diagram. When the device is turned in different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position.

Various embodiments applied to FinFETs are described herein. The embodiments can be applied to other transistor technologies, including nanosheet FETs (NanosheetFET, sometimes referred to as fully wound gate field effect transistors (GAAFET)) or the like.

In various embodiments, dummy fins may be used to separate the metal gates of adjacent transistors. The dummy fins can also help isolate adjacent source/drain regions by preventing accidental source/drain merging during the epitaxial growth process, for example. It has been observed that due to the proximity of the dummy fin to the channel area of the transistor, the dummy fin size (sometimes referred to as critical dimension (CD)) affects the device yield. Various embodiments include forming a film layer on the sidewall of the dummy fin and etching the film layer. Therefore, the cross-sectional profile of the dummy fin can be improved. For example, the middle portion of the dummy fin may be narrower than the bottom of the dummy fin (for example, having a smaller critical dimension). In this way, the interval between the dummy fin and the channel region can be increased, and the process window for gap filling of the gate stack can be increased.

FIG. 1 is a three-dimensional view of an exemplary device 10 including a fin-type field effect transistor according to some embodiments. A part of the device 10 is cut off to illustrate the parts below it (for example, the parts outlined in dashed lines). The device 10 includes a fin 52 on a substrate 50 (eg, a semiconductor substrate). The isolation region 56 is disposed in the substrate 50, and the fin 52 protrudes upward from between adjacent isolation regions 56. Although the isolation region 56 is described/illustrated as being separated from the substrate 50, as used herein, the technical term "substrate" can be used to refer to only the semiconductor substrate, or to refer only to the semiconductor substrate including the isolation region. In addition, although the fin 52 is illustrated as the same single continuous material as the substrate 50, the fin 52 and/or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to a portion extending between adjacent isolation regions 56. The device 10 further includes dummy fins 52' located between adjacent fins 52.

The gate dielectric layer 92 is along the sidewalls and on the top surface of the fin 52, the gate electrode 94 is on the gate dielectric layer 92, and the gate mask layer 96 is on the gate electrode 94. The gate dielectric layer 92, the gate electrode 94, and the gate mask layer 96 may also be disposed on the sidewall of the dummy channel region 52'. One or more layers of gate spacers 86 can be located on the sidewalls of the gate dielectric layer 92, the gate electrode 94, and the gate mask layer 96. The source/drain regions 82 are disposed on both sides of the fin 52 opposite to the gate dielectric layer 92, the gate electrode 94 and the gate mask layer 96. In some embodiments, the gate spacer 86 may also be formed on the sidewall of the dummy fin 52' as needed. The dummy fin 52' may be disposed between adjacent source/drain regions 82 and physically separate the adjacent source/drain regions 82. The adjacent source/drain regions 82 may also extend from the recessed portion of the fin 52.

The dielectric region 78 extends through the gate mask layer 96 into the gate electrode 94 (see, for example, FIG. 27A). The dielectric region 78 may extend to the dummy fin 52', and the combination of the dielectric region 78 and the dummy fin 52' may isolate the gate electrodes of adjacent fin-type field effect transistors. A contact etch stop layer (CESL) 87 is disposed on the isolation region 56, and the dielectric layer 88 is disposed on the contact etch stop layer 87. The dielectric layer 88 may further surround the source/drain region 82, a portion of the dummy fin 52', the gate mask layer 96, the gate dielectric layer 92, and the gate electrode 94.

Figure 1 further illustrates the reference section used in the subsequent drawings. The cross-section A-A is along the longitudinal axis of the gate electrode 94 and in, for example, a direction perpendicular to the direction of current flow between the source/drain regions 82 of the fin-type field effect transistor. The cross-section B-B is perpendicular to the cross-section A-A and is along the longitudinal axis of the fin 52 and in, for example, the direction of current flow between the source/drain regions 82 of the fin-type field effect transistor. The cross-section C-C is parallel to the cross-section A-A and extends through the source/drain region of the fin-type field effect transistor. For the sake of clarity, the subsequent drawings will refer to these reference profiles.

Some of the embodiments discussed herein are discussed in the context of fin-type field effect transistors formed using a gate-last process. In other embodiments, a gate-first process can be used. Moreover, some embodiments consider aspects used in planar devices (eg, planar field effect transistors).

FIGS. 2 to 37C are schematic cross-sectional views of intermediate stages of manufacturing fin-type field effect transistors according to some embodiments. Figure 2 to Figure 14, Figure 15A to Figure 15H, Figure 16A, Figure 16B, Figure 17, Figure 29 to Figure 35, and Figure 36A to Figure 36C illustrate the first picture The reference profile AA shown is except for a plurality of fins/fin field effect transistors. Figures 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, and 37A are along The reference section AA shown in Figure 1 is shown. Figures 18B, 19B, 20B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, 28B, and 37B are along The reference cross-section BB shown in FIG. 1 is shown except for a plurality of fins/fin field effect transistors. Figures 20C and 37C are drawn along the reference section C-C shown in Figure 1, except for a plurality of fins/fin field effect transistors.

In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate or the like, which may be doped (for example, p-type or n-type doped Quality) or undoped. The substrate 50 may be a wafer, for example, a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, which is usually a silicon or glass substrate. Other substrates can also be used, for example, multi-layered or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide (indium antimonide); Alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide ), gallium indium phosphide and/or gallium indium arsenide phosphide; or a combination of the above.

The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form an n-type device, for example, an n-type metal oxide semiconductor (NMOS) transistor, for example, an n-type fin field effect transistor. The region 50P can be used to form a p-type device, for example, a p-type metal oxide semiconductor (PMOS) transistor, for example, a p-type fin field effect transistor. The region 50N can be physically separated from the region 50P (as shown by the dividing line 51), and any number of device components (for example, other active devices, doped regions, isolation Structure, etc.).

A hard mask 53 is deposited on the substrate 50. The hard mask 53 may be used to define the pattern of semiconductor fins to be formed later. In some embodiments, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or other similar methods are used to deposit the hard mask. The hard mask 53 may include silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, the above-mentioned multilayer structure, or the like. For example, although only one hard mask layer is shown in the drawing, a multilayer structure (for example, a silicon oxide layer on a silicon nitride layer) can be formed as the hard mask 53.

Figures 3 to 28B illustrate various additional steps in the manufacture of the embodiment device. Figures 3 to 28B illustrate components located in one of the area 50N and the area 50P. For example, the structures depicted in FIG. 3 to FIG. 28B can be applied to both the area 50N and the area 50P. The structural differences (if any) of the area 50N and the area 50P are described in the description of each drawing.

FIGS. 3 to 16B illustrate schematic cross-sectional views of manufacturing dummy fins according to various embodiments (for example, as shown along the cross-section A-A of FIG. 1). In FIG. 3, the fin 52A and the fin 52B are formed in the substrate 50. The fins 52A/52B are semiconductor strips. The fins 52A/52B include fins 52B located between the fins 52A. As will be described in the subsequent drawings, the fin 52B will be removed and replaced by a dummy fin 52' (refer to FIG. 14).

In some embodiments, the fin 52A can be formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any acceptable etching process, for example, reactive ion etch (RIE), neutral beam etch (NBE), other similar methods, or a combination of the above. The etching can be anisotropic.

The fins can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the fins, including a double-patterning process or a multi-patterning process. Generally speaking, the double patterning or multi-patterning process combines a photolithography process and a self-aligned process to create a pattern with a smaller pitch. For example, the pattern has a pitch The pitch is smaller than the pitch that can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. A self-aligned process is used to form spacers beside the patterned sacrificial layer. After that, the sacrificial layer is removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fins 52A/52B.

In Figure 4, the insulating material 54 is formed on the substrate 50 and is located between adjacent fins 52A/52B. The insulating material 54 may be oxide (for example, silicon oxide), nitride, other similar substances, or a combination of the above, and may be formed by the following methods, including high density plasma chemical vapor deposition (high density plasma chemical vapor deposition, HDP-CVD), flowable chemical vapor deposition (FCVD) (for example, CVD-based material deposition in a remote plasma system, and post curing to convert it into another One material, for example, oxide), other similar methods, or a combination of the above. Other insulating materials formed by any acceptable method can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by a flow chemical vapor deposition process. After the insulating material is formed, the annealing process can be carried out. In one embodiment, the insulating material 54 is formed so that the excess insulating material 54 covers the fins 52A/52B. Although the insulating material 54 is shown as a single layer, some embodiments may use a multilayer structure. For example, in some embodiments, a compliant liner (not shown) may be formed along the surfaces of the substrate 50 and the fins 52A/52B. Thereafter, a filler material may be formed on the liner layer, for example, the material as discussed above.

After the deposition, a removal process is performed on the insulating material 54 to remove the excess insulating material 54 above the fins 52A/52B. In some embodiments, a planarization process (for example, chemical mechanical polishing), an etch-back process, a combination of the above, or other similar methods may be used. The planarization process exposes the fins 52A/52B, so that after the planarization process is completed, the top surface of the fins 52A/52B and the top surface of the insulating material 54 are flush. In the embodiment where the mask 53 is retained on the fins 52A/52B, the flattening process may expose the mask 53 or remove the mask 53, so that after the flattening process is completed, the top surface of the mask or the fins The top surfaces of the sheets 52A/52B are flush with the top surface of the insulating material 54 respectively.

In Figure 5, for example, at least a portion of the fin 52B is removed using an acceptable etching process. Therefore, an opening 100 is formed in the isolation material 54 between the fins 52A. In the subsequent manufacturing process, a dummy channel area may be formed in the opening 100. The fin 52B may be completely removed, or a part of the fin 52B may be left under the opening 100.

In FIG. 6, a spacer layer 102 as needed is deposited on the isolation material 54 and the substrate 50. The spacer layer 102 may be deposited along the sidewall and bottom surface of the recess 100. In an embodiment where the fin 52B is retained, a spacer layer 102 may be deposited on the top surface of the fin 52B. Any suitable process may be used to deposit the spacer layer 102, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition (PECVD), plasma enhanced ALD (PEALD) , Atomic layer deposition, physical vapor deposition or other similar methods. The spacer layer 102 can be deposited using a compliant process. The thickness of the spacer layer 102 may be in the range of about 3 Å to about 500 Å. The spacer layer 102 may include silicon-based dielectric materials (for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxynitride, silicon carbide, silicon oxycarbide). ), silicon oxide or the like); silicon-based semiconductor materials (for example, silicon germanium); metal oxides; metal nitrides or the like. In some embodiments where the spacer layer 102 includes a metal oxide or a metal nitride, the spacer layer 102 may include a metal, for example, hafnium, tantalum, aluminum, chromium, nickel, iron, yttrium, copper, tin, tungsten, or others. analog. The spacer layer 102 is a film layer provided as needed, and may be omitted in other embodiments.

In Figure 7, the film layer 104 is deposited on the spacer layer 102 (if present). In addition, in the embodiment where the spacer layer 102 is omitted, the film layer 104 may be directly deposited on the isolation material 54 and the substrate 50. The film layer 104 may be deposited along the sidewall and bottom surface of the recess 100 until the portion of the film layer 104 on the sidewall of the recess 100 is thick enough and joined together. Therefore, the film layer 104 can fill the remaining part of the groove 100, and a seam 104' can be formed in the film layer 104. The film layer 104 may be deposited by any suitable process, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, plasma-assisted atomic layer deposition, atomic layer deposition, physical vapor deposition, or other similar methods. The film layer 104 can be deposited using a compliant process. The thickness of the film layer 104 may be in the range of about 3 Å to about 500 Å. The film layer 104 may include a silicon-based dielectric material (for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxynitride, silicon carbide, silicon oxycarbide, silicon oxide, or other materials). Analogs); silicon-based semiconductor materials (for example, silicon germanium); metal oxides; metal nitrides or the like. In some embodiments where the film layer 104 includes metal oxide or metal nitride, the film layer 104 may include metal, for example, hafnium, tantalum, aluminum, chromium, nickel, iron, yttrium, copper, tin, tungsten, or the like .

The material of the film layer 104 may be the same as or different from the spacer layer 102. In addition, the spacer 102 may be included in the embodiment to partially fill a part of the notch 100 so that the film layer 104 may fill the remaining part of the notch 100 to improve the gap filling. For example, in an embodiment where the notch 100 is relatively wide, multiple layers of material may be deposited in the notch 100 so that each layer fills the notch 100 together without making any single film layer too thick. In addition, the material of the spacer 102 may be harder than the film layer 104. For example, the material of the film layer 104 can be selected for its gap filling characteristics, wherein the spacer 102 provides strength and structural support for the dummy fin 52' to be formed later (refer to FIG. 14).

In Figure 8, the film layer 104 can be etched back to a desired height. The etching of the film layer 104 may include a selective process, which can selectively etch the film layer 104 without significantly etching the isolation material 54 or the fin 52A.

In some embodiments, the etch-back process may be a plasma process, for example, plasma etching, remote plasma process, radical etch, or other similar methods. The etching gas used during the plasma process may include chlorine (Cl ₂ ), hydrogen bromide (HBr), perfluoromethane (CF ₄ ), trifluoromethane (CHF ₃ ), difluoromethane (CH ₂ F ₂ ), Monofluoromethane (CH ₃ F), hexafluorobutadiene (C ₄ F ₆ ), boron trichloride (BCl ₃ ), sulfur hexafluoride (SF ₆ ), hydrogen (H ₂ ), nitrogen trifluoride ( NF ₃ ), a combination of the above or other analogs. The plasma process may further include flowing a passivation gas through the device 10 to adjust (for example, increase) the etching selectivity between the film layer 104 and other components of the device 10. Exemplary passivation gases may include nitrogen, oxygen, carbon dioxide, sulfur dioxide, carbon monoxide, silicon tetrachloride (SiCl ₄ ), a combination of the above, or the like. One or more carrier gases may also be used during the plasma process, for example, argon, helium, neon, a combination of the above, or the like. In addition, the plasma source power in the range of about 10 W to about 3000 W, the bias power in the range of about 0 W to about 3000 W, and the pressure of about 1 mTorr to about 800 mTorr can be used. The plasma process is performed under a mixing flow rate of about 10 sccm to about 5000 sccm or other similar conditions.

In some embodiments, the etch-back process is a wet etching process (sometimes referred to as wet cleaning). Exemplary etchants that can be used during the wet etching process can include hydrofluoric acid (HF), fluorine (F ₂ ), combinations of the above, or the like. The wet etching process may further include flowing auxiliary etching chemicals through the device 10 to adjust (for example, increase) the etching selectivity between the film layer 104 and other components of the device 10. Exemplary auxiliary etching chemicals may include sulfuric acid (H ₂ SO ₄ ), hydrogen chloride (HCl), hydrogen bromide (HBr), ammonia (NH ₃ ), combinations of the foregoing, or other similar substances. Deionized water, alcohol, acetone, or the like can be used as a solvent for mixing etchant and/or auxiliary etching chemicals during the wet etching process.

In FIG. 9, the spacer layer 102 is etched back to, for example, the same height as the film layer 104. Etching the spacer layer 102 may include a selective process that can selectively etch the spacer layer 102 without significantly etching the isolation material 54 or the fin 52A. The etch-back process used for the spacer layer 102 may be the same as or different from the etch-back process used for the film layer 104.

In some embodiments, the etch-back process used for the spacer layer 102 may be a plasma process, for example, plasma etching, remote control plasma process, radical etching, or other similar methods. The etching gas used during the plasma process can include chlorine, hydrogen bromide, perfluoromethane, trifluoromethane, difluoromethane, monofluoromethane, hexafluorobutadiene, boron trichloride, sulfur hexafluoride, hydrogen , Nitrogen trifluoride, a combination of the above or other similar substances. The plasma process may further include flowing passivation gas through the device 10 to adjust (eg, increase) the etching selectivity between the spacer layer 102 and other components of the device 10. Exemplary passivation gases may include nitrogen, oxygen, carbon dioxide, sulfur dioxide, carbon monoxide, silicon tetrachloride, combinations of the above, or the like. One or more carrier gases may also be used during the plasma process, for example, argon, helium, neon, a combination of the above, or the like. In addition, the plasma source power in the range of about 10 W to about 3000 W, the bias power in the range of about 0 W to about 3000 W, and the pressure of about 1 mTorr to about 800 mTorr can be used. The plasma process is performed under a mixing flow rate of about 10 sccm to about 5000 sccm or other similar conditions.

In some embodiments, the etch-back process used for the spacer layer 102 is a wet etching process (sometimes referred to as wet cleaning). Exemplary etchants that can be used during the wet etching process can include hydrofluoric acid (HF), fluorine (F ₂ ), combinations of the above, or the like. The wet etching process may further include flowing auxiliary etching chemicals through the device 10 to adjust (for example, increase) the etching selectivity between the spacer layer 102 and other components of the device 10. Exemplary auxiliary etching chemicals may include sulfuric acid (H ₂ SO ₄ ), hydrogen chloride (HCl), hydrogen bromide (HBr), ammonia (NH ₃ ), combinations of the foregoing, or other similar substances. Deionized water, alcohol, acetone, or the like can be used as a solvent for mixing etchant and/or auxiliary etching chemicals during the wet etching process.

In Figure 10, the film layer 106 is deposited on the fin 52A, the isolation material 54, the film layer 104, and the spacer layer 102 (if present). The film layer 104 may deposit the film layer 106 along the sidewall and bottom surface of the recess 100. The film layer 106 may be deposited by any suitable process, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, plasma-assisted atomic layer deposition, atomic layer deposition, physical vapor deposition, or other similar methods. The film layer 106 can be deposited using a compliant process. Although a single-layer film layer 106 is shown, the film layer 106 may have a multi-layer structure. For example, in some embodiments, the film 106 may include up to ten layers of different materials. Each layer of the film 106 can be deposited using a process similar to the process described above. The thickness of each layer in the film 106 may range from about 3 Å to about 500 Å.

The film layer 106 may include a silicon-based dielectric material (for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxynitride, silicon carbide, silicon oxycarbide, silicon oxide, or other materials). Analogs); silicon-based semiconductor materials (for example, silicon germanium); metal oxides; metal nitrides or the like. In some embodiments where the film layer 106 includes metal oxide or metal nitride, the film layer 106 may include metal, for example, hafnium, tantalum, aluminum, chromium, nickel, iron, yttrium, copper, tin, tungsten, or the like . The material of each layer of the film layer 106 can be selected to provide etching selectivity in one or more subsequent processes. For example, the material of the film layer 106 can be selected so that it can be removed by etching to provide a dummy channel area with a thinner top/middle portion.

In FIG. 7, the film layer 108 is deposited on the film layer 106. The film layer 108 may be deposited along the sidewall and bottom surface of the recess 100 until the portion of the film layer 108 on the sidewall of the recess 100 is thick enough and joined together. Therefore, the film layer 108 can fill the remaining part of the groove 100, and a seam 108' can be formed in the film layer 108. The film layer 108 may be deposited by any suitable process, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, plasma-assisted atomic layer deposition, atomic layer deposition, physical vapor deposition, or other similar methods. The film layer 108 can be deposited using a compliant process. The thickness of the film layer 108 may be in the range of about 3 Å to about 500 Å. The film layer 108 may include a silicon-based dielectric material (for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxynitride, silicon carbide, silicon oxycarbide, silicon oxide, or other materials). Analogs); silicon-based semiconductor materials (for example, silicon germanium); metal oxides; metal nitrides or the like. In some embodiments where the film layer 108 includes metal oxide or metal nitride, the film layer 108 may include metal, for example, hafnium, tantalum, aluminum, chromium, nickel, iron, yttrium, copper, tin, tungsten, or the like .

The materials of the film layer 106 and the film layer 108 can be selected so that the film layer 106 can be selectively etched in the subsequent manufacturing process without the film layer 108 being etched significantly. In addition, the material of the film layer 108 can also be selected so that the film layer 108 is not significantly etched during the source/drain formation step of the fin-type field effect transistor. As will be described in more detail later, forming the source/drain regions may include etching the gate spacer layer to expose the fin 52A, and then etching the fin 52A. Exposing the fin 52A may also expose the film layer 108. Therefore, the material of the film layer 108 can be selected so that the film layer 108 will not be significantly etched during the etching process of the gate spacer and the fin 52'. For example, in an embodiment where the gate spacer includes nitride, the nitrogen concentration of the film layer 108 may be relatively low to provide etching selectivity during the gate spacer etching. In some embodiments, the nitrogen concentration of the film layer 108 may be less than 40 at.% (atomic percentage). The film layer 108 may be, for example, oxide or oxynitride. As another example, the film layer 108 may be a different material from the fin 52A to provide etching selectivity during fin patterning. For example, the fin 52A may include germanium. In other embodiments, the film layer 108 may include a high-k material to provide etching selectivity during gate spacer patterning and fin patterning.

In some embodiments, the material of the film layer 108 may have a higher chemical bond energy than the material of the film layer 104 and/or the spacer 102. As a result, it may be difficult to directly etch the film layer 108 and reduce the width of the film layer 108. Therefore, a film layer 106 having a lower chemical bond energy is formed on the film layer 108, and the film layer 106 is trimmed in a subsequent processing step. This trimming advantageously increases the space between the fins 52' to improve gap filling in subsequent process steps.

In FIG. 12, the film layer 106 and the film layer 108 are removed to remove the excess film layer 106 and the film layer 108 located above the fins 52A/52B. In some embodiments, a planarization process (for example, chemical mechanical polishing), an etch-back process, a combination of the above, or other similar methods may be used. The planarization process exposes the fin 52A and the insulating material 54 so that after the planarization process is completed, the top surface of the fin 52A, the top surface of the insulating material 54, the top surface of the film layer 106, and the top surface of the film layer 108 are aligned. flat.

Although the film layer 108 is only shown as a single layer, the film layer 108 may have a multi-layer structure. For example, in other embodiments, the film layer 108 may include a plurality of stacked film layers. In such an embodiment, each layer can be deposited by the method described above with respect to Figure 11, and by a method similar to that described above with respect to the recessed layer 104 (refer to Figure 8). Depression of each film layer. This process can be repeated until the required number of film layers for the film layer 108 are formed. In some embodiments, up to ten film layers can be deposited and etched back in the recess 100 above the film layer 106. 15G and 15H depict an embodiment in which the film layer 108 has multiple film layers.

In FIG. 13, the insulating material 54 is recessed to form a shallow trench isolation (STI) region 56. The insulating material 54 is recessed so that the upper part of the fin 52A protrudes from between adjacent shallow trench isolation regions 56. In addition, the top surface of the shallow trench isolation region 56 may have a flat surface, a convex surface, a concave surface (for example, a dish-shaped depression) as shown in the figure, or a combination thereof. The top surface of the shallow trench isolation region 56 may be formed flat, convex, and/or concave by appropriate etching. The shallow trench isolation region 56 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material 54 (for example, the insulating material 54 is etched at a faster rate than the material of the fin 52). Material). For example, it is possible to use, for example, oxide removal using dilute hydrofluoric acid. Recessing the insulating material 54 may use a process of selectively etching the insulating material 54 compared to the film layer 106/108 and/or the spacer layer 102.

The process described in FIGS. 2 to 13 is only an example of the fin 52a that can be formed. In some embodiments, the fins can be formed by an epitaxial growth process. For example, a dielectric layer may be formed on the top surface of the substrate 50, and a trench through the dielectric layer may be etched to expose the substrate 50 below. A homoepitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form a fin. In addition, in some embodiments, a heteroepitaxial structure may be used for the fin 52a. For example, the fin 52A in FIG. 13 can be recessed, and a material different from the fin 52A can be epitaxially grown on the recessed fin 52A. In such an embodiment, the fin 52A includes a recessed material and an epitaxial growth material disposed on the recessed material. In another embodiment, a dielectric layer may be formed on the top surface of the substrate 50, and a trench may be etched through the dielectric layer. A material different from that of the substrate 50 can be used to epitaxially grow the heteroepitaxial structure in the trench, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52A. In some embodiments of the epitaxial growth of the homoepitaxial structure or the heteroepitaxial structure, the epitaxially grown material can be doped in-situ during the growth process, so that the cloth before and after the in-situ doping can be omitted. Plant, although in-situ doping and implant doping can also be used together.

Furthermore, it may be advantageous to epitaxially grow a different material in the region 50N (for example, NMOS region) from the material in the region 50P (for example, PMOS region). Regardless of the type of device (for example, NMOS or PMOS), the epitaxial growth in the first circuit region (for example, static random access memory, SRAM) of the device 10 is different from the material in the second circuit region of the device 10 Material, this may also have advantages. In various embodiments, the upper portion of the fin 52A can be made of silicon germanium (Si _x Ge _1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V Group compound semiconductors, II-VI compound semiconductors or the like are formed. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, and arsenic. Indium aluminum arsenide (indium aluminum arsenide), gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide or other similar substances.

In addition, in FIG. 13, suitable well regions (not shown) may be formed in the fin 52A and/or the substrate 50. In some embodiments, a P-type well may be formed in the region 50N, and an N-type well may be formed in the region 50P. In some embodiments, a P-type well or an N-type well is formed in both the region 50N and the region 50P.

In embodiments with different well types, photoresist or other masks (not shown) may be used to implement different implantation steps for the area 50N and the area 50P. For example, a photoresist can be formed over the fin 52A and the shallow trench isolation region 56 in the region 50N. The photoresist is patterned to expose a region 50P of the substrate 50, for example, a PMOS region. The photoresist can be formed by using spin coating technology, and the photoresist can be patterned using acceptable photolithography technology. After the photoresist is patterned, n-type impurities are implanted in the region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted in the region 50N, for example, in the NMOS region. This n-type impurity may be phosphorus, arsenic, antimony or other like, and which implant concentration in this region is equal to or less than 10 ¹⁸ cm ^-3, for example, about 10 ¹⁸ cm to about 10 ¹⁶ cm ^{-3 -} Between ^3. After implantation, for example, the photoresist is removed by an acceptable ashing process.

After implanting the region 50P, a photoresist is formed over the fin 52A and the shallow trench isolation region 56 in the region 50P. The photoresist is patterned to expose a region 50N of the substrate 50, for example, an NMOS region. The photoresist can be formed by using spin coating technology, and the photoresist can be patterned using acceptable photolithography technology. After the photoresist is patterned, p-type impurities are implanted in the region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurities from being implanted in the region 50P, for example, in the PMOS region. The p-type impurity may be boron, boron fluoride, indium or the like, and its concentration in this area is equal to or less than 10 ¹⁸ cm ^-3 , for example, at about 10 ¹⁶ cm ^-3 And about 10 ¹⁸ cm ^-3 . After implantation, for example, the photoresist is removed by an acceptable ashing process.

After the implantation of the region 50N and the region 50P, annealing may be performed to repair the implantation damage and activate the implanted p-type and/or n-type impurities. In some embodiments, the growth material of the epitaxial fin can be doped in-situ during the growth, so that the implantation can be omitted, although in-situ doping and implantation doping can also be used together.

In FIG. 14, the film layer 106 is etched and the film layer 106 is at least partially removed from the sidewall of the film layer 108. The etching of the film layer 106 may include a selective process, which can selectively etch the film layer 106 without significantly etching the film layer 108, the spacer layer 102, or the film layer 104.

In some embodiments, the etching of the film layer 106 may include a plasma process, for example, plasma etching, remote control plasma process, radical etching, or other similar methods. The etching gas used during the plasma process can include chlorine, hydrogen bromide, perfluoromethane, trifluoromethane, difluoromethane, monofluoromethane, hexafluorobutadiene, boron trichloride, sulfur hexafluoride, hydrogen , Nitrogen trifluoride, a combination of the above or other similar substances. The plasma process may further include flowing passivation gas through the device 10 to adjust (for example, increase) the etching selectivity between the film layer 106 and other components of the device 10. Exemplary passivation gases may include nitrogen, oxygen, carbon dioxide, sulfur dioxide, carbon monoxide, silicon tetrachloride, combinations of the above, or the like. One or more carrier gases may also be used during the plasma process, for example, argon, helium, neon, a combination of the above, or the like. In addition, the plasma source power in the range of about 10 W to about 3000 W, the bias power in the range of about 0 W to about 3000 W, and the pressure of about 1 mTorr to about 800 mTorr can be used. The plasma process is performed under a mixing flow rate of about 10 sccm to about 5000 sccm or other similar conditions.

In some embodiments, the etching of the film layer 106 may include a wet etching process (sometimes referred to as wet cleaning). Exemplary etchants that can be used during the wet etching process can include hydrofluoric acid (HF), fluorine (F ₂ ), combinations of the above, or the like. The wet etching process may further include flowing auxiliary etching chemicals through the device 10 to adjust (for example, increase) the etching selectivity between the film layer 106 and other components of the device 10. Exemplary auxiliary etching chemicals may include sulfuric acid, hydrogen chloride, hydrogen bromide, ammonia, combinations of the above, or the like. Deionized water, alcohol, acetone, or the like can be used as a solvent for mixing etchant and/or auxiliary etching chemicals during the wet etching process.

The film layer 106 can shield the film layer 104 during etching, so the film layer 104 will not be etched unexpectedly. Etching the film layer 104 may cause harmful results. For example, greatly reducing the width of the film layer 104 may affect the structural stability of the dummy fin 52'. Therefore, in some embodiments, the film layer 106 is trimmed while shielding the film layer 104, so that the stability of the dummy fin 52' will not be significantly affected.

Therefore, dummy fins 52' are formed. The dummy fin 52' includes the spacer layer 102, the film layer 104, the remaining part of the film layer 106, and the film layer 108. As a result of etching the film layer 106, the middle portion of the dummy fin 52' (e.g., including the film layers 106 and 108) has a width D2. The width D2 may be smaller than the width D1 of the lower portion of the dummy fin 52' (e.g., including the spacer layer 102 and the film layer 104). The width D1 can be measured at the height position of the film layer 104, and the width D2 can be measured at the height position of the film layer 108. For example, the width D1 may be in the range of about 2 nm to about 1000 nm, and the width D2 may be in the range of about 2 nm to about 1000 nm. The widths D1 and D2 may depend on the position of the specific dummy fin 52'. For example, in the first region, the width D1 may be in the range of about 8 nm to about 14 nm, and the width D2 may be in the range of about 4 nm to about 10 nm. In the second region, the width D1 and the width D2 may be about 100 nm or more. By providing the width D2 smaller than the width D1 (for example, within the above range), the distance D3 between the fin 52A and the dummy fin 52' can be increased. For example, the space between the fin 52A and the dummy fin 52' can be enlarged, which can improve the process window used to fill the space between the fin 52A and the dummy fin 52' in the subsequent steps (for example , Dummy gate filling or metal gate filling). In addition, the base of the dummy fin 52' is not reduced, so that the structural stability of the dummy fin 52' can be improved, especially in the subsequent processing steps, the area of the dummy fin 52' in these processing steps May be exposed to one or more etchants. Therefore, manufacturing defects (for example, holes) can be reduced in the subsequent deposition process.

Figure 14 illustrates an exemplary configuration of the dummy fin 52'. In other embodiments, the dummy fin 52' may have a different configuration. For example, FIG. 15A shows a detailed view of the dummy fin 52' as shown in FIG. 14. 15B to 15H illustrate other embodiments of the fin 52', each of which can be provided in the structure of FIG. 14.

In FIG. 15A, the width of the top surface of the film layer 106 (for example, the surface adjacent to the film layer 108) is smaller than the width of the bottom surface of the film layer 106 (for example, the surface adjacent to the film layer 104). In other embodiments, as shown in FIG. 15B, the top surface of the film layer 106 may be wider than the bottom surface of the film layer 106. In other embodiments, as shown in FIG. 15C, the width of the middle portion of the film layer 106 may be smaller than the width of the top surface and the width of the bottom surface of the film layer 106, and the film layer 106 has concave sidewalls. In such an embodiment, the width of the top surface and the bottom surface of the film layer 106 may be the same or different.

In addition, in FIG. 15A, the film layer 106 is shown as being completely removed from the sidewall of the film layer 108. In other embodiments, a part of the film layer 106 may remain on the sidewall of the film layer 108. For example, as shown in FIG. 15D, the film layer 106 remains on the sidewall of the film layer 108 and extends to the top surface of the film layer 108. As another example, as shown in FIG. 15E, the film layer 106 may partially extend up to the sidewall of the film layer 108, so that the film layer 108 extends higher than the film layer 106. In the embodiments of FIGS. 15D and 15E, the maximum thickness T1 of the film layer 106 on the sidewall of the film layer 108 may be smaller than the thickness T2 of the film layer 106 on the bottom surface of the film layer 108. In some embodiments, the thickness T2 of the film layer 106 on the bottom surface of the film layer 108 may be in the range of about 2 Å to about 100 Å. In addition, the total height T3 of the film layer 106 may be in the range of about 3 Å to about 1000 Å. The height T3 can be measured from the bottommost surface of the film layer 106 to the topmost point of the film layer 106.

FIG. 15F illustrates an embodiment in which an optional spacer layer is omitted. In such an embodiment, the film layer 104 may be in direct contact with the shallow trench isolation region 56 and the rest of the substrate 50/fin 52A (refer to FIG. 14). Although FIG. 15F illustrates the film layer 106 having the same configuration as that of FIG. 15A, it should be understood that any configuration of the film layer 106 may be used instead (for example, as shown in FIGS. 15B to 15E) ).

FIG. 15G and FIG. 15H illustrate an embodiment in which the film layer 108 has a multilayer structure. In FIG. 15G, the film layer 108 includes a film layer 108A and a film layer 108B located on the top surface of the film layer 108A. In Figure 15H, the film layer 108 includes a film layer 108A, a film layer 108B located on the top surface of the film layer 108A, and a film layer 108C located on the top surface of the film layer 108B. As described above, each of the film layer 108A, the film layer 108B, and the film layer 108C may be deposited and recessed as needed. Each of the film layer 108A, the film layer 108B, and the film layer 108C may have a different material composition from the adjacent film layer. In addition, as a result of the etch-back process to recess one or more film layers (for example, the film layers 108A/108B), in some embodiments, the top surface of the etched film layers may have a V shape. Although FIGS. 15G and 15H depict the film layer 106 having the same configuration as that of FIG. 15A, it should be understood that any configuration mode of the film layer 106 may be used instead (for example, as shown in FIGS. 15B to 15E). Pictured). In addition, in FIGS. 15G and 15H, the spacer layer 102 is an optional film layer, and can be excluded as described above with respect to FIG. 15F.

In the embodiment of Figure 14, the shallow trench isolation region 56 is shown as having a lower top surface than the film layer 106/108. For example, the spacer layer 102, the film layer 104, the film layer 106, and the film layer 108 each extend to a position higher than the shallow trench isolation region 56. In other embodiments, the shallow trench isolation region 56 may be arranged at different height positions. For example, FIG. 16A illustrates an embodiment in which the top surface of the shallow trench isolation region 56 is substantially flush with the bottom surface of the film layer 106 (for example, within a manufacturing tolerance), and is The top surface of the spacer layer 102 and the top surface of the film layer 104 are substantially flush. FIG. 16B illustrates an embodiment in which the top surface of the shallow trench isolation region 56 is higher than the bottom surface of the film layer 106, the top surface of the spacer layer 102, and the top surface of the film layer 104.

In Figure 17, a dummy dielectric layer 60 is formed on the fin 52A and the dummy fin 52'. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination of the above, or the like, and can be deposited or thermally grown by an acceptable technique.

A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 may be deposited on the dummy dielectric layer 60 and then planarized, for example, by chemical mechanical polishing. The mask layer 64 may be deposited on the dummy gate layer 62. The dummy gate layer 62 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polysilicon, poly-crystalline silicon-germanium, metal nitride, metal silicide, metal oxide, and metal. . The dummy gate layer 62 may be deposited by physical vapor deposition, chemical vapor deposition, sputter deposition, or other techniques known in the art and used to deposit selected materials. The dummy gate layer 62 may be made of other materials that have high etching selectivity to the etching of the isolation region.

By removing a part of the film layer 106 from the sidewall of the dummy fin 52', the space between the fin 52A and the dummy fin 52' can be increased. In this way, the dummy gate layer 62 can be deposited on the periphery of the fin 52A/dummy fin 52' and in the space between the two with fewer defects (for example, fewer holes).

The mask layer 64 may include, for example, silicon nitride, silicon oxynitride, or the like. In this embodiment, a single dummy gate layer 62 and a single mask layer 64 are formed across the region 50N and the region 50P. It should be noted that the dummy dielectric layer 60 is shown as covering only the fin 52A, which is for illustrative purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited such that the dummy dielectric layer 60 covers the shallow trench isolation region 56 and extends between the dummy gate layer 62 and the shallow trench isolation region 56.

In FIGS. 18A and 18B, the mask layer 64 (refer to FIG. 17) can be patterned using acceptable photolithography and etching techniques to form the mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching technique to form the dummy gate 72. The dummy gate 72 covers the corresponding channel area 58 of the fin 52A. The pattern of the mask 74 may be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gate 72 may also have a length direction, which is substantially perpendicular to the length direction of the corresponding epitaxial fin 52A.

In addition, in FIGS. 18A and 18B, gate seal spacers may be formed on the exposed surfaces of the dummy gate 72, the mask 74, and/or the fin 52A/dummy fin 52'. ) 80. The gate sealing spacer 80 can be formed by thermal oxidation or deposition and subsequent anisotropic etching. The gate sealing spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

After the gate sealing spacer 80 is formed, implantation for lightly doped source/drain (LDD) regions (not explicitly shown) can be performed. In embodiments with different device types, similar to the implantation discussed in Figure 13 above, a mask, such as a photoresist, can be formed over the area 50N while exposing the area 50P, and the appropriate type (e.g., , P-type) impurities are implanted in the exposed fin 52A located in the region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, may be formed over the area 50P while exposing the area 50N, and an appropriate type (for example, n-type) impurities may be implanted into the exposed fin 52 located in the area 50N. The mask can then be removed. The aforementioned n-type impurity may be any n-type impurity previously discussed, and the aforementioned p-type impurity may be any p-type impurity previously discussed. The lightly doped source/drain regions may have an impurity concentration between ^{about 10 15} cm ^-3 and about 10 ¹⁹ cm ^-3. Annealing can be performed to repair implant damage and activate the implanted impurities.

In FIGS. 19A and 19B, gate spacers 86 are formed on the gate sealing spacers 80 along the side walls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then etching the insulating material anisotropically. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination of the above, or other similar materials.

It should be noted that the above disclosure generally describes the process of forming spacers and lightly doped source/drain regions. Other processes and sequences can be used. For example, fewer spacers or additional spacers can be used, and a different sequence of steps can be used (for example, the gate seal spacer 80 can be not etched before forming the gate spacer 86, resulting in an "L shape" Gate seal spacers), spacers can be formed and removed, and/or other similar changes. In addition, different structures and steps can be used to form n-type and p-type devices. For example, the lightly doped source/drain regions for n-type devices may be formed before the gate is formed, and the lightly doped source/drain regions for p-type devices may be formed after the gate sealing spacer 80 is formed. /Drain region.

In FIGS. 20A and 20B, an epitaxial source/drain region 82 is formed in the fin 52A. The source/drain regions 82 can apply stresses in the corresponding channel regions 58 to improve performance. An epitaxial source/drain region 82 is formed in the fin 52A, so that each dummy gate 72 is respectively disposed between an adjacent pair of epitaxial source/drain regions 82. In some embodiments, the epitaxial source/drain region 82 may extend into the fin 52A, and may also penetrate the fin 52A. In some embodiments, the gate spacer 86 is used to separate the epitaxial source/drain region 82 and the dummy gate 72 by an appropriate lateral distance, so that the epitaxial source/drain region 82 will not cause subsequent formation The gate of the fin-type field effect transistor is short-circuited.

The epitaxial source/drain region 82 in the region 50N (for example, NMOS region) can be formed by the following steps, by shielding the region 50P (for example, the PMOS region) and etching the fin 52A in the region 50N The source/drain regions are notched in the fin 52A. Then, the epitaxial source/drain region 82 located in the region 50N is epitaxially grown in the notch. The epitaxial source/drain region 82 may include any acceptable material, for example, it may be suitable for n-type fin-type field effect transistors. For example, if the fin 52A is silicon, the epitaxial source/drain region 82 located in the region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, doped phosphorus Silicon carbide, silicon phosphide or other similar substances. The epitaxial source/drain region 82 located in the region 50N may have a surface protruding from the corresponding surface of the fin 52A and may have facets.

The epitaxial source/drain region 82 in the region 50P (for example, PMOS region) can be formed by the following steps, by shielding the region 50N (for example, the NMOS region) and etching the fin 52A in the region 50P The source/drain regions are notched in the fin 52A. Then, the epitaxial source/drain region 82 located in the region 50P is epitaxially grown in the notch. The epitaxial source/drain region 82 may include any acceptable material, for example, it may be suitable for a p-type fin field effect transistor. For example, if the fin 52A is silicon, the epitaxial source/drain region 82 in the region 50P may include a material that applies a compressive strain in the channel region 58, for example, silicon germanium, boron-doped silicon germanium , Germanium, germanium tin (germanium tin) or other similar substances. The epitaxial source/drain region 82 located in the region 50P may have a surface protruding from the corresponding surface of the fin 52A and may have facets.

Dopants can be used to implant epitaxial source/drain regions 82 and/or fins 52A to form source/drain regions, similar to the lightly doped source/drain regions discussed above The process is then annealed. The impurity concentration of the source/drain region may be between about 10 ¹⁹ cm ^-3 and about 10 ²¹ cm ^-3 . The n-type and/or p-type impurities used in the source/drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source/drain region 82 may be doped in situ during growth.

As a result of the epitaxial process used to form the epitaxial source/drain region 82 in the region 50N and the region 50P, the upper surface of the epitaxial source/drain region has facets that extend laterally outward Exceed the side walls of the fin 52A. The gate spacer 86 is formed to cover a portion of the sidewall of the fin 52A, which extends above the shallow trench isolation region 56 to prevent epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacer 86 can be adjusted to remove the spacer material and allow the epitaxial growth region to extend to the surface of the shallow trench isolation region 56.

In various embodiments, as shown in FIG. 20C, after the epitaxial process is completed, adjacent source/drain regions 82 remain separated. For example, the source/drain region 82 can be grown to physically contact the dummy fin 52', which physically separates adjacent source/drain regions 82 from each other. Therefore, it is possible to prevent the adjacent epitaxial source/drain regions 82 from merging and unexpected short circuits. As described above, the material of the film layer 108 can be selected so that the film layer 108 is not significantly etched during the formation of the source/drain regions.

For example, the source/drain region 82 may be in contact with the film layer 108 of the dummy fin 52'. In some embodiments, the middle portion of the dummy fin 52' having the width D2 is the part of the dummy fin 52' that is in contact with the epitaxial source/drain region 82. The width D2 may be smaller than the width D1 of the lower portion of the dummy fin 52'. The width D1 can be measured at the height position of the film layer 104, and the width D2 can be measured at the height position of the film layer 108.

In FIGS. 21A and 21B, a first interlayer dielectric (ILD) 88 is deposited on the structure shown in FIGS. 20A and 20B. The first interlayer dielectric layer 88 may be formed of a dielectric material, and may be deposited by any suitable method, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, or flow chemical vapor deposition. The dielectric material can include phospho-silicate glass (PSG), boro-silicate glass (boro-silicate glass, BSG), and boron-doped phospho-silicate glass (boron-doped phospho-silicate glass). , BPSG), undoped silicate glass (USG) or other similar materials. Other insulating materials formed by any acceptable method can be used. In some embodiments, the contact etch stop layer 87 is disposed between the first interlayer dielectric 88 and the epitaxial source/drain region 82, the mask 74, and the gate spacer 86. The contact etch stop layer 87 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, with an etch rate different from the etch rate of the material of the first interlayer dielectric layer 88 described above.

In FIGS. 22A and 22B, a planarization process (for example, chemical mechanical polishing) may be performed to make the top surface of the first interlayer dielectric layer 88 and the top surface of the dummy gate 72 or the mask 74 The top surface is flush. The planarization process may also remove the mask 74 on the dummy gate 72, and a part of the gate sealing spacer 80 and a part of the gate spacer 86 along the sidewall of the mask 74. After the planarization process, the top surface of the dummy gate 72, the top surface of the gate sealing spacer 80, the top surface of the gate spacer 86 and the top surface of the first interlayer dielectric layer 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first interlayer dielectric layer 88. In some embodiments, the mask 74 may be retained. In this case, the planarization process makes the top surface of the first interlayer dielectric layer 88 flush with the top surface of the mask 74.

In FIGS. 23A and 23B, the dielectric region 78 is formed to extend through the dummy gate 72 to the dummy fin 52'. The dummy gate 72 can be etched to form the dielectric region 78, for example, by using a wet and/or dry etching process. This etching process can expose the dummy fin 52'. After that, a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, can be deposited in the recess. A planarization process may be performed to remove excess dielectric material from above the dummy gate 72. The dielectric region 78 is combined with the dummy fin 52', and the dummy gate 72 is divided into different regions (e.g., region 72A and region 72B). For example, different regions may correspond to the positions of different transistor devices. Therefore, the dielectric region 78 and the dummy fin 52' can provide isolation between adjacent fin-type field effect transistors.

In FIGS. 24A and 24B, the dummy gate 72 and the mask 74 (if present) are removed in one or more etching steps to form the notch 90. The portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, while the dummy dielectric layer 60 is retained and exposed by the notch 90. In some embodiments, the dummy dielectric layer 60 is removed from the notch 90 located in the first area of the die (e.g., core logic area), and remains in the second area of the die (e.g., input /Output area) in the notch 90. In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas. The reactive gas selectively etches the dummy gate 72 without etching the first interlayer dielectric layer 88 or the gate spacer 86. Each notch 90 exposes and/or covers the channel area 58 of the respective fin 52. Each channel region 58 is disposed between an adjacent pair of epitaxial source/drain regions 82. During removal, when the dummy gate 72 is etched, the dummy dielectric layer 60 may be used as an etch stop layer. After the dummy gate 72 is removed, the dummy dielectric layer 60 can be removed as needed.

In FIGS. 25A and 25B, a gate dielectric layer 92 and a gate electrode 94 are formed as replacement gates. FIG. 25C shows a detailed cross-sectional view of area 89 in FIG. 25B. The gate dielectric layer 92 is compliantly deposited in the recess 90, for example, on the top surface and sidewalls of the fin 52A, on the sidewalls of the dummy fin 52', on the sidewalls of the dielectric region 78, and on The gate seal spacer 80/gate spacer 86 is on the side wall. The gate dielectric layer 92 may also be formed on the top surface of the first interlayer dielectric layer 88. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or the above-mentioned multilayer structure. In some embodiments, the gate dielectric layer 92 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0, and may include the following metals: Oxides or silicates. These metals include hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead and combinations of the above. The formation method of the gate dielectric layer 92 may include molecular-beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, and other similar methods. In the embodiment where a portion of the dummy dielectric layer 60 remains in the recess 90, the gate dielectric layer 92 includes the material of the dummy dielectric layer 60 (for example, silicon dioxide).

A plurality of gate electrodes 94 are respectively deposited on the plurality of gate dielectric layers 92 and fill the rest of the recess 90. By removing a part of the film layer 106 from the sidewall of the dummy fin 52', the space between the fin 52A and the dummy fin 52' can be increased. In this way, the gate electrode 94 can be deposited in the space around the fin 52A/dummy fin 52' and in the space between the two with fewer defects (for example, fewer holes).

The gate electrode 94 may include a metal-containing material, for example, titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination of the foregoing, or the foregoing multilayer structure. For example, although a single-layer gate electrode 94 is shown in FIG. 25B, the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filling materials 94C, as shown in FIG. 25C As shown. After filling the recess 90, a planarization process (for example, chemical mechanical polishing) can be performed to remove the excess part of the gate dielectric layer 92 and the excess part of the material of the gate electrode 94, which are located in the first layer Above the top surface of the inter-dielectric layer 88. The rest of the materials of the gate electrode 94 and the gate dielectric layer 92 thus form a replacement gate for the resulting fin-type field effect transistor. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as a "gate stack". The gate and gate stack may extend along the sidewall of the channel region 58 of the fin 52A. When adjacent gate stacks correspond to different fin-type field effect transistors, the dielectric region 78 and the dummy fin 52' stack adjacent gate electrodes (for example, gate stack 92A/94A and gate stack 92B). /94B) Isolation.

The formation of the gate dielectric layer 92 in the region 50N and the region 50P can occur simultaneously, so that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, so that each The gate electrode 94 in one area is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed by different processes, so that the gate dielectric layer 92 can be a different material, and/or the gate electrode 94 in each region It can be formed by different processes, so that the gate electrode 94 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate areas.

In FIGS. 26A and 26B, the gate stack (including the gate dielectric layer 92 and the corresponding upper gate electrode 94) is recessed, so that the notch is formed directly above the gate stack and is located at the second spacer 86 between the two opposing parts. The etching process may be selective so that the dielectric region 78 is not significantly etched. A gate mask 96 including one or more layers of dielectric material (for example, silicon nitride, silicon oxynitride, or the like) is filled in this recess, and then a planarization process is performed to remove the interlayer between the first layer The excess portion of the dielectric material extending above the electrical layer 88. The subsequently formed gate contact 110 (please refer to FIGS. 27A and 27B) passes through the gate mask 96 to contact the top surface of the recessed gate electrode 94. The dielectric region 78 may extend through the gate mask 96.

In FIGS. 27A and 27B, the second interlayer dielectric layer 114 is deposited on the first interlayer dielectric layer 88. In some embodiments, the second interlayer dielectric layer 114 is a flowable film formed by a flow-type chemical vapor deposition method. In some embodiments, the second interlayer dielectric layer 114 is formed of a dielectric material, for example, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate Glass or the like, and the second interlayer dielectric layer 114 can be deposited by any suitable method, for example, chemical vapor deposition and plasma-assisted chemical vapor deposition.

According to some embodiments, FIG. 27A and FIG. 27B also show that the gate contact 110 and the source/drain contact 112 are formed through the second interlayer dielectric layer 114 and the first interlayer dielectric layer. 88. An opening for the source/drain contact 112 is formed through the first interlayer dielectric layer 88 and the second interlayer dielectric layer 114, and an opening for the gate contact 110 is formed through the second interlayer dielectric Layer 114 and gate mask 96. Acceptable photolithography and etching techniques can be used to form the openings. A liner layer (for example, a diffusion barrier layer, an adhesive layer, or the like) and a conductive material are formed in the opening. The liner layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process (for example, chemical mechanical polishing) may be performed to remove excess material from the surface of the second interlayer dielectric layer 114. The remaining liner and conductive materials form source/drain contacts 112 and gate contacts 110 in the openings. An annealing process may be performed to form a silicide at the interface between the epitaxial source/drain region 82 and the source/drain contact 112. The source/drain contact 112 is physically and electrically coupled to the epitaxial source/drain region 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 94. The source/drain contact 112 and the gate contact 110 may be formed in different processes, or may be formed in the same process. Although it is shown to be formed in the same cross-section, it should be understood that each of the source/drain contact 112 and the gate contact 110 may be formed in a different cross-section, so as to avoid short circuits of the contacts.

The above embodiments describe the formation of the dielectric region 78 before the gate stack 92/94. In other embodiments, the gate stack (for example, including the gate dielectric layer 92 and the gate electrode 94) may be formed before the dielectric region 78 is formed. After that, the gate stack 92/94 can be etched to expose the dummy fin 52', and a dielectric material can be deposited to form a dielectric region 78. The resulting structure is shown in Figure 28A and Figure 28B.

Figures 29 to 37C are schematic cross-sectional views of an intermediate stage of manufacturing a device 20 with dummy fins 52' according to another embodiment. In FIGS. 29 to 37C, the same reference numerals denote the same components, and these components are formed using the same manufacturing process as the components described in FIGS. 2 to 28B above. In FIG. 29, the fin 52 is formed to extend from the substrate 50. The hard mask 53 is used to pattern the fin 52 and may remain on the fin 52.

In FIG. 30, the insulating material 54 is deposited on the sidewalls of the fin 52 and along the sidewalls of the fin 52. The insulating material 54 can be deposited using a compliant process that only partially fills the space between the fins 52. During the deposition process, an opening 100 is defined between the fins 52 and above the insulating material 54. Afterwards, material may be filled in the opening 100 to form a dummy fin 52'.

In FIG. 31, the spacer layer 102 and the film layer 104 as needed are deposited in the opening. The deposition of the spacer layer 102 and the film layer 104 can be performed using a process similar to that described above with respect to FIGS. 6 and 7.

In FIG. 32, the spacer layer 102 and the thin film layer 104 are recessed in sequence as needed. The spacer layer 102 and the film layer 104 can be recessed using a similar process as described above with respect to FIGS. 8 and 9.

In FIG. 33, the film layer 106 and the film layer 108 are deposited in the opening 100. The film layer 106 and the film layer 108 may be deposited on the spacer layer 102 and the film layer 104. The film layer 106 and the film layer 108 can be deposited using a process similar to that described above with respect to FIGS. 10 and 11. The film layer 108 may be a single-layer structure or a multi-layer structure.

In FIG. 34, a removal process is performed on the film layer 106, the film layer 108, the insulating material 54 and the hard mask 53 (if present) to remove the excess material above the fin 52. In some embodiments, a planarization process (for example, chemical mechanical polishing), an etch-back process, a combination of the above, or other similar methods may be used. The planarization process exposes the fin 52 and the insulating material 54 so that after the planarization process is completed, the top surface of the fin 52, the top surface of the insulating material 54, the top surface of the film layer 106, and the top surface of the film layer 108 are aligned. flat.

In FIG. 35, the insulating material 54 is etched back to expose the sidewalls of the fin 52 and define a shallow trench isolation region 56. A process similar to that described above with respect to FIG. 13 can be used to perform the etch-back of the insulating material 54. As a result of the etch-back, the top surface of the shallow trench isolation region 56 may be higher than the top surface of the film layer 104, above the top surface of the film layer 104 (for example, refer to Figure 36B), or substantially with the film layer 104 The top surface of the layer 104 is flush (see, for example, Figure 36C).

In FIGS. 36A to 36B, the film layer 106 is etched and the film layer 106 is at least partially removed from the sidewall of the film layer 108. FIG. 36A depicts an embodiment in which the top surface of the shallow trench isolation region 56 is lower than the top surface of the film layer 104; FIG. 36B depicts an embodiment in which the top surface of the shallow trench isolation region 56 is higher than the top surface of the film layer 104 36B depicts an embodiment in which the top surface of the shallow trench isolation region 56 is substantially flush with the top surface of the film layer 104. The film layer 106 can be etched using a process similar to that described above in relation to FIG. 13. Therefore, dummy fins 52' are formed. The dummy fin 52' may be embedded in the shallow trench isolation region 56. For example, the shallow trench isolation region 56 may extend below and cover the bottom surface of the dummy fin 52'.

The middle portion of the dummy fin 52' has a width D2, and the width D2 may be smaller than the width D1 of the bottom portion of the dummy fin 52'. By reducing the width D2 of the dummy fin 52', the space between the dummy fin 52' and the fin 52 can be increased. Therefore, the gate material can be formed around the fin 52 and the dummy fin 52' with an enlarged process window, and manufacturing defects can be reduced.

Although FIGS. 36A to 36C show the dummy fins 52' as having a specific configuration, other embodiments may consider different configurations of the dummy fins 52' in the device 20. For example, any configuration similar to that described above with respect to FIGS. 15A to 15H can be integrated into the device 20.

The device can be subjected to subsequent processing to form a fin-type field effect transistor. For example, any process similar to that described above with respect to FIGS. 16A to 28B can be performed to form source/drain regions 82 in the fins 52 and along the fins 52 and the dummy fins. The sidewall of the sheet 52' forms a gate stack on the sidewalls of the fin 52 and the dummy fin 52'. The dummy fin 52' may physically separate adjacent source/drain regions 82, and the dielectric region 78 may extend through the gate stack to reach the dummy fin 52'. The resulting structure is shown in FIGS. 37A to 37C.

The fin-type field-effect transistor embodiments disclosed herein can also be applied to nano-structured devices, for example, nano-structures (for example, nano-chips, nano-wires, fully wound gates, or other similar) field-effect transistors. Crystal. In the embodiment of nanostructure field effect transistors (NSFET), the fins are formed by patterning a stacked structure of alternately arranged film layers of channel layers and sacrificial layers. The dummy gate stack and epitaxial source/drain regions are formed in a similar manner to the above. After the dummy gate stack is removed, the sacrificial layer can be partially removed or completely removed in the channel area. The replacement gate structure is formed in a similar manner as described above, and the replacement gate structure will partially or completely surround the channel layer in the channel region of the nanostructure field effect transistor device. The interlayer dielectric layer and the contacts connected to the gate structure and the source/drain are formed in a similar manner as described above. The nanostructured device can be formed by the method disclosed in US Patent Application Publication 2016/0365414, the entire content of which is incorporated herein by reference.

In various embodiments, dummy fins may be used to separate the metal gates of adjacent transistors. The dummy fins can also help isolate adjacent source/drain regions by preventing unexpected source/drain merging during the epitaxial growth process, for example. Various embodiments include forming the first film layer on the sidewall and bottom surface of the second film layer. Then the first film layer is etched, and the first film layer is at least partially removed from the sidewall of the second film layer to reduce the width of the resulting dummy fin. Therefore, the cross-sectional profile of the dummy fin can be improved. For example, the middle portion of the dummy fin may be narrower (for example, having a smaller critical dimension) than the bottom portion of the dummy fin. In this way, the gap between the dummy fin and the channel region can be increased, and the process window for gap filling of the gate stack can be increased.

In some embodiments, a semiconductor device is provided, including: a first source/drain region is located on a semiconductor substrate; a dummy fin is adjacent to the first source/drain region, and the dummy fin It includes: a first part includes a first film layer; and a second part is located on the first part, a width of the second part is smaller than the width of the first part, wherein the second part includes: a second film layer; and a third The film layer is located between the first film layer and the second film layer, and the third film layer is made of a material different from the first film layer and the second film layer; and a pole stack along the above The side walls of the dummy fins are provided. In some embodiments, the third film layer extends along the sidewall of the second film layer. In some embodiments, the above-mentioned third film layer extends to the topmost surface of the above-mentioned second film layer. In some embodiments, the chemical bond energy of the material of the third film layer is less than the chemical bond energy of the material of the second film layer. In some embodiments, the first source/drain region is in contact with the second film layer. In some embodiments, the semiconductor device further includes a second source/drain region located on a side of the dummy fin opposite to the first source/drain region, wherein the second source/drain region The pole region is in contact with the above-mentioned second film layer. In some embodiments, the second part further includes a fourth film layer located on the second film layer, and the fourth film layer is made of a different material from the second film layer. In some embodiments, the semiconductor device further includes a dielectric region located on the dummy fin and in contact with the dummy fin, wherein the gate stack extends along the sidewall of the dielectric region. In some embodiments, the first surface of the third film layer adjacent to the first film layer is narrower than the second surface of the third film layer adjacent to the second film layer. In some embodiments, the first surface of the third film layer adjacent to the first film layer is wider than the second surface of the third film layer adjacent to the second film layer. In some embodiments, the third film layer has concave sidewalls.

In some embodiments, a semiconductor device is provided, including: a first transistor located on a top surface of a semiconductor substrate, the first transistor includes: a first channel region; and a first gate stack is located in the first channel region The second transistor is located on the top surface of the semiconductor substrate, and the second transistor includes: a second channel region; and a second gate stack Located on the side wall of the second channel region and arranged along the side wall of the second channel region; and dummy fins that physically isolate the first gate stack from the second gate stack, wherein The dummy fin includes: a first film layer; and a second film layer located on the first film layer, wherein the width of the dummy fin measured at the height of the second film layer is smaller than that of the The width of the dummy fin measured at the height position of the first film layer. In some embodiments, the semiconductor structure further includes a spacer layer, which is disposed along the sidewall and bottom surface of the first film layer. In some embodiments, the semiconductor structure further includes a third film layer located between the first film layer and the second film layer. In some embodiments, the above-mentioned dummy fins are embedded in the isolation region. In some embodiments, the dummy fin is in contact with the semiconductor substrate.

In some embodiments, a method for forming a semiconductor device is provided, including: defining an opening between a first semiconductor fin and a second semiconductor fin; forming a dummy fin between the first semiconductor fin and the second semiconductor fin Between the fins, forming the dummy fin includes: depositing a first film layer in the opening; recessing the first film layer in the opening; depositing a second film layer on the first film layer In the above-mentioned opening; depositing a third film layer in the above-mentioned opening above the second film layer, the second film layer being disposed on the sidewall and bottom surface of the third film layer; and etching the second film layer , To at least partially remove the second film layer from the sidewall of the third film layer; and along the sidewall and top surface of the first semiconductor fin, the sidewall and top surface of the second semiconductor fin, and The sidewalls and top surfaces of the dummy fins form gate structures. In some embodiments, the method for forming the semiconductor device further includes depositing a spacer layer along the sidewall and bottom surface of the opening before depositing the first film layer, wherein depositing the first film layer includes depositing the first film layer. Layer on the above-mentioned spacer layer. In some embodiments, forming the dummy fin further includes: recessing the third film layer below the top surface of the second film layer; and depositing a fourth film layer above the third film layer Among the above-mentioned openings, the above-mentioned second film layer is disposed on the side wall of the above-mentioned fourth film layer. In some embodiments, etching the second film layer includes a selective etching process, wherein the selective etching process etches the second film layer at a faster rate than the third film layer.

The foregoing text summarizes the components of many embodiments, so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on the embodiments of the present invention, so as to achieve the same purpose and/or achieve the same purpose as the embodiments described herein. The same advantages. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Without departing from the spirit and scope of the present invention, various changes, substitutions or modifications can be made to the present invention.

Although the present invention has been disclosed in several preferred embodiments as above, it is not intended to limit the present invention. Anyone with ordinary knowledge in the art can make any changes without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

10: device 20: device 50: substrate 50N: area 50P: area 51: Divider 52: Fins 52’: Dummy fins (dummy channel area) 52A: Fins 52B: Fins 53: Hard cover 54: Insulating material (isolating material) 56: Isolation area (shallow trench isolation area) 58: Channel area 60: Dummy dielectric layer 62: dummy gate layer 64: mask layer 72: Dummy Gate 72A: area 72B: area 74: Curtain 78: Dielectric area 80: Gate seal spacer 82: source/drain region 86: Gate spacer 87: contact etch stop layer 88: Dielectric layer (first interlayer dielectric layer) 89: area 90: Notch 92: gate dielectric layer 92A/94A: Gate stack 92B/94B: Gate stack 94: gate electrode 94A: Lining 94B: Work function adjustment layer 94C: Filling material 96: Gate Cover 100: opening 102: Spacer layer 104: Membrane 104’: Seam 106: Membrane 108: Membrane 108’: Seam 108A: Film layer 108B: Membrane 108C: Film layer 110: Gate contact 112: source/drain contacts 114: second interlayer dielectric layer D1: width D2: width D3: width T1: thickness T2: thickness T3: total height

Complete the disclosure based on the following detailed description in conjunction with the attached drawings. It should be noted that, according to the general operation of this industry, the diagrams are not necessarily drawn according to the ratio. In fact, it is possible to arbitrarily enlarge or reduce the size of the component to make a clear description. FIG. 1 is a three-dimensional view of an exemplary fin-type field effect transistor according to some embodiments. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14 Figure, Figure 15A, Figure 15B, Figure 15C, Figure 15D, Figure 15E, Figure 15F, Figure 15G, Figure 15H, Figure 16A, Figure 16B, Figure 17, Figure 18A, Figure 18B, Figure 19A, Figure 19B, Figure 20A, Figure 20B, Figure 20C, Figure 21A, Figure 21B, Figure 22A, Figure 22B, Figure 23A, Figure 23B, Figure 24A Figures, 24B, 25A, 25B, 25C, 26A, 26B, 27A, 27B, 28A, and 28B are based on some embodiments of manufacturing fin fields Schematic diagram of the cross-section of the intermediate stage of the effect transistor. Figures 29, 30, 31, 32, 33, 34, 35, 36A, 36B, 36C, 37A, 37B, and 37C The figure is a schematic cross-sectional view of an intermediate stage of manufacturing a fin-type field effect transistor according to some embodiments.

10: device

50: substrate

52A: Fins

52’: Dummy fins

56: Isolation area (shallow trench isolation area)

102: Spacer layer

104: Membrane

106: Membrane

108: Membrane

D1: width

D2: width

D3: width

Claims (20)

A semiconductor device including: A first source/drain region located on a semiconductor substrate; A dummy fin adjacent to the first source/drain region, and the dummy fin includes: A first part, including a first film layer; and A second part is located on the first part, a width of the second part is smaller than a width of the first part, wherein the second part includes: A second film layer; and A third film layer located between the first film layer and the second film layer, the third film layer being made of a material different from the first film layer and the second film layer; and A gate stack is arranged along the sidewall of the dummy fin. The semiconductor device according to claim 1, wherein the third film layer extends along the sidewall of the second film layer. The semiconductor device according to claim 1, wherein the third film layer extends to the topmost surface of the second film layer. The semiconductor device according to claim 1, wherein a chemical bond energy of the material of the third film layer is less than a chemical bond energy of a material of the second film layer. The semiconductor device according to claim 1, wherein the first source/drain region is in contact with the second film layer. The semiconductor device according to claim 1, further comprising a second source/drain region located on a side of the dummy fin opposite to the first source/drain region, wherein the second source The pole/drain region contacts the second film layer. The semiconductor device according to claim 1, wherein the second part further includes a fourth film layer located on the second film layer, and the fourth film layer is made of a material different from the second film layer production. The semiconductor device according to claim 1, further comprising a dielectric region located on the dummy fin and in contact with the dummy fin, wherein the gate stack extends along the sidewall of the dielectric region. The semiconductor device according to claim 1, wherein a first surface of the third film layer adjacent to the first film layer is narrower than a second surface of the third film layer adjacent to the second film layer. The semiconductor device according to claim 1, wherein a first surface of the third film layer adjacent to the first film layer is wider than a second surface of the third film layer adjacent to the second film layer. The semiconductor device according to claim 1, wherein the third film layer has concave sidewalls. A semiconductor device including: A first transistor is located on a top surface of a semiconductor substrate, and the first transistor includes: A first passage area; and A first gate stack located on the sidewalls of the first channel region and arranged along the sidewalls of the first channel region; A second transistor located at the top surface of the semiconductor substrate, the second transistor including: A second passage area; and A second gate stack located on the sidewalls of the second channel region and arranged along the sidewalls of the second channel region; and A dummy fin physically isolates the first gate stack from the second gate stack, wherein the dummy fin includes: A first film layer; and A second film layer is located on the first film layer, wherein a width of the dummy fin measured at a height position of the second film layer is smaller than that measured at a height position of the first film layer A measured width of the dummy fin. The semiconductor structure according to claim 12 further includes a spacer layer disposed along the sidewall and a bottom surface of the first film layer. The semiconductor structure according to claim 12, further comprising a third film layer located between the first film layer and the second film layer. The semiconductor structure according to claim 12, wherein the dummy fin is embedded in an isolation region. The semiconductor structure according to claim 12, wherein the dummy fin contacts the semiconductor substrate. A method for forming a semiconductor device includes: Defining an opening between a first semiconductor fin and a second semiconductor fin; Forming a dummy fin between the first semiconductor fin and the second semiconductor fin, and forming the dummy fin includes: Depositing a first film in the opening; Recessing the first film layer in the opening; Depositing a second film in the opening above the first film; Depositing a third film layer in the opening above the second film layer, the second film layer being disposed on the sidewall and a bottom surface of the third film layer; and Etching the second film layer to at least partially remove the second film layer from the sidewalls of the third film layer; and A gate structure is formed along the sidewall and a top surface of the first semiconductor fin, the sidewall and a top surface of the second semiconductor fin, and the sidewall and a top surface of the dummy fin. The method for forming a semiconductor device according to claim 17, further comprising depositing a spacer layer along the sidewall and a bottom surface of the opening before depositing the first film layer, wherein depositing the first film layer includes depositing the The first film layer is on the spacer layer. The method for forming a semiconductor device according to claim 17, wherein forming the dummy fin further includes: Recessing the third film layer below a topmost surface of the second film layer; and A fourth film layer is deposited in the opening above the third film layer, wherein the second film layer is disposed on the sidewall of the fourth film layer. The method for forming a semiconductor device according to claim 17, wherein etching the second film layer includes a selective etching process, wherein the selective etching process etches the second film at a faster rate than the third film layer Floor.

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