TW202131319A - Value adjusting method, memory control circuit unit and memory storage device for flash memory - Google Patents

Abstract

A value adjusting method, a memory control circuit unit and a memory storage device for flash memory are provided. The method can be applied to a flash memory with a three-dimensional (3D) structure, an embedded memory device, or a solid-state hard disk. The method includes: writing at least one data to at least one second physical erasing unit of at least one first physical erasing unit, and obtaining a distribution state of valid data in plurality of physical erasing units; adjusting a specific threshold value according to the distribution state; and when the number of the at least one first physical erasing unit is less than the specific threshold value, performing a valid data merging operation.

Description

Data sorting method, control circuit unit and storage device of flash memory

The invention relates to a flash memory data sorting method, a flash memory control circuit unit and a flash memory storage device.

Digital cameras, mobile phones and MP3 players have grown rapidly in the past few years, which has led to a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of non-volatile data, power saving, small size, and no mechanical structure, it is very suitable for the built-in various types of memory modules mentioned above. In portable multimedia devices.

Generally speaking, a rewritable non-volatile memory module has multiple physical erasing units, and the memory management circuit is logically divided into multiple regions. These areas usually include data areas and idle areas. When receiving the write command and the data to be written from the host system, the memory management circuit extracts the physical erasing unit from the idle area and writes the data to the extracted physical erasing unit to replace the data The physical erasure unit of the zone. When the number of idle physical erasing units in the idle area of the rewritable non-volatile memory module is not greater than a specific threshold value, the memory management circuit performs an effective data merging operation. For example, the memory management circuit selects multiple physical erasing units (also known as source physical erasing units) with the least effective data from the data area, and copies valid data from these source physical erasing units to the free area At least one physical erasing unit (also referred to as a destination physical erasing unit). After that, the memory management circuit executes the erasing operation on the aforementioned source physical erasing units and re-associates the source physical erasing units in the idle area to increase the number of physical erasing units in the idle area. In addition, the memory management circuit also connects the aforementioned target physical erasing unit to the data area.

However, depending on the distribution of valid data in the rewritable non-volatile memory module, there will be different execution efficiencies when performing valid data merging operations. For example, suppose there are five source physical erasing units, and only one physical erasing unit is added to the idle area after the five source physical erasing units are used to perform a valid data merging operation. In another example, suppose there are two source physical erasing units, and only one physical erasing unit is added to the idle area after the two source physical erasing units are used to perform a valid data merging operation. Compared with the first example, the second example requires fewer physical erasing units to access when performing effective data merging operations, so the second example has better execution efficiency. In particular, when the execution efficiency of the effective data merging operation is poor, it will also affect the performance of the host system when writing to the rewritable non-volatile memory module.

Therefore, how to prevent the effective data merging operation from affecting the performance of the host system when writing to the rewritable non-volatile memory module is one of the problems that those skilled in the art want to solve.

The present invention provides a flash memory data sorting method, a flash memory control circuit unit, and a flash memory storage device, which can prevent the effective data merging operation from affecting the host system's processing of the rewritable non-volatile memory module Performance when writing.

The present invention provides a flash memory data sorting method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, the The rewritable non-volatile memory module includes an idle area, at least one first physical erasing unit of the plurality of physical erasing units is associated with the idle area, and the method includes: storing at least one data At least one second physical erasing unit written into the first physical erasing unit; obtaining a distribution state of valid data in the plurality of physical erasing units; adjusting a specific threshold value according to the distribution state And when the number of the first physical erasure unit is less than the specific threshold value, perform a valid data merging operation.

In an embodiment of the present invention, the step of obtaining the distribution status of the valid data in the plurality of physical erasing units includes: obtaining a data amount of the data; obtaining the distribution status of the effective data in the plurality of physical erasing units The number of at least one third physical erasing unit of, wherein the effective data amount of each third physical erasing unit is changed after the data is written into the second physical erasing unit.

In an embodiment of the present invention, the step of adjusting the specific threshold value according to the distribution state includes: adjusting the specific threshold value according to the amount of data and the number of the third physical erasing units.

In an embodiment of the present invention, the step of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing unit includes: obtaining a first value, wherein the first value is The quotient of the amount of data divided by the number of the third physical erasing unit; if the number of the third physical erasing unit is not greater than a first threshold and the first value is within a first range , Lower the specific threshold value.

In an embodiment of the present invention, the step of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing unit further includes: if the number of the third physical erasing unit is greater than a first When the threshold value is two, increase the specific threshold value.

In an embodiment of the present invention, the first threshold value is ten percent of the number of the first physical erasing unit and the second threshold value is less than the number of the first physical erasing unit Thirty percent.

In an embodiment of the present invention, only when a data amount of the data is equal to a specific data amount, the step of obtaining the distribution state of the valid data in the plurality of physical erasing units is performed.

The present invention provides a flash memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used for coupling to a host system. The memory interface is used for coupling to the rewritable non-volatile memory module. The rewritable non-volatile memory module has a plurality of physical erasing units, the rewritable non-volatile memory module includes an idle area, and at least one of the plurality of physical erasing units The first physical erasing unit is associated with the idle area. The memory management circuit is coupled to the host interface and the memory interface, and is configured to perform the following operation: write at least one data to at least one second physical erasing unit in the first physical erasing unit Obtain a distribution state of the valid data in the plurality of physical erasure units; adjust a specific threshold value according to the distribution state; and when the number of the first physical erasure units is less than the specific threshold value, Perform an effective data merging operation.

In an embodiment of the present invention, in the operation of obtaining the distribution state of the effective data in the plurality of physical erasing units, the memory management circuit is further configured to perform the following operation: obtain one of the data Data amount; obtaining the number of at least one third physical erasing unit in the plurality of physical erasing units, wherein each of the third entities is changed after the data is written to the second physical erasing unit The effective data amount of the erase unit.

In an embodiment of the present invention, the step of adjusting the specific threshold value according to the distribution state includes: adjusting the specific threshold value according to the amount of data and the number of the third physical erasing units.

In an embodiment of the present invention, in the operation of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing units, the memory management circuit is further configured to perform the following operations: A first value, where the first value is the quotient of dividing the amount of data by the number of the third physical erasing unit; if the number of the third physical erasing unit is not greater than the first threshold And when the first value is within a first range, the specific threshold value is lowered.

In an embodiment of the present invention, in the operation of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing unit, the memory management circuit is further configured to perform the following operations: When the number of the third physical erasing units is greater than a second threshold, the specific threshold is increased.

In an embodiment of the present invention, the first threshold value is ten percent of the number of the first physical erasing unit and the second threshold value is less than the number of the first physical erasing unit Thirty percent.

In an embodiment of the present invention, only when a data amount of the data is equal to a specific data amount, the operation of obtaining the distribution state of the effective data in the plurality of physical erasing units is performed.

The present invention provides a flash memory storage device, including: a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for coupling to a host system. The rewritable non-volatile memory module has a plurality of physical erasing units, the rewritable non-volatile memory module includes an idle area, and at least one of the plurality of physical erasing units A physical erasing unit is associated with the idle area. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, and is configured to perform the following operation: write at least one data into the first physical erasing unit At least one second physical erasing unit; obtaining a distribution state of the valid data in the plurality of physical erasing units; adjusting a specific threshold value according to the distribution state; and when the first physical erasing unit When the quantity is less than the specific threshold value, a valid data merging operation is executed.

In an embodiment of the present invention, in the operation of obtaining the distribution state of the valid data in the plurality of physical erasing units, the memory control circuit unit is further configured to perform the following operation: A data amount; obtaining the number of at least one third physical erasing unit in the plurality of physical erasing units, wherein the data is written to the second physical erasing unit and then each of the third physical erasing units is changed The effective data volume of the physical erasure unit.

In an embodiment of the present invention, the operation of adjusting the specific threshold value according to the distribution state includes: adjusting the specific threshold value according to the amount of data and the number of third physical erasing units.

In an embodiment of the present invention, in the operation of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing units, the memory control circuit unit is further configured to perform the following operations: A first value, where the first value is the quotient of dividing the amount of data by the number of the third physical erasing unit; if the number of the third physical erasing unit is not greater than a first threshold And when the first value is within a first range, the specific threshold value is lowered.

In an embodiment of the present invention, in the operation of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing units, the memory control circuit unit is further configured to perform the following operations: When the number of the third physical erasing units is greater than a second threshold, the specific threshold is increased.

In an embodiment of the present invention, the first threshold value is ten percent of the number of the first physical erasing unit and the second threshold value is less than the number of the first physical erasing unit Thirty percent.

In an embodiment of the present invention, only when a data amount of the data is equal to a specific data amount, the operation of obtaining the distribution state of the effective data in the plurality of physical erasing units is performed.

Based on the above, the flash memory data sorting method, flash memory control circuit unit, and flash memory storage device of the present invention can dynamically change according to the distribution status of valid data in the rewritable non-volatile memory module. Adjust the specific threshold value used to determine whether to perform a valid data merging operation, so as to prevent the valid data merging operation from affecting the performance of the host system when writing to the rewritable non-volatile memory module, and to improve the effective data The effectiveness of the merge operation.

Generally speaking, memory storage devices (also known as memory storage systems or flash memory storage devices) include rewritable non-volatile memory modules and controllers (also known as, Control circuit). Generally, the memory storage device is used together with the host system, so that the host system can write data to the memory storage device or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention.

1 and FIG. 2, the host system 11 generally includes a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 are all coupled to a system bus 110.

In this exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 can store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 is coupled to the I/O device 12 through the system bus 110. For example, the host system 11 can transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In this exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be coupled to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory device. Storage devices (for example, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be coupled to a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. Type I/O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

In an exemplary embodiment, the host system mentioned is any system that can substantially cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is described as a computer system, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. 3, in another exemplary embodiment, the host system 31 can also be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 can be used for it. Various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 are used. The embedded storage device 34 includes an embedded Multi Media Card (eMMC) 341 and/or an embedded Multi Chip Package (embedded Multi Chip Package, eMCP) storage device 342. The memory module is directly coupled to the Embedded storage device on the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 (also referred to as a flash memory control circuit unit), and a rewritable non-volatile memory module 406.

The connection interface unit 402 is used to couple the memory storage device 10 to the host system 11. In this exemplary embodiment, the connection interface unit 402 complies with the Peripheral Component Interconnect Express (PCI Express) standard and is compatible with the fast non-volatile memory (NVM express) interface standard. Specifically, the fast non-volatile memory interface standard is a protocol for communication between a host system and a memory device, which defines the register interface between the controller of the memory storage device and the operating system of the host system. The instruction set and function set, and by optimizing the interface standard of the memory storage device, promote the data access speed and data transfer rate of the memory storage device based on the PCIe interface. However, in another exemplary embodiment, the connection interface unit 402 may also comply with other suitable standards. In addition, the connection interface unit 402 and the memory control circuit unit 404 can be packaged in one chip, or the connection interface unit 402 can be arranged outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used to execute a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and perform data processing in the rewritable non-volatile memory module 406 according to the instructions of the host system 11 Operations such as writing, reading, and erasing.

The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and used to store data written by the host system 11. The rewritable non-volatile memory module 406 can be a single level cell (SLC) NAND flash memory module (that is, a flash memory that can store 1 bit in a memory cell). Modules), Multi Level Cell (MLC) NAND flash memory modules (that is, a flash memory module that can store 2 bits in a memory cell), and multiple-level memory cells ( Triple Level Cell, TLC) NAND flash memory module (ie, a flash memory module that can store 3 bits in a memory cell), other flash memory modules or other memories with the same characteristics Body module.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple storage states. By applying the read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the memory cells of the rewritable non-volatile memory module 406 constitute multiple physical programming units, and these physical programming units constitute multiple physical erasing units. Specifically, the memory cells on the same character line form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming unit on the same character line can be at least classified into a lower physical programming unit and an upper physical programming unit. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is higher than that of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. The reliability of the physical programming unit.

In this exemplary embodiment, the physical programming unit is the smallest programming unit. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit is a physical page (page) or a physical sector (sector). If the physical programming unit is a physical page, these physical programming units usually include a data bit area and a redundancy bit area. The data bit area includes multiple physical sectors for storing user data, and the redundant bit area is used for storing system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16, or more or less physical sectors, and the size of each physical sector can also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit of erasure. That is, each physical erasing unit contains one of the smallest number of memory cells to be erased. For example, the physical erasing unit is a physical block.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and when the memory storage device 10 is operating, these control commands are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 502 is equivalent to the description of the operation of the memory control circuit unit 404.

In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control commands are burned into the read-only memory. When the memory storage device 10 is operating, these control commands are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

6 and 7 are schematic diagrams illustrating examples of the management entity erasing unit according to an exemplary embodiment.

It must be understood that when describing the operation of the physical erasing unit of the rewritable non-volatile memory module 406, the words "extract", "grouping", "division", and "association" are used to operate the physical erasing unit. The division unit is a logical concept. In other words, the actual location of the physical erasing unit of the rewritable non-volatile memory module is not changed, but the physical erasing unit of the rewritable non-volatile memory module is logically operated.

Referring to FIG. 6, the memory control circuit unit 404 (or the memory management circuit 502) logically groups the physical erasing units 410(0)~410(N) into a data area 602, an idle area 604, a system area 606 and Replace area 608.

The physical erasing units logically belonging to the data area 602 and the idle area 604 are used to store data from the host system 11. Specifically, the physical erasing unit of the data area 602 is regarded as a physical erasing unit of stored data, and the physical erasing unit of the idle area 604 is a physical erasing unit used to replace the data area 602. That is, when receiving a write command and data to be written from the host system 11, the memory management circuit 502 will use the physical erasing unit extracted from the idle area 604 to write the data to replace the data area 602 Physical erasure unit.

The physical erasing unit logically belonging to the system area 606 is used to record system data. For example, the system data includes information about the manufacturer and model of the rewritable non-volatile memory module, the number of physical erasing units of the rewritable non-volatile memory module, and the physical programming unit of each physical erasing unit Count etc.

The physical erasing unit logically belonging to the replacement area 608 is used for the replacement process of the bad physical erasing unit to replace the damaged physical erasing unit. Specifically, if there are still normal physical erasing units in the replacement area 608 and the physical erasing unit of the data area 602 is damaged, the memory management circuit 502 will extract the normal physical erasing unit from the replacement area 608 to replace Damaged physical erasure unit.

In particular, the number of physical erasing units in the data area 602, the idle area 604, the system area 606, and the replacement area 608 will vary according to different memory specifications. In addition, it must be understood that during the operation of the memory storage device 10, the grouping relationship of the physical erasing unit associated with the data area 602, the idle area 604, the system area 606, and the replacement area 608 will dynamically change. For example, when the physical erasing unit in the idle area 604 is damaged and replaced by the physical erasing unit in the replacement area 608, the physical erasing unit in the original replacement area 608 will be associated with the idle area 604.

Referring to FIG. 7, the memory control circuit unit 404 (or the memory management circuit 502) will be configured with logical addresses LBA(0)~LBA(H) to map the physical erasing unit of the data area 602, where each logical address There are multiple logical units to map the physical programming unit corresponding to the physical erasing unit. Moreover, when the host system 11 wants to write data to the logical address or update the data stored in the logical address, the memory control circuit unit 404 (or the memory management circuit 502) extracts a physical erase from the idle area 604 The erasing unit is used as an active physical erasing unit to write data to alternate the physical erasing unit of the data area 602. And, when the physical erasing unit, which is the active physical erasing unit, is full, the memory control circuit unit 404 (or the memory management circuit 502) will extract the empty physical erasing unit from the idle area 604 as the active unit. The physical erasing unit continues to write the update data corresponding to the write command from the host system 11. In addition, when the number of available physical erasing units in the idle area 604 is less than the preset value, the memory control circuit unit 404 (or the memory management circuit 502) will perform an effective data merging operation (also known as garbage collection (garbage collection)). collection) operation) to sort the valid data in the data area 602, so as to re-associate the physical erasing units that do not store valid data in the data area 602 to the idle area 604.

In order to identify which physical erasing unit the data of each logical address is stored in, in this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) records the logical address and the physical erasing unit Mapping between. For example, in this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) stores a logical-physical mapping table in the rewritable non-volatile memory module 406 to record each logical address The mapped physical erasure unit. When data is to be accessed, the memory control circuit unit 404 (or the memory management circuit 502) loads the logical-physical mapping table into the buffer memory 508 for maintenance, and writes or reads according to the logical-physical mapping table material.

It is worth mentioning that, due to the limited capacity of the buffer memory 508, it is impossible to store a mapping table that records the mapping relationship of all logical addresses. Therefore, in this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) ) Will group the logical addresses LBA(0)~LBA(H) into multiple logical zones LZ(0)~LZ(M), and configure a logical-physical mapping table for each logical zone. In particular, when the memory control circuit unit 404 (or the memory management circuit 502) wants to update the mapping of a certain logical address, the logical-physical mapping table corresponding to the logical region to which the logical address belongs will be loaded into the buffer The memory 508 will be updated.

In another exemplary embodiment, the control commands of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of code (for example, the memory module is dedicated to storing system data). System area). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store it in the rewritable non-volatile memory The control commands in the volume module 406 are loaded into the random access memory of the memory management circuit 502. After that, the microprocessor unit runs these control commands to perform data writing, reading, and erasing operations.

In addition, in another exemplary embodiment, the control commands of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of the rewritable non-volatile memory module 406. The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erasing circuit is used to issue an erasing command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406. The data processing circuit is used for processing data to be written to the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding writing and reading. Take and erase operations. In an exemplary embodiment, the memory management circuit 502 can also send other types of command sequences to the rewritable non-volatile memory module 406 to instruct to perform corresponding operations.

Please refer to FIG. 5 again, the host interface 504 is coupled to the memory management circuit 502 and used for receiving and identifying commands and data sent by the host system 11. In other words, the commands and data sent by the host system 11 will be sent to the memory management circuit 502 through the host interface 504. In this exemplary embodiment, the host interface 504 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited to this. The host interface 504 can also be compatible with the PATA standard, IEEE 1394 standard, SATA standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is coupled to the memory management circuit 502 and used to access the rewritable non-volatile memory module 406. In other words, the data to be written into the rewritable non-volatile memory module 406 is converted into a format acceptable by the rewritable non-volatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 needs to access the rewritable non-volatile memory module 406, the memory interface 506 will send the corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and various memory operations (for example, changing read Take the voltage level or execute the garbage collection operation, etc.) corresponding to the instruction sequence. These command sequences are generated by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506, for example. These command sequences can include one or more signals, or data on the bus. These signals or data may include script codes or program codes. For example, in the read command sequence, the read identification code, memory address and other information will be included.

In an exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.

The error checking and correcting circuit 508 is coupled to the memory management circuit 502 and used to perform error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 will generate a corresponding error correcting code (ECC) for the data corresponding to the write command. And/or error detecting code (EDC), and the memory management circuit 502 will write the data corresponding to the write command and the corresponding error correction code and/or error check code to the rewritable non-volatile In the memory module 406. After that, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will read the error correction code and/or error check code corresponding to the data at the same time, and the error check and correction circuit 508 Based on this error correction code and/or error check code, error checking and correction operations will be performed on the read data.

The buffer memory 510 is coupled to the memory management circuit 502 and used to temporarily store data and commands from the host system 11 or data from the rewritable non-volatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and used to control the power of the memory storage device 10.

8A and 8B are statistical diagrams of the distribution of the effective data and the variation of the effective data drawn according to an exemplary embodiment.

Please refer to FIG. 8A. As shown in the statistical graph 701, suppose that in the initial state, the rewritable non-volatile memory module 406 has 10 physical erasing units and the effective data amount of these physical erasing units is one entity. Wipe 100% of the capacity of the unit. After the memory management circuit 502 writes at least one data into at least one physical erasing unit in the idle area 604, it is assumed that the effective data amount of the aforementioned 10 physical erasing units becomes the capacity of one physical erasing unit. 75%, as shown in statistical graph 702. The statistical graph 703 is used to represent the variation of the effective data amount of each physical erasing unit of the 10 physical erasing units, and this variation can be used to observe the distribution state of the effective data of the physical erasing unit. As shown in the statistical graph 703, it can be seen that after writing data to at least one physical erasing unit in the idle area 604, the effective data amount of each physical erasing unit is reduced by the capacity of one physical erasing unit. 25%. In other words, after writing data to at least one physical erasing unit in the idle area 604, the number of physical erasing units whose effective data amount has changed is larger (ie, 10) and the effective data amount has changed. The degree is more average.

It can be seen from the statistical graph 703 that the effective data is evenly dispersed in the aforementioned 10 physical erasure units (that is, the distribution of the effective data is relatively scattered). In particular, when the distribution of valid data is scattered, it is necessary to use a larger number of source entity erasure units (for example, four source entity erasure units) to add a physical erasure unit when performing effective data merging operations. Units are placed in the idle area 604. This situation will cause the efficiency of the effective data merging operation to be low. At this time, if the memory management circuit 502 raises the specific threshold value, more physical erasing units can be reserved in the idle area 604 when the effective data merging operation is started. In this way, when the effective data merging operation and the writing operation of the host system 11 are interleaved, the data of the host system 11 can be written into the physical erasing unit of the free area 604, and the free area 604 cannot be used. The physical erasing unit for additional writing further enhances the writing performance of the host system 11.

In another example, please refer to FIG. 8B. As shown in the statistical graph 704, it is assumed that in the initial state, the rewritable non-volatile memory module 406 has 10 physical erasing units and the effectiveness of these physical erasing units The data volume is 100% of the capacity of a physical erasing unit. After the memory management circuit 502 writes at least one data into at least one physical erasing unit in the idle area 604, it is assumed that the effective data amount of the aforementioned 10 physical erasing units becomes as shown in the statistical graph 705. The statistical graph 706 is used to represent the variation of the effective data amount of each physical erasing unit of the 10 physical erasing units, and this variation can be used to observe the distribution state of the effective data of the physical erasing unit. As shown in the statistical graph 706, it can be seen that after data is written into at least one physical erasing unit in the idle area 604, the effective data amount changes concentrated in the first to sixth physical erasing units. In this case, it means that the distribution state of the valid data in the rewritable non-volatile memory module 406 is less scattered (ie, more concentrated). In particular, when the distribution of valid data is relatively non-dispersed, a smaller number of source physical erasing units (for example, two source physical erasing units) can be used to add a physical erasing unit when performing a valid data merging operation. Excluding the cells to the free area 604, in this case, the efficiency of the effective data merging operation will be better. At this time, the memory management circuit 502 can lower (or maintain) the specific threshold value. If the memory management circuit 502 lowers the specific threshold value, the effective data merging operation can be started later to allow the host system 11 to perform more writes, thereby improving the write performance of the host system 11. In addition, since the effective data is more concentrated, fewer source physical erasing units can be used to increase the number of physical erasing units in the idle area 604, which can also improve the performance of the effective data merging operation.

FIG. 9 is a flowchart of a method for adjusting a specific threshold for performing a valid data merging operation according to an exemplary embodiment. In the example of FIG. 9, the memory management circuit 502 obtains the distribution status of the valid data in the physical erasing unit of the rewritable non-volatile memory module 406, and adjusts the valid data for execution according to the distribution status The specific threshold of the merge operation.

In more detail, please refer to FIG. 9. First, in step S801, the memory management circuit 502 writes at least one piece of data into the physical erasing unit (also referred to as the first physical erasing unit) in the idle area 604 At least one physical erasing unit (also referred to as a second physical erasing unit). In particular, in one embodiment, the memory management circuit 502 will be activated only when the amount of data written in the foregoing is equal to a certain amount of data (for example, the amount of data that can be stored by 10 physical erasing units) The operation of performing the aforementioned step S801 to obtain the distribution status of the valid data in the first physical erasing unit.

Next, in step S803, the memory management circuit 502 obtains the data amount of the written data. In step S805, the memory management circuit 502 obtains the number of at least one physical erasing unit (also referred to as a third physical erasing unit) in the rewritable non-volatile memory module 406. In particular, after the aforementioned data is written into the second physical erasing unit, the effective data amount of each third physical erasing unit is thus changed. In other words, the third physical erasing unit represents a physical erasing unit whose effective data amount changes after the write operation in step S801 is performed. The third physical erasing units may be located in the data area 602 or other areas, and there is no limitation here.

After that, the memory management circuit 502 adjusts the specific threshold value according to the aforementioned amount of data and the number of third physical erasing units. In more detail, in step S807, the memory management circuit 502 obtains a first value, and the first value is a quotient obtained by dividing the aforementioned amount of data by the number of third physical erasing units. The first value represents the effective amount of data reduced by an average physical erasure unit. After that, in step S809, the memory management circuit 502 determines whether the number of third physical erasing units is greater than the first threshold. The first threshold is, for example, ten percent of the number of physical erasing units (ie, the number of first physical erasing units) in the idle area before step S801 is performed. However, the present invention is not used to limit the first threshold. . When the number of third physical erasing units is not greater than the first threshold value, in step S811, the memory management circuit 502 also determines whether the first value is within the first range. In this embodiment, the memory management circuit 502 also determines whether the first value is between a minimum value (for example, 80%) and a maximum value (for example, 120%). However, the present invention is not used to limit the first value. One range.

When the first value is within the first range, in step S813, the memory management circuit 502 will lower the specific threshold for performing the effective data merging operation. The present invention is not used to limit how much the specific threshold value needs to be lowered. For example, suppose that the specific threshold value is set to five in the initial situation of FIG. 9, and in step S813, the minimum specific threshold value can be adjusted to three by the memory management circuit 502 (that is, the specific threshold value is set at most Minus two). In particular, when the number of third physical erasing units is less than the first threshold and the first value is within the first range, it means that the distribution of valid data in the rewritable non-volatile memory module 406 is relatively poor. Distributed (ie, more concentrated), and lowering the specific threshold value can start the effective data merging operation later to allow the host system 11 to perform more writes, thereby improving the write performance of the host system 11. In addition, since the effective data is more concentrated, fewer source physical erasing units can be used to increase the number of physical erasing units in the idle area 604. This method can also improve the performance of the effective data merging operation.

However, when the first value is not within the first range, in step S814, the memory management circuit 502 does not adjust the specific threshold value for performing the effective data merging operation.

When the number of third physical erasing units is greater than the first threshold, in step S815, the memory management circuit 502 determines whether the number of third physical erasing units is greater than the second threshold. The second threshold is, for example, 30% of the number of physical erasing units (ie, the number of first physical erasing units) in the idle area before step S801 is performed. However, the present invention is not used to limit the second threshold. value.

When the number of the third physical erasing units is not greater than the second threshold value, in step S814, the memory management circuit 502 does not adjust the specific threshold value for performing the effective data merging operation. When the number of the third physical erasing units is greater than the second threshold, in step S817, the memory management circuit 502 will increase the specific threshold for performing the effective data merging operation. The present invention is not used to limit how much the specific threshold value needs to be adjusted. For example, suppose that the specific threshold value is set to five in the initial situation of FIG. 9, and in step S817, the maximum specific threshold value can be adjusted to eight by the memory management circuit 502 (that is, the specific threshold value is set at most Plus three). In particular, when the number of third physical erasure units is greater than the second threshold, it means that the distribution of valid data in the rewritable non-volatile memory module 406 is relatively scattered, and the specific threshold can be increased at the start During the effective data merging operation, more physical erasure units are reserved in the idle area. In this way, when the effective data merging operation and the writing operation of the host system 11 are interleaved, the data of the host system 11 can be written into the physical erasing unit of the free area, and the free area 604 cannot be used. The additional physical erasing unit for writing further improves the writing performance of the host system 11.

After that, when the number of physical erasing units in the idle area (ie, the number of first physical erasing units) is less than a certain threshold, the memory management circuit 502 will perform a valid data merging operation.

It should be noted here that although the example in FIG. 9 is to perform step S809 first and then perform S815, in other embodiments, step S815 may be performed first and then S809 is performed.

FIG. 10 is a flowchart of a data sorting method according to an exemplary embodiment.

Referring to FIG. 10, in step S901, the memory management circuit 502 writes at least one piece of data to at least one second physical erasing unit in the first physical erasing unit, and obtains valid data in the plurality of physical erasing units A distribution state of the data. In step S903, the memory management circuit 502 adjusts a specific threshold value according to the distribution state. When the number of the first physical erasing units is less than the specific threshold value, in step S905, the memory management circuit 502 performs a valid data merging operation.

In summary, the flash memory data sorting method, flash memory control circuit unit and flash memory storage device of the present invention can be based on the distribution status of valid data in the rewritable non-volatile memory module , Dynamically adjust the specific threshold used to determine whether to perform a valid data merging operation, so as to prevent the valid data merging operation from affecting the performance of the host system when writing to the rewritable non-volatile memory module, and can improve The efficiency of effective data merging operations.

30, 10: Memory storage device 31, 11: host system 110: system bus 111: processor 112: Random Access Memory 113: read-only memory 114: Data Transmission Interface 12: Input/output (I/O) device 20: Motherboard 201: flash drive 202: Memory Card 203: Solid State Drive 204: wireless memory storage device 205: Global Positioning System Module 206: network interface card 207: wireless transmission device 208: keyboard 209: Screen 210: Horn 32: SD card 33: CF card 34: Embedded storage device 341: Embedded Multimedia Card 342: Embedded multi-chip package storage device 402: connection interface unit 404: Memory control circuit unit 406: rewritable non-volatile memory module 502: Memory Management Circuit 504: Host Interface 506: Memory Interface 508: error checking and correction circuit 510: buffer memory 512: power management circuit 602: Data Area 604: Idle Area 606: System Area 608: Replacement Area LBA(0)~LBA(H): logical address LZ(0)~LZ(M): logical zone 701~706: Statistical graph S801: A step of writing at least one data to at least one second physical erasing unit in the first physical erasing unit S803: Steps to obtain the data volume of the aforementioned data S805: Obtain the quantity of at least one third physical erasing unit, wherein the step of changing the effective data amount of each third physical erasing unit after writing the aforementioned data to the second physical erasing unit S807: A step of obtaining a first value, where the first value is the quotient of the amount of data divided by the number of third physical erasure units S809: Step of judging whether the number of erasure units of the third entity is greater than the first threshold S814: Steps not to adjust the specific threshold used to perform effective data merging operations S811: Step of judging whether the first value is within the first range S813: Steps to lower the specific threshold for performing effective data merging operations S815: Step of judging whether the number of erasure units of the third entity is greater than the second threshold S817: Steps to increase the specific threshold for performing effective data merging operations S901: A step of writing at least one data to at least one second physical erasing unit in a first physical erasing unit, and obtaining a distribution state of valid data in a plurality of physical erasing units S903: Step of adjusting a specific threshold value according to the distribution state S905: When the number of the first physical erasure unit is less than a specific threshold value, perform a step of merging valid data

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. 6 and 7 are schematic diagrams illustrating examples of the management entity erasing unit according to an exemplary embodiment. 8A and 8B are statistical diagrams of the distribution of the effective data and the variation of the effective data drawn according to an exemplary embodiment. FIG. 9 is a flowchart of a method for adjusting a specific threshold for performing a valid data merging operation according to an exemplary embodiment. FIG. 10 is a flowchart of a data sorting method according to an exemplary embodiment.

S901: A step of writing at least one data to at least one second physical erasing unit in a first physical erasing unit, and obtaining a distribution state of valid data in a plurality of physical erasing units

S903: Step of adjusting a specific threshold value according to the distribution state

S905: When the number of the first physical erasure unit is less than a specific threshold value, perform a step of merging valid data

Claims (21)

A flash memory data sorting method is used in a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, and the rewritable non-volatile memory module The non-volatile memory module includes an idle area, and at least one first physical erase unit of the plurality of physical erase units is associated with the idle area, and the method includes: Writing at least one data to at least one second physical erasing unit in the first physical erasing unit; Obtaining a distribution state of valid data in the plurality of physical erasing units; Adjusting a specific threshold value according to the distribution state; and When the number of the first physical erasing units is less than the specific threshold value, a valid data merging operation is performed. According to the data organization method of flash memory described in claim 1, wherein the step of obtaining the distribution state of the effective data in the plurality of physical erasing units includes: Obtain a data amount of the data; Obtain the number of at least one third physical erasing unit in the plurality of physical erasing units, wherein each of the third physical erasing units is changed after writing the data to the second physical erasing unit The amount of effective data. As described in the second item of the scope of patent application, the flash memory data sorting method, wherein the step of adjusting the specific threshold value according to the distribution state includes: The specific threshold is adjusted according to the amount of data and the number of erasure units of the third entity. In the flash memory data sorting method described in item 3 of the scope of patent application, the step of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing unit includes: Obtaining a first value, where the first value is the quotient obtained by dividing the amount of data by the number of the third physical erasing unit; If the number of the third physical erasing units is not greater than a first threshold value and the first value is within a first range, the specific threshold value is lowered. As described in item 4 of the scope of patent application, the flash memory data sorting method, wherein the step of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing unit further includes: If the number of the third physical erasing units is greater than a second threshold, the specific threshold is increased. The flash memory data sorting method as described in item 5 of the scope of patent application, wherein the first threshold value is ten percent of the number of the first physical erasing unit and the second threshold value is Thirty percent of the number of the first physical erasing unit. As described in the first item of the scope of patent application, the flash memory data organization method, wherein only when a data amount of the data is equal to a specific data amount, the effective data in the plurality of physical erasing units is obtained The steps of the distribution state. A flash memory control circuit unit is used to control a rewritable non-volatile memory module. The memory control circuit unit includes: A host interface for coupling to a host system; A memory interface for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, and the rewritable non-volatile memory module The volatile memory module includes an idle area, and at least one first physical erasing unit of the plurality of physical erasing units is associated with the idle area; A memory management circuit coupled to the host interface and the memory interface, The memory management circuit is used for writing at least one data to at least one second physical erasing unit in the first physical erasing unit, The memory management circuit is further used to obtain a distribution state of the effective data in the plurality of physical erasing units, The memory management circuit is further used to adjust a specific threshold value according to the distribution state, When the number of the first physical erasing units is less than the specific threshold value, the memory management circuit is further used to perform a valid data merging operation. The flash memory control circuit unit described in item 8 of the scope of patent application, wherein in the operation of obtaining the distribution state of the effective data in the plurality of physical erasing units, The memory management circuit is further used to obtain a data amount of the data, The memory management circuit is further used to obtain the number of at least one third physical erasing unit among the plurality of physical erasing units, wherein the data is changed every time after writing the data to the second physical erasing unit 1. The effective data amount of the third entity erasing unit. The flash memory control circuit unit as described in item 9 of the scope of patent application, wherein in the operation of adjusting the specific threshold value according to the distribution state, The memory management circuit is further configured to adjust the specific threshold value according to the amount of data and the number of the third physical erasing units. The flash memory control circuit unit described in claim 10, wherein in the operation of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing unit, The memory management circuit is further used to obtain a first value, wherein the first value is a quotient of the amount of data divided by the number of the third physical erasing unit, If the number of the third physical erasing units is not greater than a first threshold value and the first value is within a first range, the memory management circuit is further used to lower the specific threshold value. The flash memory control circuit unit described in item 11 of the scope of patent application, wherein in the operation of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing unit, If the number of the third physical erasing units is greater than a second threshold, the memory management circuit is further configured to increase the specific threshold. The flash memory control circuit unit according to item 12 of the scope of patent application, wherein the first threshold value is ten percent of the number of the first physical erasing unit and the second threshold value is Thirty percent of the number of the first physical erasure unit. The flash memory control circuit unit described in item 8 of the scope of patent application, wherein only when a data amount of the data is equal to a specific data amount, the memory management circuit executes to obtain the plurality of physical erasures The operation of the distribution state of the valid data in the unit. A flash memory storage device, including: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, and the rewritable non-volatile memory module includes an idle area, At least one first physical erasing unit of the plurality of physical erasing units is associated with the idle area; and A memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, The memory control circuit unit is used for writing at least one data to at least one second physical erasing unit in the first physical erasing unit, The memory control circuit unit is further used to obtain a distribution state of the effective data in the plurality of physical erasing units, The memory control circuit unit is further used to adjust a specific threshold value according to the distribution state, When the number of the first physical erasing units is less than the specific threshold value, the memory control circuit unit is further used to perform a valid data merging operation. The flash memory storage device described in claim 15, wherein in the operation of obtaining the distribution state of the effective data in the plurality of physical erasing units, The memory control circuit unit is further used to obtain a data amount of the data, The memory control circuit unit is further used to obtain the number of at least one third physical erasing unit in the plurality of physical erasing units, wherein the data is changed after being written to the second physical erasing unit The effective data amount of each of the third physical erasure units. The flash memory storage device described in the 16th item of the scope of patent application, wherein in the operation of adjusting the specific threshold value according to the distribution state, The memory control circuit unit is further configured to adjust the specific threshold value according to the amount of data and the number of the third physical erasing units. The flash memory storage device described in the scope of patent application, wherein in the operation of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing unit, The memory control circuit unit is further used to obtain a first value, wherein the first value is a quotient of the amount of data divided by the number of the third physical erasing unit, If the number of the third physical erasing units is not greater than a first threshold value and the first value is within a first range, the memory control circuit unit is further used to lower the specific threshold value . The flash memory storage device described in item 18 of the scope of patent application, wherein in the operation of adjusting the specific threshold value according to the amount of data and the number of the third physical erasing unit, If the number of the third physical erasing units is greater than a second threshold, the memory control circuit unit is further used to increase the specific threshold. The flash memory storage device according to item 19 of the scope of patent application, wherein the first threshold value is ten percent of the number of the first physical erasing unit and the second threshold value is the Thirty percent of the number of first physical erasure units. The flash memory storage device according to the 15th patent application, wherein only when a data amount of the data is equal to a specific data amount, the memory control circuit unit executes to obtain the plurality of physical erasures The operation of the distribution state of the valid data in the unit.

Images