TW202127449A - Memory device - Google Patents

Abstract

Memory devices are provided. A memory device includes a word line driver, a recycle multiplexer, a memory cell array, and a compensation word line driver. The word line driver is coupled to a plurality of word lines. The recycle multiplexer is coupled to a plurality of bit lines and a plurality of bit line bars. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the bit lines or one or more of the bit line bars to the compensation word line driver.

Description

Memory device

The embodiment of the present invention relates to a memory system, and particularly relates to a static random access memory (SRAM) system.

Static random access memory (SRAM) generally refers to any memory or storage that can retain stored data only when it is powered on. With the development of integrated circuit (IC) technology toward smaller technology nodes, SRAM can incorporate such things as FinFET or gate-all-around (GAA) transistors. Multi-gate structures are incorporated into SRAM cells to improve performance and increase packaging density, where each SRAM cell can store one bit of data. The SRAM cells are arranged in a densely arranged SRAM array, and their access is controlled by transmission gate transistors (or access transistors) activated by word line signals. When the word line extends from the word line driver through the SRAM array, the voltage drop along the length of the word line may reduce the voltage of the word line signal supplied to the SRAM cell far from the word line driver, resulting in reduced speed and Increase power consumption. Therefore, although the existing SRAM devices are generally sufficient for their intended purpose, the existing SRAM devices are not completely satisfactory in all aspects.

The embodiment of the present invention provides a memory device. The memory device includes a word line driver, a cyclic multiplexer, a memory cell array, and a compensation word line driver. The word line driver is coupled to a plurality of word lines. The cyclic multiplexer is coupled to multiple bit lines and multiple anti-bit lines. The memory cell array includes a first end adjacent to the word line driver, a second end far from the word line driver, and a plurality of memory cells. Each memory cell is coupled to one of a plurality of word lines, one of a plurality of bit lines, and one of a plurality of anti-bit lines. The compensation word line driver is arranged adjacent to the second end of the memory cell array and is coupled to a plurality of word lines. The cyclic multiplexer is configured to selectively couple one or more bit lines or one or more inverted bit lines to the compensation word line driver. .

The following disclosure provides many different embodiments or examples for implementing different components of the subject matter provided herein. Specific examples of components and arrangements are described below to simplify the embodiments of the present invention. Of course, these are only examples, and are not intended to limit the scope of protection of the present invention. For example, in the following description, forming the first member above or on the second member may include an embodiment in which the first member and the second member are formed in direct contact, and may also be included in the first member and the second member. An embodiment in which additional components are formed between the components so that the first component and the second component may not directly contact. In addition, the embodiments of the present invention may repeat reference numerals and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and is not used in itself to specify the relationship between the various embodiments and/or configurations discussed.

In addition, different examples in the description of the present disclosure may use repeated reference symbols and/or words. These repeated symbols or words are for the purpose of simplification and clarity, and are not used to limit the relationship between the various embodiments and/or the appearance structure. Furthermore, the following disclosure of this specification describes that a feature is formed on, connected to, or coupled to another feature, which means that it includes an embodiment in which the formed feature is in direct contact. It also includes embodiments in which additional features can be formed between these features so that these features are not in direct contact. In addition, related terms in space, such as "down", "up", "horizontal", "vertical", "above", "below", "up", "down", "top", "bottom" Etc. and its derivatives (for example, "horizontally", "downwardly", "upwardly", etc.) are used to easily express the relationship between the features in this specification and the additional features. These spatially related terms cover different orientations of devices with specific characteristics.

This disclosure is about memory systems, especially static random access memory (SRAM) systems. For advanced integrated circuit technology nodes, multi-gate transistors (such as FinFET or gate-all-around (GAA) transistors) have become high-performance and low-leakage applications Popular and promising candidates. Memory arrays, such as SRAM arrays, can be incorporated into memory cells formed by FinFETs or GAA transistors to enhance performance or increase packaging density. Each memory cell can store one bit of data. As the size of the cells in the SRAM array shrinks, the word lines that provide access signals to the cells in the SRAM array also shrink in size. In a smaller word line, the impedance will increase, which results in a voltage drop along the length of the word line. When the word line driver is placed on one side of the SRAM array, the word line from the word line driver can provide access signals to the SRAM cells adjacent to the word line driver, and provide relatively low voltage due to the influence of the voltage drop. The small access signal goes to the SRAM cell far away from the word line driver.

The memory system according to the embodiment of the disclosure includes: a first word line driver disposed adjacent to one end of the SRAM array, and a second word line driver disposed adjacent to the other end of the SRAM array. Each word line is coupled to the first word line driver and the second word line driver. When a word line is selected, the first word line driver provides an access signal to the selected word line, and the second word line driver provides a feedback signal to the selected word line. The feedback signal comes from a charge recycle mechanism, which collects charge from unselected SRAM cells via bit lines and bit line bars coupled to unselected SRAM cells. The charge collected by the charge recycle mechanism will dissipate through the leakage path and cause waste. That is, the generation of the feedback signal does not require additional energy input. Due to the impedance along the length of each word line, the feedback signal provided by the second word line driver will compensate for the voltage drop in the access signal, thereby reducing RC (resistance-capacitance) delay and enhancing memory System performance

Static random access memory (SRAM) is a volatile semiconductor memory that uses a bistable latch circuit to store each bit. Each bit in SRAM is stored in four transistors (first pull-up transistor (PU-1), second pull-up transistor (PU-2), first pull-down transistor (PD-1) And the second pull-down transistor (PD-2)), which form two cross-coupled inverters. This memory cell has two stable states, which are used to represent 0 and 1 respectively. The other two additional access transistors (the first transfer gate transistor (PG-1) and the second transfer gate transistor (PG-2)) are used to control the storage of the storage cell during read and write operations. Pick. A typical SRAM cell includes six transistors (6T), which are used to store each memory bit. FIG. 1 is a circuit diagram of the SRAM cell 10 according to some embodiments of the disclosure. In some cases, the SRAM cell 10 of FIG. 1 includes six (6) transistors, and may be referred to as a single-port SRAM cell 10 or a 6T SRAM cell 10. It should be noted that even though the embodiments of the present disclosure are described in conjunction with 6T SRAM cells, the present disclosure is not limited thereto. The present disclosure can be applied to SRAM cells including more transistors, such as 7T, 8T, 9T, or 10T, which can be single-port, dual-port or multi-port.

The SRAM cell 10 of FIG. 1 includes a first transmission gate transistor (PG-1) 2 and a second transmission gate transistor (PG-2) 4, a first pull-up transistor (PU-1) 6 and a second upper Pull-down transistor (PU-2) 8, and first pull-down transistor 12 (PD-1) and second pull-down transistor (PD-2) 14. In the SRAM cell 10, each of the transmission gate transistor, the pull-up transistor, and the pull-down transistor may be a multi-gate transistor, such as a GAA transistor. The gates of the first transmission gate transistor 2 and the second transmission gate transistor 4 are electrically connected to the word line WL, and the word line WL determines whether to select/activate the SRAM cell 10 or not. In the SRAM cell 10, the first pull-up transistor 6 and the second pull-up transistor 8 and the first pull-down transistor 12 and the second pull-down transistor 14 form memory bits (such as latches or flip-flops). ) To store one-bit data. The complementary value of the bit is stored in the first storage node 16 and the second storage node 18. The stored bits can be written to or read from the SRAM cell 10 through the bit line BL and the bit line bar BLB. In this arrangement, the bit line BL and the inverted bit line BLB can carry complementary bit line signals. The SRAM cell 10 is powered by a voltage bus CVdd having a positive power supply voltage (Vdd), and is also connected to the ground potential bus CVss at a ground potential (Vss).

The SRAM cell 10 includes a first inverter 20 formed by a first pull-up transistor (PU-1) 6 and a first pull-down transistor (PD-1) 12, and a second pull-up transistor (PU- 2) The second inverter 22 formed by 8 and the second pull-down transistor (PD-2) 14. The first inverter 20 and the second inverter 22 are coupled between the voltage bus CVdd and the ground potential bus CVss. As shown in Figure 1, the first inverter 20 and the second inverter 22 are cross-coupled. That is, the input of the first inverter 20 is coupled to the output of the second inverter 22. Similarly, the input of the second inverter 22 is coupled to the output of the first inverter 20. The output of the first inverter 20 is referred to as the first storage node 16, and the output of the second inverter 22 is referred to as the second storage node 18. In the normal operation mode, the first storage node 16 is in a logical state opposite to that of the second storage node 18. By using two cross-coupled inverters, the SRAM cell 10 can use a latch structure to retain data, so that as long as it is powered by the positive power supply voltage Vdd, there is no need to apply a refresh cycle and the stored data will not be lost.

In operation, if the first transmission gate transistor (PG-1) 2 and the second transmission gate transistor (PG-2) 4 are inactive (not activated by the word line WL), as long as the power is supplied through the voltage bus CVdd , The SRAM cell 10 will maintain/maintain the complementary value in the first storage node 16 and the second storage node 18 indefinitely. This is because each inverter in the pair of cross-coupled inverters drives the input of the other inverter, thereby maintaining the voltage on the storage nodes 16 and 18. This situation will remain stable until the power is disconnected from the SRAM cell 10, or a write cycle is performed to change the data stored on the storage nodes 16 and 18.

During the write operation, according to the new data to be written to the SRAM cell 10, the bit line BL and the inverted bit line BLB are set to opposite logic values. For example, in an SRAM write operation, by setting the bit line BL to "0" and the inverted bit line BLB to "1", the logic state stored in the data latch of the SRAM cell 10 can be reset " 1". Corresponding to the binary code from the row decoder (not shown), coupled to the first transmission gate transistor (PG-1) 2 and the second transmission gate transistor (PG-2) 4 of the SRAM cell 10 The word line of will be assigned to select the memory cell, and then turn on the first transmission gate transistor (PG-1) 2 and the second transmission gate transistor (PG-2) 4. As a result, the first storage node 16 and the second storage node 18 are connected to the bit line BL and the inverted bit line BLB, respectively. Furthermore, the first storage node 16 of the data latch will be discharged to "0" by the bit line BL, and the second storage node 18 of the data latch will be charged to "1" by the inverted bit line BLB. Therefore, the new data logic "0" will be latched into the SRAM cell 10.

In the read operation, both the bit line BL and the inverted bit line BLB of the SRAM cell 10 are precharged to a voltage approximately equal to the operating voltage of the memory bank in which the SRAM cell 10 is located. In some cases, such an operating voltage is the positive power supply voltage Vdd. Corresponding to the binary code from the column decoder, the word line WL of the first transmission gate transistor (PG-1) 2 and the second transmission gate transistor (PG-2) 4 coupled to the SRAM cell 10 will be Assigned so that the data latch is selected for read operation.

During the read operation, the first transmission gate transistor (PG-1) 2 and the second transmission gate transistor (PG-2) 4 that are turned on are coupled to a bit of the storage node storing logic "0" The line will be discharged to a lower voltage. At the same time, the other bit lines maintain the precharge voltage because there is no discharge path between the other bit lines and the storage node storing logic "1". The differential voltage between the bit line BL and the inverted bit line BLB is detected by the sense amplifier (as shown in Figure 3). In addition, the sense amplifier will amplify the differential voltage and report the logic state of the memory cell through the data buffer. In other words, the sense amplifier converts the analog voltage difference into a digital signal.

In an SRAM array formed of a plurality of SRAM cells 10, the SRAM cells 10 are arranged in columns and rows. The rows of the SRAM array are formed by bit line pairs, that is, bit line BL and inverted bit line BLB. The cells of the SRAM array are arranged between each bit line pair. As shown in Figure 1, the SRAM cell 10 is placed between the bit line BL and the inverted bit line BLB. The first transmission gate transistor (PG-1) 2 is connected between the bit line BL and the output 16 of the first inverter 20 (ie, the first storage node 16). The second transmission gate transistor (PG-2) 4 is connected between the inverted bit line BLB and the output 18 of the second inverter 22 (ie, the second storage node 18). The gates of the first transmission gate transistor (PG-1) 2 and the second transmission gate transistor (PG-2) 4 are connected to the word line WL, and the word line WL is connected to the SRAM array in one column SRAM cell.

Referring to FIG. 2, FIG. 2 is a schematic diagram showing the first SRAM system 100. The first SRAM system 100 includes an SRAM array 102, a word line driver 104, a compensation word line driver 106, a memory controller 108, a loop multiplexer (MUX) 110, and a read/write block 112. The SRAM array 102 may include SRAM cells arranged in m columns extending along the X direction and n rows extending along the Y direction. That is, the SRAM array 102 may include (m*n) SRAM cells. For example, the SRAM array 102 includes 64 SRAM cells, 128 SRAM cells, or 256 SRAM cells. In some embodiments, the SRAM array 102 has a rectangular shape and has a first end E1 along the X direction and an opposite second end E2. In the embodiment shown in FIG. 2, for illustration purposes, only six SRAM cells 1011, 1012, 1013, 1021, 1022, and 1023 are shown. As similarly described for the SRAM cell 10 in Figure 1, each SRAM cell in the SRAM array 102 is coupled to a word line WL, a bit line BL, and an inverted bit line BLB. For example, the SRAM cell 1011 is coupled to the first word line WL1, the first bit line BL1 and the first inverted bit line BLB1, and the SRAM cell 1012 is coupled to the first word line WL1 and the second bit line. BL2 and the second inverted bit line BLB2, the SRAM cell 1013 is coupled to the first word line WL1, the third bit line BL3 and the third inverted bit line BLB3, and the SRAM cell 1021 is coupled to the second word line The line WL2, the first bit line BL1 and the first inverted bit line BLB1, the SRAM cell 1022 is coupled to the second word line WL2, the second bit line BL2 and the second inverted bit line BLB2, and the SRAM cell 1023 is coupled The second word line WL2, the third bit line BL3, and the third inverted bit line BLB3 are connected. The SRAM array 102 can be considered to include m columns of SRAM cells or n rows of SRAM cells. The SRAM cells in each column are coupled to a common word line, and the SRAM cells in each row are coupled to a common bit line and a common inverted bit line. In some embodiments shown in FIG. 2, the SRAM cells 1011, 1012, and 1013 arranged in the same column along the X direction are coupled to the first word line WL1. Similarly, the SRAM cells 1021, 1022, and 1023 arranged in the same column along the X direction are coupled to the second word line WL2. The SRAM cells 1011 and 1021 arranged in the same row along the Y direction are coupled to the first bit line BL1 and the first inverted bit line BLB1. The SRAM cells 1012 and 1022 arranged in the same row along the Y direction are coupled to the second bit line BL2 and the second inverted bit line BLB2. The SRAM cells 1013 and 1023 are coupled to the third bit line BL3 and the third inverted bit line BLB3. Continue row-wise sharing word lines for each m-column SRAM cell, and continue column-wise sharing bit lines and inverse bit lines for each n-row SRAM cell Bit line pair (pair). In this way, by selecting individual word lines and individual pairs of bit lines, each SRAM cell can be addressed. For example, the SRAM cell 1011 can be addressed by activating the first word line WL1 and selecting the first bit line BL1 and the first inverted bit line BLB1.

Still referring to FIG. 2, each word line is coupled to a word line driver 104 disposed adjacent (or close to) the first end E1 and a compensation character disposed adjacent (or close to) the second end E2 The line driver 106 is driven by it. That is, one end of each word line is coupled to the word line driver 104 to receive the access signal, and the other end of each word line is coupled to the compensation word line driver 106 to receive the feedback signal. . As described below, since the word line driver 104 and the compensating word line driver 106 are synchronized to select the same group of word lines, the feedback signal provided by the compensating word line driver 106 will be affected by the word line driver 106. 104 provides compensation for the reduced impedance access signal.

The memory controller 108 controls the operations of the word line driver 104, the compensation word line driver 106, the cyclic multiplexer 110, and the read/write block 112. One or more SRAM cells in the SRAM array 102 can be addressed through a row number signal and a column number signal. The column number signal is sent from the memory controller 108 to the word line driver 104 and the compensation word line driver 106 to select a column of SRAM cells via one of the word lines. The row number signal is sent to the read/write block 112 through one of the bit line/inverted bit line pair to select a row of SRAM cells. Then, the SRAM cell at the intersection of the selected column and the selected row is selected or addressed. For example, in order to read the bits stored in the SRAM cell 1011, an access signal can be sent to the first word line WL1 to provide (or activate) access to the SRAM cell in the column where the SRAM cell 1011 is provided. . Then, the bit stored in the SRAM cell can be read through the first bit line BL1 and the first inverted bit line BLB1. In order to write bits into the SRAM cell 1011, an access signal is sent to the first word line WL1 to provide (or activate) access to the SRAM cell in the column where the SRAM cell 1011 is provided. The input data signal can be written into the SRAM cell 1011 through the first bit line BL1 and the first inverted bit line BLB1. The same is true for SRAM cells 1012, 1013, 1021, 1022, and 1023.

Each bit line, such as the first bit line BL1, the second bit line BL2, and the third bit line BL3, and each inverted bit line, such as the first inverted bit line BLB1 and the second inverted bit line The line BLB2 and the third inverted bit line BLB3 are coupled to the read/write block 112. Refer now to FIG. 3, which is a more detailed schematic diagram showing the read/write block 112. In some embodiments shown in FIG. 3, the read/write block 112 includes a row decoder 202. The row decoder 202 selects a pair of bit lines and inverted bit lines according to the row number signal 206 from the memory controller 108. In some embodiments shown in FIG. 3, the row decoder 202 can also receive input data 208 during the write operation and input it to the selected memory unit. The read/write block 112 further includes a sense amplifier 204 for detecting the differential voltage between the bit line BL and the inverted bit line BLB during the read operation. The sense amplifier 204 can amplify the differential voltage and report the logic state 210 (output data 210) of the memory cell via the data buffer.

In some embodiments shown in FIG. 2, the first SRAM system 100 includes a precharge circuit 114 to precharge all bit lines, all inverted bit lines, or both. In some cases, the precharge circuit 114 will precharge all bit lines, all inverted bit lines, or both to the positive power supply voltage Vdd. The pre-charge circuit 114 may be coupled to the memory controller 108 to receive the enable signal. The enable signal from the memory controller 108 can turn on one or more transistors in the pre-charge circuit 114 to connect the bit line, the inverted bit line, or both to the power line or the power line at the positive power supply voltage Vdd. Power rail. Conventionally, the bit line and the inverted bit line charged to the positive power supply voltage Vdd by the precharge circuit 114 can be allowed to be discharged to a lower voltage or ground potential Vss. The bit line and the inverted bit line of the selected SRAM cell can be allowed to discharge through the pull-down transistor. The bit line and the inverted bit line of the memory cell not selected by the read/write block 112 should be floating, but in fact, the charge stored therein is likely to pass through the leakage in the first SRAM system 100 The path dissipated. Therefore, the charge in the precharged bit line and the inverted bit line of the unselected SRAM cell in the conventional SRAM system may be wasted.

The SRAM system according to the present disclosure includes a charge recycling mechanism, which can collect charge from the bit line and the inverted bit line of the unselected SRAM cell, and guide the collected charge to the compensation word line driver 106. In some embodiments shown in FIG. 2, the charge recycling mechanism includes a recycling multiplexer 110 coupled to the compensation word line driver 106. Each bit line, such as the first bit line BL1, the second bit line BL2, and the third bit line BL3, and each inverted bit line, such as the first inverted bit line BLB1, and the second inverted bit line The line BLB2 and the third inverted bit line BLB3 are also coupled to the circular multiplexer (MUX) 110. The loop multiplexer 110 is coupled to the memory controller 108. The memory controller 108 can send the inverted row number signal to the cyclic multiplexer 110 so that the cyclic multiplexer 110 can be electrically coupled to memory cells not selected by the read/write block 112. In some embodiments, the memory controller 108 sends the same row number signal to both the read/write block 112 and the cyclic multiplexer 110, but the row number signal is transmitted by the cyclic multiplexer 110 or The separate inverter circuit is inverted, so that the cyclic multiplexer 110 can be electrically coupled to memory cells not selected by the read/write block 112. In some other embodiments, the cyclic multiplexer 110 is electrically coupled to a part (subset) of unselected bit lines and inverted bit lines, instead of all unselected bit lines and inverted bit lines. . The charge collected by the cyclic multiplexer 110 will be used as the power source of the compensation word line driver 106 so that the collected charge is redirected to the selected word line coupled to the compensation word line driver 106. In other words, the cyclic multiplexer 110 and the compensation word line driver 106 will operate together to redirect the wasted charge to the far end/remote (relative to the word line driver 104) of the selected word line for compensation The voltage drop caused by impedance. As previously described, the word line driver 104 and the compensation word line driver 106 both receive the column number signal from the memory controller 108 and are synchronized to select the same group of word lines. In this way, the word lines of this group are coupled to the word line driver 104 at the first end E1, and are coupled to the compensation word line driver 106 at the second end E2. The word line driver 104 directly draws power from the positive power supply voltage Vdd, and the compensation word line driver 106 draws power from the recovered charges collected by the charge recycling mechanism (ie, the cyclic multiplexer 110 in FIG. 2). In the first SRAM system 100, each selected word line is composed of a first word line driver (that is, the word line driver 104) at one end (that is, the first end E1) and the other end (that is, the second end E2) The second word line driver (that is, the compensation word line driver 106) is driven by the second word line driver, instead of being driven by a single word line driver in the traditional configuration.

Some benefits of the disclosed embodiment are described in conjunction with Figure 4. Figure 4 shows the word line driver 104, the bit line/inverted bit line, the access signal to the first end E1, and the access signal to the second end E2. Time sequence 300 of the voltage of the access signal. The first time sequence 302 represents the access signal on the word line driver 104 as time changes. The second time series 304 represents the voltage of the unselected bit line/inverted bit line as time changes. The third time sequence 306 represents the access signal of the memory cell near the first end E1 of the word line driver 104. The fourth time series 308 represents the access signal of the memory cell near the second end E2 of the compensation word line driver 106. As shown in the first time series 302 in FIG. 4, when the word line driver 104 sends an access signal down to the selected word line, the access signal at the word line driver 104 will be at time T ₀ Change from "0" to "1". Due to the impedance in the selected word line, the access signal arriving at the SRAM cell near the first end E1 has almost no resistance-capacitive delay (RC delay), while the SRAM cell arriving near the second end E2 will experience More obvious RC delay. As shown in FIG. 4, a third time series at a time point T ₁ 306 from "0" to "1", which are small and acceptable. Without the charge recycling mechanism of the present disclosure, the access signal of the SRAM cell near the second end E2 will experience a significant RC delay. Thus, the fourth time series 308 and 314 will be along a dashed curve at a time point T ₃ from "0" to "1." However, when the charge recycling mechanism of the present disclosure is implemented, the access signal of the SRAM cell near the second end E2 will be supplemented by the recovered charge supplied by the compensation word line driver 106. Thus, the fourth time series along a steep curve 308 will be 316, and at time point T ₂ from "0" to "1." The RC delay of the SRAM cell close to the first end E1 can be expressed as the difference between the time points T1 and T0 (ie, T ₁ -T ₀ ). In the absence of a charge recycling mechanism, the RC delay of the SRAM cell near the second end E2 can be expressed as the difference between T3 and T0 (ie, T ₃ -T ₀ ). The RC delay of the SRAM cell near the second end E2 with the charge recycling mechanism can be expressed as the difference between T2 and T0 (ie, T ₂ -T ₀ ). (T ₃ -T ₀ ) is greater than (T ₂ -T ₀ ). (T ₃ -T ₀ ) can be equal to or greater than (T ₁ -T ₀ ). It has been observed that when the time delay is shortened (that is, from (T ₃ -T ₀ ) to (T ₂ -T ₀ )), the speed of the SRAM system can increase between about 5% and about 15%, including about 10%.

Depending on whether the unselected SRAM cell is accessed by the word line, the voltage on the bit line or the inverted bit line may be different. To avoid any doubt, when the SRAM array 102 is addressed by the row number and column number, each SRAM cell in the SRAM array 102 is selected. However, if any of its word line or bit line/inverted bit line pair is not selected, the SRAM cell will not be selected. Therefore, when the word line driver 104 energizes the word line to provide access (or activation) to a column of SRAM cells, an SRAM cell of the column of SRAM cells will not be selected unless the block is read/written 112 also selects the bit line and the inverted bit line of the SRAM cell. Compared with the SRAM cell accessed by the unselected word line, the SRAM cell accessed by the access signal in the word line includes a charge dissipation path through the conductive transfer thyristor. As shown in FIG. 4, when the bit line and the inverted bit line are not allowed to dissipate through the transmission thyristor, the second time series 304 will fall along the flat curve 310. In comparison, when the bit line and the inverted bit line are allowed to dissipate through the transmission thyristor turned on by the selected word line, the second time series 304 will fall faster along the steep curve 312.

Figure 5 shows a second SRAM system 400 according to some embodiments of the disclosure. Compared with the first SRAM system 100 in FIG. 2, the second SRAM system 400 further includes a feedback controller 116. In the second SRAM system 400, the feedback controller 116 can be regarded as a part of the charge recycling mechanism, which includes a cyclic multiplexer. Throughout this disclosure, the same number represents the same feature. For brevity, the description of the features in the second SRAM system 400 having similar reference numerals as those in the first SRAM system 100 will not be repeated here. In some embodiments shown in FIG. 5, the feedback controller 116 allows the selective connection of the compensation word line driver 106 and adjusts the recovered charge fed to the compensation word line driver 106. In some embodiments, the feedback controller 116 is coupled to the memory controller 108. In those embodiments, when the memory controller 108 sends an enable signal to the feedback controller 116, the feedback controller 116 can be activated to direct the charge collected in the loop multiplexer 110 to the compensation word line. Drive 106. In other words, when the feedback controller 116 is enabled, the second SRAM system 400 will operate like the first SRAM system 100. When the feedback controller 116 is disabled, the connection between the cyclic multiplexer 110 and the compensation word line driver 106 will be cut off, and the second SRAM system 400 will operate like a traditional SRAM system.

Referring now to FIG. 6, FIG. 6 shows an embodiment of the feedback controller 116. As shown in Figure 6, the feedback controller 116 includes a first inverter 502, a first p-type transistor 504, a second inverter 506, a third inverter 508, a fourth inverter 510, and a Two p-type transistors 512. The first inverter 502, the second inverter 506, the third inverter 508, and the fourth inverter 510 include an input and an inverted output, respectively. The first p-type transistor 504 includes a first gate G1, a first drain D1, and a first source S1. The second p-type transistor 512 includes a second gate G2, a second drain D2, and a second source S2. In some embodiments, the input of the first inverter 502 is coupled to the memory controller 108 to receive the enable signal 501. The output of the first inverter 502 is the second drain D2 coupled to the second p-type transistor 512. The first source S1 of the first p-type transistor 504 is coupled to the cyclic multiplexer 110 to receive the charge recovered from the unselected bit line and the inverted bit line. The first drain D1 of the first p-type transistor 504 is coupled to the input of the compensation word line driver 106 and the second inverter 506. The output of the second inverter 506 is coupled to the input of the third inverter 508. The output of the third inverter 508 is coupled to the input of the fourth inverter 510. The output of the fourth inverter 510 is the second gate G2 coupled to the second p-type transistor 512. The second source S2 is coupled to the positive power supply voltage Vdd.

Without the enable signal 501, the output of the first inverter 502 is “1”, which will not turn on the first gate G1 of the first p-type transistor 504. Using the non-conducting first p-type transistor 504, the connection between the cyclic multiplexer 110 and the compensation word line driver 106 will be cut off, and the compensation word line driver 106 will not provide any signal to the selected Character line. When the memory controller 108 sends the enable signal 501 to the first inverter 502, the inverted output of the first inverter 502 will turn on the first gate G1 of the first p-type transistor 504, so that the cycle The output of the multiplexer 110 is connected to the compensation word line driver 106, and the compensation word line driver 106 supplies the recovered charge from the second terminal E2 to the selected word line. In other words, when the first p-type transistor 504 is turned on, the charge recycling mechanism of the present disclosure will start to work to compensate for the RC delay in the selected word line. When the voltage of the compensated word line driver 106 rises to a level ("1") close to Vdd, the second inverter 506 can invert the "1" signal to output a "0" signal to the third inverter 508 , And the third inverter 508 inverts the "0" signal to "1". Then, the "1" signal from the output of the third inverter 508 is sent to the fourth inverter 510 to generate a "0" signal. The "0" signal output from the fourth inverter 510 turns on the second gate G2 of the second p-type transistor 512, thereby connecting the second source S2 and the second drain D2. The Vdd of the second source S2 is a "1" signal, which will not turn on the first gate G1, thereby turning off the charge circulation mechanism. It can be seen that when the voltage of the compensation word line driver 106 (that is, the access signal voltage near the second terminal E2) is high (that is, "1"), the charge recycling mechanism will be turned off. However, when the voltage of the compensation word line driver 106 (ie, the access signal voltage near the second terminal E2) is low (ie "0") and the feedback controller 116 is enabled by the enable signal 501, there are many cycles. The worker 110 is allowed to send the collected charges to the compensation word line driver 106. The series connection of the second inverter 506, the third inverter 508, and the fourth inverter 510 can provide a propagation delay, thereby preventing an unstable operation mechanism of charge circulation.

Although FIG. 6 provides a detailed description of an embodiment of the feedback controller 116, the present disclosure considers other embodiments of the feedback controller 116. For example, the feedback controller 116 may include more or fewer inverters, different types of transistors, more or fewer p-type transistors or other logic gates or circuits. In some embodiments, the feedback controller 116 may have fewer components. For example, the second inverter 506, the third inverter 508, the fourth inverter 510, and the second p-type transistor 512 can be omitted, so that the operation of the feedback controller 116 is only controlled by the memory controller 108 . In another exemplary embodiment, the third inverter 508 and the fourth inverter 510 may be omitted. In some other embodiments, the feedback controller 116 may have more components. For example, the feedback controller 116 may include a capacitor to store the electric charge recovered by the cyclic multiplexer 110, and to release the stored electric charge when it is enabled by the memory controller 108.

Figure 7 shows the third SRAM system 600. In some embodiments, the third SRAM system 600 includes a word line driver 604, a memory controller 608, a first SRAM array 6021, a second SRAM array 6022, a first cyclic multiplexer 6101, a second cyclic multiplexer 6102. First read/write block 6121, second read/write block 6122, first compensated word line driver 6061, second compensated word line driver 6062, first precharge circuit 6141, and first Two pre-charge circuit 6142. In some alternative embodiments, the third SRAM system 600 may optionally include a first feedback controller 6161 and a second feedback controller 6162. As shown in Figure 7, the third SRAM system 600 includes a first half L and a second half R, and the operation of each half is the same as the first SRAM system 100 without feedback controllers (6161 and 6162) , And the operation is like the second SRAM system 400 with feedback controller (6161 and 6162). The word line driver 604 and the memory controller 608 are configured so that the first SRAM array 6021 and the second SRAM array 6022 can be read or written independently. Each of the first half L and the second half R includes a charge recycling mechanism. Regarding the first half L, the charge recycling mechanism includes a first recycling multiplexer 6101 coupled to a first compensation word line driver 6061. Regarding the second half R, the charge recycling mechanism includes a second recycling multiplexer 6102 coupled to a second compensation word line driver 6062. The word line extending on the first SRAM array 6021 is coupled to both the first compensation word line driver 6061 and the word line driver 604. Similarly, the word lines extending on the second SRAM array 6022 are coupled to both the second compensation word line driver 6062 and the word line driver 604. The first compensation word line driver 6061 and the second compensation word line driver 6062 supply the regenerative charge to one end of the selected word line, which is far away from the word line driver 604.

The embodiments of the present disclosure provide benefits. The memory system according to the embodiment of the disclosure includes: a first word line driver disposed adjacent to one end of the SRAM array, and a second word line driver disposed adjacent to the other end of the SRAM array. Each word line is coupled to the first word line driver and the second word line driver. When the word line is selected, the first word line driver will transmit the access signal to the selected word line, and the second word line driver will provide the feedback signal to the selected word line. The feedback signal comes from the charge recycling mechanism, which collects the charge from the unselected SRAM cell through the bit line and the inverted bit line of the unselected SRAM cell by the cycle multiplexer. The collected charges will power the second word line driver to generate a feedback signal. The generation of the feedback signal does not require additional energy input. The feedback signal provided by the second word line driver will compensate for the voltage drop in the access signal caused by the impedance along the length of each word line, thereby reducing RC (resistance-capacitance) delay and enhancing memory The performance of the system.

The present disclosure provides a memory device. The memory device includes a word line driver, a cyclic multiplexer, a memory cell array, and a compensation word line driver. The word line driver is coupled to a plurality of word lines. The cyclic multiplexer is coupled to multiple bit lines and multiple anti-bit lines. The memory cell array includes a first end adjacent to the word line driver, a second end far from the word line driver, and a plurality of memory cells. Each memory cell is coupled to one of a plurality of word lines, one of a plurality of bit lines, and one of a plurality of anti-bit lines. The compensation word line driver is arranged adjacent to the second end of the memory cell array and is coupled to a plurality of word lines. The cyclic multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of inverted bit lines to the compensation word line driver.

In some embodiments, the memory device further includes a read/write block and a memory controller. The read/write block is coupled to a plurality of memory cells via a plurality of bit lines and a plurality of inverted bit lines. The memory controller is electrically coupled to the word line driver, the cyclic multiplexer, the compensation word line driver, and the read/write block. The memory controller is configured to: cause the word line driver to activate a group of word lines among the plurality of word lines, enable the compensation word line driver to be coupled to the group of word lines, and pass the first word line of the plurality of bit lines. A group of bit lines and a first group of inverted bit lines of a plurality of inverted bit lines enable the read/write block to read or write to the first group of memory cells among the plurality of memory cells, And the cyclic multiplexer is coupled to the second set of memory in the plurality of memory cells through the second set of bit lines in the plurality of bit lines and the second set of inverted bit lines in the plurality of inverted bit lines Body unit. The second group of memory cells is different from the first group of memory cells.

In some embodiments, each bit line and each inverted bit line are electrically coupled to the precharge circuit to be precharged to a positive power supply voltage (Vdd).

In some embodiments, when the memory controller couples the cyclic multiplexer to the second set of memory cells, the second set of bit lines and the second set of inverted bit lines are coupled to the compensation word line driver .

In some embodiments, the read/write block includes a row of decoders and a sense amplifier. The row decoder is coupled to a plurality of bit lines and a plurality of inverted bit lines. The sense amplifier is coupled to a plurality of bit lines and a plurality of inverted bit lines.

In some embodiments, the memory device further includes a feedback controller. The feedback controller is coupled to the cyclic multiplexer and the compensation word line driver. The feedback controller is configured to adjust the access signal from the compensated word line driver to the word line group.

In some embodiments, the feedback controller is coupled to the memory controller. The memory controller is configured to send an enable signal to the feedback controller to activate the feedback controller. The feedback controller is configured to couple the loop multiplexer to the second group of memory cells when activated.

The present disclosure provides a memory device. The memory device includes a first word line driver, a second word line driver, and a memory cell array. The first word line driver is coupled to a plurality of word lines and draws power from the first power source. The second word line driver is coupled to a plurality of word lines and draws power from a second power source different from the first power source. The memory cell array is sandwiched between the first word line driver and the second word line driver. The memory cell array includes multiple rows of memory cells, and each of the multiple rows of memory cells is coupled to one of a plurality of word lines.

In some embodiments, the memory device further includes a plurality of bit lines and a plurality of inverted bit lines. The memory cell array includes multiple rows of memory cells, and each memory cell of the multiple rows of memory cells is coupled to one of a plurality of bit lines and one of a plurality of inverted bit lines.

In some embodiments, the memory device further includes a loop multiplexer. The cyclic multiplexer is coupled to multiple bit lines and multiple anti-bit lines.

In some embodiments, the memory device further includes a read/write block. The read/write block is coupled to multiple bit lines and multiple inverted bit lines.

In some embodiments, the read/write block includes a row of decoders and a sense amplifier. The row decoder is coupled to a plurality of bit lines and a plurality of inverted bit lines. The sense amplifier is coupled to a plurality of bit lines and a plurality of inverted bit lines.

In some embodiments, the memory device further includes a memory controller. The memory controller is electrically coupled to the first word line driver, the cyclic multiplexer, the second word line driver, and the read/write block. The memory controller is configured to: cause the first word line driver to activate the word lines of one column, couple the second word line driver to the word lines of the column, and make the read/write block pair multiple columns The first group of memory cells in the memory cells reads or writes, and the cyclic multiplexer is through-coupled to the second group of memory cells in the plurality of rows of memory cells. The second group of memory cells is different from the first group of memory cells.

In some embodiments, the memory device further includes a feedback controller. The feedback controller is coupled to the cyclic multiplexer and the second word line driver. The feedback controller is configured to couple the cyclic multiplexer to the second word line driver corresponding to the enable signal from the memory controller.

The present disclosure provides a memory device. The memory device includes a memory cell array, a first word line driver, a second word line driver, and a charge recycling mechanism. The memory cell array includes a plurality of word lines, a plurality of bit lines, a plurality of inverted bit lines, and a plurality of memory cells. The plurality of word lines extend along the first direction from the first end of the memory cell array to the second end of the memory cell array. The bit line extends along a second direction perpendicular to the first direction. The inverted bit line extends along the second direction. Each memory cell is coupled to one of a plurality of word lines, one of a plurality of bit lines, and one of a plurality of inverted bit lines. The first word line driver is adjacent to the first end of the memory cell array, and the first word line driver is coupled to a plurality of word lines. The second word line driver is adjacent to the second end of the memory cell array, and the second word line driver is coupled to a plurality of word lines. The charge recycling mechanism is coupled to a plurality of bit lines, a plurality of inverted bit lines, and a second word line driver.

In some embodiments, the memory device further includes a read/write block and a memory controller. The read/write block is coupled to a plurality of memory cells via a plurality of bit lines and a plurality of inverted bit lines. The memory controller is electrically coupled to the first word line driver, the second word line driver and the read/write block. The memory controller is configured to: cause the first word line driver to activate a group of word lines among the plurality of word lines, couple the second word line driver to the group of word lines, and enable reading/writing The input block is coupled to the first set of bit lines of the plurality of bit lines and the first set of inverted bit lines of the plurality of inverted bit lines, and the charge recycling mechanism is coupled to the first set of the plurality of bit lines The second group of inverted bit lines of the two groups of bit lines and the plurality of inverted bit lines is used to collect charges on the second group of bit lines and the second group of inverted bit lines. The first group of bit lines are different from the second group of bit lines, and the first group of inverted bit lines are different from the second group of bit lines.

In some embodiments, the charge recycling mechanism includes a recycling multiplexer and a feedback controller. The cyclic multiplexer is coupled to multiple bit lines and multiple anti-bit lines. The feedback controller is coupled to the cyclic multiplexer and the second word line driver, and is configured to control the electrical coupling between the cyclic multiplexer and the second word line driver.

In some embodiments, the feedback controller includes a first inverter, a second inverter, a first p-type transistor, and a second p-type transistor. The first inverter includes a first input and a first output. The second inverter includes a second input and a second output. The first p-type transistor includes a first gate, a first source, and a first drain. The second p-type transistor includes a second gate, a second source, and a second drain. The first input of the first inverter is coupled to the memory controller. The first output of the first inverter is the first gate coupled to the first p-type transistor. The first source of the first p-type transistor is coupled to the cyclic multiplexer. The first drain of the first p-type transistor is coupled to the second word line driver. The second input of the second inverter is coupled to the second word line driver. The second output of the second inverter is the second gate coupled to the second p-type transistor. The second source of the second p-type transistor is coupled to the positive power supply voltage (Vdd). The second drain of the second p-type transistor is coupled to the first gate of the first p-type transistor.

In some embodiments, the memory controller is electrically coupled to the loop multiplexer and the feedback controller.

In some embodiments, the memory controller is configured to send an enable signal to the feedback controller to activate the feedback controller. The feedback controller is configured to couple the cyclic multiplexer to the second set of bit lines and the second set of inverted bit lines when activated.

Although the present invention has been invented as above in the preferred embodiment, it is not intended to limit the present invention. Anyone in the technical field including ordinary knowledge can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

2. PG-1: the first transmission gate transistor 4. PG-2: The second transmission gate transistor 6. PU-1: The first pull-up transistor 8. PU-2: The second pull-up transistor 12. PD-1: the first pull-down transistor 14. PD-2: The second pull-down transistor 16: first storage node 18: The second storage node 20: The first inverter 22: second inverter 10, 1011, 1012, 1013, 1021, 1022, 1023: SRAM cell 100: The first SRAM system 102: SRAM array 104,604: character line driver 106: Compensation character line driver 108,608: Memory controller 110: Loop Multiplexer 112: Read/write block 114: Precharge circuit 202: Line decoder 204: Sense Amplifier 206: Line number signal 208: Input data 210: output data 300: Time series 302: The first time series 304: second time series 306: Third Time Series 308: Fourth Time Series 400: Second SRAM system 501: enable signal 502: first inverter 504: The first p-type transistor 506: second inverter 508: third inverter 510: fourth inverter 512: second p-type transistor 600: Third SRAM system 6021: The first SRAM array 6022: Second SRAM array 6101: first loop multiplexer 6102: second loop multiplexer 6121: First read/write block 6122: Second read/write block 6061: First compensation character line driver 6062: Second compensation character line driver 6141: The first pre-charge circuit 6142: second pre-charge circuit BL, BL1-BL4: bit line BLB, BLB1-BLB4: reverse bit line D1: The first drain D2: second drain E1: first end E2: second end G1: first gate G2: second gate L: The first half R: The second half S1: first source S2: second source WL, WL1-WL4: character line

Figure 1 is a circuit diagram showing the SRAM cell. Figure 2 shows the first memory system according to some embodiments of the disclosure. Figure 3 shows the read/write block according to some embodiments of the disclosure. FIG. 4 is a schematic diagram showing the voltage signals on the word line driver, the word line, the bit line, and the inverted bit line according to some embodiments of the present disclosure. Figure 5 shows the second memory system according to some embodiments of the disclosure. Figure 6 shows the feedback controller according to some embodiments of the present disclosure. FIG. 7 shows the third memory system according to some embodiments of the disclosure.

100: The first SRAM system

102: SRAM array

104: character line driver

106: Compensation character line driver

108: Memory Controller

110: Loop Multiplexer

112: Read/write block

114: Precharge circuit

1011, 1012, 1013, 1021, 1022, 1023: SRAM cell

BL1-BL3: bit line

BLB1-BLB3: Inverted bit line

E1: first end

E2: second end

WL1-WL2: Character line

Claims (1)

A memory device includes: One-character line driver, coupled to the complex-digital line; A loop multiplexer, coupled to the complex bit line and the complex anti-bit line; A memory cell array, including: Adjacent to a first end of the character line driver; A second end far away from the character line driver; and A plurality of memory cells, wherein each of the memory cells is coupled to one of the word lines, one of the bit lines, and one of the inverted bit lines; and A compensating word line driver, arranged adjacent to the second end of the memory cell array and coupled to the word line, The loop multiplexer is configured to selectively couple one or more of the bit lines or one or more of the inverted bit lines to the compensation word line driver.

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