TW202125715A - Semiconductor device - Google Patents

Abstract

A static random-access memory (SRAM) semiconductor device including a memory unit. The memory unit includes a bit array arranged in rows and columns. The columns are defined by a plurality of bit line pairs connecting to a plurality of memory cells in the column. The memory unit also includes an edge area adjacent an edge row of the bit array, wherein the edge row includes a plurality of dummy memory cells. The memory unit further includes a plurality of bit line drivers adjacent the bit array and opposite the edge area. The bit line drivers are for driving the bit lines with data to the memory cells during a write operation. The dummy memory cells include a write assist circuit for each bit line pair. The write assist circuit is used for facilitating the writing of the data on the bit line pairs to the memory cells.

Description

Semiconductor device

This disclosure relates to a semiconductor device, particularly a semiconductor device that improves the read/write margin of an SRAM cell.

The semiconductor integrated circuit (IC) industry is growing exponentially. Technological advances in IC materials and IC design have produced multiple IC generations, each of which has smaller and more complex circuits than the previous IC generation. In the process of IC development, the geometric dimensions (for example, the smallest component (or circuit)) that can be made by the process will decrease, and the functional density (for example: the number of connected components per chip area) will generally increase. This miniaturization process provides advantages by increasing production efficiency and reducing related costs. This miniaturization also increases the complexity of the IC manufacturing process and manufacturing.

Static random-access memory (SRAM) generally refers to any memory or storage device that can retain stored data only when power is applied. In order to save power and improve energy efficiency, and to reduce the leakage current in the OFF state, it is usually helpful to reduce the power supply voltage. However, the reduction of the power supply voltage is limited by the minimum threshold voltage (Vcc-min). When working with a power supply voltage close to or lower than Vcc-min, the SRAM chip may experience increased failure rate or even failure. For example, the speed of the write operation depends on the discharge speed, which in turn depends on the applied voltage. When the power supply voltage is close to or lower than Vcc-min, this discharge becomes inefficient, and the speed and/or stability are low. For the bit cells around the SRAM chip far away from the power supply, this challenge is even more serious. This is because the resistance of the bit line further reduces the voltage applied to these elements. As the manufacturing process continues to shrink, the resistance of the bit line increases, further exacerbating the problem.

The present disclosure provides a semiconductor device. The semiconductor device includes a bit array, an edge area, and a plurality of bit line drivers. The bit array is arranged in plural columns and plural rows, where the rows are defined by the plural bit line pairs connected to the plural memory elements in the rows. The edge area is adjacent to the edge row of the bit array, and the edge row includes a plurality of redundant memory elements. The plural bit line drivers are adjacent to the bit array and opposite to the edge area. The redundant memory device includes a write assist circuit for each of the bit line pairs.

The present disclosure provides a semiconductor device. The semiconductor device includes an array of memory elements, a plurality of bit line pairs, a plurality of bit lines, and a plurality of bit line drivers. The memory element array includes a plurality of memory elements, the memory elements are arranged in a plurality of rows along a first direction, and are arranged in a plurality of rows along a second direction different from the first direction. A plurality of bit line pairs connect the memory elements in each of the above rows. The multiple-digit cell lines connect the memory elements in each of the above-mentioned lists. The multiple bit line drivers are connected to the multiple bit lines of the bit line pair, and the bit line drivers are adjacent to the first row of the memory element array. The memory cell array includes a row of redundant elements, which is a distance away from the bit line driver. Each of the redundant elements is modified from the remaining memory elements to include a write assist device connected to at least one bit line of each of the bit line pairs.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a memory element array, a plurality of write auxiliary circuits, and a plurality of wires. The substrate has a first area and a second area. The memory element array is in the first region. The memory element array includes a plurality of memory elements, the memory elements are arranged in a plurality of rows along a first direction, and are arranged in a plurality of rows along a second direction different from the first direction. The complex write auxiliary circuit is in the second area. The plurality of wires electrically couple the memory element array to the writing auxiliary circuit. Each of the wires electrically couples a row of the memory device to one of the write auxiliary circuits. The second area is a redundant area of the substrate. The redundant area is far away from the driver circuit for driving data on the wires, and is separated from the driver circuit by the memory element array.

This disclosure provides many different embodiments or examples to implement different features of the case. The following disclosure describes specific embodiments of each component and its arrangement in order to simplify the description. Of course, these specific examples are not meant to be limiting. For example, if the present disclosure describes that a first feature is formed on or above a second feature, it means that it may include an embodiment in which the first feature is in direct contact with the second feature, or it may include The additional feature is formed between the first feature and the second feature, and the first feature and the second feature may not be in direct contact with each other. In addition, the same reference symbols and/or marks may be used repeatedly in different embodiments of the present disclosure below. These repetitions are for the purpose of simplification and clarity, and are not used to limit the specific relationship between the different embodiments and/or structures discussed.

In addition, it is related to space terms. For example, "below", "below", "lower", "above", "higher" and similar terms are used to facilitate the description of one element or feature and another element(s) in the figure. Or the relationship between features. In addition to the orientations depicted in the drawings, these spatially related terms are intended to include different orientations of the device in use or operation. In addition, the device may be turned to different orientations (rotated by 90 degrees or other orientations), and the spatially related words used here can also be interpreted in the same way.

The present disclosure generally relates to semiconductor device and circuit design, and more specifically relates to memory arrays, such as static random access memory (SRAM).

FIG. 1 shows a semiconductor device 100 having a memory unit 102. As shown in FIG. The semiconductor device can be a microprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a digital signal processor (DSP). The memory unit 102 may be a single-port static random access memory (SRAM), a dual-port SRAM macro, or other types of memory. In this embodiment, the memory unit 102 is an embedded SRAM used in the semiconductor device 100. It should be understood that other array types of devices, such as stand-alone SRAM devices, can also benefit from one or more embodiments of the present disclosure.

The memory unit 102 includes one or more memory bit blocks for storage. The semiconductor device 100 also includes a peripheral logic circuit adjacent to the memory unit 102. The peripheral logic circuit is used to implement various functions, such as address decoding, character/bit selector, data driver, and memory self-test (memory self-test). testing) and so on. Each memory bit and logic circuit can be implemented with various P-type metal oxide semiconductor (PMOS) and N-type metal oxide semiconductor (NMOS) transistors, such as planar Transistor, Fin Field-Effect Transistor (FinFET), magnetic random access memory (MRAM), gate-all-around (GAA) nanochip Transistors, GAA nanowire transistors or other types of transistors. In addition, the memory cell 102 and the logic circuit may include various contact features (or contacts), vias, and vias for connecting the source, drain, and gate electrodes (or terminals) of the transistor. Metal wires to form integrated circuits.

Still referring to FIG. 1, for illustrative purposes, the memory unit 102 is shown as a single memory block, and it should be understood that there may be more blocks as needed. The memory unit 102 includes an edge area 104. In this embodiment, the edge area 104 is located at the edge of the memory cell and is longitudinally oriented along the direction X. In this embodiment, the edge area 104 does not contain memory bits, and is used to implement various peripheral circuits, including a well pick-up (WPU) area. The WPU area provides a well picking structure for supplying voltage (or bias) to the N-well and P-well in the memory unit 102. The memory cell 102 also includes a memory bit array 106 adjacent to the edge area 104. The memory bit array 106 includes memory bits of the memory cell 102. The memory cell 102 also includes an area for the bit line driver 108. The bit line driver area provides drivers for bit lines (bit lines BL) and complementary bit lines (bit lines BLB), and each driver pair is used for each memory bit in the memory cell 102. In this embodiment, the bit line driver 108 and the edge area 104 are arranged on both sides of the memory bit array 106.

Referring to FIG. 2, in order to simplify the example, according to the x-y axis shown in the figure, the memory bit array 106 includes 48 memory elements 120, and the memory elements 120 are arranged in a plurality of columns and rows. Continuing this example, each memory device is a six transistor (6T) memory device connected to a word line WL and a pair of bit lines BL and BLB. Each bit line pair (bit line BL, BLB) is also connected to a corresponding pair of bit line drivers 108. The word line WL is selected by the decoded row address, so that a single column is selected for read or write operations at any time.

The memory block (memory block) may include one or more redundant rows of memory elements, and in this embodiment, the memory bit array 106 is adjacent to the edge area 104 (Figure 1) and is connected to the bit A redundant column 128 is provided on the opposite edge of the meta line driver 108. In addition, in this embodiment, the redundant row 128 of memory devices is one-row thick, that is, it is a single row of redundant memory devices. In other embodiments, the redundant row 128 may have multiple rows of redundant memory elements.

There are reasons for providing redundant rows of memory components. For example, compared with the peripheral area of the memory bit array 106, the active/isolated area of the memory device area usually has a difference. As a result, the rows of memory devices adjacent to the peripheral area (for example, the edge area 104) are usually unused (redundant).

For the memory write operation, the bit line driver 108 uses the data to be stored in the memory element 120 of the specific row selected by the corresponding word line WL to drive the corresponding bit lines BL and BLB. Arrow 130 is provided to show the transmission line effect of bit lines BL, BLB. With the advancement of technology, the line width and thickness of the bit lines BL and BLB have become smaller and smaller. Similarly, the number of columns of memory devices and the lengths of bit lines BL and BLB have become longer and longer. The arrow 130 shows that the resistor 132 is included, and the resistor 132 further represents the transmission line effect of the bit line. That is, as each bit line BL, BLB extends away from its corresponding driver, there is a corresponding current-voltage drop (IR drop) along the line.

Referring to FIG. 3, in this embodiment, the memory device 120 is a six transistor (6T) SRAM. The 6T SRAM memory device includes a flip-flop 140 located between two transmission transistors T1 and T2. The gates of the transmission transistors T1 and T2 are commonly connected to the corresponding word line WL, so that the signal 142 on the word line WL enables the transmission transistor for data to flow from the flip-flop 140 or flow into the flip-flop 140 140 for read or write operations. The source/drain of the transmission transistor T1 is connected between the bit line BL and the flip-flop 140, and the source/drain of the transmission transistor T2 is connected between the bit line BLB and the flip-flop 140.

Although only one column of memory elements can be enabled at any one time, the transmission line effect of the bit line is adversely affected, making it relatively far away from the bit line driver 108 (section 2) The row of memory devices receives the changed signal. This is again shown by the resistors 144, 146 shown on the bit line. It should be understood that the resistance shown represents the inherent transmission line effect of the bit line.

As discussed in more detail below, in this embodiment, a write assist device 150 is provided on the bit line BL and on the end opposite to the bit line driver 108 (BL). Similarly, a write assist device 160 is provided on the end of the bit line BLB opposite to the bit line driver 108 (BLB). In one embodiment, the write assist devices 150 and 160 are transistors connected in a straight line between the corresponding bit line and the ground, and each gate is individually connected to the write assist signals 152 and 162. Also in this embodiment, the write auxiliary signals 152 and 162 are individually controlled. In another embodiment, the write assist signals 152, 162 are the same and are provided to both the write assist devices 150, 160. In this embodiment, the two write assist devices 150 and 160 may have transistors with opposite polarities.

The writing auxiliary signals 152 and 162 are driven by the writing auxiliary signal drivers 168 and 169, which may be located in the edge area 104. The circuit may be based on the write data (Data, DataB) provided to the corresponding bit line driver 108 and the write signal W indicating that the write operation is to be performed. In other words, if “0” is written to the bit line BL, the write signal 152 will be asserted instead of the write assist signal 162. Similarly, if "1" is written to the bit line BL, the write auxiliary signal 162 will be used instead of the write auxiliary signal 152. Such a drive can be composed of one or more logic gates, which are functions of the data to be written, the write enable signal and other timing signals, as known by those skilled in the art of.

The write assist devices 150, 160 are placed in the memory elements of the redundant column 128 (Figure 2). That is, it is possible to modify the unused memory components in the redundant row 128, and provide the write auxiliary driver/signal function with minimal modification and no or almost no increase in size. The modification of the memory elements in the redundant column will be described below with reference to FIGS. 4a and 4b.

In operation, when it is desired to write a "0" (or ground or low) voltage to the memory device 120, the bit line driver 108 (BL) drives the "0" onto the bit line BL. In addition, the write assist signal 152 is used, which also drives "0" from the write assist device 150 onto the bit line BL. At the same time, another bit line driver 108 (BLB) drives a "1" (or Vccmin or high) voltage to the bit line BLB. During this operation, the signal 142 is provided on the word line WL, so that the data from the bit line driver passes through the individual transmission transistors T1 and T2 and is stored in the flip-flop 140.

It should be understood that in this embodiment, there is only a writing auxiliary device/signal for writing "0" on the corresponding bit line, but no writing auxiliary device/signal for writing a "1" on the bit line. In another embodiment, the write assist device/signal can be used to write "1" on the corresponding bit line. In yet another embodiment, two write auxiliary drivers/signals can be used for each bit line to write "0" or "1" as needed.

Referring now to FIGS. 4a and 4b, a part of the memory unit 102 is shown. It is worth noting that the memory unit 102 is rotated by 90 degrees from the schematic diagrams in FIGS. 1 and 2. The memory unit 102 includes a plurality of bit cells in the memory bit array 106, which has the following features: Refer to the circuit described in Figure 3. This circuit includes a plurality of lines extending horizontally in a metal layer (for example, the zeroth metal layer (M0)), which includes a bit line pair (bit line BL, BLB) and a pair of power supplies Vss, VDD. As shown in the figure, these multiple lines connect multiple memory devices 120 including dummy cells.

The redundant column 128 of memory devices includes a plurality of lines extending vertically in the upper metal layer (for example, the first metal layer (M1)), which includes two write assist signals 152 and 162. As shown in FIG. 4a, these write auxiliary signals connect multiple redundant elements in the redundant column 128. In order to refer to Figure 4a, the two redundant elements are identified as redundant elements 128a and 128b.

For each redundant element in the redundant column 128, there are (at least) two source/drain regions 170, 176 electrically connected to the power source Vss (M0). The source/drain region 170 is connected to the power supply Vss (M0) through the M0-to-substrate contact 190, and the source/drain region 176 is connected to the power supply through the M0-to-substrate contact 196 Vss(M0). Each redundant element in the redundant column 128 further includes (at least) a source/drain region 172 electrically connected to the bit line BLB (M0) and a source/drain region 172 electrically connected to the bit line BL (M0). Source/drain region 174. The source/drain region 172 is connected to the bit line BLB(M0) through the contact 192 of M0 to the substrate, and the source/drain region 176 is connected to the bit line BL(M0) through the contact 194 of the M0 to the substrate .

In this embodiment, the well picking area (WPU) 180 is included in the edge area 104 between adjacent redundant elements in the redundant column 128. In this embodiment, WPU 180 is the N-well pickup area, although the P-well pickup area may be used instead. Two redundant lines 182, 184 are provided for each redundant element, which extend horizontally in the drawing. In this example, the redundant lines 182, 184 are also arranged on the WPU 180. Redundant lines 182b, 184b are related to redundant element 128b. The redundant line 182b is connected to the write auxiliary signal 152 through the via 198 from M1 to M0, and is connected to the gate electrode 202 of the write auxiliary device 150 through the contact 199 from M0 to the gate. The redundant line 184b is connected to the write auxiliary signal 162 through the M1 to M0 via 200, and is connected to the gate electrode 204 of the write auxiliary device 160 through the M0 to gate contact 201.

In operation, the write auxiliary signal 152 is used during a memory write operation in which "0" is written to one or more memory devices. The write assist signal 152 is transmitted to the redundant line 182b through the through hole 198, and then is transmitted to the gate electrode 202 of the write assist device 150 through the contact 199. The value of the signal transmitted to the gate electrode 202 depends on various design choices, but for illustrative reasons, the gate electrode 202 is used for the NMOS transistor of the writing auxiliary device 150. In this example, the write assist signal 152 is logic "1", so that the write assist device is "on". When the write assist device 150 is “on”, the source/drain region 174 is electrically connected to the source/drain region 176 through the channel. As described above, the source/drain region 176 is connected to the power supply Vss ("0") through the contact 196, and the source/drain region 174 is connected to the bit line BL through the contact 194. In this way, the bit line BL in the redundant element 128b will be driven to "0". At the same time, because this is a memory write operation in which "0" is written, the corresponding bit line driver 108 will also drive "0" on the bit line BL (will drive "0" on the corresponding bit line BLB 1"). This means that driving "0" at the two opposite ends of the bit line BL effectively reduces the transmission line effect (for example: inline resistance) by half.

During a memory write operation in which "1" is written to one or more memory devices, the write assist signal 162 is used. The writing signal is transmitted to the redundant line 184b through the via 200, and then transmitted to the gate electrode 204 of the writing auxiliary device 160 through the contact 201. The value of the signal transmitted to the gate electrode 204 depends on various design choices, but for illustrative reasons, the gate electrode 204 is used for the NMOS transistor of the write assist device 160. In this example, the write assist signal 162 is logic "1", so that the write assist device is "on". When the write assist device 160 is “on”, the source/drain region 172 is electrically connected to the source/drain region 170 through the channel. As described above, the source/drain region 170 is connected to the power supply Vss (“0”) through the contact 190, and the source/drain region 172 is connected to the bit line BBL through the contact 192. In this way, the bit line BLB in the redundant element 128b will be driven to "0". At the same time, because this is a memory write operation in which "1" is written, the corresponding bit line driver 108 will also drive "0" on the bit line BLB (will drive "0" on the corresponding bit line BL 0"). This means that driving "0" at the two opposite ends of the bit line BLB effectively reduces the transmission line effect (for example: line resistance) by half.

In some embodiments, it is worth noting that driving the bit line to "0" or the transmission line effect is disadvantageous than when the bit line is driven to "1". For these embodiments, only auxiliary "0" bit lines are needed. However, in other embodiments, another write auxiliary driver may be included to assist in driving the bit line to "1". According to the present disclosure, such a driver can be implemented in a very simple manner. For example, the polarity of the write assist signal and/or the transistor can be switched to be suitable for driving "1". In yet another embodiment, a single write auxiliary driver may be used to accommodate both driving "0" and "1".

Referring now to FIG. 5, in another embodiment, the memory unit 102 is shown as a single memory block. It should be understood that there can be more blocks as needed. The memory unit 102 includes an edge area 104 shown on the bottom side of the drawing and an edge area 244 shown on the top side of the drawing. In this embodiment, the edge regions 104 and 244 do not contain memory bits, and are used to implement a well pickup (WPU) structure. The WPU structure provides a well picking structure for supplying voltage (or bias) to the N-well and P-well in the memory unit 102. The memory unit 102 also includes a memory bit array 106 between the two WPU areas of the edge areas 104 and 244. The memory bit array 106 includes memory bits of the memory cell 102. The memory cell 102 also includes an area for the bit line driver 108. The bit line driver area provides drivers for the bit lines BL and BLB, and each driver pair is used for each memory bit in the memory unit 102. Also in this embodiment, there are redundant rows adjacent to the edge regions 104 and 244 at the edge of the memory bit array 106.

In operation, the implementation of the embodiment of FIG. 5 is similar to the embodiment of FIG. 1 to FIG. 4, except that the bit line driver 108 in the bit line driver area can drive the bit in either direction or in both directions. Line (up and down, as shown in the diagram). The advantage of this embodiment is that the bit line is already half of the bit line in the first embodiment (the same number of columns is given in each embodiment). Also in this embodiment, the write auxiliary driver and the corresponding circuit can be provided in both redundant columns to further assist in writing "0" and/or "1" to the corresponding memory device.

Several advantages are achieved by one or more of the above-mentioned embodiments. First, the write assist circuit provides an improved write speed. This is because the bit line length of the farthest column from the bit line driver to the memory device is effectively cut in half, thereby reducing the transmission line effect of the bit line. In addition to increasing the writing speed, it also provides an improved minimum power supply (Vccmin) for the memory bit array. Second, these improvements can be achieved with little or no additional area of peripheral circuitry. This means that by using edge circuits with redundant components, the overall size of the embedded memory array will not be increased.

In one embodiment, a semiconductor device including a memory cell is provided. The semiconductor device may be a memory device (such as static random access memory (SRAM)), or another device with embedded memory (such as embedded SRAM). The memory cell includes a bit array arranged in plural columns and plural rows. A row is defined by a plurality of bit line pairs connected to the plurality of memory devices in the row. The memory cell further includes an edge area adjacent to the edge row of the bit array, wherein the edge row includes a plurality of redundant memory elements. The memory cell also includes a plurality of bit line drivers adjacent to the bit array and opposite to the edge area. The bit line driver is used to drive the bit line with data to the memory device during the write operation. The redundant memory device includes a write assist circuit for each of the bit line pairs. The write auxiliary circuit is used to facilitate writing the data on the bit line pair into the memory device.

In some embodiments, the memory device is a static random access memory device.

In some embodiments, the write assist circuit includes a transistor for selectively connecting the bit line of the bit line pair to the power source during the write operation. The power source can be a grounded power source.

In some embodiments, the write assist signal is connected to the write assist circuit such that when a logic "0" is written on the bit line, the write assist circuit connects the bit line to the ground power supply. In addition, when writing logic "1" on the bit line, the write auxiliary circuit does not connect the bit line to the power source.

In some embodiments, the transistor includes a gate connected to a write assist signal driven outside the bit array.

In some embodiments, the transistor includes a first source/drain connected to the power source and a second source/drain connected to the bit line.

In another embodiment, a semiconductor device including an array of memory elements is provided. The memory element array includes a plurality of memory elements, the memory elements are arranged in a plurality of rows along a first direction, and are arranged in a plurality of rows along a second direction different from the first direction. The semiconductor device also includes a plurality of bit line pairs connecting the memory elements in each of the rows and a plurality of digital element lines connecting the memory elements in each of the rows. The multiple bit line drivers are connected to the multiple bit lines of the bit line pair, and the bit line drivers are adjacent to the first row of the memory element array. The memory cell array also includes a row of redundant elements, which is a distance away from the bit line driver, for example, on the side opposite to the bit line driver in the memory element array. Modify each of the redundant elements from the remaining memory elements to include at least one bit line write assist device connected to each of the bit line pairs. Each of the write assist devices can be controlled by a write assist signal used during a plurality of write operations.

In some embodiments, each of the write assist devices includes a transistor having a gate electrode connected to the write assist signal. The transistor may include a source connected to a power source (for example, ground) and a drain connected to one of the bit lines of the bit line pair.

In some embodiments, the power source is a grounded power source.

In some embodiments, the semiconductor device further includes an edge region adjacent to the redundant element column.

In some embodiments, the write assist signal is provided in the first metal layer and is connected to the gate electrode through the zeroth metal layer located in the well pick-up area in the edge area.

In some embodiments, the well picking area is located between adjacent redundant elements.

In another embodiment, an SRAM semiconductor device is provided. The SRAM semiconductor device includes a substrate having a first region and a second region. The substrate includes an array of memory elements in the first region. The array of memory elements includes a plurality of memory elements. The memory elements are arranged in a plurality of rows along a first direction and arranged in a second direction different from the first direction. Plural lines. The SRAM semiconductor device further includes a plurality of write auxiliary circuits in the second region; and a plurality of wires for electrically coupling the memory element array to the write auxiliary circuit. Each of the wires electrically couples a row of the memory device to one of the write auxiliary circuits. The second area is a redundant area of the substrate. The redundant area is far away from the driver circuit and is separated from the driver circuit by the memory element array.

In some embodiments, each of the wires is a bit line, and each of the write auxiliary circuits is configured to set the voltage level of the corresponding bit line to be less than the ground reference level.

In some embodiments, the second area is adjacent to the well strip area.

In some embodiments, the second area is an edge area of the substrate.

In one embodiment, a method for operating a semiconductor device including a memory cell is provided. The semiconductor device may be a memory device (such as static random access memory (SRAM)), or another device with embedded memory (such as embedded SRAM). The memory cell includes a bit array arranged in plural columns and plural rows. A row is defined by a plurality of bit line pairs connected to the plurality of memory devices in the row. The memory cell further includes an edge area adjacent to the edge row of the bit array, wherein the edge row includes a plurality of redundant memory elements. The memory cell also includes a plurality of bit line drivers adjacent to the bit array and opposite to the edge area. The bit line driver is used to drive the bit line with data to the memory device during the write operation. The redundant memory device includes a write assist circuit for each of the bit line pairs. The method includes using a write assist circuit to drive the write assist signal into the edge area. The write assist signal selectively enables the write assist circuit in the redundant memory device to facilitate writing the data on the bit line pair to the memory device.

The foregoing text outlines the features of many embodiments, so that those skilled in the art can better understand the present disclosure from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on the present disclosure, and achieve the same purpose and/or the same as the embodiments introduced herein. The advantages. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure. Without departing from the spirit and scope of the present disclosure, various changes, substitutions or modifications can be made to the present disclosure.

100: Semiconductor device 102: memory unit 104: edge area/first edge area 106: Memory bit array 108: bit line driver 120: Memory component 128: Redundant column 130: Arrow 132: Resistance BL, BLB: bit line WL: Character line T1, T2: transmission transistor 140: Flip-flop 144,146: resistance 150: Write assist device 160: Write assist device 152,162: Write auxiliary signal 168,169: Write auxiliary signal driver Data, DataB: write data W: write signal 108(BL): bit line driver 108(BLB): bit line driver 142: Signal Vss, VDD: power supply M0: Zero metal layer 128a, 128b: redundant components 170,176: source/drain region 190, 192, 194, 196: contact 172,174: source/drain region 180: Well Picking Area 182, 184, 182a, 182b, 184b, 184c: redundant line 198: Through hole 199: Contact 202: gate electrode 200: Through hole 201: Contact 204: gate electrode 244: edge area

This disclosure can be better understood from the subsequent embodiments and the accompanying drawings. Note that the schematic diagram is an example, and the different features are not shown here. The size of different features may be increased or decreased arbitrarily for clear discussion. FIG. 1 is a schematic diagram of an integrated circuit (IC) with embedded memory according to an embodiment of the disclosure. FIG. 2 is a top view of a part of the memory unit in FIG. 1 according to an embodiment of the present disclosure. FIG. 3 is a circuit diagram of a memory cell of the memory cell in FIG. 1 according to an embodiment of the present disclosure. Figures 4a and 4b are schematic diagrams of two redundant memory elements and a part of the well pick-up area of the memory cell in Figure 1 according to an embodiment of the present disclosure. FIG. 5 is a top view of a part of the memory cell in FIG. 1 according to an embodiment of the present disclosure.

none

BL, BLB: bit line

WL: Character line

102: memory unit

106: Memory bit array

108: bit line driver

120: Memory component

128: Redundant column

130: Arrow

132: Resistance

Claims (1)

A semiconductor device including: A memory unit, wherein the above-mentioned memory unit includes: A bit array, arranged in a plurality of columns and rows, wherein the row is defined by a plurality of bit line pairs connected to the plurality of memory elements in the row; An edge area adjacent to an edge row of the bit array, wherein the edge row includes a plurality of redundant memory elements; and A plurality of bit line drivers are adjacent to the above-mentioned bit array and opposite to the above-mentioned edge area, The redundant memory device includes a write auxiliary circuit for each of the bit line pairs.

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