TW202121597A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips. A manufacturing method of a semiconductor package is also provided.

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly to a semiconductor package of a semiconductor chip with a sensing region and a manufacturing method thereof.

In recent years, more and more electronic devices such as smart phones, tablet computers, and wearable electronic devices have gradually adopted sensors to control various manipulation functions provided by the devices. As the requirements for high manufacturability and quality of sensor packages are increasing, it is necessary to have a flexible and reliable method to package the sensors on a chip. Therefore, in order to achieve better operability and higher manufacturability of sensor packaging, how to improve the traditional chip packaging method has become an urgent issue to be solved.

The present invention provides a semiconductor package and a manufacturing method thereof, which can integrate and interconnect a semiconductor chip with a sensor in a wafer-level package and optimize it.

The invention provides a semiconductor package, which includes a plurality of first chips, a plurality of silicon through holes, at least one insulator, a first circuit structure and a first sealing body. Each first chip includes a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface, and a plurality of through holes extending from the first back surface toward the first active surface. A plurality of silicon vias are arranged in the plurality of through holes of the plurality of first chips and are electrically connected to the plurality of first chips. The insulator is disposed on the first active surface of the plurality of first chips. The first circuit structure is disposed on the first back surface of the plurality of first chips and is electrically connected to the plurality of silicon vias. The first sealing body laterally encapsulates a plurality of first wafers.

In an embodiment of the present invention, the above-mentioned first sealing body is disposed on the insulator.

In an embodiment of the present invention, the above-mentioned first sealing body further laterally encapsulates the insulator.

In an embodiment of the present invention, the above-mentioned first sealing body further laterally encapsulates the first circuit structure.

The present invention provides a method for manufacturing a semiconductor package. The method includes at least the following steps. A first chip is provided, wherein the first chip includes a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface, and a plurality of communication channels extending from the first back surface toward the first active surface Hole; forming a plurality of silicon through holes in a plurality of through holes of the first chip. Forming a first circuit structure on the first back surface of the first chip to be electrically connected to a plurality of silicon vias; disposing a second chip on the second circuit structure, wherein the second chip includes a first active surface facing the first chip The second active surface of the second chip is electrically connected to the first chip; and a second sealing body is formed on the first circuit structure to laterally encapsulate the second chip.

In an embodiment of the present invention, before forming a plurality of silicon vias, the first sealing body is formed to encapsulate the first chip laterally.

The present invention provides a method for manufacturing a semiconductor package. The method includes at least the following steps. A plurality of first chips are provided, and each first chip includes a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface, and a first back surface extending from the first back surface toward the first active surface A plurality of through holes; forming a plurality of silicon through holes in the plurality of through holes of the plurality of first chips; forming a first circuit structure on the first back surface of the first chip to be electrically connected with the plurality of silicon through holes; providing a carrier board Provide at least one insulator; join the carrier, the insulator and the first chip in the plurality of silicon vias and the first circuit structure, wherein the insulator is disposed between the carrier and the first chip, and the first active surface of the first chip faces An insulator, and the first chip is disposed on the board and physically separated from each other; forming a first sealing body on the carrier plate, wherein the first sealing body laterally encapsulates the first chip; and forming a second circuit structure in the first sealing Physically.

In an embodiment of the present invention, a plurality of conductive terminals are formed in the second circuit structure, wherein the plurality of conductive terminals are electrically connected to the first chip and the second chip.

In an embodiment of the present invention, the above-mentioned providing the first chip includes providing a carrier board. Form an insulator on the carrier board. The first chip is arranged on the insulator, wherein the first active surface of the first chip faces the insulator.

In an embodiment of the present invention, after the second circuit structure is formed as described above, the plurality of first chips are electrically connected to each other through the second circuit structure.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Hereinafter, reference numerals will be added to describe the preferred embodiments of the present invention in detail, and the description will be given with figures. Where possible, the same or similar components will be shown with the same reference numbers in the drawings.

1A to 1J are schematic cross-sectional views of a method of manufacturing a semiconductor package according to an embodiment of the invention. 2A and 2B are schematic enlarged cross-sectional views of the area TV of the method of manufacturing the semiconductor package in FIG. 1C.

Referring to FIG. 1A, a temporary carrier board 50 may be provided. The temporary carrier 50 may be a glass substrate, a wafer substrate or other suitable substrate materials, as long as the aforementioned materials can carry the packages formed thereon in the subsequent manufacturing process.

In some embodiments, the debonding layer 51 may be formed on the temporary carrier 50 to improve the releasability of the structure (such as an intermediate structure in the process) and the temporary carrier 50 in the subsequent manufacturing process. For example, the debonding layer 51 may be a light-to-heat-conversion (LTHC) release layer or other suitable release layer.

The insulator 110 may be formed on the temporary carrier 50. For example, the insulator 110 may be formed by a deposition process, a spin coating process, a slit coating process, or other suitable processes, using insulating materials such as polymers, curable resins, or Other suitable protective materials are formed. In an embodiment, the insulator 110 may be referred to as a cover layer or a hard coating layer.

In some embodiments, the insulator 110 may be formed on the debonding layer 51, but the invention is not limited thereto.

In an embodiment not shown, the insulator 110 may be directly formed on the temporary carrier 50.

After the insulator 110 is formed, a plurality of first wafers 120 may be arranged on the insulator 110. The number of first wafers 120 in FIG. 1A is only used for exemplary illustration, and the present invention is not limited thereto. For example, four first wafers 120 are exemplarily shown in FIG. 1A.

In one embodiment, after the first chip 120 is configured, the insulator 110 can be cured according to design requirements to improve the protection of the first chip 120.

The first chip 120 has a first active surface 122, a sensing area 122 a located on the first active surface 122, and a first back surface 124 opposite to the first active surface 122. The first chip 120 may be disposed on the insulator 110 in such a manner that the first active surface 122 faces the insulator 110.

In some embodiments, the first chip 120 may include a plurality of first conductive pads 126 located on the first active surface 122 and surrounding the sensing area 122a.

In some embodiments, the first conductive pad 126 on the first active surface 122 of the first chip 120 may be covered by the insulator 110. In an embodiment, the sensing area 122 a on the first active surface 122 of the first chip 120 and the first conductive pad 126 may be covered by the insulator 110.

In some embodiments, the first wafer 120 may be a sensing wafer. According to design requirements, any suitable sensor can be used on the first wafer 120, and the present invention is not limited to this.

In some embodiments, the first chip 120 may include an optical sensor, which may use a photodetector such as a photodiode, a phototransistor, or the like to sense light and receive The light energy is converted into an electrical signal for processing by the electronic circuit on the first chip 120. In this case, the insulator 110 may be semi-transparent or transparent to allow light to be transmitted to the sensing area 122 a of the first wafer 120.

In an embodiment, the first chip (such as the first chip in FIG. 4B, FIG. 5 or FIG. 6B) may include a molecular sensor which may use a chemical sensor, a biological sensor, or the like. In an embodiment not shown, the first wafer may be a microelectromechanical system (MEMS) wafer.

In an embodiment, the plurality of first wafers 120 may include a first wafer 120A (may be referred to as a first sensing wafer) and a first wafer 120B (may be referred to as a second sensing wafer). The photoelectric sensing material included in the sensing area 122a1 of the first chip 120A and the photoelectric sensing material included in the sensing area 122a2 of the first chip 120B may be of different forms. Therefore, the sensing wavelength range of the first wafer 120A may be different from the sensing wavelength range of the first wafer 120B. In other words, the plurality of first wafers 120 with optical sensors can respectively collect light of different wavelengths and provide complementary spectral responsivity. For example, the first chip 120A is an infrared (IR) detection chip and the first chip 120B is a visible light detection chip, but the invention is not limited thereto.

1B, the first sealing body 130 may be formed on the temporary carrier 50 to encapsulate the first chip 120 laterally.

In one embodiment, the first sealing body 130 may be formed by a molding process (such as an over-molding process) or other suitable processes, such as a resin (such as epoxy) ) Insulating materials or other suitable insulating materials. In an embodiment, the thickness of the aforementioned insulating material formed on the temporary carrier 50 may be greater than the thickness of the first wafer 120. In this case, for example, the thickness of the insulating material may be reduced by a grinding process, a polishing process, or other suitable processes, so as to expose the first back surface 124 of the first chip 120 .

In one embodiment, part of the bulk semiconductor material (such as bulk silicon) on the back side of the first wafer 120 (such as the side opposite to the first active surface 122) can be removed during the thickness reduction process. ), but the present invention is not limited to this.

The first back surface 124 of the first wafer 120 may be coplanar with the top surface 130 a of the first sealing body 130 (for example, the surface of the first sealing body 130 away from the temporary carrier 50 ).

After the first sealing body 130 is formed, a plurality of through holes 128 from the first back surface 124 toward the first active surface 122 may be formed on each first wafer 120 by etching, drilling or other suitable processes, so as to expose The first conductive pad 126.

1C, 2A, and 2B, a plurality of silicon vias (TSVs) 140 may be formed in the through holes 128 of each first chip 120 to be electrically connected to the first conductive pads 126. The first circuit structure 150 electrically connected to the silicon via 140 may be formed on the first back surface 124 of the first chip 120.

In some embodiments, part of the first circuit structure 150 may be formed on the top surface 130a of the first sealing body 130, and the present invention is not limited thereto.

In some embodiments, the conductive portion of the first circuit structure 150 and the conductive portion of the silicon via 140 may be formed together during the same process or a similar process (such as a deposition process), but the invention is not limited thereto.

In an embodiment, the wires used for signal transmission in the first chip 120 can be redistributed by the first circuit structure 150. In an embodiment, the first circuit structure 150 may be referred to as a redistribution layer (RDL).

An example of forming the silicon via 140 and the first circuit structure 150 is as follows.

2A, for example, the insulating material can be formed on the first back surface 124 of the first wafer 120 and in the through hole 128 by a deposition process, a spin coating process, or other suitable processes. The insulating material can be made of polymers such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or tetraethoxysilane (tetraethoxysilane). , TEOS) is made of silicon oxide formed by chemical vapor deposition (Chemical Vapor Deposition, CVD) or atomic deposition (Atomic layer deposition, ALD) or the like.

After the insulating material is formed, for example, an etching process may be used to remove the bottom of the insulating material in the through hole 128 to expose the first conductive pad 126 to form the insulating layer L1. For example, the insulating layer L1 may include a first insulating portion 142 and a second insulating portion 152. The first insulating portion 142 is formed on the inner sidewall 128a of the through hole 128, and the second insulating portion 152 is formed on the first back surface 124 and has a lotus root. Joined to the first insulating part 142.

In an embodiment, the second insulating portion 152 may completely cover the first back surface 124 of the first wafer 120, but the invention is not limited thereto. In an embodiment, the second insulating portion 152 may completely cover the first back surface 124 of the first chip 120 and the top surface 130a of the first sealing body 130, but the invention is not limited thereto.

2B, after the insulating layer L1 is formed, the barrier layer L2, the seed layer L3, and the conductive layer L4 may be formed in the through hole 128 of the first chip 120 and on the first back surface 124 to cover the insulating layer L1 and The first conductive pad 126.

In some embodiments, after the barrier layer L2 is formed, at least a portion of the insulating layer L1 on the first back surface 124 of the first chip 120 may be exposed through the barrier layer L2.

In an embodiment, the seed layer L3 may be conformally formed on the barrier layer L2 and the conductive layer L4 may be conformally formed on the seed layer L3. In other words, the barrier layer L2, the seed layer L3, and the conductive layer L4, which may conform to each other, are referred to as a single layer.

In an embodiment, the barrier layer L2 can be used as a diffusion barrier to prevent the conductive layer formed thereon from migrating into the dielectric. The seed layer L3 can improve the bonding force of the conductive layer L4 in the via 128. In an embodiment, the conductive layer L4 may be electroplated and filled in the through hole 128 to form a conductive pillar. The material of the barrier layer L2 may include titanium, tantalum or other suitable materials. The material of the seed layer L3 may include copper, gold, nickel or alloys thereof. The material of the conductive layer L4 may include copper, gold, silver, or a combination thereof.

For example, the barrier layer L2 may include a first barrier portion 144 and a second barrier portion 154. The first barrier portion 144 is formed in the through hole 128 and is coupled to the first conductive pad 126, and the second barrier The portion 154 is formed on the first back surface 124 and is coupled to the first barrier portion 144. The seed layer L3 covering the barrier layer L2 may include a first seed portion 146 and a second seed portion 156. The first seed portion 146 is formed in the through hole 128, and the second seed portion 156 is formed on the first back surface. 124 and coupled to the first seed part 146. The conductive layer L4 covering the seed layer L3 may include a first conductive portion 148 and a second conductive portion 158. The first conductive portion 148 is formed in the through hole 128, and the second conductive portion 158 is formed on the first back surface 124 and is coupled to The first conductive portion 148.

In some embodiments, the portions formed in the through holes 128 (such as the first insulating portion 142 of the insulating layer L1, the first barrier portion 144 of the barrier layer L2, the first seed portion 146 of the seed layer L3, and The first conductive portion 148) of the conductive layer L4 may be referred to as a silicon via 140.

At least the conductive portion formed on the first back surface 124 (such as the second barrier portion 154 of the barrier layer L2, the second seed portion 156 of the seed layer L3, and/or the second conductive portion 158 of the conductive layer L4) can be It is referred to as the first circuit structure 150. In an embodiment, the first circuit structure 150 may include conductive portions (such as the second barrier portion 154 of the barrier layer L2, the second seed portion 156 of the seed layer L3, and/or the second conductive portion of the conductive layer L4). Part 158) and an insulating part (such as the second insulating part 152 of the insulating layer L1).

The silicon via 140 extends through the first chip 120 and is electrically connected to the first circuit structure 150, and can provide input/output (I/O) contact with the first conductive pad 126 at the first back surface 124 of the first chip 120 .

1D, for example, a plurality of conductive terminals 160 may be formed on the first circuit structure 150 by an electroplating process, a ball placement process or other suitable processes.

In an embodiment, the first protection layer P1 having a plurality of openings P1 a may be formed on the first circuit structure 150 and/or the first sealing body 130. For example, a protective material (such as epoxy resin, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB)) may be formed on the first circuit structure 150 and the first sealing body 130. Then, a part of the protective material may be removed to form a first protective layer P1 having an opening P1a to expose at least a part of the first circuit structure 150. In an embodiment, the first protection layer P1 may include a photoresist material and the opening P1a is formed by an exposure and development process. Then, the conductive terminal 160 may be formed in the opening P1 a of the first protection layer P1 to directly contact the exposed first circuit structure 150 and electrically connect with the first chip 120. In an embodiment, the conductive terminal 160 may include a conductive ball, a conductive pillar, a conductive bump, or a combination thereof. However, the present invention is not limited to this. Conductive terminals 160 in other possible forms or shapes can be used according to design requirements. In order to increase the bonding force between the conductive terminal 160 and the first circuit structure 150, a soldering process and a reflowing process may be selectively performed.

1E, the second chip 210 can be configured on the first circuit structure 150 via the conductive terminals 160.

The second chip 210 may include a second active surface 212 facing the first back surface 124 of the first chip 120, a second back surface 214 opposite to the second active surface 212, and a plurality of second conductive surfaces distributed on the second active surface 212.接垫216。 Connecting pad 216. In other words, the second active surface 212 of the second chip 210 and the first back surface 124 of the first chip 120 may face each other. The second chip 210 may be electrically connected to the first chip 120 via the first circuit structure 150. In other words, the electrical signal passing through the first chip 120 can pass through the first conductive pad 126 to the silicon via 140, the first circuit structure 150, the conductive terminal 160 and the second conductive pad 216 of the second chip 210.

1F, the second sealing body 220 is formed on the first circuit structure 150 to laterally encapsulate the second chip 210 and the conductive terminals 160. In other words, the second chip 210 encapsulated by the second sealing body 220 can be disposed on the first chip 120 and the first sealing body 130.

In an embodiment, the second sealing body 220 may be similar to the first sealing body 130. For example, the second sealing body 220 can be formed by a molding process (such as an overmolding process) or other suitable processes, using an insulating material such as resin (such as epoxy resin) or other suitable insulating materials. In an embodiment, the thickness of the aforementioned insulating material formed on the first circuit structure 150 may be greater than the thickness of the second wafer 210. In this case, for example, the thickness of the insulating material can be reduced by a grinding process or other suitable processes, so as to expose the second back surface 214 of the second wafer 210.

In one embodiment, during the thickness reduction process, part of the bulk semiconductor material (such as bulk silicon) on the back side of the second wafer 210 (such as the side opposite to the second active surface 212) can be removed , But the present invention is not limited to this.

The second back surface 214 of the second wafer 210 may be coplanar with the top surface 220 a of the second sealing body 220. The top surface 220 a of the second sealing body 220 is a surface away from the first sealing body 130.

In one embodiment, after the second sealing body 220 is formed, for example, the plurality of through holes 222 surrounding the second wafer 210 may be formed in the second sealing by laser drilling, mechanical drilling, or other suitable processes.体220上。 Body 220. The through hole 222 may expose at least a part of the first circuit structure 150.

1G, a plurality of molded through holes (TMVs) 230 may be formed in the through holes 222 to be electrically connected to the first circuit structure 150 and the first chip 120. The second circuit structure 240 electrically connected to the molded through hole 230 may be formed on the second back surface 214 of the second chip 210.

In an embodiment, the wires used for signal transmission in the second chip 210 can be redistributed by the second circuit structure 240. In an embodiment, the second circuit structure 240 may be referred to as a redistributed circuit layer.

In an embodiment, the molded through hole 230 and the second circuit structure 240 may be formed together during the same process or a similar process (such as a deposition process), but the invention is not limited thereto.

For example, conductive materials (not shown) such as copper, aluminum, nickel or the like can be formed on the second back surface 214 of the second chip 210 by a sputtering process, a deposition process, an electroplating process or other suitable processes. In the through hole 222 of the upper and second sealing body 220. Then, the conductive material can be patterned by photolithography and etching processes to form a patterned conductive layer. A part of the patterned conductive layer formed in the through hole 222 may be referred to as a molded through hole 230 and another part of the patterned conductive layer formed on the second back surface 214 of the second wafer 210 may be referred to as a second circuit structure 240. In an embodiment, before the conductive material, a seed material may be formed on the second back surface 214 of the second wafer 210 and in the through hole 222 of the second sealing body 220.

1H, a plurality of conductive terminals 250 may be formed on the second circuit structure 240 to be electrically connected to the first chip 120 and the second chip 210.

In an embodiment, the second protective layer P2 having a plurality of openings P2a may be formed on the second sealing body 220 to cover the second circuit structure 240 and the second protective layer P2 may be exposed through the openings P2a of the second protective layer P2. At least a part of the circuit structure 240. The formation process of the second protection layer P2 may be similar to that of the first protection layer P1, and detailed description is omitted.

After the second protection layer P2 is formed, the conductive terminal 250 may be formed in the opening P2a of the second protection layer P2 to directly contact the exposed second circuit structure 240 and electrically connect to the second chip 210. For example, the conductive terminal 250 may include a conductive ball, a conductive pillar, a conductive bump, or a combination thereof formed by a ball planting process, an electroplating process, or other suitable processes. However, the present invention is not limited to this. In addition, in order to increase the bonding force between the conductive terminal 250 and the second circuit structure 240, a welding process and a reflow process can be selectively performed.

In an embodiment, the conductive terminal 250 may include a plurality of first elements 252 and a plurality of second elements 254. The first elements 252 are formed in the central region CR of the second chip 210, and the plurality of elements are formed around the center of the second chip 210 The peripheral area PR of the area CR. The size of the second element 254 may be larger than the size of the first element 252. In other words, the shortest distance from the top surface 252 a of the first element 252 to the second circuit structure 240 may be less than the shortest distance from the top surface 254 a of the second element 254 to the second circuit structure 240. In some alternative embodiments, the top surface 252 a of the first element 252 may be aligned with the top surface 254 a of the second element 254.

Please refer to FIG. 1I, the third chip 310 may be configured on the second circuit structure 240. For example, the third chip 310 may include a front surface 312 facing the second back surface 214 of the second chip 210 and a plurality of conductive connectors 314 distributed on the front surface 312. The conductive connector 314 of the third chip 310 can be electrically connected to the second circuit structure 240.

In one embodiment, before the conductive terminals 250 are formed, the third chip 310 may be disposed on the second circuit structure 240. In this case, after the third chip 310 is configured on the second circuit structure 240 using flip-chip technology, the first element 252 forming the conductive terminal 250 may be omitted. In other words, the third chip 310 can be directly electrically connected to the second circuit structure 240 through the conductive connector 314, which can serve as the first element 252, so the first element 252 forming the conductive terminal 250 may be unnecessary.

In an embodiment, the primer 316 may be formed between the gap between the third chip 310 and the second protective layer P2 to improve the reliability of the attaching process. In an exemplary embodiment, the third chip 310 as a memory is electrically connected to the first chip 120 having the sensing region 122a and the second chip 210 as a processor. In this case, the third wafer 310 can be used for various applications under the processing of the second wafer 210.

In one embodiment, a third chip 310 with more than one different function may be provided on the second circuit structure 240. The number of third wafers 310 shown in FIG. 1I is only shown as an example and the present invention is not limited thereto.

The singulation process can be performed and the temporary carrier 50 can be removed, so that the manufacturing process of the semiconductor package 100 as shown in FIG. 1J is substantially completed.

In an embodiment, after the third wafer 310 is configured, a dicing process may be performed. After the singulation process, the temporary carrier 50 can be removed from the insulator 110. For example, external energy such as ultraviolet laser, visible light, or heat can be applied to the debonding layer 51 so that the insulator 110 can be peeled from the temporary carrier 50.

In an embodiment, the dicing process may be performed before the third wafer 310 is configured. The present invention does not limit the sequence of the dicing process and the process of disposing the third wafer 310.

The first chip 120, the second chip 210, and the third chip 310 can be integrated by the above-mentioned manufacturing method of the semiconductor package 100, and the operating performance and manufacturability of the semiconductor package 100 can be improved.

3A to 3D are schematic cross-sectional views of a method of manufacturing a semiconductor package according to an embodiment of the present invention. The manufacturing method of this embodiment is similar to the description of the embodiment of FIGS. 1A to 1J, and the description of the manufacturing process may be omitted.

Referring to FIG. 3A, the through silicon via 440 may be a conductive pillar, and the through silicon via 440 is filled in the through hole 128 of the first chip 120 to be electrically connected to the first circuit structure 150. For example, the conductive layer L4 of the uppermost layer in FIG. 2B may be formed into the insulating layer L1, the barrier layer L2, and the seed layer L3 and then filled in the through hole 128. Next, after forming the first circuit structure 150 and the silicon via 440, the first protection layer P1 may be formed on the first circuit structure 150 and the first sealing body 130. The first protection layer P1 has an opening P1 a exposing at least a part of the first circuit structure 150. Then, a plurality of molded through holes 530 may be formed on the exposed first circuit structure 150.

For example, the photoresist material can be spin-coated, and the photoresist material is baked and lithographic (ie, exposure and development process) to form a patterned photoresist with a predetermined pattern on the first protective layer P1 Layer (not shown). The partially exposed first circuit structure 150 may be further exposed to the patterned photoresist layer. Next, an electroplating process or other suitable processes may be used to form a molded through hole 530 on the first circuit structure 150 further exposed by the patterned photoresist layer. After the molded via 530 is formed, the patterned photoresist layer can be removed by, for example, etching, ashing, or other suitable removal processes.

Referring to FIG. 3B, after forming the molded via 530, the second chip 510 can be configured by flip chip bonding on the first circuit structure 150. In other words, in this embodiment, the first chip 120 and the second chip 510 using flip chip technology can be electrically connected via the second conductive pads 516 distributed on the second active surface 512. Compared with the embodiment shown in FIG. 1E, in this embodiment, the formation of conductive terminals between the first wafer 120 and the second wafer 510 can be omitted. In an embodiment, the formed through-molding hole 530 may surround the first chip 120, and the second chip 510 may be disposed on the first circuit structure 150, and the second chip 510 may cover the first chip 120. Then, the second sealing body 220 may be formed to laterally encapsulate the second wafer 510 and the molded through hole 530. The forming process of the second sealing body 220 may be similar to the embodiment shown in FIG. 1F, and detailed description is omitted. For further electrical connection, the thickness of the second sealing body 220 may be reduced to expose at least a part of the molded through hole 530.

Referring to FIGS. 3C and 3D, after the second sealing body 220 is formed, the second circuit structure 540 may be formed on the molded through hole 530 and the second back surface 514 of the second chip 510. For example, the second protection layer P2' having a plurality of openings P2a' may be formed on the second sealing body 220 and the second chip 510, and the opening P2a' exposes at least a part of the molded through hole 530. Next, the second circuit structure 540 may be formed in the opening P2a' of the second protection layer P2'. In one embodiment, the forming process of the second protection layer P2' and the second circuit structure 540 may be performed multiple times to obtain a multilayer circuit according to the requirements of the circuit design. For further electrical connection, the uppermost second protective layer P2' may have an opening P2a' exposing at least a part of the top second circuit structure 540. After the second circuit structure 540 is formed, the subsequent manufacturing process may be similar to the description in the embodiments of FIGS. 1H to 1J, and detailed description is omitted. After the singulation process is performed and the temporary carrier 50 is removed, the process of the semiconductor package 200 as shown in FIG. 3D is substantially completed.

Based on the above, the insulator covering the first active surface of the first chip can protect the sensing area on the first active surface to avoid damage in the subsequent manufacturing process. In addition, the distance between the insulator and the sensing area is minimized to improve the sensing capability of the semiconductor package. The second active surface of the second chip faces the first back surface of the first chip. In addition, the first circuit structure and the silicon via are electrically connected between the first chip and the second chip. In this way, the semiconductor package can maintain a short electron transmission path between the first chip and the second chip, so as to reduce signal transmission, lower capacitance, and achieve better circuit performance. In addition, the surface of the third chip with the conductive connector faces the second back surface of the second chip and is electrically connected to the first chip and the second chip via the first circuit structure and the second circuit structure. In this way, the manufacturing method of the semiconductor package can integrate the first chip, the second chip and the third chip, and can achieve better operation efficiency and better manufacturability.

4A to 4D are schematic cross-sectional views of a method of manufacturing a semiconductor package according to an embodiment of the invention. 4E is a schematic top view of a method of manufacturing a semiconductor package according to an embodiment of the present invention. For example, FIG. 4E may be a top view of the structure of FIG. 4A.

Please refer to FIG. 4A and FIG. 4E, a permanent carrier board 53 may be provided. The permanent carrier 53 may include a glass substrate, a wafer substrate, a metal substrate, a laminated substrate or other suitable substrate materials, as long as the aforementioned materials can carry the packages formed thereon in the subsequent manufacturing process.

In an embodiment, a plurality of insulators 411 may be formed on the permanent carrier board 53. The insulator 411 has at least one opening 412. The number of insulators 411 in FIG. 4A or FIG. 4E is only shown as an example and the present invention is not limited thereto. In an embodiment, the insulator 411 may be referred to as a dam structure.

In some embodiments, the insulator 411 and the permanent carrier board 53 may be in direct contact, but the present invention is not limited to this. In an embodiment not shown, the adhesive layer may be disposed between the insulator 411 and the permanent carrier board 53.

In an embodiment, the material forming the insulator 411 may be epoxy resin, silicon-based resin, rubber or other suitable insulating materials, but the present invention is not limited thereto.

Referring to FIG. 4B, a plurality of first chips 420 may be disposed on the insulator 411. A plurality of silicon vias 140, a first circuit structure 427, and a plurality of conductive pillars 428 may be disposed on each first chip 420.

In an embodiment, one of the first wafers 420 may correspond to one of the insulators 411, but the invention is not limited thereto.

In an embodiment, the first wafer 420 may be similar to the first wafer 120. For example, the first chip 420 may include an active surface 422, a sensing area 422a on the active surface 422, a back surface 424 opposite to the active surface 422, and a plurality of through holes 128 extending from the back surface 424 toward the active surface 422.

In an embodiment, the first chip 420 may include a plurality of conductive pads 426 located on the active surface 422 and surrounding the sensing area 422a. For example, the first chip 420 may be disposed on the insulator 411 with the active surface 422 facing the insulator 411. In other words, the sensing area 422 a and the conductive pad 426 on the active surface 422 of the first chip 420 can be covered by the insulator 411. The sensing area 422 a of the first wafer 420 corresponds to the opening 412 of the insulator 411. In other words, the sensing area 422a of the first chip 420, the opening 412 of the insulator 411, and the permanent carrier 53 can form a cavity 413 (as indicated in FIG. 4C).

Referring to FIGS. 1C, 2B, and 4B, a plurality of silicon vias (TSVs) 140 may be formed in the through holes 128 of each first chip 420 to be electrically connected to the conductive pads 426. The formation process of the through-silicon via 140 can be the same or similar to the formation process of the through-silicon via 140, so the formation process of the through-silicon via will not be repeated here.

In some embodiments, the first circuit structure 427 may be configured on the back surface 424 of each first chip 420. In an embodiment, the first circuit structure 427 may include a plurality of conductive layers, a plurality of insulating layers, and a plurality of conductive vias. The corresponding part of the conductive layer and/or the corresponding part of the conductive via may form a corresponding circuit. The corresponding circuit of the first circuit structure 427 can be electrically connected to the corresponding silicon via 140. The first circuit structure 427 can be formed by a general semiconductor manufacturing process, and will not be repeated here.

In an embodiment, the first circuit structure 427 may be referred to as a redistributed circuit layer.

In one embodiment, the orthographic projection area of the first circuit structure 427 projected on the permanent carrier board 53 is substantially equal to the orthographic projection area of the first chip 420 projected on the permanent carrier board 53.

In an embodiment, a plurality of conductive pillars 428 may be disposed on the first circuit structure 427. The conductive pillar 428 may be electrically connected to the corresponding circuit of the first circuit structure 427.

4C, the sealing body 430 may be formed on the permanent carrier board 53 to laterally encapsulate the first chip 420, the first circuit structure 427 and the conductive pillars 428. The sealing body 430 may be formed by a molding process (such as an overmolding process). In an embodiment, the sealing body 430 may be formed of an insulating material such as resin (such as epoxy resin) or other suitable insulating materials.

In an embodiment, the thickness of the insulating material formed on the permanent carrier 53 may cover the top surface 428 a of the conductive pillar 428. In this case, for example, the thickness of the insulating material formed on the permanent carrier 53 may be reduced by a grinding process or other suitable processes to expose the top surface 428a of the conductive pillar 428 to form the sealing body 430.

In some embodiments, the top surface 428 a of the conductive pillar 428 may be coplanar with the top surface 430 a of the sealing body 430 away from the permanent carrier board 53.

In some embodiments, the sealing body 430 may laterally encapsulate the insulator 411.

Referring to FIG. 4D, the second circuit structure 440 may be formed on the sealing body 430. The corresponding circuit of the second circuit structure 440 may be electrically connected to the corresponding conductive pillar 428. The first chips 420 can be electrically connected to each other through the corresponding circuits of the second circuit structure 440. The second circuit structure 440 can be formed by a general semiconductor manufacturing process, so it will not be repeated here.

In an embodiment, the orthographic projection area of the second circuit structure 440 projected on the permanent carrier board 53 may be larger than the orthographic projection area of the first chip 420 projected on the permanent carrier board 53. In an embodiment, the second circuit structure 440 may be referred to as a fan-out redistribution line layer (FO RDL).

After the second circuit structure 440 is formed, a plurality of conductive terminals 460 may be formed on the second circuit structure 440. The forming process of the conductive terminal 460 can be the same or similar to the forming process of the conductive terminal 160, so the forming process of the conductive terminal will not be repeated here.

After the foregoing manufacturing process is performed, the semiconductor package 400 provided in this embodiment is substantially formed.

5 is a schematic cross-sectional view of a method of manufacturing a semiconductor package according to an embodiment of the present invention. The manufacturing method of this embodiment is similar to the embodiment shown in FIGS. 4A to 4E, so the description of the manufacturing process may be omitted.

Please refer to FIG. 5, before the first chip 420 is disposed on the permanent carrier 53, the insulator 411 may be disposed on the active surface 422 of the first chip 420. In other words, the first chip 420 with the insulator 411 on it can be disposed on the permanent carrier board 53.

After the insulator 411 and the first chip 420 are disposed on the permanent carrier board 53, the semiconductor package in this embodiment can be provided through steps similar to those shown in FIGS. 4C to 4D.

6A to 6D are schematic cross-sectional views of a method of manufacturing a semiconductor package according to an embodiment of the present invention. 6E is a schematic top view of a method of manufacturing a semiconductor package according to an embodiment of the present invention. For example, FIG. 6E is a schematic top view of the structure of FIG. 6A. The manufacturing method of this embodiment is similar to the embodiment shown in FIGS. 4A to 4E and the description of the manufacturing process may be omitted.

6A to 6E, the insulator 611 may be formed on the permanent carrier board 53. The insulator 611 has a plurality of openings 612. In an embodiment, the insulator 611 may be referred to as a barrier structure.

Referring to FIG. 6B, a plurality of first chips 420 may be disposed on the insulator 611. In an embodiment, more than one first wafer 420 may be disposed on one of the corresponding insulators 611, but the present invention is not limited to this.

The sensing area 422a of the first wafer 420 corresponds to the opening 612 of the insulator 611. In other words, the sensing area 422 of the first chip 420, the opening 612 of the insulator 611, and the permanent carrier board 53 may constitute a corresponding cavity 613.

In an embodiment, the insulator 611 may further have a plurality of microchannels. The microchannels can be formed by grooves on the surface of the insulator 611 (such as the surface facing the permanent carrier 53), but the present invention is not limited thereto. The micro channel can be connected to the corresponding cavity 613.

Referring to FIGS. 6C to 6D, after the first chip 420 is disposed on the permanent carrier board 53, the semiconductor package 600 of this embodiment can be provided through steps similar to those of FIGS. 4C to 4D (as indicated in FIG. 6D).

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

50: Temporary Carrier Board 51: Debonding layer 53: permanent carrier board 100, 200, 400, 600: semiconductor packaging 110, 411, 611: insulator 120, 120A, 120B, 420: the first chip 122: The first active side 122a, 122a1, 122a2, 422a: sensing area 124: The first back 126: The first conductive pad 128, 222: through hole 128a: inner wall 130: The first sealing body 130a, 220a, 252a, 254a: top surface 140, 440: Silicon perforation 142: The first insulating part 144: The first barrier part 146: The first seed part 148: The first conductive part 150, 427: the first circuit structure 152: The second insulating part 154: The second barrier part 156: The second seed part 158: The second conductive part 160, 250, 460: conductive terminals 210, 510: second chip 212, 512: second active surface 214, 514: second back 216, 516: second conductive pad 220: second sealing body 230, 530: Molded through holes 240, 440, 540: second circuit structure 252: The first element 254: second element 310: third chip 312: front surface 314: Conductive connector 316: Primer 412, 612, P1a, P2a, P2a’: opening 413, 613: Hole 422: active side 424: back 426: conductive pad 428: Conductive column 430: Seal body CR: Central District L1: insulating layer L2: barrier layer L3: Seed layer L4: conductive layer P1: The first protective layer P2, P2’: the second protective layer PR: Peripheral area TV: area

1A to 1J are schematic cross-sectional views of a method of manufacturing a semiconductor package according to an embodiment of the invention. 2A and 2B are schematic enlarged cross-sectional views of the area TV of the method of manufacturing the semiconductor package in FIG. 1C. 3A to 3D are schematic cross-sectional views of a method of manufacturing a semiconductor package according to an embodiment of the present invention. 4A to 4D are schematic cross-sectional views of a method of manufacturing a semiconductor package according to an embodiment of the invention. 4E is a schematic top view of a method of manufacturing a semiconductor package according to an embodiment of the present invention. 5 is a schematic cross-sectional view of a method of manufacturing a semiconductor package according to an embodiment of the invention. 6A to 6D are schematic cross-sectional views of a method of manufacturing a semiconductor package according to an embodiment of the present invention. FIG. 6E is a schematic top view of a method of manufacturing a semiconductor package according to an embodiment of the present invention.

100: Semiconductor packaging

110: Insulator

120, 120A, 120B: the first chip

122: The first active side

122a1, 122a2: sensing area

130: The first sealing body

140: Silicon perforation

150: The first circuit structure

160: conductive terminal

210: second chip

212: The second active surface

214: second back

220: second sealing body

230: Molded through hole

240: Second circuit structure

250: conductive terminal

252: The first element

254: second element

310: third chip

Claims (10)

A semiconductor package including: A plurality of first chips, each of the first chips includes a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface, and a back surface from the first back surface A plurality of through holes extending toward the first active surface; A plurality of silicon vias, arranged in the plurality of through holes of the first chip and electrically connected to the plurality of first chips; At least one insulator disposed on the first active surface of the first chip; A first circuit structure, configured on the first back surface of the first chip and electrically connected to the plurality of silicon vias; and The first sealing body encapsulates the plurality of first wafers laterally. The semiconductor package according to claim 1, wherein the plurality of first chips includes a first sensor chip and a second sensor chip, and the photoelectric sensor included in the sensing area of the first sensor chip The material is different from the photoelectric sensing material in the sensing area of the second sensing chip. The semiconductor package as described in claim 1, further including: There is only one second chip, which is disposed on the first circuit structure and includes a second active surface facing the first back surface of the first chip, wherein the second chip is connected to the first circuit structure The plurality of first chips are electrically connected. The semiconductor package as described in claim 1, further including: The permanent carrier, wherein the insulator is disposed between the permanent carrier and the plurality of first chips. The semiconductor package described in claim 4 further includes: The second circuit structure is circuit-connected with the first circuit structure, wherein a part of the first sealing body is disposed between the first circuit structure and the second circuit structure. The semiconductor package according to claim 5, wherein the orthographic projection area of the first circuit structure projected on the permanent carrier is substantially equal to the orthographic projection of the plurality of first chips on the permanent carrier Area, and the orthographic projection area of the second circuit structure projected on the permanent carrier board is larger than the orthographic projection area of the plurality of first chips projected on the permanent carrier board. A method for manufacturing a semiconductor package includes: A first chip is provided, wherein the first chip includes a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface, and a first back surface facing from the first back surface. A plurality of through holes extending from the first active surface; Forming a plurality of silicon vias in the plurality of through holes of the first chip; Forming a first circuit structure on the first back surface of the first chip to be electrically connected to the plurality of silicon vias; A second chip is arranged on the first circuit structure, wherein the second chip includes a second active surface facing the first back surface of the first chip, and the second chip and the first chip Electrical connection; and A second sealing body is formed on the first circuit structure to laterally encapsulate the second chip. The manufacturing method as described in claim 7, further including: Before disposing the second chip, a plurality of conductive terminals are formed on the first circuit structure, wherein after disposing the second chip, the second chip uses the plurality of silicon vias and the first circuit structure. A circuit structure is electrically connected with the plurality of conductive terminals and the first chip. The manufacturing method as described in claim 7, further including: A plurality of molded through holes are formed on the first circuit structure to be electrically connected to the plurality of silicon vias and the first chip, wherein after the second sealing body is formed, the A second sealing body laterally encapsulates the plurality of molded through holes; A second circuit structure is formed on the second back surface of the second chip opposite to the second active surface, wherein after the second circuit structure is formed, the second chip is molded through the plurality of through holes Electrically connected to the second circuit structure; and A third chip is arranged on the second circuit structure, wherein the third chip is electrically connected to the first chip and the second chip. A method for manufacturing a semiconductor package includes: A plurality of first chips are provided, and each of the first chips includes a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface, and A plurality of through holes extending from the back side toward the first active surface; Forming a plurality of silicon through holes in the plurality of through holes of the first chip; Forming a first circuit structure on the first back surface of the first chip to be electrically connected to the plurality of silicon vias; Provide carrier board; Provide at least one insulator; Bonding the carrier board, the insulator, and the plurality of first chips to the plurality of silicon vias and the first circuit structure, wherein the insulator is disposed on the carrier board and the plurality of first chips In between, the first active surface of the first chip faces the insulator, and the plurality of first chips are disposed on the carrier board and are physically separated from each other; Forming a first sealing body on the carrier plate, wherein the first sealing body laterally encapsulates the plurality of first chips; and A second circuit structure is formed on the first sealing body.

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