TW202121259A - Precision tuning for the programming of analog neural memory in a deep learning artificial neural network - Google Patents

Abstract

Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a nonvolatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Description

It is used to adjust the precision of the programming of analog neural memory in the deep learning artificial neural network

[Priority Claim] This application claims the priority of U.S. Patent Application No. 16/576,533 filed on September 19, 2019 and titled "PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK" right.

Several specific examples of accuracy adjustment algorithms and equipment are revealed, which are used to accurately and quickly deposit on floating gates of non-volatile memory cells in a vector matrix multiplication (VMM) array in artificial neural networks The correct amount of charge.

Artificial neural networks simulate biological neural networks (animal central nervous system, in particular, the brain) and are used for estimation or estimation may depend on a large number of inputs and generally unknown functions. Artificial neural networks usually include layers of interconnected "neurons" that exchange information with each other.

Figure 1 shows an artificial neural network, where the circles represent the inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to the input and be able to learn. Generally, a neural network includes multiple input layers. There are usually one or more interneuron layers and output neuron layers that provide the output of the neural network. Neurons at each level individually or collectively make decisions based on data received from synapses.

One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of sufficient hardware technology. In fact, a practical neural network relies on a very large number of synapses, which can achieve high connectivity between neurons, that is, extremely high computational parallelism. In principle, this complexity can be achieved using digital supercomputers or clusters of dedicated graphics processing components. However, in addition to high cost, these methods are also plagued by moderate energy efficiency compared to biological networks, mainly because biological networks perform low-precision analog calculations, so they consume much less energy. CMOS analog circuits have been used in artificial neural networks, but in view of the large number of neurons and synapses, the synapses in most CMOS implementations are too large.

The applicant previously disclosed an artificial (analogous) neural network using one or more non-volatile memory arrays as synapses in US Patent Application No. 15/594,439 incorporated by reference. The non-volatile memory array operates as an analog neuromorphic memory. The neural network device includes a first plurality of synapses, the first plurality of synapses are configured to receive a first plurality of inputs and to generate a first plurality of outputs from the first plurality of inputs, and a first plurality of nerves The element is configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: spaced source regions and drain regions formed in the semiconductor substrate, wherein the channel region is in the source region Extending between the drain region and the drain region; a floating gate installed above the first part of the channel region and insulated from the first part; and a non-floating gate installed above the second part of the channel region and connected to the first part Two parts are insulated. Each of the plurality of memory cells is configured to store a weight value corresponding to the number of electrons on the floating gate. The plurality of memory cells are configured such that the first plurality of inputs are multiplied by the stored weight values to generate the first plurality of outputs.

Each non-volatile memory cell used in the analog neuromorphic memory system must be erased and programmed to maintain a very specific and precise amount of charge, that is, the number of electrons, in the floating gate. For example, each floating gate must maintain one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.

One of the challenges in the VMM system is the ability to program selected units with the accuracy and fineness required for different values of N. For example, if the selected unit can include one of 64 different values, extremely high accuracy is required in the programming operation.

There is a need for an improved programming system and method suitable for use with the VMM in the analog neuromorphic memory system.

Several specific examples of accuracy adjustment algorithms and equipment are revealed, which are used to accurately and quickly deposit on floating gates of non-volatile memory cells in a vector matrix multiplication (VMM) array in artificial neural networks The correct amount of charge. The selected unit can thus be programmed with extremely high precision to maintain one of the N different values.

The artificial neural network of the present invention uses a combination of CMOS technology and a non-volatile memory array. Non-volatile memory unit

Digital non-volatile memory is well known. For example, US Patent No. 5,029,130 ("the '130 Patent") incorporated herein by reference discloses a separate gate type non-volatile memory cell array, which is a type of flash memory cell. This memory unit 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in the semiconductor substrate 12, wherein the channel region 18 is located between the source region and the drain region. The floating gate 20 is formed above and insulated from the first part of the channel region 18 (and controls the conductivity of the first part), and is formed above a part of the source region 14. The word line terminal 22 (which is usually coupled to the word line) has: a first part installed above the second part of the channel region 18 and insulated from the second part (and controlling the conductivity of the second part); and The second part, which extends on and above the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by the gate oxide. The bit line terminal 24 is coupled to the drain region 16.

The memory cell 210 is erased by placing a high positive voltage on the word line terminal 22 (where the electrons are removed from the floating gate), which causes the electrons on the floating gate 20 to pass through Fowler-Nordheim (Fowler-Nordheim). ) Tunneling from the floating gate 20 through the intermediate insulating member to the word line terminal 22.

The memory cell 210 is programmed by placing a positive voltage on the word line terminal 22 and a positive voltage on the source region 14 (where electrons are placed on the floating gate). The electron current will flow from the source region 14 (source line terminal) toward the drain region 16. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, the electrons will be accelerated and heated. Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20.

The memory cell 210 is read by placing a positive read voltage on the drain region 16 and the word line terminal 22 (this turns on the part of the channel region 18 below the word line terminal). If the floating gate 20 is positively charged (that is, the electrons are erased), the part of the channel region 18 below the floating gate 20 is also turned on, and current will flow across the channel region 18, which is sensed as erasing Divide or "1" status. If the floating gate 20 is negatively charged (that is, electronically programmed), the part of the channel area under the floating gate 20 is mostly or completely disconnected, and no current will flow (or very little current will flow) ) Channel area 18, which is sensed as programmed or "0" state.

Table 1 depicts may be applied to the terminal memory unit 110 for performing a read, erase and programmed typical voltage range of operation: Table 1: Operation of the flash memory 2 of the unit 210 WL BL SL Read 1 0.5-3V 0.1-2V 0V Read 2 0.5-3V 0-2V 2-0.1V Erase ~11-13V 0V 0V Stylized 1-2V 1-3μA 9-10V "Read 1" is the read mode in which the cell current is output on the bit line. "Read 2" is the read mode in which the cell current is output on the source line terminal.

FIG. 3 shows the memory cell 310, which is similar to the memory cell 210 of FIG. 2 with a control gate (CG) terminal 28 added. The control gate terminal 28 is biased at a high voltage such as 10 V when programming, is biased at a low or negative voltage such as 0 V/-8 V when erasing, and is at a low or intermediate range when reading, for example 0 V/2.5 V down bias. The other terminals are biased in a manner similar to that of FIG. 2.

4 depicts a four-gate memory cell 410, which includes a source region 14, a drain region 16, a floating gate 20 above the first part of the channel region 18, and a select gate above the second part of the channel region 18. 22 (usually coupled to the word line WL), the control gate 28 above the floating gate 20, and the erase gate 30 above the source region 14. This configuration is described in US Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating gates, which means that the gates are electrically connected or can be electrically connected to a voltage source. The programming is performed by injecting itself onto the floating gate 20 by heated electrons from the channel region 18. The erasing is performed by electron tunneling from the floating gate 20 to the erasing gate 30.

Table 2 depicts may be applied to the terminals of the memory unit 410 for performing the read, erase and programmed typical voltage range of operation: Table 2: FIG 4 the flash memory 410 of the operation unit WL/SG BL CG EG SL Read 1 0.5-2V 0.1-2V 0-2.6V 0-2.6V 0V Read 2 0.5-2V 0-2V 0-2.6V 0-2.6V 2-0.1V Erase -0.5V/0V 0V 0V/-8V 8-12V 0V Stylized 1V 1μA 8-11V 4.5-9V 4.5-5V "Read 1" is the read mode in which the cell current is output on the bit line. "Read 2" is the read mode in which the cell current is output on the source line terminal.

FIG. 5 shows the memory cell 510, which is similar to the memory cell 410 of FIG. 4, except that the memory cell 510 does not contain an erase gate EG terminal. Erasing is performed by biasing the substrate 18 to a high voltage and biasing the control gate CG terminal 28 to a low or negative voltage. Alternatively, the erasure is performed by biasing the word line terminal 22 to a positive voltage and the control gate terminal 28 to a negative voltage. The programming and reading are similar to the programming and reading in FIG. 4.

FIG. 6 depicts a triple-gate memory cell 610, which is another type of flash memory cell. The memory unit 610 is the same as the memory unit 410 of FIG. 4, except that the memory unit 610 does not have a separate control gate terminal. The erasing operation (where erasing is performed by using an erasing gate terminal) and reading operation are similar to the erasing operation and reading operation of FIG. 4, except that no control gate bias is applied. The programming operation is also performed without the control gate bias, and therefore a higher voltage must be applied to the source line terminal during the programming operation to compensate for the lack of the control gate bias.

Table 3 depicts the terminal unit 610 may be applied to the memory for performing the read, erase and programmed typical voltage range of operation: the operation of FIG flash memory cells 610. 6: TABLE 3 WL/SG BL EG SL Read 1 0.5-2.2V 0.1-2V 0-2.6V 0V Read 2 0.5-2.2V 0-2V 0-2.6V 2-0.1V Erase -0.5V/0V 0V 11.5V 0V Stylized 1V 2-3μA 4.5V 7-9V "Read 1" is the read mode in which the cell current is output on the bit line. "Read 2" is the read mode in which the cell current is output on the source line terminal.

FIG. 7 depicts a stacked gate memory cell 710, which is another type of flash memory cell. The memory cell 710 is similar to the memory cell 210 of FIG. 2 except that the floating gate 20 extends over the entire channel region 18 and the control gate terminal 22 (which will be coupled to the word line here) is above the floating gate 20 Outside of the extension, the floating gate 20 is separated by an insulating layer (not shown). The erasing, programming, and reading operations operate in a similar manner to that previously described for the memory cell 210.

Table 4 depicts a memory cell can be applied to the terminal 710 and the substrate 12 for performing the read, erase, and the typical voltage range of programmable operations: TABLE 4: operation flash memory cell 710 of FIG. 7 of CG BL SL Substrate Read 1 0-5V 0.1-2V 0-2V 0V Read 2 0.5-2V 0-2V 2-0.1V 0V Erase -8 to -10V/0V FLT FLT 8-10V / 15-20V Stylized 8-12V 3-5V/0V 0V/3-5V 0V

"Read 1" is the read mode in which the cell current is output on the bit line. "Read 2" is the read mode in which the cell current is output on the source line terminal. Optionally, in an array including columns and rows of memory cells 210, 310, 410, 510, 610, or 710, the source line can be coupled to one column of memory cells or two adjacent columns of memory cells . That is, the source line terminal can be shared by adjacent rows of memory cells.

In order to utilize a memory array containing one of the non-volatile memory cell types described above in the artificial neural network, two modifications are made. First, configure the lines so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as explained further below. Second, provide continuous (analogous) programming of memory cells.

Specifically, the memory state of each memory cell in the array (that is, the charge on the floating gate) can be continuously changed from the completely erased state to the fully programmed state, which is independent and independent of other memories. The interference of the body unit is the least. In another specific example, the memory state (that is, the charge on the floating gate) of each memory cell in the array can be continuously changed from the fully programmed state to the fully erased state, and vice versa. The method is independent and has the least interference to other memory units. This means that the cell storage is analog, or at least one of many discrete values (such as 16 or 64 different values) can be stored, which allows extremely precise and individual tuning of all cells in the memory array, and This makes the memory array ideal for storing the synaptic weights of the neural network and fine-tuning the synaptic weights.

The methods and methods described in this article can be applied to other non-volatile memory technologies, such as silicon oxide-nitride-oxide-silicon (SONOS, charge trap in nitride), metal-oxide-nitride-oxide Substance-silicon (MONOS, metal charge trap in nitride), resistive ram (ReRAM), phase change memory (PCM), magnetic ram (MRAM), ferroelectric ram (FeRAM), double-level or multi-level once Sexual programmable (OTP) and related electronic ram (CeRAM), but not limited to this. The methods and methods described herein can be applied to volatile memory technologies of neural networks, such as SRAM, DRAM, and other volatile synaptic units, but are not limited thereto. Neural network using non-volatile memory cell array

FIG. 8 conceptually illustrates a non-limiting embodiment of a neural network using a non-volatile memory array of a specific example of the present invention. This embodiment uses a non-volatile memory array neural network for facial recognition applications, but any other suitable application can be implemented using a neural network based on a non-volatile memory array.

S0 is the input layer. For this embodiment, the input layer is a 32×32 pixel RGB image with 5-bit accuracy (that is, three 32×32 pixel arrays, one array for each color R, G, and B, Each pixel has a 5-bit accuracy). Synapse CB1 traveling from input layer S0 to layer C1 applies different weight sets in some cases and shares weights in other cases, and scans the input image with a 3×3 pixel overlap filter (core), shifting the filter by 1 Pixels (or more than 1 pixel, as specified by the model). Specifically, the values of 9 pixels in the 3×3 part of the image (that is, called the filter or the core) are provided to the synapse CB1, where the 9 input values are multiplied by appropriate weights, and the After the output of the multiplication is summed, a single output value is determined and the single output value is provided by the first synapse CB1 for generating one of the pixels in the feature layer C1. The 3×3 filter is then shifted by one pixel to the right in the input layer S0 (that is, a row of three pixels is added on the right side, and a row of three pixels is discarded on the left side), thereby positioning the new filter Nine of the pixel values are provided to the synapse CB1, where the pixel values are multiplied by the same weight, and the second single output value is determined by the associated synapse. This process continues for all three colors and for all bits (precision values) until the 3×3 filter spans the entire 32×32 pixel image scan of the input layer S0. The procedure is then repeated using different weight sets to generate different feature maps of C1 until all feature maps of layer C1 have been calculated.

In the layer C1, in the specific example of the present invention, there are 16 feature maps, and each feature map has 30×30 pixels. Each pixel is a new feature pixel extracted by multiplying the input and the core, and therefore each feature map is a two-dimensional array, and therefore in this embodiment, layer C1 constitutes 16 layers of the two-dimensional array (remember , The layers and arrays mentioned in this article are logical relationships, not necessarily physical relationships, that is, the arrays may not necessarily be oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of the sixteen different synaptic weight sets applied to the filter scan. The C1 feature maps can all target different aspects of the same image feature, such as boundary recognition. For example, the first image (generated using the first weight set, which is used in all scans used to generate this first image) can identify circular edges, and the second image (using a second weight set different from the first weight set) Generated) can identify the edge of a rectangle, or the aspect ratio of certain features, etc.

The excitation function P1 (pooling) is applied before entering the layer S1 from the layer C1, and the pooling is derived from the values of the continuous non-overlapping 2×2 regions in each feature map. The purpose of the pooling function is to average the nearby locations (or the maximum function can also be used), for example to reduce the dependency of edge locations and reduce the data size before entering the next stage. At layer S1, there are 16 15×15 feature maps (that is, 16 different arrays of 15×15 pixels each). The synapse CB2 entering layer C2 from layer S1 scans the image in S1 with a 4×4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 12×12 feature maps. The excitation function P2 (pooling) is applied before entering layer S2 from layer C2, which pools values from continuous non-overlapping 2×2 regions in each feature map. At layer S2, there are 22 6×6 feature maps. The firing function (pooling) is applied at the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each graph in layer S2 via a separate synapse of CB3. At layer C3, there are 64 neurons. The synapse CB4 entering the output layer S3 from layer C3 fully connects C3 to S3, that is, every neuron in layer C3 is connected to every neuron in layer S3. The output at S3 includes 10 neurons, of which the highest output neuron determines the category. This output can, for example, indicate the identification or classification of the content of the original image.

Each synapse layer is implemented using an array or part of an array of non-volatile memory cells.

Figure 9 is a block diagram of a system that can be used for that purpose. The vector matrix multiplication (VMM) system 32 includes non-volatile memory cells and serves as a synapse between one layer and the next layer (such as CB1, CB2, CB3, and CB4 in FIG. 6). Specifically, the VMM system 32 includes a VMM array 33 including non-volatile memory cells arranged in columns and rows, an erase gate and word line gate decoder 34, a control gate decoder 35, and a bit line decoder. The decoder 36 and the source line decoder 37 are used for the respective input of the non-volatile memory cell array 33 for decoding. The input to the VMM array 33 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 also decodes the output of the VMM array 33 in this embodiment. Alternatively, the bit line decoder 36 may decode the output of the VMM array 33.

The VMM array 33 serves two purposes. First, it stores the weights to be used by the VMM system 32. Second, the VMM array 33 effectively multiplies the input by the weight stored in the VMM array 33, and adds the result by the output line (source line or bit line) to generate an output, which will be the input to the next layer Or the input to the final layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic circuits, and is also power efficient due to its on-site memory calculations.

The output of the VMM array 33 is supplied to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the VMM array 33 to produce a single value for that convolution. The difference summer 38 is configured to perform the summation of the positive weight input and the negative weight input to output a single value.

Then, the total output value of the differential summer 38 is supplied to the excitation function circuit 39 that rectifies the output. The excitation function circuit 39 can provide a sigmoid, a hyperbolic tangent (tanh), a ReLU function, or any other non-linear function. The rectified output value of the excitation function circuit 39 becomes an element of the feature map of the next layer (for example, C1 in FIG. 8), and is then applied to the next synapse to generate the next feature layer or final layer. Therefore, in this embodiment, the VMM array 33 constitutes a plurality of synapses (which receive their input from the previous neuron layer or from an input layer such as an image database), and the summer 38 and the excitation function circuit 39 constitute a plurality of synapses. Neurons.

The inputs (WLx, EGx, CGx, and BLx and SLx as appropriate) to the VMM system 32 in Figure 9 can be analog level, binary level, digital pulse (in this case, a pulse to analog converter PAC may be required to Convert the pulse to the appropriate input analog level) or digital bit (in this case, a DAC is provided to convert the digital bit to the appropriate input analog level), and the output can be analog level, binary level, digital pulse or digital bit Yuan (in this case, an output ADC is provided to convert the output analog level into digital bits).

Figure 10 is a block diagram depicting the use of many layers of the VMM system 32 (labeled here as VMM systems 32a, 32b, 32c, 32d, and 32e). As shown in FIG. 10, the input represented as Inputx is converted from digital to analog by the digital to analog converter 31, and is provided to the input VMM system 32a. The converted analog input can be voltage or current. The input D/A conversion of the first layer can be performed by using a function or a look-up table (LUT) that maps the input Inputx to an analog level suitable for the matrix multiplier of the input VMM system 32a. The input conversion can also be performed by an analog-to-analog (A/A) converter to convert the external analog input to a mapped analog input to the input VMM system 32a. The input conversion can also be performed by a digital-to-digital pulse (D/P) converter to convert an external digital input into one or more mapped digital pulses to the input VMM system 32a.

The output produced by the input VMM system 32a is provided as input to the next VMM system (hidden level 1) 32b, which in turn produces an output that is provided as input to the next VMM system (hidden level 2) 32c, etc. . The various layers of the VMM system 32 serve as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be an independent, physical system including a separate non-volatile memory array, or multiple VMM systems can use different parts of the same physical non-volatile memory array, or Multiple VMM systems can utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also time multiplex various parts of its array or neurons. The embodiment shown in Figure 10 contains five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c) and two fully connected layers (32d, 32e) ). Those skilled in the art will understand that this is merely illustrative, and the system may alternatively include more than two hidden layers and more than two fully connected layers. VMM array

FIG. 11 depicts a neuron VMM array 1100, which is particularly suitable for the memory unit 310 as shown in FIG. 3, and is used as a synapse and neuron part between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (at the top of the array). Alternatively, another reference array can be placed at the bottom.

In the VMM array 1100, the control gate line (such as the control gate line 1103) extends in the vertical direction (therefore, the reference array 1102 in the column direction is orthogonal to the control gate line 1103), and the gate line is erased (Such as erase gate line 1104) extends in the horizontal direction. Here, the input to the VMM array 1100 is arranged on the control gate lines (CG0, CG1, CG2, CG3), and the output of the VMM array 1100 appears on the source lines (SL0, SL1). In one specific example, only even-numbered columns are used, and in another specific example, only odd-numbered columns are used. The current placed on each source line (SL0, SL1, respectively) performs a summation function on all currents from the memory cells connected to that specific source line.

As described herein for the neural network, the non-volatile memory unit of the VMM array 1100, that is, the flash memory of the VMM array 1100, is preferably configured to operate in the secondary threshold area.

The non-volatile reference memory cell and the non-volatile memory cell described in this article are biased in weak inversion: Ids = Io * e ^(Vg-Vth)/nVt = w * Io * e ^(Vg)/nVt , where w = e ^(-Vth)/nVt where Ids is the drain-to-source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the heat Voltage k*T/q, where k is Boltzmann's constant, T is the temperature in Kelvin, and q is the electronic charge; n is the slope factor = 1 + (Cdep/Cox), where Cdep = depletion The capacitance of the layer and Cox is the capacitance of the gate oxide layer; Io is the current of the memory cell at the gate voltage equal to the threshold voltage, and Io is the same as (Wt/L)*u*Cox* (n-1) * Vt ^{2 is} proportional, where u is the carrier mobility of the memory cell, and Wt and L are the width and length, respectively.

In order to make the I to V log converter using memory cells (such as reference memory cells or peripheral memory cells) or transistors convert the input current Ids into input voltage, Vg: Vg= n*Vt*log [Ids/wp*Io] Here, wp is the w of the reference or peripheral memory unit.

In order to make the I to V log converter using memory cells (such as reference memory cells or peripheral memory cells) or transistors convert the input current Ids into input voltage, Vg: Vg= n*Vt*log [Ids/wp*Io]

Here, wp is the w of the reference or peripheral memory unit.

For a memory array used as a vector matrix multiplier VMM array, the output current is: Iout = wa * Io * e ^(Vg)/nVt , that is, Iout = (wa/wp) * Iin = W * Iin W = e ^{( Vthp-Vtha)/nVt} Iin = wp * Io * e ^(Vg)/nVt where wa = w of each memory cell in the memory array.

The word line or the control gate can be used as the input of the memory cell for the input voltage.

Alternatively, the non-volatile memory cells of the VMM array described herein can be configured to operate in the linear region: Ids = beta* (Vgs-Vth)*Vds; beta = u*Cox*Wt/L, Wα (Vgs-Vth), This means that the weight W in the linear region is proportional to (Vgs-Vth)

Word lines or control gates or bit lines or source lines can be used as inputs for memory cells operating in the linear region. The bit line or the source line can be used as the output of the memory cell.

For I to V linear converters, memory cells (such as reference memory cells or peripheral memory cells) or transistors or resistors operating in the linear region can be used to linearly convert input/output currents into input/output Voltage.

Alternatively, the VMM memory cell array of the described herein may be configured to operate in the saturation _{^{region: Ids = 1/2 * beta}} * (Vgs-Vth) 2; beta = u * Cox * Wt / L Wα (Vgs-Vth) ² , which means that the weight W is proportional to (Vgs-Vth) ²

Word lines, control gates or erase gates can be used as inputs for memory cells operating in the saturation region. The bit line or the source line can be used as the output of the output neuron.

Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (second threshold, linear, or saturation).

Other specific examples for the VMM array 33 of FIG. 9 are depicted in U.S. Patent Application No. 15/826,345, which is incorporated herein by reference. As described in that application, source lines or bit lines can be used as neuron output (current summation output).

FIG. 12 depicts a neuron VMM array 1200, which is particularly suitable for the memory cell 210 as shown in FIG. 2, and is used as a synapse between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of first non-volatile reference memory cells, and a reference array 1202 of second non-volatile reference memory cells. The reference arrays 1201 and 1202 arranged in the row direction of the array are used to convert the current input flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In fact, the first and second non-volatile reference memory cells are diode-connected through multiplexers 1214 (only partially depicted), in which current input flows into the multiplexers. The reference unit is tuned (eg, programmed) to the target reference level. The target reference level is provided by the reference mini-array matrix (not shown in the figure).

The memory array 1203 serves two purposes. First, it stores the weights to be used by the VMM array 1200 on its individual memory cells. Second, the memory array 1203 effectively makes the input (ie, the current input provided in the terminals BLR0, BLR1, BLR2, and BLR3) converted into input voltages by the reference arrays 1201 and 1202 to be supplied to the word lines WL0, WL1, and WL1. WL2 and WL3) are multiplied by the weights stored in the memory array 1203, and then all the results (memory cell currents) are added to generate an output on the respective bit lines (BL0 to BLN), and the output will be to Input to the next layer or input to the final layer. By performing multiplication and addition functions, the memory array 1203 eliminates the need for separate multiplication and addition logic circuits, and is also power efficient. Here, the voltage input is provided on the word lines WL0, WL1, WL2, and WL3, and the output appears on the respective bit lines BL0 to BLN during the read (inference) operation. The current placed on each of the bit lines BL0 to BLN performs a summation function on the currents from all non-volatile memory cells connected to that specific bit line.

Table 5 depicts the operating voltage for the VMM array 1200. The rows in the table indicate the word lines used for selected cells, the word lines used for unselected cells, the bit lines used for selected cells, the bit lines used for unselected cells, and the word lines used for selected cells. The voltage on the source line of the cell and the source line for unselected cells, where FLT indicates floating, that is, no voltage is applied. Column indicates the operations of reading, erasing and programming. Table 5 : Operation of the VMM array 1200 in Figure 12: WL WL- not selected BL BL- not selected SL SL- not selected Read 0.5-3.5V -0.5V/0V 0.1-2V (Ineuron) 0.6V-2V/FLT 0V 0V Erase ~5-13V 0V 0V 0V 0V 0V Stylized 1-2V -0.5V/0V 0.1-3 uA Vinh ~2.5V 4-10V 0-1V/FLT

FIG. 13 depicts a neuron VMM array 1300, which is particularly suitable for the memory unit 210 as shown in FIG. 2, and is used as a synapse and neuron part between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. The reference arrays 1301 and 1302 extend in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that in the VMM array 1300, the word lines extend in the vertical direction. Here, the input is set on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the output appears on the source line (SL0, SL1) during the read operation. The current placed on each source line performs a summation function on all currents from the memory cells connected to that specific source line.

Table 6 depicts the operating voltage for the VMM array 1300. The rows in the table indicate the voltages placed on each of the following: word lines for selected cells, word lines for unselected cells, bit lines for selected cells, and bits for unselected cells Element lines, source lines for selected cells, and source lines for unselected cells. Column indicates the operations of reading, erasing and programming. Table 6 : Operation of the VMM array 1300 in Figure 13 WL WL-not selected BL BL-not selected SL SL-not selected Read 0.5-3.5V -0.5V/0V 0.1-2V 0.1V-2V/FLT ~0.3-1V (Ineuron) 0V Erase ~5-13V 0V 0V 0V 0V SL-inhibition (~4- 8V) Stylized 1-2V -0.5V/0V 0.1-3 uA Vinh ~2.5V 4-10V 0-1V/FLT

FIG. 14 depicts a neuron VMM array 1400, which is particularly suitable for the memory unit 310 as shown in FIG. 3, and is used as a synapse and neuron part between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of first non-volatile reference memory cells, and a reference array 1402 of second non-volatile reference memory cells. The reference arrays 1401 and 1402 are used to convert the current inputs flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In fact, the first and second non-volatile reference memory units are diode-connected through multiplexers 1412 (only partly shown), in which current input flows to these multiplexers via BLR0, BLR1, BLR2, and BLR3 in. The multiplexers 1412 each include a respective multiplexer 1405 and a tandem transistor 1404 to ensure the bit line (such as BLR0) of each of the first and second non-volatile reference memory cells during a read operation Constant voltage on. The reference unit is adjusted to the target reference level.

The memory array 1403 serves two purposes. First, it stores the weights to be used by the VMM array 1400. Second, the memory array 1403 effectively makes the input (current input provided to the terminals BLR0, BLR1, BLR2, and BLR3), and the reference arrays 1401 and 1402 convert these current inputs into input voltages to be supplied to the control gates (CG0, BLR2, and BLR3). CG1, CG2, and CG3)) are multiplied by the weights stored in the memory array, and then all the results (cell currents) are added to produce an output, which appears on BL0 to BLN, and will be the input to the next layer or Input to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the input is provided on the control gate lines (CG0, CG1, CG2, and CG3), and the output appears on the bit lines (BL0 to BLN) during the read operation. The current placed on each bit line performs a summation function on all currents from the memory cells connected to that specific bit line.

The VMM array 1400 performs unidirectional calibration on the non-volatile memory cells in the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until it reaches the required charge on the floating gate. This can be performed, for example, using the sophisticated programming techniques described below. If too much charge is placed on the floating gate (so that the error value is stored in the cell), the cell must be erased and the sequence of partial programming operations must be restarted. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (this is known as page erase), and after that, each cell is partially programmed until the floating gate is reached The required electric charge on the extreme.

Table 7 depicts the operating voltage for the VMM array 1400. The rows in the table indicate the voltages placed on each of the following: word lines for selected cells, word lines for unselected cells, bit lines for selected cells, and bit lines for unselected cells Bit line, used for the control gate of the selected cell, used for the control gate of the unselected cell in the same sector as the selected cell, used for the unselected cell in a different sector from the selected cell The control gate is used for the erase gate of the selected cell, used for the erase gate of the unselected cell, used for the source line of the selected cell, and used for the source line of the unselected cell. These lines indicate reading, erasing, and programming operations. Table 7 : Operation of the VMM array 1400 in Figure 14 WL WL - not selected BL BL - not selected CG CG- the same sector not selected CG - not selected EG EG - not selected SL SL - not selected Read 0.5-2V -0.5V/ 0V 0.1-2V (Ineuron) 0V/FLT 0-2.6V 0-2.6V 0-2.6V 0-2.6V 0-2.6V 0V 0V Erase 0V 0V 0V 0V 0V 0-2.6V 0-2.6V 5-12V 0-2.6V 0V 0V Stylized 0.7-1V -0.5V/ 0V 0.1-1uA Vinh (1-2V) 4-11V 0-2.6V 0-2.6V 4.5-5V 0-2.6V 4.5-5V 0-1V

FIG. 15 depicts a neuron VMM array 1500, which is particularly suitable for the memory unit 310 as shown in FIG. 3, and is used as a synapse and neuron part between the input layer and the next layer. The VMM array 1500 includes a memory array 1503 of non-volatile memory cells, a reference array 1501 of first non-volatile reference memory cells, and a reference array 1502 of second non-volatile reference memory cells. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1500 is similar to the VMM array 1400, except that the VMM array 1500 implements two-way calibration. Due to the use of a separate EG line, each individual unit can be completely erased, partially programmed and partially erased as needed. The amount of charge required on the floating gate. As shown, the reference arrays 1501 and 1502 convert the input currents in the terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the column direction (diode The connected reference unit runs through the actions performed by the multiplexer 1514). The current output (neuron) is in the bit lines BL0 to BLN, where each bit line sums all the currents from the non-volatile memory cells connected to that specific bit line.

Table 8 depicts the operating voltage for the VMM array 1500. The rows in the table indicate the voltages placed on each of the following: word lines for selected cells, word lines for unselected cells, bit lines for selected cells, and bit lines for unselected cells Bit line, used for the control gate of the selected cell, used for the control gate of the unselected cell in the same sector as the selected cell, used for the unselected cell in a different sector from the selected cell The control gate is used for the erase gate of the selected cell, used for the erase gate of the unselected cell, used for the source line of the selected cell, and used for the source line of the unselected cell. These lines indicate reading, erasing, and programming operations. Table 8 : Operation of the VMM array 1500 in Figure 15 WL WL- not selected BL BL- not selected CG CG - not selected the same sector CG- not selected EG EG- not selected SL SL- not selected Read 1.0-2V -0.5V/ 0V 0.6-2V (Ineuron) 0V/FLT 0-2.6V 0 -2.6V 0-2.6V 0-2.6V 0-2.6V 0V 0V/FLT Erase 0V 0V 0V 0V 0V 4-9V 0-2.6V 5-12V 0-2.6V 0V 0V Stylized 0.7-1V -0.5V/ 0V 0.1-1uA Vinh (1-2V) 4-11V 0-2.6V 0-2.6V 4.5-5V 0-2.6V 4.5 5V 0-1V

FIG. 16 depicts a neuron VMM array 1600, which is particularly suitable for the memory unit 210 as shown in FIG. 2, and is used as a synapse and neuron part between the input layer and the next layer. In the VMM array 1600, the inputs INPUT ₀ ,..., INPUT _N are respectively received on the bit lines BL ₀ ,..., BL _N , and the outputs OUTPUT ₁ , OUTPUT ₂ , OUTPUT _3, and OUTPUT ₄ are respectively generated on On the source lines SL ₀ , SL ₁ , SL ₂ and SL ₃ .

FIG. 17 depicts a neuron VMM array 1700, which is particularly suitable for the memory unit 210 as shown in FIG. 2, and is used as a synapse and neuron part between the input layer and the next layer. In this specific example, the inputs INPUT ₀ , INPUT ₁ , INPUT ₂ and INPUT ₃ are received on the source lines SL ₀ , SL ₁ , SL ₂ and SL ₃ respectively, and the outputs OUTPUT ₀ ,..., OUTPUT _{N are} generated On the bit lines BL ₀ ,..., BL _N.

FIG. 18 depicts a neuron VMM array 1800, which is particularly suitable for the memory unit 210 as shown in FIG. 2, and is used as a synapse and neuron part between the input layer and the next layer. In this embodiment, the inputs INPUT ₀ , ..., INPUT _M are respectively received on the word lines WL ₀ , ..., WL _M , and the outputs OUTPUT _{0 ,} ..., OUTPUT _{N are} generated on the bit lines BL ₀ ,..., BL _N on.

FIG. 19 depicts a neuron VMM array 1900, which is particularly suitable for the memory unit 310 as shown in FIG. 3, and is used as a synapse and neuron part between the input layer and the next layer. In this embodiment, the inputs INPUT ₀ , ..., INPUT _M are respectively received on the word lines WL ₀ , ..., WL _M , and the outputs OUTPUT _{0 ,} ..., OUTPUT _{N are} generated on the bit lines BL ₀ ,..., BL _N on.

FIG. 20 depicts a neuron VMM array 2000, which is particularly suitable for the memory unit 410 as shown in FIG. 4, and is used as a synapse and neuron part between the input layer and the next layer. In this embodiment, the inputs INPUT ₀ ,..., INPUT _n are respectively received on the vertical control gate lines CG ₀ ,..., CG _N , and the outputs OUTPUT ₁ and OUTPUT _{2 are} generated on the source line SL ₀ and SL ₁ .

FIG. 21 depicts a neuron VMM array 2100, which is particularly suitable for the memory unit 410 as shown in FIG. 4, and is used as a synapse and neuron part between the input layer and the next layer. In this embodiment, the inputs INPUT ₀ ,..., INPUT _N are respectively on the gates of the bit line control gates 2901-1, 2901-2,..., 2901-(N-1) and 2901-N Upon reception, the bit line control gates are respectively coupled to the bit lines BL ₀ ,..., BL _N. The exemplary outputs OUTPUT ₁ and OUTPUT _{2 are} generated on the source lines SL ₀ and SL ₁ .

FIG. 22 depicts a neuron VMM array 2200, which is particularly suitable for the memory unit 310 as shown in FIG. 3, the memory unit 510 as shown in FIG. 5, and the memory unit 710 as shown in FIG. 7, and Used as the synapse and neuron part between the input layer and the next layer. In this embodiment, the inputs INPUT ₀ , ..., INPUT _{M are} received on the word lines WL ₀ , ..., WL _M , and the outputs OUTPUT ₀ , ..., OUTPUT _N are respectively generated on the bit lines BL ₀ ,..., BL _N on.

FIG. 23 depicts a neuron VMM array 2300, which is particularly suitable for the memory unit 310 as shown in FIG. 3, the memory unit 510 as shown in FIG. 5, and the memory unit 710 as shown in FIG. 7, and Used as the synapse and neuron part between the input layer and the next layer. In this embodiment, the inputs INPUT ₀ ,..., INPUT _{M are} received on the control gate lines CG ₀ ,..., CG _M. The outputs OUTPUT ₀ ,..., OUTPUT _N are respectively generated on the vertical source lines SL ₀ ,..., SL _N , where each source line SL _{i is} coupled to the source of all memory cells in row i Polar line.

FIG. 24 depicts a neuron VMM array 2400, which is particularly suitable for the memory unit 310 as shown in FIG. 3, the memory unit 510 as shown in FIG. 5, and the memory unit 710 as shown in FIG. 7, and Used as the synapse and neuron part between the input layer and the next layer. In this embodiment, the inputs INPUT ₀ ,..., INPUT _M are received on the control gate lines CG ₀ ,..., CG _M. The outputs OUTPUT ₀ ,..., OUTPUT _N are respectively generated on the vertical bit lines BL ₀ ,..., BL _N , wherein each bit line BL _{i is} coupled to one of all memory cells in row i Bit line. Long and short term memory

The prior art includes a concept known as long and short-term memory (LSTM). LSTM components are often used in neural networks. LSTM allows the neural network to remember information within a predetermined arbitrary time interval and use that information in subsequent operations. Conventional LSTM components include cells, input gates, output gates, and forget gates. The three gates regulate the flow of information into and out of the unit and the time interval for remembering information in the LSTM. VMM is especially suitable for LSTM components.

Figure 25 depicts an exemplary LSTM 2500. The LSTM 2500 includes units 2501, 2502, 2503, and 2504 in this embodiment. The unit 2501 receives an input vector x ₀ and generates an output vector h ₀ and a unit state vector c ₀ . The unit 2502 receives the input vector x ₁ , the output vector (hidden state) h ₀ from the unit 2501 and the unit state c ₀ from the unit 2501, and generates an output vector h ₁ and a unit state vector c ₁ . The unit 2503 receives the input vector x ₂ , the output vector (hidden state) h ₁ from the unit 2502 and the unit state c ₁ from the unit 2502, and generates an output vector h ₂ and a unit state vector c ₂ . The unit 2504 receives the input vector x ₃ , the output vector (hidden state) h ₂ from the unit 2503 and the unit state c ₂ from the unit 2503, and generates an output vector h ₃ . Additional units can be used, and the LSTM with four units is just an example.

FIG. 26 depicts an exemplary implementation of LSTM cell 2600, which can be used in cells 2501, 2502, 2503, and 2504 in FIG. 25. The LSTM unit 2600 receives the input vector x(t), the unit state vector c(t-1) from the aforementioned unit, and the output vector h(t-1) from the aforementioned unit, and generates the unit state vector c(t) and output vector h(t).

The LSTM unit 2600 includes S-shaped function devices 2601, 2602, and 2603, each of which applies a number between 0 and 1 to control the amount by which each component of the input vector is allowed to pass through the output vector. The LSTM unit 2600 also includes hyperbolic tangent devices 2604 and 2605 for applying the hyperbolic tangent function to the input vector, multiplier devices 2606, 2607 and 2608 for multiplying the two vectors together, and multiplier devices 2606, 2607 and 2608 for multiplying the two vectors. Adding device 2609 for adding up. The output vector h(t) can be provided to the next LSTM unit in the system, or it can be accessed for other purposes.

FIG. 27 depicts an LSTM unit 2700, which is an implementation example of the LSTM unit 2600. For the convenience of the reader, the same number from the LSTM unit 2600 is used in the LSTM unit 2700. The S-shaped function devices 2601, 2602, and 2603 and the hyperbolic tangent device 2604 each include a plurality of VMM arrays 2701 and excitation circuit blocks 2702. Therefore, it can be seen that the VMM array is particularly suitable for LSTM units used in certain neural network systems.

An alternative to the LSTM unit 2700 (and another embodiment of the implementation of the LSTM unit 2600) is shown in FIG. 28. In FIG. 28, the S-shaped function devices 2601, 2602, and 2603 and the hyperbolic tangent device 2604 can share the same physical hardware (VMM array 2801 and excitation function block 2802) in a time multiplexing manner. The LSTM unit 2800 also includes a multiplier device 2803 for multiplying two vectors, an adding device 2808 for adding two vectors, a hyperbolic tangent device 2605 (which includes an excitation circuit block 2802), a The register 2807 that stores the value i(t) when outputting i(t) from the S-shaped functional block 2802 is used to output the value f(t) * c( The register 2804 to store that value at t-1), the register 2805 to store the value when the value i(t) * u(t) is output from the multiplier device 2803 through the multiplexer 2810, and The register 2806 and the multiplexer 2809 are used to store the value o(t) * c~(t) when the value o(t) * c~(t) is output from the multiplier device 2803 through the multiplexer 2810.

Although the LSTM unit 2700 contains multiple sets of VMM arrays 2701 and individual activation function blocks 2702, the LSTM unit 2800 only contains a set of VMM arrays 2801 and activation function blocks 2802, which are used to represent many of the specific examples of the LSTM unit 2800 Layers. The LSTM unit 2800 will require less space than the LSTM 2700, because the LSTM unit 2800 will require 1/4 of the space for the VMM and excitation function blocks compared to the LSTM unit 2700.

It can be further understood that LSTM components will generally include multiple VMM arrays, each of which requires functions provided by specific circuit blocks outside the VMM array (such as summer and excitation circuit blocks and high voltage generation blocks). Providing a separate circuit block for each VMM array will require a lot of space in the semiconductor device and will be slightly inefficient. Therefore, the specific example described below attempts to minimize the external circuitry required by the VMM array itself. Gated loop components

The analog VMM implementation can be used in a gated loop unit (GRU) system. GRU is the gate control mechanism in the cyclic neural network. GRU is similar to LSTM, except that GRU units usually contain fewer components than LSTM units.

Figure 29 depicts an exemplary GRU 2900. In this embodiment, the GRU 2900 includes units 2901, 2902, 2903, and 2904. Unit 2901 receives input vector x ₀ and generates output vector h ₀ . The unit 2902 receives the input vector x ₁ and the output vector h ₀ from the unit 2901, and generates an output vector h ₁ . The unit 2903 receives the input vector x ₂ and the output vector (hidden state) h ₁ from the unit 2902, and generates an output vector h ₂ . The unit 2904 receives the input vector x ₃ and the output vector (hidden state) h ₂ from the unit 2903 and generates an output vector h ₃ . Additional units can be used, and a GRU with four units is just an example.

FIG. 30 depicts an exemplary implementation of the GRU unit 3000, which can be used for the units 2901, 2902, 2903, and 2904 of FIG. 29. The GRU unit 3000 receives the input vector x(t) and the output vector h(t-1) from the previous GRU unit, and generates an output vector h(t). The GRU unit 3000 includes S-shaped function devices 3001 and 3002, each of which applies a number between 0 and 1 to the components from the output vector h(t-1) and the input vector x(t). The GRU unit 3000 also includes a hyperbolic tangent device 3003 for applying a hyperbolic tangent function to the input vector, and a plurality of multiplier devices 3004, 3005, and 3006 for multiplying two vectors together, to phase the two vectors An adding device 3007 for adding up and a complementary device 3008 for subtracting input from 1 to generate output.

FIG. 31 depicts the GRU unit 3100, which is an implementation example of the GRU unit 3000. For the convenience of the reader, the same number as the GRU unit 3000 is used in the GRU unit 3100. As can be seen in FIG. 31, the S-shaped function devices 3001 and 3002 and the hyperbolic tangent device 3003 each include a plurality of VMM arrays 3101 and excitation function blocks 3102. Therefore, it can be seen that the VMM array is particularly used for GRU units used in certain neural network systems.

An alternative to the GRU unit 3100 (and another embodiment of the implementation of the GRU unit 3000) is shown in FIG. 32. In FIG. 32, the GRU unit 3200 utilizes the VMM array 3201 and the excitation function block 3202. When the VMM array and the excitation function block are configured as sigmoid functions, a number between 0 and 1 is used to control the input vector. Each component is allowed to pass through the amount of output vector. In FIG. 32, the S-shaped function devices 3001 and 3002 and the hyperbolic tangent device 3003 share the same physical hardware (VMM array 3201 and excitation function block 3202) in a time multiplexing manner. The GRU unit 3200 also includes a multiplier device 3203 for multiplying two vectors, an adding device 3205 for adding two vectors, a complementary device 3209 for subtracting an input from 1 to generate an output, and a multiplier device 3203 for adding two vectors together. The multiplexer 3204, the register 3206 used to store the value h(t-1) * r(t) when the value h(t-1) * r(t) is output from the multiplier device 3203 through the multiplexer 3204, and the register 3206 used when the multiplexer 3204 outputs the value h(t-1) * r(t). When the self-multiplier device 3203 outputs the value h(t-1) *z(t), the register 3207 that saves that value and is used when the self-multiplier device 3203 outputs the value h^(t) through the multiplexer 3204 * (1-z(t)) is the register 3208 that saves that value.

Although the GRU unit 3100 contains multiple sets of VMM arrays 3101 and excitation function blocks 3102, the GRU unit 3200 only contains one set of VMM arrays 3201 and excitation function blocks 3202, which are used to represent multiple layers in the specific example of the GRU unit 3200 . The GRU unit 3200 will require less space than the GRU unit 3100, because the GRU unit 3200 will require 1/3 of the space for the VMM and excitation function block compared to the GRU unit 3100.

It can be further understood that the GRU system will usually include multiple VMM arrays, each of which requires functions provided by certain circuit blocks outside the VMM array (such as summer and excitation circuit blocks and high voltage generation blocks). . Providing a separate circuit block for each VMM array will require a lot of space in the semiconductor device and will be slightly inefficient. Therefore, the specific example described below attempts to minimize the external circuitry required by the VMM array itself.

The input to the VMM array can be analog level, binary level, timing pulse or digital bit, and the output can be analog level, binary level, timing pulse or digital bit (in this case, the output ADC is required to output analog Level current or voltage is converted into digital bits).

For each memory cell in the VMM array, each weight w can be implemented by a single memory cell or a differential cell or two mixed memory cells (average of 2 or more cells). In the case of the differential unit, two memory units are required to use the weight w as the differential weight (w = w+-w-). In two hybrid memory cells, two memory cells are required to make the weight w as the average of the two cells. Specific examples of precise programming of units used in VMM

Figure 33A depicts a stylized method 3300. First, the method starts (step 3301), which usually proceeds in response to receiving program commands. Next, a large number of programming operations program all units to the "0" state (step 3302). Then, the soft erase operation erases all cells to the middle weak erase level, so that each cell will draw a current of, for example, about 3 to 5 μA during the read operation (step 3303). This is in contrast to the deep erase level, where each cell will draw approximately ~20 to 30 μA of current during the read operation. Then, perform hard programming on all unselected cells to make them in a very deep programming state to add electrons to the floating gates of the cells (step 3304) to ensure that their cells are actually "closed". This means that their cells will draw a negligible amount of current during the read operation.

Then a rough programming method is performed on the selected unit (to make the unit closer to the target, such as a 2X-100X target) (step 3305), and then a precise programming method is performed on the selected unit (step 3306) to program each selection The exact value required by the unit.

FIG. 33B depicts another stylization method 3310, which is similar to the stylization method 3300. However, instead of programming all cells to the "0" state as in step 3302 of FIG. 33A, after the method starts (step 3301), use an erase operation to erase all cells to "0". 1" state (step 3312). Then, a soft programming operation (step 3313) is used to program all cells to an intermediate state (level), so that each cell will draw about 3 to 5 uA of current during the read operation. After that, the rough and precise programming method as shown in Figure 33A will be followed. The change in the specific example of FIG. 33B will completely remove the soft programming method (step 3313).

FIG. 34 depicts a first specific example of the coarse programming method 3305, which is the search and execution method 3400. First, a lookup table search is performed to determine the rough target current value (I _CT ) for the selected cell based on the value intended to be stored in the selected cell (step 3401). This table is created, for example, by silicon characterization or calibration from wafer testing. Assume that the selected cell can be programmed to store one of N possible values (for example, 128, 64, 32, etc.). Each of the N values corresponding to the different desired current value (I _D) during a read operation of the draw by the selected cell. In a specific example, the look-up table may contain M possible current values to be used as a rough target current value I _CT for the selected cell during the search and execution of the method 3400, where M is an integer less than N. For example, if N is 8, then M can be 4, which means that there are 8 possible values that the selected cell can store, and one of the 4 rough target current values will be selected for the search and execution method Rough target for 3400. That is, search and execution method 3400 (again, which is one specific example of the coarse stylized Method 3305) is expected to quickly close the selected cell to be slightly stylized desired value (I _D) of values (I _CT), and then precisely method 3306 stylized expected more accurately selected unit is very close to the desired value stylized (I _D).

Tables 9 and 10 depict examples of cell values, required current values, and rough target current values for simple embodiments with N=8 and M=4: Table 9 : Examples of N required current values for N=8 Example The value stored in the selected cell Required current value (I _D ) 000 100 pA 001 200 pA 010 300 pA 011 400 pA 100 500 pA 101 600 pA 110 700 pA 111 800 pA Table 10: Example M = 4 for the current target value M Rough target current value (I _CT ) Associated unit value 800 pA+ I _CTOFFSET1 000, 001 1600 pA+ I _CTOFFSET2 010, 011 2400 pA+ I _CTOFFSET3 100, 101 3200 pA+ I _CTOFFSET4 110, 111 The offset value I _{CTOFFSETx is} used to prevent overshoot of the required current value during the rough adjustment.

Once the rough target current value I _{CT is selected, the selected cell is programmed by applying voltage v 0} to the appropriate terminal of the selected cell based on the cell structure type of the selected cell (e.g., memory cell 210, 310, 410, or 510) ( Step 3402). If the selected cell belongs to the type of memory cell 310 in FIG. 3, the voltage v ₀ will be applied to the control gate terminal 28, and v ₀ can be 5 to 7 V depending on the rough target current value I _CT. Depending on the situation, the value of _{v 0} can be determined from a voltage look-up table that _{stores v 0} with respect to the rough target current value I _CT.

Next, program the _{selected cell by applying voltage v i} = v _i-1 + v _increment , where i starts at 1 and increments every time this step is repeated, and where v _{increment is} smaller than the fine voltage, which will cause The degree of programming suitable for the fineness of the desired change (step 3403). Therefore, the first step 3403 is executed, i=1, and v ₁ will be v ₀ + v _increment . Then, a verification operation (step 3404) is performed, in which a read operation is performed on the selected cell and the current drawn _{by the selected cell (I cell) is measured.} If I _{cell is} less than or equal to I _CT (which is the first threshold here), the search and execution method 3400 is completed and the precise programming method 3306 can begin. If I _{cell is} not less than or equal to I _CT , step 3403 is repeated, and i is incremented.

Thus, the method 3305 ends the coarse stylized stylized and precise point method 3306 begins, the voltage v _i will be the last for a selected programmable voltage unit, the selected cell and the target current value storage and coarse associated I _CT Value. 3306 stylized precisely a target cell is selected stylized thereto during a read operation, which draws a current I _D (± acceptable amount of deviation, such as +/- 50 pA or +/- 30% or less) , Which is the required current value associated with the value, which is intended to be stored in the selected cell.

Figure 35 depicts examples of different voltage progressions that can be applied to the control gates of selected memory cells during the coarse and/or precise programming method 3306.

In the first method, gradually increasing voltage is gradually applied to the control gate to further program the selected memory cell. Origin-based v _i, which is the last voltage applied during the coarse stylized 3305 method. The increment of v _p1 is added to v ₁ , and the voltage v ₁ + v _{p1 is} then used to program the selected cell (indicated by the second pulse on the left in progress 3501). v _{p1 is an increment} smaller than v increment (the voltage increment used during the coarse programming method 3305). After applying each programmed voltage, a verification step (similar to step 3404) is performed, in which it is determined _{whether I cell} is less than or equal to I _PT1 (which is the first accuracy target current value and here is the second threshold value), Where I _PT1 = I _D + I _PT1OFFSET , where I _PT1OFFSET is the offset value added to prevent programming overshoot. If I _{cell is} not less than or equal to I _PT1 , another increment v _{p1 is} added to the previously applied programming voltage, and the procedure is repeated. At _{the point where I cell is} less than or equal to I _PT1 , then this part of the programming sequence stops. Optionally, if I _PT1 with sufficient accuracy equal to or nearly equal to I _D I _D, the stylized successfully selected memory cell.

If I _{PT1 is} not close enough to I _D , further programming with a smaller degree of precision can be performed. Here, progress 3502 is now used. The starting point for progression 3502 is the last voltage used for programming under progression 3501. The increment of V _p2 (which is less than v _p1 ) is added to that voltage, and the combined voltage is applied to program the selected memory cell. After applying each programmed voltage, a verification step (similar to step 3404) is performed, in which it is determined _{whether I cell} is less than or equal to I _PT2 (which is the second accuracy target current value and here is the third threshold value), Where I _PT2 = I _D + I _PT2OFFSET , I _PT2OFFSET is the offset value added to prevent programming overshoot. If I _{cell is} not less than or equal to I _PT2 , another increment V _{p2 is} added to the previously applied programming voltage, and the procedure is repeated. At _{the point where I cell is} less than or equal to I _PT2 , then this part of the programming sequence stops. Here, it is assumed I _PT2 sufficiently close to or equal to I _D I _D may be programmable so that the stop, this is due to sufficient accuracy has reached the target value. Those who are generally familiar with the art can understand that additional advancements can be applied using smaller and smaller stylized increments. For example, in Figure 36, three progressions (3601, 3602, and 3603) are applied instead of just two.

The second method is shown in progress 3503. Here, instead of increasing the voltage applied during the programming period of the selected memory cell, the same voltage is applied for the duration of the gradually increasing period. Instead of adding incremental voltages, such as v _{p1 in progression 3501 and v p2 in} progression 3503, an additional increment of time t _p1 is added to the programmed pulse so that each applied pulse is longer than the previously applied pulse t _p1 . After each stylized pulse is applied, the same verification steps are performed, as previously described for progress 3501. Optionally, additional progress may be applied, where the duration of the additional increment added to the time of the programmed pulse is shorter than the previously used progress. Although only one time progression is shown, generally those skilled in the art will understand that any number of different time progressions can be applied.

Additional details will now be provided for three additional specific examples of the rough stylized method 3305.

FIG. 37 depicts a first specific example of a rough programming method 3305, which is an adaptive calibration method 3700. The method starts (step 3701). The unit is programmed with a preset starting value v ₀ (step 3702). Unlike in the search and execution method 3400, here v ₀ is not derived from the lookup table, and may actually be a relatively small initial value. The control gate voltage of the unit is measured at the first current value IR1 (for example, 100na) and the second current value IR2 (for example, 10na), and the sub-threshold slope is based on these measurements (for example, 360 mV/ dec) to determine and store (step 3703).

Determining a new desired voltage v _i. When this step is executed for the first time, i=1, and v ₁ is determined based on the stored sub-threshold slope value, current target and offset value using a sub-threshold equation such as the following: Vi = Vi-1 + Vincrement, Vincrement is proportional to the slope of Vg Vg= n*Vt*log [Ids/wa*Io] Here, wa is the w of the memory unit, and Ids is the current target plusoffset value.

If the stored slope value is relatively steep, a relatively small current offset value can be used. If the stored slope value is relatively flat, a relatively high current offset value can be used. Therefore, determining the slope information will allow the selection of a current offset value customized for the specific cell in question. This will eventually make the programming process shorter. When this procedure is repeated, I is incremented, and _{v i = v i-1 +} v increment. Then use vi to program the unit. Available from the stored value v _increment lookup table with respect to the target current value determination v _increment.

Next, a verification operation is performed, in which a read operation is performed on the selected cell, and _{the current drawn by the selected cell (I cell} ) is measured (step 3705). If I _{cell is} less than or equal to I _CT (which is the rough target threshold here), I _CT is set = I _D + I _CTOFFSET , where I _CTOFFSET is the offset value added to prevent programmed overshoot, Then the adaptive calibration method 3700 is completed and the precision programming method 2206 can begin. If I _{cell is} not less than or equal to I _CT , steps 3704 to 3705 are repeated and i is incremented.

Figure 38 depicts an aspect of the adaptive calibration method 3700. During step 3803, the current source 3801 is used to apply the exemplary current values IR1 and IR2 to the selected cell (here, the memory cell 3802), and then measure the voltage at the control gate of the memory cell 3802 (using CGR1 for IR1 and CGR2 for IR2). The slope will be (CGR2-CGR1)/dec.

FIG. 39 depicts a second specific example of the programming method 3305, which is the adaptive calibration method 3900. The method starts (step 3901). The unit is programmed with a preset starting value V ₀ (step 3902). V _{0 is} derived from a look-up table, such as created from a silicon characterization, the table value is offset so as not to pass the programmed target.

In the next step 3903, an IV slope parameter is created, which is used to predict the next programmed voltage, the first control gate read voltage V _CGR1 is applied to the selected cell, and the resulting cell current IR ₁ is measured. Then, the second control gate read voltage V _CGR2 is applied to the selected cell, and the resulting cell current IR ₂ is measured. The slope is determined and stored, for example, based on the equations in the sub-threshold area (units operating in the sub-threshold value) based on their measurements: Slope = (V _CGR1 -V _CGR2 ) / (LOG(IR ₁ )- LOG(IR ₂ )) (Step 3903). _Examples used for the values of V CGR1 and V _CGR2 are 1.5 V and 1.3 V, respectively.

The determination slope information allows the selection of a V _increment value customized for the specific unit in question. This will eventually make the programming process shorter.

When step 3904 is repeated, i is incremented, and the new required programmed voltage V _i is determined based on the stored slope value, current target and offset value using an equation such as the following: V _i = V _i-1 + V _increment , Where for i-1, V _increment = α*slope* (LOG (IR ₁ )-LOG (I _CT )), where I _CT is the target current and α is a predetermined constant <1 (programmed offset value) to prevent Overshoot, for example, 0.9. For example, Vi is VSLP or VCGP, source line or control gate programming voltage.

The unit was then programmed using Vi. (Step 3904)

Next, a verification operation is performed, in which a read operation is performed on the selected cell, and _{the current drawn by the selected cell (I cell} ) is measured (step 3906). If I _{cell is} less than or equal to I _CT (which is the rough target threshold here), where I _CT is set = I _D + I _CTOFFSET , where I _CTOFFSET is the offset value added to prevent programmed overshoot, Then the procedure continues to step 3907. Otherwise, the procedure returns to step 390 and i is incremented.

In step 3907, I _{cell is} compared with a threshold value _CT2 that is less than I _CT. The purpose of this is to observe whether overshoot will occur. That is, although the target is to make I _cell smaller than I _CT , if it is much smaller than I _CT , overshoot will occur and the stored value may actually correspond to an error value. If I _{cell is} not less than or equal to I _CT2 , no overshoot will occur, and the adaptive calibration method 3900 has been completed. At this time, the procedure proceeds to the precise programming method 3306. If I _{cell is} less than or equal to I _CT2 , overshoot will occur. The selected cell is then erased (step 3908), and the programming process starts at step 3902. Optionally, if step 3908 is executed more than a predetermined number of times, the selected unit can be considered as a bad unit that should not be used.

The precise programming method 3306 is, for example, composed of multiple verification and programming cycles, in which the programming voltage is incremented by a constant pulse with a constant precision voltage or the programming voltage is fixed and the programming pulse changes or is constant with respect to the next pulse.

Optionally, the step of determining whether the current passing through the selected non-volatile memory cell during the read or verify operation is less than or equal to the first threshold current value can be performed by applying a fixed bias to the non-volatile memory cell The terminal, measurement and digitization are performed by generating a digital output bit by the current drawn by the selected non-volatile memory unit, and comparing the digital output bit with the digital bit representing the first threshold current.

Optionally, the step of determining whether the current passing through the selected non-volatile memory cell during the read or verify operation is less than or equal to the first threshold current value can be performed by applying a fixed bias to the non-volatile memory cell The terminal, measurement and digitization are performed by generating a digital output bit by the current drawn by the selected non-volatile memory unit, and comparing the digital output bit with the digital bit representing the first threshold current.

Optionally, the step of determining whether the current passing through the selected non-volatile memory cell during the read or verify operation is less than or equal to the first threshold current value can be performed by applying an input to the terminal of the non-volatile memory cell , The output pulse modulates the current drawn by the selected non-volatile memory unit to generate a modulated output, digitizes the modulated output to generate a digital output bit, and compares the digital output bit with the first temporary It is implemented by the digital bits of the current limit.

FIG. 40 depicts a third specific example of the programming method 3305, which is the absolute calibration method 4000. The method starts (step 4001). The unit is programmed with a preset starting value V ₀ (step 4002). The control gate voltage (VCGRx) of the cell is measured and stored under the current value Itarget (step 4003). The new required voltage v ₁ is determined based on the stored control gate voltage and current target and the offset value Ioffset+Itarget (step 4004). For example, the new required voltage v ₁ can be calculated as follows: v ₁ = v ₀ + (VCGBIAS-stored VCGR), where VCGBIAS = ~ 1.5 V, which is the default read control gate at the maximum target current The voltage and the stored VCGR is the measured and read control gate voltage in step 4003.

V _i using the programmable unit. When i=1, the voltage v ₁ from step 4004 is used. When i> = 2, using a voltage _{v i = v i-1 +} V increment. Available from the stored value v _increment lookup table with respect to the target current value determination v _increment. Next, a verification operation is performed, in which a read operation is performed on the selected cell, and _{the current drawn by the selected cell (I cell} ) is measured (step 4006). If I _{cell is} less than or equal to I _CT (which is the threshold here), then the absolute calibration method 4000 is completed and the precision programming method 3306 can begin. If I _{cell is} not less than or equal to I _CT , steps 4005 to 4006 are repeated and i is incremented.

Figure 41 depicts a circuit 4100 for implementing step 4003 of the absolute calibration method 4000. A voltage source (not shown) generates VCGR, which starts at the initial voltage and ramps up. Here, n+1 different current sources 4101 (4101-0, 4101-1, 4101-2,..., 4101-n) generate different currents IO0, IO1, IO2,..., with gradually increasing magnitudes. IOn. Each current source 4101 is connected to inverter 4102 (4102-0, 4102-1, 4102-2,..., 4102-n) and memory unit 4103 (4103-0, 4103-1, 4103-2, ..., 4103-n). As VCGR ramps up, each memory cell 4103 draws an increasing amount of current, and the input voltage to each inverter 4102 decreases. Because IO0 ＜ IO1 ＜ IO2 ＜... ＜ IOn, the output of inverter 4102-0 will switch from low to high as VCGR increases. The output of inverter 4102-1 will then switch from low to high, and then the output of inverter 4102-2 will switch from low to high and so on, until the output of inverter 4102-n switches from low to high. Each inverter 4102 controls the switch 4104 (4104-0, 4104-1, 4104-2,..., 4104-n) so that when the output of the inverter 4102 is high, the switch 4104 is turned on, which will make the capacitor 4105 (4105-0, 4105-1, 4105-2,..., 4105-n) samples the VCGR. Therefore, the switch 4104 and the capacitor 4105 form a sample-and-hold circuit. The values of IO0, IO1, IO2, ..., IOn are used as possible values of Itarget, and the respective sampled voltages are used as the associated value VCGRx in the absolute calibration method 4000 of FIG. 40. Diagram 4106 shows that VCGR ramps up over time, and the outputs of inverters 4102-0, 4102-1, and 4102-n switch from low to high at each time.

FIG. 42 depicts an exemplary progression 4200 for programming selected cells during the adaptive calibration method 3700 or the absolute calibration method 4000. In a specific example, the voltage Vcgp is applied to the control gate of the selected row of memory cells. The number of selected memory cells in the selected row is, for example, = 32 cells. Therefore, up to 32 memory cells in the selected row can be programmed in parallel. Each memory cell can be coupled to the programming current Iprog through the bit line enable signal. If the bit line enable signal is invalid (meaning that a positive voltage is applied to the selected bit line), the memory cell is disabled (unprogrammed). As shown in Figure 42, the bit line enable signal En_blx (where x varies between 1 and n, where n is the number of bit lines) at different times varies with that bit line (therefore the selected bit line on the bit line The Vcgp voltage level required by the memory) is activated. In another specific example, the enable signal on the bit line can be used to control the voltage applied to the control gate of the selected cell. Each bit line enable signal causes the required voltage corresponding to that bit line (such as vi described in FIG. 40) to be applied as Vcgp. The bit line enable signal can also control the programmed current flowing into the bit line. In this embodiment, each subsequent control gate voltage Vcgp is higher than the previous voltage. Alternatively, each subsequent control gate voltage may be lower or higher than the previous voltage. Each subsequent increment of Vcgp may be equal to or not equal to the previous increment.

FIG. 43 depicts an exemplary progression 4300 for programming selected cells during the adaptive calibration method 3700 or the absolute calibration method 4000. In a specific example, the bit line enable signal enables the selected bit line (meaning the selected memory cell in the bit line) to be programmed with the corresponding Vcgp voltage level. In another specific example, the bit line enable signal can be used to control the voltage applied to the incremental ramp-up control gate of the selected cell. Each bit line enable signal causes the required voltage corresponding to that bit line (such as vi described in FIG. 40) to be applied to the control gate voltage. In this embodiment, each subsequent increment is equal to the previous increment.

Figure 44 depicts a system for implementing input and output methods for reading or verifying VMM arrays. The input function circuit 4401 receives the digital bit values and converts them into analog signals. The analog signals are then used to apply voltage to the control gates of the selected cells in the array 4404. The analog signals are controlled by the control gates. The pole decoder 4402 determines. At the same time, the word line decoder 4403 is also used to select the column where the selected cell is located. The output neuron circuit block 4405 executes the output action of each row (neuron) of the unit in the array 4404. The output circuit block 4405 may be implemented using an integral analog-to-digital converter (ADC), successive approximation (SAR) ADC, integral delta ADC, or any other ADC scheme.

In a specific example, the digital value provided to the input function circuit 4401 includes four bits (DIN3, DIN2, DIN1, and DIN0) as an example, and various bit values correspond to different numbers of inputs applied to the control gate pulse. A larger number of pulses will produce a larger output value (current) of the unit. Examples of bit values and pulse values are shown in Table 11 : Table 11: Digital bit input relative to generated pulse DIN3 DIN2 DIN1 DIN0 Input pulse 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15

In the above example, there are at most 15 pulses for reading the 4-bit digital value of the cell value. Each pulse is equal to a unit cell value (current). For example, if the unit of Icell = 1 nA, then for DIN[3-0] = 0001, Icell = 1*1 nA = 1 nA, and for DIN[3-0] = 1111, Icell = 15*1nA = 15 nA.

In another specific example, the digital bit input uses the sum of the digital bit positions to read the value of the cell or neuron (for example, the value on the bit line output) as shown in Table 12. Here, only 4 pulses or 4 fixed inputs of the same bias voltage (for example, inputs on the word line or control gate) are needed to evaluate the 4-bit digital value. For example, the first pulse or the first fixed bias voltage is used to evaluate DIN0, and the second pulse or the second fixed bias voltage having the same value as the first pulse or the first fixed bias voltage is used to evaluate DIN1. Or the third pulse or the third fixed bias with the same value of the first fixed bias is used to evaluate DIN2, and the fourth pulse or the fourth fixed bias with the same value as the first pulse or the first fixed bias is used for Evaluate DIN3. Then, the results from the four pulses are summed according to the bit position, where each output result is multiplied by a multiplier factor of 2^n (by its proportional adjustment), n is the number shown in Table 13 Bit position. The realized digital bit summation equation is as follows: output = 2^0*DIN0 + 2^1*DIN1 + 2^2*DIN2 + 2^3*DIN3)*Icell unit.

For example, if Icell unit = 1 nA, then for DIN[3-0] = 0001, the total number of Icells = 0+0+0+1*1nA = 1 nA; and for DIN[3-0] = 1111, Icell Total = 8*1nA + 4*1nA + 2*1nA + 1*1nA = 26 nA. Table 12 : Digital input sum 2 ^ 3*DIN3 2 ^ 2*DIN2 2 ^ 1*DIN1 2 ^ 0*DIN0 Total value 0 0 0 0 0 0 0 0 1 1 0 0 2 0 2 0 0 2 1 3 0 4 0 0 4 0 4 0 1 5 0 4 2 0 6 0 4 2 1 7 8 0 0 0 8 8 0 0 1 9 8 0 2 0 10 8 0 2 1 11 8 4 0 0 12 8 4 0 1 13 8 4 2 0 14 8 4 2 1 15 Table 13 : Sum of digital input bits Dn with 2^n output multiplication factors DIN3 DIN2 DIN1 DIN0 Output X factor Y X1 Y X2 Y X4 Y X8

Table 14 shows another specific example of a mixed input with multiple digital input pulse ranges and the sum of input digital ranges for an exemplary 4-digit digital inputIn. This specific example DINn-0 can be divided into m different groups. Among them, each group is evaluated and the output is proportionally adjusted by a multiplication factor based on the group binary position. As a benefactor, for 4-bit DIN3-0, the group can be DIN3-2 and DIN1-0, where the output for DIN1-0 is proportionally adjusted by one (X1) and used for the output of DIN3-2 It is adjusted proportionally by 4 (X4). Table 14 : Mixed input and output summation with multiple input ranges DIN3 DIN2 DIN1 DIN0 Input pulse (or equivalent pulse width) Output X factor 0 0 0 X1 0 1 1 X1 1 0 2 X1 1 1 3 X1 0 0 0 X4 0 1 1 X4 1 0 2 X4 1 1 3 X4

Another specific example combines a hybrid input range with a hybrid ultra-large unit. The hybrid super cell includes multiple physical x-bit cells to implement a logical n-bit cell with x-cell output proportionally adjusted by 2^n binary positions. For example, in order to implement an 8-bit logic cell, two 4-bit cells (cell1, cell0) are used. The output for cell0 is scaled by one (X1), and the output for cell1 is scaled by four (X, 2^2). Other combinations of physical x-units used to implement n-bit logic cells are possible, such as two 2-bit physical cells and one 4-bit physical cell to implement 8-bit logic cells.

Figure 45 depicts another specific example of the system similar to Figure 44, except that the digital bit input uses the digital bit position summation to read out the output pulse width modulation designed by the modulator 4510 according to the digital input bit position The cell or neuron (for example, the value on the bit line output) current (for example, to convert the current into an output voltage V = current * pulse width / capacitance). For example, the first bias voltage (applied on the word line or control gate input) is used to evaluate DIN0, and the current (unit or neuron) output is proportional to the DIN0 bit position by the modulator 4510 The unit pulse width is modulated. The unit pulse width is one (x1) unit. The second input bias is used to evaluate DIN1. The current output is a pulse proportional to DIN1 bit position by modulator 4510 The pulse width is modulated. The pulse width is two (x2) units. The third input bias is used to evaluate DIN2. The current output is modulated by modulator 4510 with a pulse width proportional to the DIN2 bit position. The pulse width is four (x4) units. The fourth input bias is used to evaluate DIN3. The current output is modulated by the modulator 4510 with a pulse width proportional to the DIN3 bit position. The pulse width It is eight (x8) units. Each converted voltage is then converted by an analog-to-digital converter (ADC) 4511 into a digital bit for each digital input bit. The total output is then output by the summer 4512 as the sum of the four digital outputs generated from the DIN0-3 input.

FIG. 46 depicts a charge summer 4600 that can be used to sum the output of the VMM during the verification operation or during the analog-to-digital conversion of the output neuron to obtain a single analog value that represents the output and can then be converted into a digital bit value as appropriate.的实施例。 Example. For example, the charge summer 4600 may be used as the summer 4512. The charge summer 4600 includes a current source 4601 and a sample-and-hold circuit. The sample-and-hold circuit includes a switch 4602 and a sample-and-hold (S/H) capacitor 4603. As shown for the example of a 4-bit digital value, there are 4 S/H circuits to hold the values from the 4 evaluation pulses, where the values are totaled at the end of the program. Select the S/H capacitor 4603 at the ratio associated with the 2^n*DINn bit position for that S/H capacitor; for example, C_DIN3 = x8 Cu, C_DIN2 = x4 Cu, C_DIN1 = x2 Cu, DIN0 = x1 Cu . The current source 4601 is also ratioed accordingly.

Figure 47 depicts a current summer 4700, which can be used to total the output of the VMM during verification operations or during output neuron analog-to-digital conversion. The current summer 4700 includes a current source 4701, a switch 4702, switches 4703 and 4704, and a switch 4705. As shown for the example of a 4-bit digital value, there is a current source circuit to maintain the values from the 4 evaluation pulses, where the values are totaled at the end of the program. The current source is based on 2^n*DINn bit position and ratio; for example, I_DIN3 = x8 Icell unit, _I_DIN2 = x4 Icell unit, I_DIN1 = x2 Icell unit, I_DIN0 = x1 Icell unit.

Figure 48 depicts a digital summer 4800, which receives a plurality of digital values, totals them, and produces an output DOUT that represents the sum of the inputs. The digital summer 4800 can be used during verification operations or during output neuron analog-to-digital conversion. As shown for the example of a 4-bit digital value, there are digital output bits to hold the values from 4 evaluation pulses, where the values are totaled at the end of the program. The digital output is based on the 2^n*DINn bit position and is adjusted digitally in proportion; for example, DOUT3 = x8 DOUT0, _DOUT2 = x4 DOUT1, I_DOUT1 = x2 DOUT0, I_DOUT0 = DOUT0.

Figure 49A shows the Integral Dual Slope ADC 4900, which is applied to the output neuron to convert the cell current into digital output bits. An integrator composed of an integrating operational amplifier 4901 and an integrating capacitor 4902 integrates the cell current ICELL and the reference current IREF. As shown in FIG. 49B, during a fixed time t1, the cell current is up-integrated (Vout rises), and then the reference current is applied to the lower integration (Vout falls) during time t2. The current Icell is = t2/t1* IREF. For example, for t1, for a 10-bit resolution, 1024 cycles are used, and the number of cycles used for t2 varies from 0 to 1024 cycles depending on the Icell value.

Figure 49C shows an integral single slope ADC 4960, which is applied to the output neuron to convert the cell current into digital output bits. An integrator composed of an integrating operational amplifier 4961 and an integrating capacitor 4962 integrates the cell current ICELL. As shown in Figure 49D, during time t1, the cell current is up-integrated (Vout rises until it reaches Vref2), and during time t2, another cell current is up-integrated. The cell current Icell = Cint*Vref2/t. The pulse counter is used to count the number of pulses (digital output bits) during the integration time t. For example, as shown, the digital output bits used for t1 are smaller than the digital output bits of t2, which means that the cell current during t1 is greater than the cell current during the integration period t2. Perform the initial calibration to calibrate the integrating capacitor value using the reference current and a fixed time, Cint = Tref*Iref/Vref2.

Figure 49E shows the Integral Dual Slope ADC 4980, which is applied to the output neuron to convert the cell current into digital output bits. The Integral Dual Slope ADC 4980 does not use an integrating operational amplifier. The cell current or reference current is directly integrated on the capacitor 4982. The pulse counter is used to count the pulses (digital output bits) during the integration time. The current Icell is = t2/t1* IREF.

Figure 49F shows an integral single slope ADC 4990, which is applied to the output neuron to convert the cell current into digital output bits. The integrating single-slope ADC 4980 does not use an integrating operational amplifier. The cell current is directly integrated on the capacitor 4992. The pulse counter is used to count the pulses (digital output bits) during the integration time. The cell current Icell = Cint*Vref2/t.

Figure 50A shows a successive approximation register (SAR) ADC, which is applied to output neurons to convert cell currents into digital output bits. The cell current can drop across the resistor to be converted into VCELL. Alternatively, the cell current can charge the S/H capacitor to be converted into VCELL. Binary search is used to calculate the bits starting from the MSB bit (most significant bit). To bias the digital bits from the SAR 5001, the DAC 5002 is used to set an appropriate analog reference voltage for the comparator 5003. The output of the comparator 5003 is fed back to the SAR 5001 to select the next analog level. As shown in Figure 50B, for the example of a 4-bit digital output bit, there are 4 evaluation cycles: the first pulse evaluates DOUT3 by setting the analog level midway, and then the second pulse is evaluated by midway or in the upper half of the pulse. In the middle of the lower part, an analog level is set to evaluate DOUT2 and so on.

Improved binary search such as cyclic (algorithmic) ADC can be used for unit calibration (for example, programming) verification or output neuron conversion. An improved binary search such as a switched capacitor (SC) charge redistribution ADC can be used for cell calibration (eg, programming) verification or output neuron conversion.

Figure 51 shows the Integral Triangle ADC 5100, which is applied to the output neuron to convert the cell current into digital output bits. The integrator composed of the operational amplifier 5101 and the capacitor 5105 integrates the sum of the current from the selected cell current and the reference current generated by the 1-bit current DAC 5104. The comparator 5102 compares the integrated output voltage with a reference voltage. The time-controlled DFF 5103 depends on the output of the comparator 5102 to provide a digital output stream. The digital output stream is usually transferred to a digital filter before being output as digital output bits.

52A depicts a ramp analog-to-digital converter 5200, which includes a current source 5201 (which represents the received neuron current, Ineu), a switch 5202, a variable configurable capacitor 5203, and a comparator 5204, the ramp analog-to-digital conversion The device receives the voltage labeled Vneu generated across the variable configurable capacitor 5203 as a non-inverting input and receives a configurable reference voltage Vreframp as an inverting input and generates an output Cout. Vreframp gradually rises in discrete levels with each comparison clock cycle. The comparator 5204 compares Vneu with Vreframp, and thus when Vneu>Vreframp, the output Cout will be "1", otherwise it will be "0". Therefore, the output Cout will be a pulse whose width changes in response to Ineu. A larger Ineu will make Cout "1" for a longer period of time, thereby generating a wider pulse for outputting Cout. The digital counter 5220 converts each pulse of the output Cout into a digital output bit, as shown in FIG. 52B for two different Ineu currents respectively labeled OT1A and OT2A. Alternatively, the ramp voltage Vreframp is a continuous ramp voltage 5255, as shown in diagram 5250 of FIG. 52B. A specific example of multi-slope is shown in FIG. 52C, which is used to reduce the conversion time by using the coarse-precision ramp conversion algorithm. The first rough reference ramp reference voltage 5271 gradually rises in a rapid manner to find the sub-range for each Ineu. Next, the precision reference ramp reference voltage 5272, namely Vreframp1 and Vreframp2, are respectively used for each sub-range to convert Ineu. currents in each sub-range. As shown, there are two sub-ranges for the precision reference ramp voltage. More than two rough/precise steps or two sub-ranges are possible.

Figure 53 depicts an algorithm analog to digital output converter 5300, which includes a switch 5301, a switch 5302, a sample-and-hold (S/H) circuit 5303, a 1-bit analog-to-digital converter (ADC) 5304, and a 1-bit digital-to-analog The gain of converter (DAC) 5305, summer 5306 and two residual operational amplifiers (2x opamp) 5307. The algorithm analog-to-digital output converter 5300 generates a converted digital output 5308 in response to the analog input Vin and control signals applied to the switches 5302 and 5302. The input received at the analog input Vin (such as Vneu in FIG. 52) is first sampled by the S/H circuit 5303 through the switch 5302, and then the N bits are converted in N clock cycles. For each conversion clock cycle, the 1-bit ADC 5304 compares the S/H voltage 5309 with a reference voltage (for example, VREF/2, where VREF is the full-scale voltage for N bits) and outputs digital bits (for example , If input <=VREF/2, it will be "0" and if input >VREF/2, it will be "1"). This digital bit is the digital output signal 5308, which is converted into an analog voltage (for example, to VREF/2 or 0 V) by the 1-bit DAC 5305 and fed to the summer 5306 to subtract from the S/H voltage 5309 . The 2x residual operational amplifier 5307 then amplifies the summator difference voltage output into a converted residual voltage 5310, which is fed to the S/H circuit 5303 through the switch 5301 for the next clock cycle. Instead of this 1-bit (ie, 2-level) algorithm ADC, a 1.5-bit (ie, 3-level) algorithm ADC can be used to reduce effects such as offset from the ADC 5304 and the residual operational amplifier 5307. The 1.5-bit algorithm ADC requires a 1.5-bit or 2-bit (ie, 4 levels) DAC.

In another specific example, a hybrid ADC can be used. For example, for a 9-bit ADC, the first 4 bits can be generated by a SAR ADC, and the remaining 5 bits can be generated by a slope ADC or a ramp ADC.

It should be noted that as used herein, the terms "above" and "above" both include "directly on" (no intermediate materials, components or spaces are installed therebetween) and "Indirectly on" (intermediate materials, components or spaces are installed in between). Similarly, the term "adjacent" includes "directly adjacent" (no intermediate materials, components or spaces are installed in between) and "indirect adjacent" (intermediate materials, components or spaces are installed in between), and "installed to" includes "directly "Install to" (no intermediate materials, components or spaces are installed in between) and "indirect installation to" (with intermediate materials, components or spaces in between), and "electrical coupling" includes "directly electrically coupled to" ( There is no intermediate material or element that electrically connects the elements together) and "indirect electrical coupling to" (there is an intermediate material or element that electrically connects the elements together). For example, forming an element "above the substrate" may include directly forming the element on the substrate without intermediate materials/elements in between, and indirectly forming the element on the substrate with one or more intermediate materials/elements in between.

12: Semiconductor substrate 14: Source area 16: Drain area 18: Channel area 20: Floating gate 22: Word line terminal 24: Bit line terminal 28: Control gate terminal 30: Erase gate 32: Vector matrix Multiplication system 32a, 32b, 32c, 32d, 32e: VMM system 33, 2801, 3101, 3201: VMM array 34: erase gate and word line gate decoder 35, 4402: control gate decoder 36: bit Line decoder 37: Source line decoder 38: Differential summator 39: Excitation function circuit 110, 210, 310, 510, 3802, 4103, 4103-0, 4103-1, 4103-2, 4103-n: Memory unit 410: Four gates Memory cell 610: Tri-gate memory cell 710: Stacked gate memory cell 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2300, 2400: Neuron VMM array 1101, 1203, 1303, 1403, 1503: Memory array 1102, 1301, 1302, 1201, 1202, 1401, 1402, 1501, 1502: Reference array 1103: Control gate line 1104: Erase gate line 1214: Diode Through multiplexer 1404 for body connection: Tandem transistor 1405, 3204, 2809, 2810: Multiplexer 1412: Through multiplexer for diode connection 1514: Reference unit for diode connection through multiplexer 2206: Precise programming method 2500: Long and short-term memory (LSTM) 2501,2502, 2503, 2504: Unit 2600, 2700, 2800: LSTM unit 2601, 2602, 2603: S-type function device 2604, 2605, 3003: Hyperbolic tangent device 2606, 2607, 2608, 2803, 3004, 3005, 3006, 3203: Multiplier device 2609, 2808, 3007, 3205: Adding device 2701: MM array 2702: Excitation circuit block 2802, 3102, 3202: Excitation function block 2804 , 2805, 2806, 2807, 3206, 3207, 3208: Register 2900: Gated Circulation Unit (GRU) 2901-1, 2901-2, 2901-(N-1), 2901-N: Bit line control gate Pole 2901, 2902, 2903, 2904: Unit 3000, 3100, 3200: GRU unit 3001, 3002: S-type function device 3008, 3209: Complementary device 3300, 3310: Stylized method 390, 3301, 3302, 3303, 3304, 3305 ,3306,3312,3313,3401,3402 ,3403,3404,3701,3702,3703,3704,3705,3803,3901,3902,3903,3904,3906,3907,3908,4001,4002,4003,4004,4005,4006: Step 3400: Search and execute method 3501, 3502, 3503, 3601, 3602, 3603: Progress 3700, 3900: Adaptive calibration method 3801, 4101, 4101-0, 4101-1, 4101-2, 4101-n, 4601, 4701, 5201: Current source 4000: Calibration method 4100: Circuit 4102, 4102-0, 4102-1, 4102-2, 4102-(n-1), 4102-n: Inverter 4104, 4104-0, 4104-1, 4104-2, 4104-n, 4602, 4702, 4703, 4704, 4705, 5202, 5301, 5302: Switch 4105, 4105-0, 4105-1, 4105-2, 4105-n, 4982, 4992, 5105: Capacitor 4106, 5250: Illustration 4200, 4300: Illustrative progress 4401: Input function circuit 4404: Array 4405: Output neuron circuit block 4510: Modulator 4511: Analog to digital converter (ADC) 4512, 5306: Summer 4600, 4700 : Charge summer 4603: Sample-and-hold (S/H) capacitor 4800: Digital summer 4900, 4980: Integral dual slope ADC 4901, 4961: Integral operational amplifier 4902, 4962: Integrating capacitor 4960, 4990: Integral single slope ADC 5001: SAR 5002: DAC 5003, 5102, 5204: Comparator 5100: Integral triangle ADC 5101: Operational amplifier 5103: Time-controlled DFF 5200: Ramp analog to digital converter 5203: Variable configurable capacitor 5220: Digital counter 5255 : Ramp voltage 5271: first rough reference ramp reference voltage 5272: precision reference ramp reference voltage 5300: algorithm analog to digital output converter 5303: sample and hold (S/H) circuit 5304: 1 bit analog to digital converter ( ADC) 5305: 1-bit digital-to-analog converter (DAC) 5307: Residual operational amplifier 5308: Convert digital output 5309: S/H voltage 5310: Convert residual voltage BL: Bit lines BL0, BL1, BL2, BL3, BLN-1, BLN: bit line BLR0, BLR1, BLR2, BLR3: terminal c ₀ , c ₁ , c ₂ , c(t-1), c(t): cell state vector C1, C2, C3: layer C B1, CB2, CB3, CB4: Synapse CG: control gate CG ₀ , CG ₁ , CG ₂ , CG ₃ , CG _M-1 , CG _M, CG _N : control gate line DIN3, DIN2, DIN1, DIN0: Bit EG: erase gate EGR0, EG0, EG1, EGR1: EG line FG: floating gate h ₀ , h ₁ , h ₂ , h ₃ , h(t-1), h(t): output vector IO0 ,IO1,IO2,IOn: Current INPUT ₀ , INPUT ₁ , INPUT ₂ , INPUT ₃ , INPUT ₄ , INPUT _M-1 , INPUT _M , INPUT _N-1 , INPUT _N : Input OUTPUT ₀ , OUTPUT ₁ , OUTPUT ₂ , OUTPUT ₃ , OUTPUT ₄ , OUTPUT _N-1 , OUTPUT _N:: output P1, P2: excitation function S0, S1, S2: layer SG: select gate SL: source line SL0, SL1, SL2, SL3: source line WL : Word line WL0, WL1, WL2, WL3: Voltage input WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3: Word line x ₀ , x ₁ , x ₂ , x ₃ , x(t): input vector

Figure 1 is a diagram showing a prior art artificial neural network.

Figure 2 depicts a prior art split gate flash memory cell.

Figure 3 depicts another prior art split gate flash memory cell.

Figure 4 depicts another prior art split gate flash memory cell.

Figure 5 depicts another prior art split gate flash memory cell.

Figure 6 depicts another prior art split gate flash memory cell.

Figure 7 depicts a prior art stacked gate flash memory cell.

FIG. 8 is a diagram showing different levels of an exemplary artificial neural network using one or more non-volatile memory arrays.

Figure 9 is a block diagram showing a vector matrix multiplication system.

FIG. 10 is a block diagram showing an exemplary artificial neural network using one or more vector matrix multiplication systems.

Fig. 11 depicts another specific example of the vector matrix multiplication system.

Fig. 12 depicts another specific example of the vector matrix multiplication system.

Fig. 13 depicts another specific example of the vector matrix multiplication system.

Fig. 14 depicts another specific example of the vector matrix multiplication system.

Fig. 15 depicts another specific example of the vector matrix multiplication system.

Fig. 16 depicts another specific example of the vector matrix multiplication system.

Fig. 17 depicts another specific example of the vector matrix multiplication system.

Figure 18 depicts another specific example of the vector matrix multiplication system.

Figure 19 depicts another specific example of the vector matrix multiplication system.

Fig. 20 depicts another specific example of the vector matrix multiplication system.

Fig. 21 depicts another specific example of the vector matrix multiplication system.

Fig. 22 depicts another specific example of the vector matrix multiplication system.

Fig. 23 depicts another specific example of the vector matrix multiplication system.

Fig. 24 depicts another specific example of the vector matrix multiplication system.

Figure 25 depicts a prior art long and short-term memory system.

Figure 26 depicts an exemplary unit for use in a long- and short-term memory system.

FIG. 27 depicts a specific example of the exemplary unit of FIG. 26.

FIG. 28 depicts another specific example of the exemplary unit of FIG. 26.

Figure 29 depicts a prior art gated cyclic component system.

Figure 30 depicts an exemplary unit for use in a gated circulatory component system.

FIG. 31 depicts a specific example of the exemplary unit of FIG. 30.

FIG. 32 depicts another specific example of the exemplary unit of FIG. 30.

FIG. 33A depicts a specific example of a method of programming a non-volatile memory cell.

FIG. 33B depicts another specific example of the method of programming the non-volatile memory cell.

Figure 34 depicts a specific example of the rough stylization method.

Figure 35 depicts an exemplary pulse used in the programming of a non-volatile memory cell.

Figure 36 depicts an exemplary pulse used in the programming of a non-volatile memory cell.

Figure 37 depicts a programmed calibration algorithm for non-volatile memory cells, which adjusts the programmed parameters based on the slope characteristics of the cell.

Figure 38 depicts the circuit used in the calibration algorithm of Figure 37.

Figure 39 depicts the programmed calibration algorithm for non-volatile memory cells.

Figure 40 depicts a programmed calibration algorithm for non-volatile memory cells.

Figure 41 depicts the circuit used in the calibration algorithm of Figure 41.

FIG. 42 depicts an exemplary development of the voltage applied to the control gate of the non-volatile memory cell during the programming operation.

FIG. 43 depicts an exemplary development of the voltage applied to the control gate of the non-volatile memory cell during the programming operation.

FIG. 44 depicts a system for applying a programming voltage during programming of a non-volatile memory cell in a vector matrix multiplication system.

Figure 45 depicts a vector matrix multiplication system with an output block including a modulator, an analog-to-digital converter, and a summer.

Figure 46 depicts the charge summer circuit.

Figure 47 depicts the current summer circuit.

Figure 48 depicts a digital summer circuit.

Figure 49A depicts a specific example of an integral analog-to-digital converter for neuron output.

FIG. 49B depicts a graph showing the voltage output of the integral analog-to-digital converter of FIG. 49A over time.

Fig. 49C depicts another specific example of an integral analog-to-digital converter for neuron output.

FIG. 49D depicts a graph showing the voltage output of the integral analog-to-digital converter of FIG. 49C over time.

Figure 49E depicts another specific example of an integral analog-to-digital converter for neuron output.

Fig. 49F depicts another specific example of an integral analog-to-digital converter for neuron output.

Figures 50A and 50B depict successive approximation analog-to-digital converters for neuron output.

Figure 51 depicts a specific example of the integral triangle analog to digital converter.

Figures 52A, 52B, and 52C depict specific examples of ramp analog-to-digital converters.

Figure 53 depicts a specific example of the algorithm analog to digital converter.

C1: Layer

C2: Layer

C3: Layer

CB1: Synapse

CB2: Synapse

CB3: Synapse

CB4: Synapse

P1: Excitation function

P2: Excitation function

S0: layer

S1: layer

S2: layer

Claims (49)

A method for programming a selected non-volatile memory cell to store one of N possible values, where N is an integer greater than 2, and the selected non-volatile memory cell includes a floating gate and A control gate, the method includes: Perform a rough stylized procedure, which includes: Program the non-volatile memory unit with an initial programmed voltage; Applying a first voltage to the control gate of the selected non-volatile memory cell and measuring a first current generated through the selected non-volatile memory cell; Applying a second voltage to the control gate of the selected non-volatile memory cell and measuring a second current generated through the selected non-volatile memory cell; Determining a slope value based on the first voltage, the second voltage, the first current, and the second current; Determine a programmed voltage based on the slope value; Program the non-volatile memory unit with the next programmed voltage; Repeat the steps of determining a programming voltage and programming the non-volatile memory cell with the next programming voltage until a current passing through the selected non-volatile memory cell during a read or verify operation is less than or Equal to a first threshold current value; and A precise programming procedure is performed until a current passing through the selected non-volatile memory cell during a read or verify operation is less than or equal to a second threshold current value. Such as the method of claim 1, wherein the step of executing a rough stylized procedure further includes: When a current passing through the selected non-volatile memory cell is less than or equal to a third threshold current value, the selected non-volatile memory cell is erased and the rough programming process is repeated. Such as the method of claim 1, which further includes: A second precise programming process is performed until a current passing through the selected non-volatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value. The method of claim 1, wherein the precise programming process includes applying a voltage pulse of gradually increasing magnitude to the control gate of the selected non-volatile memory cell. The method of claim 1, wherein the precise programming process includes applying a voltage pulse of gradually increasing duration to the control gate of the selected non-volatile memory cell. Such as the method of claim 1, wherein the selected non-volatile memory cell is a split gate flash memory cell. Such as the method of claim 1, wherein the selected non-volatile memory unit is in a vector matrix multiplication array in an analog memory deep neural network. Such as the method of claim 1, which further includes: Before running this rough stylized procedure: Program the selected non-volatile memory unit to a "0" state; and The selected non-volatile memory cell is erased to a weak erase level. Such as the method of claim 1, which further includes: Before running this rough stylized procedure: Erase the selected non-volatile memory cell to a "1" state; and The selected non-volatile memory unit is programmed to a weak programming level. Such as the method of claim 1, which further includes: Perform a read operation on the selected non-volatile memory cell; and An integral analog-to-digital converter is used to integrate the current drawn by the selected non-volatile memory cell during the read operation to generate digital bits. Such as the method of claim 1, which further includes: Perform a read operation on the selected non-volatile memory cell; and An integral triangle analog-to-digital converter is used to convert the current drawn by the selected non-volatile memory cell during the read operation into digital bits. Such as the method of claim 1, which further includes: Perform a read operation on the selected non-volatile memory cell; and An algorithmic analog-to-digital converter is used to convert the current drawn by the selected non-volatile memory cell during the read operation into digital bits. Such as the method of claim 2, which further includes: A second precise programming process is performed until a current passing through the selected non-volatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value. The method of claim 2, wherein the precise programming process includes applying a voltage pulse of gradually increasing magnitude to the control gate of the selected non-volatile memory cell. The method of claim 2, wherein the precise programming process includes applying a voltage pulse of gradually increasing duration to the control gate of the selected non-volatile memory cell. Such as the method of claim 2, wherein the selected non-volatile memory cell is a split gate flash memory cell. Such as the method of claim 2, wherein the selected non-volatile memory unit is in a vector matrix multiplication array in an analog memory deep neural network. Such as the method of claim 2, which further includes: Before running this rough stylized procedure: Program the selected non-volatile memory unit to a "0" state; and The selected non-volatile memory cell is erased to a weak erase level. Such as the method of claim 2, which further includes: Before running this rough stylized procedure: Erase the selected non-volatile memory cell to a "1" state; and The selected non-volatile memory unit is programmed to a weak programming level. Such as the method of claim 2, which further includes: Perform a read operation on the selected non-volatile memory cell; and An integral analog-to-digital converter is used to integrate the current drawn by the selected non-volatile memory cell during the read operation to generate digital bits. Such as the method of claim 2, which further includes: Perform a read operation on the selected non-volatile memory cell; and An integral triangle analog-to-digital converter is used to convert the current drawn by the selected non-volatile memory cell during the read operation into digital bits. Such as the method of claim 2, which further includes: Perform a read operation on the selected non-volatile memory cell; and An algorithmic analog-to-digital converter is used to convert the current drawn by the selected non-volatile memory cell during the read operation into digital bits. Such as the method of claim 1, which further includes: By applying an input pulse to a terminal of the non-volatile memory unit, measuring and digitizing the current drawn by the selected non-volatile memory unit to generate digital output bits, and comparing the digital outputs Bit and a digital bit representing the first threshold current to determine whether the current passing through the selected non-volatile memory cell during a read or verify operation is less than or equal to the first threshold current value . Such as the method of claim 1, which further includes: By applying a fixed bias to a terminal of the non-volatile memory cell, measuring and digitizing the current drawn by the selected non-volatile memory cell to generate digital output bits, and comparing the digital bits Output bits and digital bits representing the first threshold current to determine whether the current passing through the selected non-volatile memory cell during a read or verify operation is less than or equal to the first threshold current value. Such as the method of claim 1, which further includes: By applying an input to a terminal of the non-volatile memory unit, the current drawn by the selected non-volatile memory unit is modulated with an output pulse to generate a modulated output and digitize the modulated Output to generate digital output bits, and compare the digital output bits with the digital bit representing the first threshold current to determine whether to pass through the selected non-volatile memory cell during a read or verify operation Whether the current is less than or equal to the first threshold current value. A method for performing a read or verify operation in a vector matrix multiplication system including an input function circuit, a memory array, and an output circuit block, which includes: Receiving digital bit input values through the input function circuit; Converting the digital input values into an input signal; Applying the input signal to the control gate terminal of the selected cell in the memory array; and In response to the current received from the memory array, an output value is generated by the output circuit block. Such as the method of claim 26, wherein the output value includes a set of digits. Such as the method of claim 26, wherein the output value includes an output component corresponding to each bit position in the digital input values, and each output component is multiplied by the corresponding bit of the digital input values A factor that is proportional to the meta position. Such as the method of claim 28, wherein the factor is one for the first bit position of the digital input values. Such as the method of claim 28, wherein the second bit position of the factor for the digital input values is two. Such as the method of claim 28, wherein the factor is 2 ⁿ for the n-th bit position of the digital input value. Such as the method of claim 26, wherein the output value includes an output component corresponding to each bit position in the digital bit input values, and each output component is a part of a bit position group, the The bit position group is multiplied by a factor proportional to the corresponding bit position of the bit position group. Such as the method of claim 32, wherein the factor is one for the first bit position group. Such as the method of claim 32, wherein the factor is two for the second bit position group. Such as the method of claim 32, wherein the factor is 2 ⁿ for the n-th bit position group. Such as the method of claim 26, wherein the input signal is an analog voltage. The method of claim 26, wherein the input signal includes one or more digital pulses. Such as the method of claim 29, wherein the number of generated digital pulses is proportional to the value represented by the digital input values. Such as the method of claim 26, wherein the output circuit block includes an integral analog-to-digital converter. Such as the method of claim 26, wherein the output circuit block includes a successive approximation analog to digital converter. Such as the method of claim 26, wherein the output circuit block includes an integral triangle analog-to-digital converter. A method for performing a read or verify operation in a vector matrix multiplication system including an input function circuit, a memory array, and an output circuit block, which includes: Receive a set of digital input bits through the input function circuit; and For each digital input bit in the group of digital input bits: Converting the digital input bit into an input signal; Applying the input signal to a terminal of the selected cell in the memory array; and A pulse width modulation proportional to a bit position of the digital input bit is coupled to an output current on a bit line of the selected cell to generate an output voltage. Such as the method of claim 42, which further includes: An analog-to-digital converter converts the output voltage into a set of digital output bits. Such as the method of claim 43, which further includes: The sets of digital output bits generated for the set of digital input bits are summed to generate a digital output. Such as the method of claim 42, wherein each input signal is a voltage. Such as the method of claim 42, wherein each input signal includes one or more digital pulses. Such as the method of claim 43, wherein the analog-to-digital converter includes an integral analog-to-digital converter. Such as the method of claim 43, wherein the analog-to-digital converter includes a successive approximation analog-to-digital converter. Such as the method of claim 43, wherein the analog-to-digital converter includes an integral triangle analog-to-digital converter.

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