TW202117975A - Integrated circuit package and manufacturing method thereof - Google Patents

Abstract

In an embodiment, an integrated circuit package includes: a graphics processor device; a passive device coupled to the graphics processor device, the passive device being directly face-to-face bonded to the graphics processor device; a shared memory device coupled to the graphics processor device, the shared memory device being directly face-to-face bonded to the graphics processor device; a central processor device coupled to the shared memory device, the central processor device being directly back-to-back bonded to the shared memory device, the central processor device and the graphics processor device each having active devices of a smaller technology node than the shared memory device; and a redistribution structure coupled to the central processor device, the shared memory device, the passive device, and the graphics processor device.

Description

Integrated circuit packaging and manufacturing method thereof

As semiconductor technology continues to evolve, integrated circuit die becomes smaller and smaller. In addition, more functions are integrated into the die. Therefore, although the area available for I/O pads is reduced, the number of input/output (I/O) pads required by the die increases. Over time, the density of I/O pads has grown rapidly, increasing the difficulty of die packaging. Some applications require greater parallel processing capabilities of integrated circuit dies. Packaging technology can be used to integrate multiple dies, allowing a greater degree of parallel processing capabilities.

In some packaging technologies, the integrated circuit die is singulated from the wafer before the integrated circuit die is packaged. The advantageous feature of this packaging technology is the possibility of forming a fan-out package that allows the I/O pads on the die to be redistributed to a larger area. The number of I/O pads on the surface of the die can thereby be increased.

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these components and configurations are only examples and are not intended to be limiting. For example, in the following description, the formation of the first feature on or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include additional features that may be formed between the first feature and the second feature. An embodiment is formed between the second feature such that the first feature and the second feature may not directly contact each other. In addition, the content of the present disclosure may repeat graphical element symbols and/or letters in various examples. This repetition is for the purpose of simplification and clarity, and by itself does not indicate the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, spatial relative terms such as "below", "below", "lower", "above", "upper" and the like can be used to describe as illustrated in the figures The relationship of one element or feature with respect to another element or feature. In addition to the orientations depicted in the drawings, spatially relative terms are intended to cover different orientations of elements in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used in this article can therefore be interpreted in the same way.

According to some embodiments, the integrated circuit package includes a memory element sandwiched between two different types of processor elements such as a graphics processing unit and a central processing unit. The memory element is shared by the two processor elements during operation. The semiconductor elements are joined by hybrid joining. As described further below, the data transmission among the semiconductor components of the integrated circuit package can be realized by direct connection through hybrid bonding rather than by the data signal line of the rewiring structure. Although the integrated circuit package can be formed with a rewiring structure, the amount of data signal lines in the rewiring structure is reduced by interconnecting the dies by hybrid bonding.

1A to 1D are cross-sectional views of semiconductor devices according to some embodiments. Specifically, FIGS. 1A, 1B, 1C, and 1D illustrate the first processor element 20, the second processor element 40, the memory element 60, and the passive element 80, respectively. Semiconductor components will be packaged in subsequent processing to form integrated circuit packages, such as system-on-integrated-chip (SoIC) components. Each semiconductor element can be a bare integrated circuit die or a package die. In the illustrated embodiment, each semiconductor element is a bare integrated circuit die. In other embodiments, one or more of the described semiconductor elements may be sealed package dies.

1A, the first processor element 20 may be any acceptable processor or logic element, such as a graphics processing unit (GPU), a central processing unit (CPU), a system on a chip (system on chip). -on-a-chip; SoC), application processor (AP), digital signal processing (DSP), field programmable gate array (FPGA), microcontroller , Artificial intelligence (AI) accelerator or similar. The first processor element 20 can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the first processor device 20 includes a semiconductor substrate 22, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 22 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates can also be used, such as multilayer substrates or gradient substrates. The semiconductor substrate 22 has an active surface 22A and an inactive surface 22N.

The device may be formed on the active surface 22A of the semiconductor substrate 22. The components may be active components (for example, transistors, diodes, etc.), capacitors, resistors, and so on. The non-active surface 22N may contain no components. An inter-layer dielectric (ILD) is located above the active surface 22A of the semiconductor substrate 22. The ILD surrounds and can cover the component. The ILD can include, for example, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass; One or more dielectric layers formed of BPSG), undoped Silicate Glass (USG) or similar materials.

The interconnect structure 24 is located above the active surface 22A of the semiconductor substrate 22. The interconnect structure 24 interconnects the components on the active surface 22A of the semiconductor substrate 22 to form an integrated circuit. The interconnect structure 24 may be formed by, for example, a metallization pattern in a dielectric layer. The metallization pattern includes metal lines and vias formed in one or more dielectric layers. The metallization pattern of the interconnect structure 24 is electrically connected to the components on the active surface 22A of the semiconductor substrate 22.

The die connector 28 is located at the front side 20F of the first processor element 20. The die connecting member 28 may be a conductive pillar, a pad, or the like that forms an external connection therewith. The die connector 28 is located in the interconnect structure 24 and/or on the interconnect structure 24, and may be formed of a metal such as copper, aluminum or the like. The die connecting member 28 may be formed by, for example, plating or the like.

The dielectric layer 30 is located at the front side 20F of the first processor element 20, such as on the interconnect structure 24. The dielectric layer 30 laterally seals the die connector 28, and the dielectric layer 30 is laterally connected to the sidewall of the first processor device 20. Initially, the dielectric layer 30 may bury the die connection 28 such that the topmost surface of the dielectric layer 30 is above the topmost surface of the die connection 28. The dielectric layer 30 may be a polymer, such as PBO, polyimide, BCB or the like; nitride, such as silicon nitride or the like; oxide, such as silicon oxide, PSG, BSG, BPSG or the like; similar者, or a combination thereof. The dielectric layer 30 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD) or the like. After being formed, the die connecting member 28 and the dielectric layer 30 may be processed by, for example, chemical-mechanical polish (CMP) processing, etch-back processing, the like, or a combination thereof. After the planarization, the surfaces of the die connector 28 and the dielectric layer 30 are flat and exposed at the front side 20F of the first processor element 20.

1B, the second processor element 40 can be any acceptable processor or logic element, such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP) ), digital signal processing (DSP), field programmable gate array (FPGA), microcontroller, artificial intelligence (AI) accelerator or the like. The second processor element 40 can be processed according to applicable manufacturing processes to form an integrated circuit. For example, the second processor device 40 includes a semiconductor substrate 42 having an active surface 42A and an inactive surface 42N. The semiconductor substrate 42 may be similar to the semiconductor substrate 22. The second processor element 40 also includes an interconnection structure 44 at the front side 40F of the second processor element 40. The interconnection structure 44 may be similar to the interconnection structure 24. The second processor device 40 further includes a via 46 formed to extend between the active surface 42A and the inactive surface 42N of the semiconductor substrate 42. The via 46 is also sometimes referred to as a through-silicon via (TSV). The via 46 is physically and electrically connected to the metallization pattern of the interconnect structure 44.

As an example of forming the via hole 46, the recess may be formed in the semiconductor substrate 42 by, for example, etching, milling, laser technology, a combination thereof, and/or the like. Thin dielectric materials can be formed in the recesses, such as by using oxidation techniques. The thin barrier layer may be conformally deposited on the semiconductor substrate, such as by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, and/or the like. 42 above the active surface 42A and in the opening. The barrier layer may be formed of oxide, nitride, or oxynitride such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, combinations thereof, and/or the like. The conductive material can be deposited above the barrier layer and in the opening. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, a combination thereof, and/or similar methods. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, and/or the like. The excess conductive material and barrier layer are removed from the active surface 42A of the semiconductor substrate 42 by, for example, CMP. The remaining part of the barrier layer and the conductive material forms a via 46.

The die connection 48 and the dielectric layer 50 are formed on the inactive surface 42N of the semiconductor substrate 42. The die connecting member 48 may be formed by similar materials and methods to the die connecting member 28. The die connector 48 is physically connected to the through hole 46, and is electrically connected to the integrated circuit of the second processor device 40 through the through hole 46. The dielectric layer 50 may be formed of materials and methods similar to those of the dielectric layer 30. Before forming the die connection 48 and the dielectric layer 50, the inactive surface 42N of the semiconductor substrate 42 may be ground to expose the via 46. After formation, the die connection 48 and the dielectric layer 50 can be planarized using, for example, a CMP process, an etch-back process, the like, or a combination thereof. After planarization, the surfaces of the die connector 48 and the dielectric layer 50 are flat and exposed at the backside 40B of the second processor element 40.

1C, the memory device 60 may be any acceptable memory device, such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device , Resistive random-access memory (RRAM) components, magnetoresistive random-access memory (MRAM) components, phase-change random-access memory (phase-change random-access memory) -access memory; PCRAM) components or similar. The memory device 60 can be processed according to applicable manufacturing processes to form an integrated circuit. For example, the memory device 60 includes a semiconductor substrate 62 having an active surface 62A and an inactive surface 62N. The semiconductor substrate 62 may be similar to the semiconductor substrate 22. The memory device 60 also includes an interconnect structure 64, a die connector 68, and a dielectric layer 70 that can be similar to the interconnect structure 24, the via 46, the die connector 28, and the dielectric layer 30, respectively. The die connector 68 and the dielectric layer 70 are exposed at the front side 60F of the memory device 60.

The memory device 60 further includes a via 66. In the illustrated embodiment, the via 66 has not yet been exposed at the backside 60B of the memory device 60. Actually, the via 66 is buried in the semiconductor substrate 62. As discussed further below, the via 66 will be exposed at the backside 60B of the memory device 60 through a planarization process in the subsequent processing.

1D, the passive component 80 can be any acceptable passive component, such as integrated passive device (IPD), power management integrated circuit (power management integrated circuit; PMIC), integrated voltage regulator (integrated passive device; IPD); voltage regulator; IVR) or similar. The passive component 80 can be processed according to applicable manufacturing processes to form an integrated circuit. For example, the passive component 80 includes a semiconductor substrate 82 that may be similar to the semiconductor substrate 22, but further includes passive components (for example, resistors, capacitors, inductors, etc.) and no active components (for example, transistors, diodes, etc.). Wait). The passive device 80 also includes an interconnection structure 84, a die connection 88, and a dielectric layer 90 that can be similar to the interconnection structure 24, the die connection 28, and the dielectric layer 30, respectively. The die connector 88 and the dielectric layer 90 are exposed at the front side 80F of the passive element 80.

The passive component 80 further includes a via 86 which can be similar to the via 46. In the illustrated embodiment, the via 86 has not yet been exposed at the back side 80B of the passive component 80. Actually, the via 86 is buried in the semiconductor substrate 82. As discussed further below, the via 86 will be exposed to the backside 80B of the passive element 80 through a planarization process in the subsequent processing.

Chip probe (CP) testing can be performed on the first processor element 20, the second processor element 40, the memory element 60, and/or the passive element 80 to confirm whether the element is a known good die. ; KGD). Therefore, only KGD components undergo subsequent processing and packaging, and components that fail the CP test do not undergo subsequent processing and are not packaged.

2A to 2D are various views of the integrated circuit package 100 according to some embodiments. The integrated circuit package 100 includes a stack of components joined together by, for example, hybrid bonding. The integrated circuit package 100 may be a heterogeneous component, such as a system integrated chip (SoIC) component. The process for forming the integrated circuit package 100 will be further described below with respect to FIGS. 3A to 8B.

2A and 2B are cross-sectional views of the integrated circuit package 100. FIG. 2C is a three-dimensional diagram illustrating electrical connections among the semiconductor elements of the integrated circuit package 100. FIG. 2D is a top view of the integrated circuit package 100 illustrating the positioning of the semiconductor element. Fig. 2A is described along the reference cross-section A-A in Fig. 2C and Fig. 2D, and Fig. 2B is described along the reference cross-section B-B in Fig. 2C and Fig. 2D. Cross section B-B is perpendicular to cross section A-A. Some features of the first processor element 20, the second processor element 40, the memory element 60, and the passive element 80 are not marked in FIGS. 2A and 2B for clarity of description, but are marked in FIGS. 1A and 1B, respectively , Figure 1C and Figure 1D. In addition, some features are omitted from FIGS. 2C and 2D for clarity of description.

The integrated circuit package 100 includes a first processor element 20, a second processor element 40, a memory element 60, and optional passive elements 80. According to some embodiments, the first processor element 20 and the second processor element 40 are different types of processor elements. For example, the first processor element 20 may be a graphics processor element and the second processor element 40 may be a central processor element. In addition, the memory element 60 is electrically coupled to each of the first processor element 20 and the second processor element 40, and includes a memory used by one or two processor elements. For example, the memory device 60 may be a shared memory device, such as a shared level 3 (L3) cache, embedded DRAM (eDRAM), or the like. Using a separate memory element 60 instead of including a memory with the first processor element 20 and/or the second processor element 40 allows the total amount of memory in the integrated circuit package 100 to be increased without substantially increasing The manufacturing cost of the processor components. In addition, forming the first processor element 20 and/or the second processor element 40 without memory allows more processing units (eg, cores) to be included in the processor element without substantially increasing the coverage of the processor element area.

The first processor element 20, the second processor element 40, and the memory element 60 may have active elements with different technology nodes. Specifically, the first processor element 20 and the second processor element 40 may each have an active element with a smaller technology node than the memory element 60. For example, the first processor element 20 and the second processor element 40 may each include an active element of a 7-nanometer technology node, and the memory element 60 may include an active element of a 16-nanometer technology node. Forming the memory device 60 with a larger technology node reduces the manufacturing cost of the memory device 60.

The integrated circuit package 100 further includes a rewiring structure 102 (described further below). The rewiring structure 102 includes a metallization pattern in a dielectric layer. The metallization pattern of the rewiring structure 102 is electrically coupled to the semiconductor element of the integrated circuit package 100. Specifically, the metallization pattern of the rewiring structure 102 includes a power supply source line (V _DD ) and a power supply ground line (V _SS ), the power supply source line and the power supply ground line are electrically coupled to the first processor Each of the device 20, the second processor device 40, the memory device 60, and the passive device 80 forms a power transmission network for the semiconductor device. In the embodiment where the passive component 80 is a PMIC, the passive component 80 may also be part of the power transmission network used for the first processor component 20. In some embodiments, the first processor element 20 has its own PMIC and is not connected to the passive element 80.

The metallization pattern of the rewiring structure 102 also includes a data signal line directly connected to the front side 40F of the second processor element 40. In an embodiment in which the second processor element 40 is a central processing element, directly connecting the front side 40F of the second processor element 40 to the metallization pattern of the redistribution structure 102 can help increase the input to the central processing element. / Output (I/O) connection amount. In addition, the metallization pattern of the rewiring structure 102 can conduct heat away from the second processor element 40, which can be particularly advantageous when the second processor element 40 is an element with large heat dissipation, such as a central processing element.

As described further below, the data transmission among the semiconductor elements of the integrated circuit package 100 can be realized by direct connection between the semiconductor elements (for example, metal-to-metal bonding) rather than by the data signal line of the redistribution structure 102 . The amount of data signal lines in the rewiring structure 102 can thus be reduced.

A dielectric layer (described further below) is located around some of the semiconductor elements of the integrated circuit package 100, thereby protecting the semiconductor elements. Vias (described further below) extend through the dielectric layer, thereby allowing the interconnection of the semiconductor elements of the integrated circuit package 100. Specifically, the first dielectric layer 104 laterally surrounds the memory device 60 and the passive device 80, and the first via 106 extends through the first dielectric layer 104. The first via 106 connects the front side 20F of the first processor element 20 to the back side 40B of the second processor element 40. Similarly, the second dielectric layer 108 laterally surrounds the second processor device 40, and the second via 110 extends through the second dielectric layer 108. The second via 110 connects the rewiring structure 102 to the back side 60B of the memory device 60 and to the back side 80B of the passive device 80. Some vias extend through multiple dielectric layers. Specifically, the third via hole 112 extends through both the first dielectric layer 104 and the second dielectric layer 108. The third via 112 connects the rewiring structure 102 to the front side 20F of the first processor element 20. In some embodiments, the second via 110 and the third via 112 are electrically coupled to the power supply source line (V _DD ) and the power supply ground line (V _SS ) of the rewiring structure 102, and connect the power and ground A semiconductor element provided to the integrated circuit package 100. In some embodiments, some of the second via 110 and the third via 112 are also electrically coupled to the data signal line of the rewiring structure 102.

The semiconductor elements of the integrated circuit package 100 may have different sizes so that they do not overlap each other concentrically, thereby allowing sufficient space for connection with the via 106, the via 110, the via 112, and the redistribution structure 102. Specifically, the width of the semiconductor element may be different in different cross-sectional views.

The memory element 60 is narrower than the second processor element 40 in the first plane (e.g., the cross section illustrated in FIG. 2A), and the memory element 60 is in the second plane (e.g., the cross section illustrated in FIG. 2B). Cross section) is wider than the second processor element 40. For example, referring to FIG. 2D, the memory element 60 may have a width W ₁ and a width W ₂ , and the second processor element 40 may have a width W ₃ and a width W ₄ , where the width W _{1 is} greater than the width W ₃ , and the width W _{2 is} smaller than width W ₄ .

The passive element 80 is narrower than the second processor element 40 in the first plane (for example, the cross section illustrated in FIG. 2A), and the passive element 80 is in the second plane (for example, the cross section illustrated in FIG. 2B). ) Is wider than the second processor element 40. For example, referring to FIG. 2D, the passive element 80 may have a width W ₅ and a width W ₆ , where the width W _{5 is} greater than the width W ₃ , and the width W _{6 is} less than the width W ₄ .

The first processor element 20 is larger than the second processor element 40 and the memory element in the first plane (for example, the cross section illustrated in FIG. 2A) and the second plane (for example, the cross section illustrated in FIG. 2B). 60 and the passive element 80 are wider. For example, referring to FIG. 2D, the first processor element 20 may have a width W ₇ and a width W ₈ , where the width W _{7 is} greater than each of the width W ₁ , the width W ₃ and the width W ₅ , and the width W ₈ It is greater than each of the width W ₂ , the width W _4, and the width W ₆ .

The memory element 60 is disposed between the first processor element 20 and the second processor element 40 and is connected to the two processor elements. The first processor element 20 is directly face-to-face bonded to the memory element 60. For example, the front side 20F of the first processor element 20 may be bonded to the front side 60F of the memory element 60 by hybrid bonding (for example, by metal-to-metal bonding and by dielectric-to-dielectric bonding). The second processor element 40 is directly connected to the memory element 60 back-to-back. For example, the backside 40B of the second processor device 40 may be bonded to the backside 60B of the memory device 60 by hybrid bonding (for example, by metal-to-metal bonding and by dielectric-to-dielectric bonding). The second processor element 40 is also bonded to other features of the integrated circuit package 100. Specifically, the second processor element 40 is directly bonded to a portion of the first dielectric layer 104 and some of the first via 106. For example, the backside 40B of the second processor element 40 can be bonded to the portion of the first dielectric layer 104 by dielectric-to-dielectric bonding, and the backside 40B of the second processor element 40 can also be bonded by Metal-to-metal bonding is used to bond to some of the first via holes 106.

In the embodiment where the passive element 80 is included, the passive element 80 is joined to the first processor element 20. The passive element 80 is directly connected to the first processor element 20 face to face. For example, the front side 80F of the passive component 80 may be bonded to the front side 20F of the first processor component 20 by hybrid bonding (for example, by metal-to-metal bonding and by dielectric-to-dielectric bonding). The passive element 80 is laterally disposed outside the coverage area of the second processor element 40 and is not joined to the second processor element 40.

After packaging, the first processor element 20 and the second processor element 40 can be interconnected by several features. The first processor element 20 and the second processor element 40 can communicate directly via the first via 106. In addition, since the internal wiring is formed by direct bonding, the first processor element 20 and the second processor element 40 can communicate indirectly via the memory element 60. Specifically, the first processor element 20 and the second processor element 40 can communicate through the interconnect structure 64 and the via 66 of the memory element 60. Data transmission between semiconductor elements is performed via these interconnections, which are shorter than the rewiring of the rewiring structure 102. The data transmission delay and interconnection bandwidth in the semiconductor components of the integrated circuit package 100 can thereby be reduced. In addition, the impedance can also be reduced and therefore the power consumption of the connection.

3A to 8B are cross-sectional views of intermediate steps during the process for forming the integrated circuit package 100 according to some embodiments. 3A, 4A, 5A, 6A, 7A, and 8A are cross-sectional views along the reference cross-section A-A in FIGS. 2C and 2D. 3B, 4B, 5B, 6B, 7B, and 8B are cross-sectional views along the reference cross-section B-B in FIGS. 2C and 2D. The integrated circuit package 100 is formed by stacking components on an unsingulated wafer 120. The stacking of devices in one device region 120A of the wafer 120 has been described, but it should be understood that the wafer 120 can have any number of device regions and the devices can be stacked in each device region.

In FIGS. 3A and 3B, a wafer 120 is obtained. The wafer 120 includes the first processor element 20 in the element area 120A. As such, the device area 120A of the wafer 120 has similar features to the first processor device 20. The first processor element 20 will be singulated in subsequent processing (see FIG. 8A and FIG. 8B) to be included in the integrated circuit package 100.

The memory element 60 is bonded to the first processor element 20 (for example, to the wafer 120). The first processor element 20 and the memory element 60 are directly bonded in a face-to-face manner by hybrid bonding, wherein the dielectric layer 30 of the first processor element 20 is bonded to the dielectric of the memory element 60 through dielectric-to-dielectric bonding. The layer 70 does not use any adhesive material (for example, die attach film), and the die connector 28 of the first processor element 20 is bonded to the die connector of the memory element 60 through metal-to-metal bonding 68 without using any eutectic material (for example, solder).

Bonding may include pre-bonding and annealing. During the pre-bonding period, a small pressing force is applied to press the first processor element 20 and the memory element 60 against each other. The pre-bonding is performed at a low temperature, such as room temperature, such as a temperature in the range of about 15° C. to about 30° C., and after the pre-bonding, the dielectric layer 30 and the dielectric layer 70 are bonded to each other. The bonding strength is then improved in a subsequent annealing step, in which the dielectric layer 30 and the dielectric layer 70 are annealed at a high temperature, such as a temperature in the range of about 100°C to about 450°C. After annealing, a direct bond, such as a fusion bond, is formed, thereby bonding the dielectric layer 30 and the dielectric layer 70. For example, the bonding may be a covalent bonding between the material of the dielectric layer 30 and the material of the dielectric layer 70. The die connector 28 and the die connector 68 are physically and electrically connected to each other in a one-to-one correspondence. The die connector 28 and the die connector 68 may be in physical contact after the pre-bonding, or may be expanded to become physical contact during annealing. In addition, during the annealing, the materials (for example, copper) of the die connector 28 and the die connector 68 are mixed so that a metal-to-metal bond is also formed. Therefore, the resulting bond between the first processor device 20 and the memory device 60 is a hybrid bond including both a dielectric-to-dielectric bond and a metal-to-metal bond.

The passive component 80 is optionally bonded to the first processor component 20 (eg, bonded to the wafer 120). The first processor element 20 and the passive element 80 are directly bonded face-to-face by hybrid bonding, wherein the dielectric layer 30 of the first processor element 20 is bonded to the dielectric layer 90 of the passive element 80 through dielectric-to-dielectric bonding , Without using any adhesive material (for example, die bonding film), and wherein the die connector 28 of the first processor element 20 is bonded to the die connector 88 of the passive element 80 through metal-to-metal bonding, and No eutectic materials (for example, solder) are used. The hybrid bonding may be similar to the bonding of the first processor element 20 and the memory element 60 described above.

In FIGS. 4A and 4B, the first dielectric layer 104 is formed around the memory device 60 and the passive device 80. The first dielectric layer 104 may be formed after placement of the memory device 60 and the passive device 80 but before annealing to complete the hybrid bonding, or may be formed after annealing. The first dielectric layer 104 fills the gap between the memory device 60 and the passive device 80, thereby protecting the semiconductor device. The first dielectric layer 104 may be an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride, such as silicon nitride or the like; a polymer, such as polybenzoxazole (PBO), Polyimide, benzocyclobuten (BCB), or the like; sealing body, such as molding compound, epoxy resin, or the like; the like, or a combination thereof. In some embodiments, the first dielectric layer 104 is an oxide, such as silicon oxide.

The first via 106 is then formed to extend through the first dielectric layer 104. As an example for forming the first via hole 106, the opening is patterned in the first dielectric layer 104. The patterning can be performed by an acceptable process, such as by exposing the first dielectric layer 104 when the first dielectric layer 104 is a photosensitive material, or by etching the first dielectric layer 104 using, for example, anisotropic etching. The dielectric layer 104. The opening exposes the die connector 28 of the first processor element 20. The seed layer is formed on the first dielectric layer 104 and on the portion of the die connecting member 28 exposed by the opening. In some embodiments, the seed layer is a metal layer, and the metal layer may be a single layer or a composite layer including multiple sub-layers formed of different materials. In certain embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. For example, PVD or the like can be used to form the seed layer. The conductive material is formed on the seed layer. The conductive material can be formed by plating such as: electroplating or electroless plating, or the like. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. The excess part of the seed layer and the conductive material is then removed, wherein the excess part is the part overlying the first dielectric layer 104. The removal can be performed by a planarization process. The planarization process is performed on the seed layer, the conductive material, the first dielectric layer 104, the semiconductor substrate 62 and the semiconductor substrate 82. The removal simultaneously removes the seed layer and the excess portion of the conductive material and exposes the via 66 and via 86. The planarization process can be, for example, a CMP process, a polishing process, an etch-back process, the like, or a combination thereof. The seed layer and the remaining part of the conductive material in the opening form the first via hole 106. The top surfaces of the first dielectric layer 104, the first via 106, the semiconductor substrate 62, the semiconductor substrate 82, and the via 66 and the via 86 are flat after the planarization process.

In FIGS. 5A and 5B, the second processor element 40 is bonded to the memory element 60, the first via 106 and the first dielectric layer 104. The second processor element 40 and the memory element 60 are directly connected in a back-to-back manner by hybrid bonding. Because the second processor element 40 and the memory element 60 do not overlap each other concentrically, the first via 106 and some parts of the first dielectric layer 104 participate in the hybrid bonding. Specifically, the dielectric layer 50 of the second processor element 40 is bonded to the portion of the first dielectric layer 104 through dielectric-to-dielectric bonding without using any adhesive material (for example, a die attach film). Similarly, the die connector 48 of the second processor element 40 is bonded to the first via 106 and the via 66 of the memory element 60 through metal-to-metal bonding without using any eutectic material (for example, solder) . The hybrid bonding may be similar to the bonding of the first processor element 20 and the memory element 60 described above. Because the first dielectric layer 104 participates in the hybrid bonding, the ferro-dielectric-to-dielectric bonding with the second processor device 40 can be formed even if the dielectric characteristics of the memory device 60 are not exposed.

In FIGS. 6A and 6B, the second dielectric layer 108 is formed around the second processor element 40. The second dielectric layer 108 may be formed after placement of the second processor element 40 but before annealing to complete the hybrid bonding, or may be formed after annealing. The second dielectric layer 108 may be formed of materials and methods similar to those of the first dielectric layer 104. In some embodiments, the second dielectric layer 108 is an oxide, such as silicon oxide.

The second via hole 110 is then formed to extend through the second dielectric layer 108 and connect to the via hole 66 and the via hole 86. The second via hole 110 may be formed by a material and method similar to the first via hole 106. The third via hole 112 is then formed to extend through the first dielectric layer 104 and the second dielectric layer 108 and connect to the die connector 28. Except that the opening for the third via hole 112 can be patterned through both the first dielectric layer 104 and the second dielectric layer 108, the third via hole 112 can be made of a material similar to the first via hole 106 and Method formation. In some embodiments, the second via hole 110 and the third via hole 112 are formed at the same time. During the formation of the second via hole 110 and/or the third via hole 112, a planarization process may be performed. The top surfaces of the second dielectric layer 108, the second via 110, the third via 112, and the second processor element 40 are flat after the planarization process.

In FIGS. 7A and 7B, the rewiring structure 102 is formed on the second dielectric layer 108, the second via 110, the third via 112, and the second processor element 40. The rewiring structure 102 includes a plurality of dielectric layers, metallization patterns and vias. For example, the rewiring structure 102 may be patterned into a plurality of discrete metallization patterns separated from each other by corresponding dielectric layers. In some embodiments, the dielectric layer is formed of a polymer, which may be a photosensitive material, such as PBO, polyimide, BCB, or the like, which may be patterned using a lithographic mask. In other embodiments, the dielectric layer is formed of: nitride, such as silicon nitride; oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer can be formed by spin coating, lamination, CVD, the like, or a combination thereof. After formation, the dielectric layer is patterned to expose the underlying conductive features. For example, the bottom dielectric layer is patterned to expose portions of the metallization pattern of the interconnect structure 44, and the middle dielectric layer is patterned to expose portions of the underlying metallization pattern. The patterning can be performed by an acceptable process, such as by exposing the dielectric layer when the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer is a photosensitive material, the dielectric layer can be developed after exposure.

A metallization pattern extending along and through each dielectric layer is formed. A seed layer (not illustrated) is formed above each corresponding dielectric layer and in the opening passing through the corresponding dielectric layer. In some embodiments, the seed layer is a metal layer, and the metal layer may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using a deposition process such as PVD or the like. Then a photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating or the like, and can be exposed for patterning. The pattern of the photoresist corresponds to the metallization pattern. The patterning forms an opening through the photoresist to expose the seed layer. The conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as: electroplating or electroless plating, or the like. The conductive material may include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, the like, or a combination thereof. Subsequently, the photoresist and the part of the seed layer where no conductive material is formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as the use of oxygen plasma or the like. After the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The seed layer and the remaining part of the conductive material form a metallization pattern for one layer of the rewiring structure 102.

The rewiring structure 102 is illustrated as an example. More or fewer dielectric layers and metallization patterns than those described can be formed in the rewiring structure 102 by repeating or omitting the steps described above.

In FIGS. 8A and 8B, the singulation process is performed by, for example, sawing along the dicing path area around the device area 120A. The singulation process includes sawing the redistribution structure 102, the first dielectric layer 104, the second dielectric layer 108 and the wafer 120. The singulation process separates the element area 120A (including the first processor element 20) of the wafer 120 from the adjacent element area (not illustrated) to form an integrated circuit package 100 including the first processor element 20. The memory element 60 is bonded to the first processor element 20 in a face-to-face manner, and the memory element 60 is bonded to the second processor element 40 in a back-to-back manner without using solder. The resulting integrated circuit package 100 thus contains no solder. After singulation, the rewiring structure 102, the first dielectric layer 104, the second dielectric layer 108, and the first processor element 20 are laterally connected.

9A and 9B are cross-sectional views of an integrated circuit package 100 according to some embodiments. Fig. 9A is described along the reference cross section A-A in Fig. 2C and Fig. 2D. Fig. 9B is described along the reference cross section B-B in Fig. 2C and Fig. 2D. In this embodiment, the first processor element 20 is not a bare integrated circuit die, but is actually a package die. The first processor element 20 may be formed by obtaining a wafer including the first processor element 20, sawing the wafer to singulate the first processor element 20, and then sealing the first processor with a sealing body 32 Element 20. Another semiconductor element of the integrated circuit package 100 can then be stacked on the sealed first processor element 20.

10 and 11 are cross-sectional views of intermediate steps during a process for forming a system implementing an integrated circuit package 100 according to some embodiments. Fig. 10 and Fig. 11 are described along the reference cross section B-B in Fig. 2C and Fig. 2D. In this embodiment, the integrated circuit package 100 is directly mounted on the package substrate.

In FIG. 10, a conductive connector 114 that is physically and electrically connected to the redistribution structure 102 is formed. The conductive connector 114 may be formed before or after the integrated circuit package 100 is singulated. The top dielectric layer of the rewiring structure 102 may be patterned to expose portions of the underlying metallization pattern. In some embodiments, under bump metallurgy (UBM) may be formed in the opening. The conductive connection 114 is formed on the UBM. The conductive connectors 114 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel- Bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG) or similar. The conductive connector 114 may be formed of a metal or metal alloy, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connector 114 is formed by initially forming a solder layer through common methods such as evaporation, electroplating, printing, solder transfer, bumping, or the like. After the solder layer has been formed on the structure, reflow can be performed to mold the material into the desired bump shape. In another embodiment, the conductive connection member 114 is a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. The conductive connector 114 is electrically coupled to the metallization pattern of the rewiring structure 102.

In FIG. 11, the integrated circuit package 100 is turned over and connected to the package substrate 200 using conductive connections 114. The package substrate 200 may be made of semiconductor materials, such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphate, indium gallium phosphide, combinations of these, and the like can also be used. In addition, the package substrate 200 may be an SOI substrate. Generally, the SOI substrate includes a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an alternative embodiment, the package substrate 200 is based on an insulating core such as a fiberglass reinforced resin core. An example core material is fiberglass resin such as FR4. Alternatives to the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. A build-up film such as Ajinomoto build-up film (ABF) or other laminates may be used for the packaging substrate 200.

The packaging substrate 200 may include active components and passive components (not illustrated). Elements such as transistors, capacitors, resistors, combinations of these, and the like can be used to generate structural and functional requirements for the design of the system. Any suitable method can be used to form the element.

The package substrate 200 may also include a metallization layer and through holes (not illustrated), and bonding pads 202 above the metallization layer and the through holes. The metallization layer can be formed on the active device and the passive device, and is designed to connect various devices to form a functional circuit. The metallization layer may be formed by alternating layers of dielectric (for example, low-k dielectric material) and conductive material (for example, copper) (where via holes interconnect the conductive material layer) and may be formed by any suitable process (such as deposition, Mosaic, double mosaic or similar). In some embodiments, the package substrate 200 contains substantially no active devices and passive devices.

The conductive connector 114 is reflowed to attach the UBM of the rewiring structure 102 to the bonding pad 202. The conductive connector 114 electrically and/or physically connects the package substrate 200 (including the metallization layer in the package substrate 200) to the integrated circuit package 100. In some embodiments, passive components (for example, surface mount devices (SMD), not illustrated) may be attached to the integrated circuit package 100 (for example, bonded to bonding pads 202) before being mounted on the package substrate 200 ). In such an embodiment, the passive component may be bonded to the same surface of the integrated circuit package 100 as the conductive connector 114. In some embodiments, passive components (for example, SMD, not illustrated) may be attached to the package substrate 200, for example, to the bonding pad 202.

The conductive connector 114 may have epoxy flux (not shown) that utilizes the epoxy remaining after the integrated circuit package 100 is attached to the package substrate 200 in the conductive connector 114 At least some of the epoxy resin portion of the flux is formed on the conductive connector 114 before being reflowed. This remaining epoxy resin part can serve as an underfill to reduce stress and protect the joint created by the reflow conductive connector 114. In some embodiments, an underfill (not illustrated) may be formed between the integrated circuit package 100 and the package substrate 200 around the conductive connection member 114. The underfill may be formed by a capillary flow process after the integrated circuit package 100 is attached, or may be formed by a suitable deposition method before the integrated circuit package 100 is attached.

12 to 16 are cross-sectional views of intermediate steps during the process for forming a system implementing the integrated circuit package 100 according to some other embodiments. 12 to 16 are described along the reference cross section B-B in FIG. 2C and FIG. 2D. In this embodiment, the integrated circuit package 100 is singulated and included in the package assembly. The packaging of components in one package area 302A has been described, but it should be understood that any number of package areas can be formed at the same time. The packaging area 302A will be singulated in the subsequent processing. The monolithic package component may be a fan-out package, such as an integrated fan-out (InFO) package. The fan-out package is then mounted on the package substrate.

In FIG. 12, a carrier substrate 302 is provided, and a release layer 304 is formed on the carrier substrate 302. The carrier substrate 302 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 302 can be a wafer, so that multiple packages can be formed on the carrier substrate 302 at the same time. The release layer 304 can be formed of a polymer-based material, and the polymer-based material together with the carrier substrate 302 can be removed from the overlying structure to be formed in a subsequent step. In some embodiments, the release layer 304 is an epoxy-based heat release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 304 may be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light. The release layer 304 may be formulated as a liquid and cured, may be a laminated film laminated to the carrier substrate 302, or may be the like. The top surface of the release layer 304 may be leveled, and may have a high degree of flatness.

The rewiring structure 306 may be formed on the release layer 304. The rewiring structure 306 may be formed in a similar manner and material to the rewiring structure 102 described with respect to FIGS. 7A and 7B. The redistribution structure 306 includes a dielectric layer and a metallization pattern (sometimes called a redistribution layer or redistribution). More or fewer dielectric layers and metallization patterns than illustrated may be formed in the rewiring structure 306. The rewiring structure 306 is selected as appropriate. In some embodiments, a dielectric layer without a metallization pattern is formed on the release layer 304 instead of the rewiring structure 306.

In FIG. 13, a via 308 extending through the topmost dielectric layer of the rewiring structure 306 is formed. Therefore, the via 308 is connected to the metallization pattern of the rewiring structure 306. The via 308 is optional and can be omitted. For example, in an embodiment in which the rewiring structure 306 is omitted, the via 308 may (or may not) be omitted.

As an example for forming the via 308, the opening may be formed in the topmost dielectric layer of the rewiring structure 306. The seed layer is then formed over the rewiring structure 306, for example, on the top dielectric layer of the rewiring structure 306 and the portion of the metallization pattern of the rewiring structure 306 exposed by the opening. In some embodiments, the seed layer is a metal layer, and the metal layer may be a single layer or a composite layer including multiple sub-layers formed of different materials. In certain embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. For example, PVD or the like can be used to form the seed layer. A photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating or the like, and can be exposed for patterning. The pattern of the photoresist corresponds to the via hole. The patterning forms an opening through the photoresist to expose the seed layer. The conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as: electroplating or electroless plating, or the like. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. The part of the photoresist and the seed layer where no conductive material is formed is removed. The photoresist can be removed by an acceptable ashing or stripping process, such as the use of oxygen plasma or the like. After the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining part of the seed layer and the conductive material forms a via 308.

The singular integrated circuit package 100 is placed on the rewiring structure 306. In the illustrated embodiment, a structure similar to that described with respect to FIGS. 8A and 8B is obtained. In another embodiment, a structure similar to that described with respect to FIGS. 9A and 9B is obtained. As noted above, in the integrated circuit package 100, components are joined to each other without using solder. The singulated integrated circuit package 100 thus does not contain solder.

In FIG. 14, a sealing body 310 is formed around the integrated circuit package 100. The sealing body 310 laterally surrounds the integrated circuit package 100. The sealing body 310 may be a molding compound, epoxy resin, or the like. The sealing body 310 may be applied by compression molding, transfer molding, or the like, and may be applied in a liquid or semi-liquid form and then cured.

In some embodiments, the sealing body 310 is formed above the integrated circuit package 100 so that the rewiring structure 102 is buried or covered. The planarization process may be performed on the sealing body 310 to expose the integrated circuit package 100. The planarization process can remove the material of the sealing body 310 until the rewiring structure 102 is exposed. The top surface of the sealing body 310 and the redistribution structure 102 are coplanar after the planarization process. The planarization process can be, for example, a CMP process, a polishing process, an etch-back process, the like, or a combination thereof. In other embodiments, the sealing body 310 is not formed on the integrated circuit package 100, and the planarization process does not necessarily expose the integrated circuit package 100.

The redistribution structure 312 is subsequently formed on the sealing body 310 and the redistribution structure 102. The rewiring structure 312 may be formed in a similar manner and material to the rewiring structure 102 described with respect to FIGS. 7A and 7B. The redistribution structure 312 includes a dielectric layer and a metallization pattern (sometimes called a redistribution layer or redistribution). More or fewer dielectric layers and metallization patterns than illustrated may be formed in the rewiring structure 306. The bottom dielectric layer of the rewiring structure 312 physically contacts the sealing body 310 and the metallization pattern of the top dielectric layer of the rewiring structure 102 and the rewiring structure 312 is electrically coupled to the metallization pattern of the rewiring structure 102.

A conductive connector 314 that is physically and electrically connected to the metallization pattern of the rewiring structure 312 is formed. The conductive connector 314 may be formed in a similar manner and material to the conductive connector 114 described with respect to FIG. 10.

In FIG. 15, the carrier substrate peeling is performed to detach (peel off) the carrier substrate 302 from the weighted wiring structure 306 (for example, the bottommost dielectric layer of the rewiring structure 306 ). According to some embodiments, peeling includes projecting light such as laser light or UV light onto the release layer 304 so that the release layer 304 decomposes under light and heat and the carrier substrate 302 can be removed. The structure is then turned over and placed on, for example, a carrier tape.

In addition, a conductive connection 316 passing through the bottommost dielectric layer of the rewiring structure 306 is formed. An opening may be formed through the bottommost dielectric layer of the redistribution structure 306, thereby exposing a portion of the metallization pattern of the redistribution structure 306. For example, laser drilling, etching, or the like can be used to form the opening. The conductive connection member 316 is formed in the opening and is connected to the exposed portion of the metallization pattern of the rewiring structure 306. The conductive connector 316 can be formed in a similar manner and material to the conductive connector 114 described with respect to FIG. 10.

In FIG. 16, the singulation process is performed by, for example, sawing along the dicing bead area around the package area 302A. The singulation process includes sawing the redistribution structure 306, the redistribution structure 312, and the sealing body 310. The singulation process separates the package area 302A from the adjacent package area (not illustrated) to form an integrated circuit package 300. After singulation, the rewiring structure 306, the rewiring structure 312, and the sealing body 310 are connected laterally.

Another integrated circuit package 400 may be attached to the integrated circuit package 300 to form a stacked package structure. The integrated circuit package 400 may be a memory package. The integrated circuit package 400 may be attached to the integrated circuit package 300 before or after the integrated circuit package 300 is singulated. The integrated circuit package 400 includes a substrate 402 and one or more dies 404 connected to the substrate 402. In some embodiments (not shown), one or more stacks of die 404 are connected to substrate 402. The substrate 402 may be made of a semiconductor material, such as silicon, germanium, diamond, or the like. In some embodiments, compound materials may also be used, such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphate, indium gallium phosphide, combinations of these, and the like By. In addition, the substrate 402 may be a silicon-on-insulator (SOI) substrate. Generally, the SOI substrate includes a semiconductor material layer, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. In an alternative embodiment, the substrate 402 is based on an insulating core such as a fiberglass reinforced resin core. An example core material is fiberglass resin such as FR4. Alternatives to the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. An accumulation film or other laminates such as flavor accumulation film (ABF) may be used for the substrate 402.

The substrate 402 may include active devices and passive devices (not shown). As those with ordinary knowledge in the art will recognize, a wide variety of components such as transistors, capacitors, resistors, combinations of these, and the like can be used to generate structural and functional requirements for the design of the integrated circuit package 400. Any suitable method can be used to form the element. The substrate 402 may also include a metallization layer (not shown) and perforations. The metallization layer can be formed on the active device and the passive device, and is designed to connect various devices to form a functional circuit. The metallization layer may be formed by alternating layers of dielectric (for example, low-k dielectric material) and conductive material (for example, copper) (where via holes interconnect the conductive material layer) and may be formed by any suitable process (such as deposition, Mosaic, double mosaic or similar). In some embodiments, the substrate 402 contains substantially no active devices and passive devices.

The substrate 402 may have a bonding pad 406 on one side of the substrate 402 connected to the conductive connector 316. In some embodiments, the bonding pad 406 is formed by forming a recess (not shown) into the dielectric layer (not shown) on the side of the substrate 402. The recess may be formed to allow the bonding pad 406 to be embedded in the dielectric layer. In other embodiments, the recess is omitted because the bonding pad 406 can be formed on the dielectric layer. In some embodiments, the bonding pad 406 includes a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bonding pad 406 may be deposited over the thin seed layer. The conductive material can be formed by an electrochemical plating process, an electrodeless plating process, CVD, ALD, PVD, the like, or a combination thereof. In one embodiment, the conductive material of the bonding pad 406 is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In an embodiment, the bonding pad 406 is a UBM including three conductive material layers (such as a titanium layer, a copper layer, and a nickel layer). For example, the bonding pad 406 may be formed of copper, may be formed on a titanium layer (not shown), and have a nickel finish, which can improve the shelf life of the integrated circuit package 400 This can be particularly advantageous when the integrated circuit package 400 is a memory device (such as a DRAM module). However, those with ordinary knowledge in the art will recognize that there are many suitable material and layer configurations suitable for forming the bonding pad 406, such as the configuration of chromium/chromium-copper alloy/copper/gold, titanium/titanium tungsten/ Copper configuration or copper/nickel/gold configuration. Any suitable material or material layer that can be used for the bonding pad 406 is all intended to be included in the scope of the current application.

In the illustrated embodiment, the die 404 is connected to the substrate 402 by conductive bumps, but other connections, such as wire bonding, may be used. In one embodiment, the die 404 is a stacked memory die. For example, the die 404 may be a memory die, such as a low-power (LP) double data rate (DDR) memory module, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like .

The die 404 and wire bonds (when present) may be sealed by the molding material 410. The molding material 410 may be molded on the die 404 and wire bonds, for example, using compression molding. In some embodiments, the molding material 410 is a molding compound, polymer, epoxy, silica filler material, the like, or a combination thereof. The curing process may be performed to cure the molding material 410; the curing process may be thermal curing, UV curing, the like, or a combination thereof. In some embodiments, the die 404 is buried in the molding material 410, and after the curing of the molding material 410, a planarization step such as grinding is performed to remove the excess portion of the molding material 410 and provide for the product The bulk circuit package 400 has a substantially flat surface.

After the integrated circuit package 400 is formed, the integrated circuit package 400 is attached to the integrated circuit package 300 by means of conductive connections 316. The conductive connector 316 can be connected to the bonding pad 406 by reflowing the conductive connector 316. The die 404 can thus be electrically coupled to the integrated circuit package 100 via the conductive connector 316, the via 308, and the rewiring structure 306 and the rewiring structure 312.

In some embodiments, solder resist (not shown) is formed on the side of the substrate 402 opposite to the die 404. The conductive connections 316 may be disposed in openings in the solder resist to be connected to conductive features in the substrate 402 (eg, bond pads 406). The solder resist can be used to protect the area of the substrate 402 from external damage.

In some embodiments, the conductive connector 316 has an epoxy solder (not shown) that uses the ring remaining after the integrated circuit package 400 is attached to the redistribution structure 306 when the conductive connector 316 is attached. At least some of the epoxy resin portion of the oxyresin flux is formed on the conductive connector 316 before reflowing.

In some embodiments, an underfill (not shown) is formed between the rewiring structure 306 and the substrate 402 and surrounds the conductive connection 316. The underfill can reduce stress and protect the joint created by the reflow of the conductive connector 316. The underfill may be formed by a capillary flow process after the integrated circuit package 400 is attached, or may be formed by a suitable deposition method before the integrated circuit package 400 is attached. In embodiments in which epoxy resin flux is formed, epoxy resin flux may serve as an underfill.

The stacked package structure is then turned over and attached to the package substrate 200 using conductive connections 314. The packaging substrate 200 may be similar to the packaging substrate 200 described with respect to FIG. 11. For example, the package substrate 200 may include bonding pads 202 connected to the conductive connectors 314.

FIG. 17 is a cross-sectional view of a system for implementing the integrated circuit package 100 according to some other embodiments. Fig. 17 is described along the reference cross section B-B in Fig. 2C and Fig. 2D. In this embodiment, the integrated circuit package 300 similar to that of FIG. 16 is formed, but the rewiring structure 306, the via 308, the conductive connector 316, and the integrated circuit package 400 are omitted.

The embodiments may realize advantages. Interconnecting the dies by hybrid bonding reduces the amount of data signal lines in the rewiring structure of the integrated circuit package. Power transmission and wiring can also be simplified by using passive components integrated in the integrated circuit package. Using a separate memory element instead of a memory including a processor element with an integrated circuit package may allow the total amount of memory in the integrated circuit package to be increased without substantially increasing the manufacturing cost of the processor element. In addition, the processor element without memory forming the integrated circuit package allows more processing units (eg, cores) to be included in the processor element without substantially increasing the coverage area of the processor element. The coverage area and manufacturing cost of the integrated circuit package can therefore be reduced.

It can also include other characteristics and manufacturing processes. For example, a test structure can be included to help verify and test 3D packages or 3DIC components. The test structure may include, for example, test pads formed in the redistribution layer or on the substrate, which allow testing of 3D packages or 3DIC, the use of probes and/or probe cards, and the like. The verification test can be performed on the intermediate structure and the final structure. In addition, the structure and method disclosed in this document can be used in conjunction with a test method incorporating intermediate verification of good bare dies to improve yield and reduce cost.

In one embodiment, the integrated circuit package includes: a first processor element having a front side; a shared memory element having a front side and a back side opposite to the front side, and the front side of the shared memory element is formed by metal-to-metal bonding and borrowing It is bonded to the front side of the first processor element by dielectric-to-dielectric bonding; the first dielectric layer laterally surrounds the shared memory element; the first via hole extends through the first dielectric layer; the second processor The component has a front side and a back side opposite to the front side. The first through hole connects the front side of the first processor component to the back side of the second processor component. The back side of the second processor component is joined by metal-to-metal bonding. Bonded to the backside of the first via and the shared memory element, the backside of the second processor element is bonded to the first dielectric layer, the first processor element and the second processor by dielectric-to-dielectric bonding The elements are each different types of processor elements; and the first rewiring structure is connected to the front side of the second processor element.

In some embodiments, the integrated circuit package further includes: a second dielectric layer laterally surrounding the second processor element; a second via hole extending through the second dielectric layer, the second via hole connecting the first layer The wiring structure is connected to the back side of the common memory device; and a third via extends through the first dielectric layer and the second dielectric layer, and the third via connects the first rewiring structure to the first processor device The front side. In some embodiments, the first rewiring structure includes a power supply source line and a power supply ground line, and the second via hole and the third via hole are each electrically coupled to the power supply source line and the power supply ground line. In some embodiments, the shared memory device includes a substrate via (TSV), and the second processor device is electrically coupled to the first processor device through the TSV and the first via. In some embodiments, the integrated circuit package further includes a passive component having a front side and a back side opposite to the front side. The front side of the passive component is bonded to the first by metal-to-metal bonding and by dielectric-to-dielectric bonding. The front side of the processor element; a second dielectric layer laterally surrounding the second processor element; and a second via hole extending through the second dielectric layer, the second via hole connecting the first redistribution structure to the passive device The back side. In some embodiments, the first processor element is a graphics processing unit (GPU), the second processor element is a central processing unit (CPU), and the passive element is a power management integrated circuit (PMIC) for the GPU. In some embodiments, the integrated circuit package further includes: a sealing body that laterally surrounds the shared memory element, the first processor element, the second processor element, and the first redistribution structure; and the second redistribution structure, which contacts The sealing body, the second redistribution structure is connected to the first redistribution structure. In some embodiments, the integrated circuit package further includes: a packaging substrate; and a conductive connection member for connecting the packaging substrate to the second redistribution structure. In some embodiments, the integrated circuit package further includes: a packaging substrate; and a conductive connection member for connecting the packaging substrate to the first redistribution structure. In some embodiments, the first processor element and the second processor element have active elements with smaller technology nodes than the shared memory element.

In one embodiment, the integrated circuit package includes: a graphics processor component; a passive component, coupled to the graphics processor component, the passive component is directly face-to-face bonded to the graphics processor component; a shared memory component, coupled to the graphics processor Components, shared memory components are directly face-to-face bonded to graphics processor components; CPU components are coupled to shared memory components, and CPU components are directly back-to-back bonded to shared memory components, CPU components, and graphics processor components Active components each having a smaller technology node than the shared memory component; and a rewiring structure, coupled to the central processing unit, the shared memory component, the passive component, and the graphics processor component.

In some embodiments, the shared memory device is narrower than the CPU device in the first plane, and the shared memory device is wider than the CPU device in the second plane, and the first plane is perpendicular to the second plane. In some embodiments, the graphics processor element is wider in the first plane and the second plane than the central processor element and the shared memory element.

In one embodiment, a method of manufacturing an integrated circuit package includes: bonding a common memory element to a first processor element; forming a first dielectric layer around the common memory element; forming a first dielectric layer that extends through The first via hole, the first via hole is connected to the first processor element; the second processor element is joined to the first via hole, the first dielectric layer and the shared memory element, the first processor element and the second Each of the processor elements is a different type of processor element; a second dielectric layer is formed around the second processor element; a second via hole extending through the second dielectric layer is formed, and the second via hole is connected to the shared memory Device; forming a third via hole extending through the first dielectric layer and the second dielectric layer, the third via hole is connected to the first processor element; and in the second via hole, the third via hole, the second dielectric A rewiring structure is formed on the electrical layer and the second processor element.

In some embodiments, the method further includes: obtaining a wafer including the first processor element, wherein bonding the common memory element to the first processor element includes bonding the common memory element to the wafer; and forming the redistribution After the structure, sawing the wafer, the first dielectric layer, the second dielectric layer and the rewiring structure. In some embodiments, the method further includes, before bonding the shared memory device to the first processor device: obtaining a wafer containing the first processor device; sawing the wafer to singulate the first processor device; And sealing the first processor element. In some embodiments, forming the first via hole includes: patterning a first opening in the first dielectric layer, the first opening exposing the die connector of the first processor element; and plating a conductive material in the first opening And planarizing the conductive material and the first dielectric layer, the remaining part of the conductive material in the first opening forms a first via hole. In some embodiments, forming the second via hole includes: patterning the second opening in the second dielectric layer, the second opening exposing the die connector of the shared memory device; plating a conductive material in the second opening; And planarizing the conductive material and the second dielectric layer, and the remaining part of the conductive material in the second opening forms a second via hole. In some embodiments, the method further includes bonding the passive device to the first processor device, wherein forming the first dielectric layer includes forming a first dielectric layer around the passive device, and wherein a subset of the second vias are connected To passive components. In some embodiments, the first processor element is a graphics processing unit (GPU), the second processor element is a central processing unit (CPU), and the passive element is a power management integrated circuit (PMIC) for the GPU.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspect of the disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other manufacturing processes and structures for achieving the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes in this article without departing from the spirit and scope of the present disclosure. Changes, substitutions and changes.

20: first processor element 20F, 40F, 60F, 80F: front side 22, 42, 62, 82: semiconductor substrate 22A, 42A, 62A: active surface 22N, 42N, 62N: non-active surface 24, 44, 64, 84 : Interconnect structure 28, 48, 68, 88: die connector 30, 50, 70, 90: dielectric layer 32, 310: sealing body 40: second processor element 40B, 60B, 80B: back side 46 , 66, 86, 308: Via 60: Memory component 80: Passive component 100, 300, 400: Integrated circuit package 102, 306, 312: Redistribution structure 104: First dielectric layer 106: First via 108: second dielectric layer 110: second via hole 112: third via hole 114, 314, 316: conductive connection 120: wafer 120A: component area 200: package substrate 202, 406: bonding pad 302: carrier substrate 302A: Package area 304: Release layer 402: Substrate 404: Die 410: Molding materials AA, BB: Reference cross-sections W ₁ , W ₂ , W ₃ , W ₄ , W ₅ , W ₆ , W ₇ , W ₈ :width

When read in conjunction with the accompanying drawings, the aspect of the disclosure can be best understood from the following detailed description. It should be noted that according to standard practices in the industry, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or decreased for clarity of discussion. 1A, 1B, 1C, and 1D are cross-sectional views of semiconductor devices according to some embodiments. 2A, 2B, 2C, and 2D are various views of integrated circuit packages according to some embodiments. Figures 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, and 8B illustrate the use of an integrated circuit package according to some embodiments. A cross-sectional view of an intermediate step during the manufacturing process. 9A and 9B are cross-sectional views of integrated circuit packages according to some embodiments. 10 and 11 are cross-sectional views of intermediate steps during a process for forming a system implementing integrated circuit packaging according to some embodiments. Figures 12, 13, Figure 14, Figure 15, and Figure 16 are cross-sectional views of intermediate steps during a process for forming a system implementing integrated circuit packaging according to some embodiments. Figure 17 is a cross-sectional view of a system implementing integrated circuit packaging according to some embodiments.

20: The first processor element

40: second processor element

60: memory components

80: Passive components

100: Integrated circuit package

102: Rewiring structure

104: first dielectric layer

106: first via

108: second dielectric layer

110: second via

112: third via

Claims (20)

An integrated circuit package, including: The first processor element has a front side; A shared memory device having a front side and a back side opposite to the front side, and the front side of the shared memory device is bonded to the first process by metal-to-metal bonding and by dielectric-to-dielectric bonding The front side of the device element; A first dielectric layer laterally surrounds the shared memory device; A first via hole extending through the first dielectric layer; The second processor element has a front side and a back side opposite to the front side, and the first via hole connects the front side of the first processor element to the back side of the second processor element , The back side of the second processor element is bonded to the back side of the first via and the shared memory element by metal-to-metal bonding, and all of the second processor element The backside is bonded to the first dielectric layer by dielectric-to-dielectric bonding, and the first processor element and the second processor element are each different types of processor elements; and The first rewiring structure is connected to the front side of the second processor element. For example, the integrated circuit package of claim 1, including: A second dielectric layer laterally surrounding the second processor element; A second via hole extending through the second dielectric layer, the second via hole connecting the first rewiring structure to the back side of the shared memory device; and The third via hole extends through the first dielectric layer and the second dielectric layer, and the third via hole connects the first rewiring structure to the first processor element Front side. The integrated circuit package of claim 2, wherein the first rewiring structure includes a power supply source line and a power supply ground line, and the second via and the third via are each electrically coupled to the power A supply source line and the power supply ground line. The integrated circuit package of claim 1, wherein the shared memory element includes a substrate via (TSV), and the second processor element is electrically coupled to the first via via the TSV and the first via A processor element. For example, the integrated circuit package of claim 1, including: A passive element has a front side and a back side opposite to the front side, and the front side of the passive element is joined to all of the first processor element by metal-to-metal bonding and by dielectric-to-dielectric bonding. The front side A second dielectric layer laterally surrounding the second processor element; and A second via hole extends through the second dielectric layer, and the second via hole connects the first redistribution structure to the back side of the passive element. Such as the integrated circuit package of claim 5, wherein the first processor element is a graphics processing unit (GPU), the second processor element is a central processing unit (CPU), and the passive element is used for all The power management integrated circuit (PMIC) of the GPU is described. For example, the integrated circuit package of claim 1, including: A sealing body laterally surrounding the shared memory element, the first processor element, the second processor element, and the first rewiring structure; and A second redistribution structure contacts the sealing body, and the second redistribution structure is connected to the first redistribution structure. For example, the integrated circuit package of claim 7, including: Package substrate; and A conductive connector connects the packaging substrate to the second rewiring structure. For example, the integrated circuit package of claim 1, including: Package substrate; and A conductive connector connects the packaging substrate to the first redistribution structure. The integrated circuit package of claim 1, wherein the first processor element and the second processor element have active elements with smaller technology nodes than the shared memory element. An integrated circuit package, including: Graphics processor components; A passive element coupled to the graphics processor element, and the passive element is directly connected to the graphics processor element face-to-face; A shared memory element coupled to the graphics processor element, and the shared memory element is directly connected to the graphics processor element face-to-face; The central processing unit is coupled to the shared memory element, the central processing unit is directly connected to the shared memory element back-to-back, and the central processing unit and the graphics processing unit each have a higher ratio than the Share active components of smaller technology nodes with memory components; and The rewiring structure is coupled to the central processing unit, the shared memory component, the passive component, and the graphics processing unit. The integrated circuit package of claim 11, wherein the shared memory element is narrower than the central processing unit element in the first plane, and the shared memory element is narrower than the central processing unit in the second plane The element is wider, and the first plane is perpendicular to the second plane. The integrated circuit package of claim 12, wherein the graphics processor element is wider in the first plane and the second plane than the central processing unit and the shared memory element. A manufacturing method of integrated circuit packaging, including: Bonding the shared memory element to the first processor element; Forming a first dielectric layer around the shared memory device; Forming a first via hole extending through the first dielectric layer, the first via hole being connected to the first processor element; Bonding a second processor element to the first via, the first dielectric layer, and the shared memory element, the first processor element and the second processor element are each of a different type Processor element Forming a second dielectric layer around the second processor element; Forming a second via hole extending through the second dielectric layer, the second via hole being connected to the common memory device; Forming a third via hole extending through the first dielectric layer and the second dielectric layer, the third via hole being connected to the first processor element; and A rewiring structure is formed on the second via, the third via, the second dielectric layer, and the second processor element. Such as the method of claim 14, including: Obtaining a wafer including the first processor element, wherein bonding the common memory element to the first processor element includes bonding the common memory element to the wafer; and After forming the rewiring structure, sawing the wafer, the first dielectric layer, the second dielectric layer, and the rewiring structure. The method of claim 14, further comprising, before joining the shared memory component to the first processor component: Obtaining a wafer including the first processor element; Sawing the wafer to singulate the first processor element; and The first processor element is sealed. The method of claim 14, wherein forming the first via hole includes: Patterning a first opening in the first dielectric layer, the first opening exposing the die connector of the first processor element; Plating a conductive material in the first opening; and The conductive material and the first dielectric layer are planarized, and the remaining part of the conductive material in the first opening forms the first via hole. The method of claim 17, wherein forming the second via hole includes: Patterning a second opening in the second dielectric layer, the second opening exposing the die connector of the shared memory device; Plating the conductive material in the second opening; and The conductive material and the second dielectric layer are planarized, and the remaining part of the conductive material in the second opening forms the second via hole. Such as the method of claim 14, including: Bonding a passive device to the first processor device, wherein forming the first dielectric layer includes forming the first dielectric layer around the passive device, and wherein a subset of the second vias Connected to the passive component. Such as the method of claim 19, wherein the first processor element is a graphics processing unit (GPU), the second processor element is a central processing unit (CPU), and the passive element is for the GPU Power management integrated circuit (PMIC).

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