TW202117712A - Semiconductor memory - Google Patents

Abstract

To provide a semiconductor memory capable of accelerating a reading operation of the semiconductor memory. A semiconductor memory of the embodiment includes first and second memory cells, word lines connected to the first and second memory cells, first and second bit lines respectively connected to the first and second memory cells, first and second sense amplifiers respectively connected to the first and second bit lines, and a controller. Each of the first and second sense amplifiers includes first to third transistors. The third transistor has one end electrically connected to the first and second transistors and the other end connected to the bit line. In a reading operation, the controller applies a read-out voltage ER to the word line. At a first time t5, the controller respectively applies a first voltage Vblk and a second voltage Vblc to the first and second transistors, the first sense amplifier applies a voltage to the first bit line through the first to third transistors, and the second sense amplifier applies the voltage to the second bit line through the second and third transistors.

Description

Semiconductor memory

The embodiment is related to a semiconductor memory.

A NAND (Not And) type flash memory that can store data non-volatilely is known.

The embodiment provides a semiconductor memory capable of speeding up the read operation.

The semiconductor memory of the embodiment includes first and second memory cells, word lines, first and second bit lines, first and second sense amplifiers, and a controller. The first and second memory cells respectively store multiple bits of data based on the threshold voltage. The character line is connected to the respective gates of the first and second memory cells. The first and second bit lines are connected to the first and second memory cells, respectively. The first and second sense amplifiers are connected to the first and second bit lines, respectively. The first and second sense amplifiers respectively include a first transistor, a second transistor, and a third transistor. One end of the third transistor is electrically connected to the first transistor and the second transistor, and the other end is connected to the corresponding bit line. In the read operation of the first and second memory cells, the controller applies the first read voltage to the word line. At the first time included in the first period in which the controller applies the first readout voltage, the controller applies a first voltage higher than the ground voltage to the first transistor, and applies a second voltage different from the first voltage to the second transistor. 2 voltage. At the first moment, the first sense amplifier applies voltage to the first bit line via the first transistor and the third transistor, and the second sense amplifier applies voltage to the second bit line via the second transistor and the third transistor. Apply voltage.

Hereinafter, the embodiment will be described with reference to the drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of the invention. The diagram is a schematic or conceptual diagram, and the size and ratio of each diagram are not necessarily limited to the same as the actual diagram. The technical idea of the present invention is not specified by the shape, structure, arrangement, etc. of the constituent elements.

In addition, in the following description, components having substantially the same function and structure are denoted by the same reference numerals. The numbers after the characters constituting the reference symbols are referred to by the reference symbols containing the same characters, and are used to distinguish elements with the same structure from each other. When there is no need to distinguish the elements shown by the reference signs containing the same text from each other, these elements are respectively referred to by the reference signs containing only text. [1] The first embodiment

Hereinafter, the semiconductor memory 1 of the first embodiment will be described. [1-1] The structure of semiconductor memory 1 [1-1-1] The overall structure of semiconductor memory 1

The semiconductor memory 1 is, for example, a NAND flash memory capable of storing data non-volatilely. The semiconductor memory 1 is controlled by, for example, an external memory controller 2. FIG. 1 shows a configuration example of the semiconductor memory 1 of the embodiment.

As shown in FIG. 1, the semiconductor memory 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a column decoder module 15, and a sense amplifier module 16.

The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer greater than 1). The block BLK is a collection of a plurality of memory cells that can memorize data non-volatilely, for example, it is used as a data deletion unit.

Moreover, in the memory cell array 10, a plurality of bit lines and a plurality of character lines are provided. Each memory cell is associated with, for example, one bit line and one character line. The detailed structure of the memory cell array 10 will be described below.

The command register 11 stores the command CMD received by the semiconductor memory 1 from the memory controller 2. The command CMD includes, for example, a command for the sequencer 13 to execute a read operation, a write operation, a delete operation, and the like.

The address register 12 stores the address information ADD received by the semiconductor memory 1 from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a row address CAd. For example, the block address BAd, the page address PAd, and the row address CAd are respectively used for the selection of the block BLK, the word line, and the bit line.

The sequencer 13 controls the overall operation of the semiconductor memory 1. For example, the sequencer 13 controls the driver module 14, the column decoder module 15, and the sense amplifier module 16, etc. based on the command CMD stored in the command register 11, and executes the read operation, the write operation, and the delete operation. Wait.

The driver module 14 generates voltages used in read operations, write operations, delete operations, and the like. Furthermore, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line based on the page address PAd stored in the address register 12, for example.

The column decoder module 15 selects a block BLK in the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Moreover, the column decoder module 15 transmits, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

In the write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. In addition, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line during the read operation, and transmits the determination result to the memory controller 2 as the read data DAT.

The communication between the semiconductor memory 1 and the memory controller 2 supports the NAND interface standard, for example. For example, in the communication between the semiconductor memory 1 and the memory controller 2, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REn are used , Ready and busy signal RBn, and input and output signal I/O.

The command latch enabling signal CLE is a signal indicating that the input/output signal I/O received by the semiconductor memory 1 is the command CMD. The address latch enable signal ALE is a signal indicating that the signal I/O received by the semiconductor memory 1 is the address information ADD. The write enable signal WEn is a signal for sending the input command of the input/output signal I/O to the semiconductor memory 1. The read enable signal REn is a signal for sending the output command of the input/output signal I/O to the semiconductor memory 1.

The ready busy signal RBn is a signal for notifying the memory controller 2 of the ready state of the semiconductor memory 1 accepting the command from the memory controller 2 or the busy state of not accepting the command. The input and output signal I/O is, for example, an 8-bit wide signal, which may include command CMD, address information ADD, data DAT, and so on.

The semiconductor memory 1 and the memory controller 2 described above can also be combined to form a semiconductor device. As such a semiconductor device, for example ^{, a memory card such as an SD TM} card or an SSD (solid state drive) can be cited. [1-1-2] Circuit configuration of memory cell array 10

FIG. 2 shows an example of the circuit configuration of the memory cell array 10 included in the semiconductor memory 1 of the embodiment by extracting one block BLK from the plurality of blocks BLK included in the memory cell array 10.

As shown in FIG. 2, the block BLK includes, for example, four string units SU0 to SU3. Each string unit SU includes a plurality of NAND strings NS.

A plurality of NAND strings NS are respectively associated with bit lines BL0 to BLm (m is an integer greater than 1). Each NAND string NS includes, for example, memory cell transistors MT0 to MT11, and select transistors ST1 and ST2.

The memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a non-volatile manner. The selection transistors ST1 and ST2 are respectively used for the selection of the string unit SU during various actions.

In each NAND string NS, the memory cell transistors MT0 to MT11 are connected in series between the selection transistors ST1 and ST2. In the same block BLK, the control gates of the memory cell transistors MT0 to MT11 are respectively connected to the word lines WL0 to WL11 in common.

In each NAND string NS, the drain of the select transistor ST1 is connected to the bit line BL to be associated, and the source of the select transistor ST1 is connected to one end of the memory cell transistors MT0 to MT11 connected in series. In the same block BLK, the gates of the selection transistors ST1 in the string units SU0 to SU3 are respectively connected to the selection gate lines SGD0 to SGD3 in common.

In each NAND string NS, the drain of the selected transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT11 connected in series. In the same block BLK, the source of the selection transistor ST2 is commonly connected to the source line SL, and the gate of the selection transistor ST2 is commonly connected to the selection gate line SGS.

In the circuit configuration of the memory cell array 10 described above, the bit line BL is, for example, commonly connected between a plurality of NAND strings NS corresponding to each block BLK. The source line SL is, for example, commonly connected between a plurality of blocks BLK.

A collection of a plurality of memory cell transistors MT connected to a common word line WL in one string unit SU is called a unit CU, for example. For example, the memory capacity of a cell CU including a memory cell transistor MT that respectively stores 1 bit of data is defined as "1 page of data". The unit CU can have a memory capacity of more than 2 pages of data according to the number of bits of the data stored in the memory cell transistor MT.

In addition, the circuit configuration of the memory cell array 10 included in the semiconductor memory 1 of the embodiment is not limited to the configuration described above. For example, the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number, respectively. The number of string units SU included in each block BLK can be designed to be any number. [1-1-3] Structure of memory cell array 10

Hereinafter, an example of the structure of the semiconductor memory 1 of the embodiment will be described.

Furthermore, in the drawings referred to below, the X direction corresponds to the extending direction of the word line WL, the Y direction corresponds to the extending direction of the bit line BL, and the Z direction corresponds to the semiconductor substrate 20 on which the semiconductor memory 1 is formed. The surface corresponds to the vertical direction.

In addition, in the cross-sectional views referred to below, in order to facilitate the observation of the drawings, constituent elements such as insulating layers (interlayer insulating films), wiring, and contacts are appropriately omitted. Also, in the plan view, hatching is appropriately added in order to make it easier to observe the figure. The hatching attached to the top view is not necessarily related to the materials or characteristics of the component elements to which the hatching is attached.

(Planar layout of memory cell array 10)

FIG. 3 shows an example of the planar layout of the memory cell array 10 included in the semiconductor memory 1 of the embodiment by extracting eight blocks BLK0 to BLK7 from the plurality of blocks BLK.

As shown in FIG. 3, the blocks BLK0 to BLK7 respectively extend along the X direction. The blocks BLK0 to BLK7 are arranged in the Y direction.

The area of the memory cell array 10 can be divided into, for example, a unit area CA and lead-out areas HA1 and HA2. For example, the lead-out areas HA1 and HA2 are respectively arranged at one end portion and the other end portion of the block BLK in the X direction. The unit area CA is arranged between the lead-out area HA1 and the lead-out area HA2.

The cell area CA is an area where a plurality of NAND strings NS are formed. The lead-out areas HA1 and HA2 are respectively areas for forming contacts for electrically connecting each of the select gate lines SGD and SGS and the word line WL connected to the NAND string NS and the column decoder module 15.

In addition, in the area where the block BLK is provided, for example, a plurality of slits SLT, SLTa, and SLTb are provided. In each of the slits SLT, SLTa, and SLTb, for example, an insulator is embedded.

Each slit SLT extends from the lead-out area HA1 to the lead-out area HA2 along the X direction, and the plurality of slits SLT are arranged in the Y direction. Between adjacent slits SLT, for example, one slit SLTa and two slits SLTb are arranged.

For example, between adjacent slits SLT, the slits SLTa and SLTb respectively extend along the X direction. The two slits SLTb are respectively arranged in the lead-out areas HA1 and HA2. The slit SLTa is arranged between the slit SLTb in the lead-out area HA1 and the slit SLTb in the lead-out area HA2.

In other words, between adjacent slits SLT, for example, a horizontal slit extending in the X direction and including the slit dividing portion DJ is provided. The horizontal slit is divided by the slit dividing part DJ in each of the lead-out areas HA1 and HA2.

Among the divided horizontal slits, the slit part extending from the lead-out area HA1 to the lead-out area HA2 corresponds to the slit SLTa, and the slit parts provided in the lead-out areas HA1 and HA2 correspond to the slit SLTb.

The structure between the adjacent slits SLT described above corresponds to, for example, one block BLK. Furthermore, the number of slits SLTa and SLTb arranged between the slits SLT can be designed to be any number. Between the slit SLT, the slit dividing part DJ can also be omitted.

(Structure of the memory cell array 10 in the cell area CA)

FIG. 4 shows an example of the planar layout in the cell area CA of the memory cell array 10 included in the semiconductor memory 1 of the first embodiment by extracting one block BLK.

As shown in FIG. 4, the memory cell array 10 in the cell area CA includes, for example, a plurality of memory pillars MP and a plurality of dummy pillars DMP. Between the slit SLT and the slit SLTa, for example, a slit SHE is provided.

The slit SHE extends from the lead-out area HA1 to the lead-out area HA2 along the X direction. In the slit SHE, for example, an insulator is embedded.

The dummy pillar DMP is, for example, a structure that has the same structure as the memory pillar MP, but is not used for data storage. The dummy pillar DMP is arranged so as to overlap with the slit SHE, for example.

A plurality of memory pillars MP are arranged between the slit SLT and the slit SHE, for example, in a grid pattern. Similarly, a plurality of memory pillars MP are arranged between the slit SLTa and the slit SHE, for example, in a grid pattern.

The memory pillar MP functions as, for example, one NAND string NS. For example, a set of a plurality of memory pillars MP arranged between the slit SLT and the slit SHE corresponds to one string unit SU. Similarly, a set of a plurality of memory pillars MP arranged between the slit SLTa and the slit SHE corresponds to one string unit SU.

Moreover, in the cell area CA, in the memory cell array 10, corresponding to the arrangement of the memory pillar MP, a plurality of bit lines BL and a plurality of contacts CP are provided.

The bit lines BL respectively extend in the Y direction and are arranged in the X direction. The bit line BL is arranged to overlap with at least one memory pillar MP for each string unit SU. In each memory pillar MP, for example, two bit lines BL overlap.

The contact point CP is arranged between one bit line BL of the plurality of bit lines BL overlapping with the memory pillar MP and the memory pillar MP. Each memory pillar MP is electrically connected to the corresponding bit line BL through the contact CP.

Furthermore, the number of string units SU arranged between adjacent slits SLT can be designed to be any number. The number and arrangement of the memory pillars MP shown in the figure are just an example, and the memory pillars MP can be designed to have any number and arrangement. The number of bit lines BL overlapping with each memory pillar MP can be designed to be any number.

5 is a cross-sectional view of the memory cell array 10 along the line V-V of FIG. 4, showing an example of the cross-sectional structure of the block BLK in the cell area CA.

As shown in FIG. 5, the area corresponding to the cell area CA includes, for example, conductors 21-25, memory pillars MP, dummy pillars DMP, contacts CP, and slits SLT, SLTa, and SHE.

Above the semiconductor substrate 20, a conductor 21 is provided with an insulating edge layer. Although the illustration is omitted, the insulating layer between the semiconductor substrate 20 and the conductor 21 is provided with circuits such as the column decoder module 15 or the sense amplifier module 16, for example.

The conductor 21 is formed, for example, in a plate shape extending along the XY plane, and is used as a source line SL.

On the conductor 21, a conductor 22 is provided with an insulating edge layer. The conductor 22 is formed, for example, in a plate shape extending along the XY plane, and is used as a selective gate line SGS.

On the conductor 22, insulating layers and conductors 23 are alternately laminated. The conductor 23 is formed, for example, in a plate shape extending along the XY plane. For example, the plurality of laminated conductors 23 are used as the word lines WL0 to WL11 in order from the side of the semiconductor substrate 20, respectively.

On the conductor 23, a conductor 24 is provided with an insulating edge layer. The conductor 24 is formed, for example, in a plate shape extending along the XY plane, and is used as a selective gate line SGD.

On the conductor 24, a conductor 25 is provided with an insulating edge layer. The conductor 25 is formed, for example, in a linear shape extending in the Y direction, and is used as a bit line BL. That is, in a region not shown, a plurality of conductors 25 are arranged in the X direction.

The memory pillar MP is formed in a pillar shape extending along the Z direction, for example, through the conductors 22-24. For example, the upper end of the memory pillar MP is included in the layer between the layer provided with the conductive body 24 and the layer provided with the conductive body 25. The lower end of the memory pillar MP is, for example, included in the layer provided with the conductor 21 and is in contact with the conductor 21.

In addition, the memory pillar MP includes, for example, a core member 30, a semiconductor 31, and a build-up film 32. The core member 30 is, for example, an insulator, and is formed in a columnar shape extending along the Z direction. The upper end of the core member 30 is, for example, included in the upper layer than the layer provided with the conductor 24. The lower end of the core member 30 is, for example, contained in a layer where the conductor 21 is provided.

The core member 30 is covered by a semiconductor 31. The semiconductor 31 is in contact with the conductor 21 via the side surface of the memory pillar MP. The laminated film 32 covers the side surface and the bottom surface of the semiconductor 31 except for the part where the conductor 21 and the semiconductor 31 are in contact.

On the semiconductor 31, a columnar contact CP is provided. On the upper surface of the contact CP, there is a conductive body 25 in contact, that is, a bit line BL. Furthermore, the memory pillar MP and the conductor 25 may be electrically connected through two or more contacts, or may be electrically connected through other wiring.

The dummy post DMP is formed in a columnar shape extending along the Z direction, and penetrates the conductors 22-24, for example. The detailed structure of the dummy pillar DMP is, for example, the same as the structure of the memory pillar MP. In the dummy column DMP, for example, the contact point CP is not connected.

The slit SLT is formed, for example, in a plate shape extending along the XZ plane, and divides the conductors 22 to 24. For example, the upper end of the slit SLT is included in the layer between the layer including the upper end of the memory pillar MP and the layer provided with the conductor 25. The lower end of the slit SLT is, for example, included in the layer provided with the conductor 21. The structure of the slit SLTa is, for example, the same as the structure of the slit SLT.

The slit SHE extends in the X direction, for example, and divides the conductor 24. The slit SHE can also divide a part of the dummy post DMP. For example, the upper end of the slit SHE is included in the layer between the layer including the upper end of the memory pillar MP and the layer provided with the conductor 25. The lower end of the slit SHE includes, for example, a layer between the conductor 23 and the conductor 24 of the uppermost layer. The slit SHE extending in the X direction can also be divided by the dummy post DMP at a position overlapping with the dummy post DMP.

FIG. 6 shows an example of the cross-sectional structure of the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductor 23.

As shown in FIG. 6, in the layer including the conductor 23, the core member 30 is disposed at the center of the memory pillar MP. The semiconductor 31 surrounds the side surface of the core member 30. The build-up film 32 surrounds the side surface of the semiconductor 31. The build-up film 32 includes, for example, a tunnel oxide film 33, an insulating film 34, and a barrier insulating film 35.

The tunnel oxide film 33 surrounds the side surface of the semiconductor 31. The insulating film 34 surrounds the side surface of the tunnel oxide film 33. The barrier insulating film 35 surrounds the side surface of the insulating film 34. The conductor 23 surrounds the side surface of the barrier insulating film 35.

In the configuration of the memory pillar MP described above, for example, the intersection of the memory pillar MP and the conductor 22 functions as the selective transistor ST2. The intersection of the memory pillar MP and the conductor 23 functions as a memory cell transistor MT. The intersection of the memory pillar MP and the conductor 24 functions as a selective transistor ST1.

That is, the semiconductor 31 in the memory pillar MP functions as the respective channels of the memory cell transistor MT and the selection transistors ST1 and ST2. The insulating film 34 in the memory pillar MP functions as a charge storage layer of the memory cell transistor MT.

(The structure of the memory cell array 10 in the lead-out area HA)

FIG. 7 shows an example of the planar layout in the lead-out area HA1 of the memory cell array 10 included in the semiconductor memory 1 of the first embodiment by extracting the adjacent blocks BLK0 and BLK1 of the plurality of blocks BLK. First, the planar layout of the block BLK0 in the lead-out area HA1 will be described.

As shown in FIG. 7, in the area corresponding to the block BLK0 in the lead-out area HA1, the selection gate line SGD (conductor 24) is divided into four by slits SLT, SLTa, and SHE. The selected gate lines SGD divided into four correspond to the string units SU0 to SU3, respectively.

The word lines WL0 to WL11 (conductors 23) have portions (step surface portions) that do not overlap with the upper layer conductors. For example, the plurality of conductors 23 respectively corresponding to the word lines WL0 to WL11 are arranged in a step shape with two steps in the Y direction and three rows of steps in the X direction.

The slit dividing portion DJ is disposed, for example, on the step surface portion of the character line WL11. The character lines WL arranged in the same layer in the same block BLK are short-circuited through the slit dividing portion DJ. The slit SLTb is arranged in such a way as to divide the step surfaces of the word lines WL1, WL4, WL7, and WL10, for example.

The selection gate line SGS (conductor 22) is drawn in the X direction from the end regions of the word lines WL0 to WL2, for example. The slit SLTb can either disconnect the selective gate line SGS or not. Each selection gate line SGS arranged in the adjacent block BLK is divided by the slit SLT.

In addition, in the area corresponding to the block BLK0, for example, the step surface portions of the selection gate line SGS, the word lines WL0 to WL11, and the selection gate line SGD are respectively provided with contacts CC.

The select gate line SGS, the word lines WL0 to WL11, and the select gate line SGD of the block BLK0 are respectively electrically connected to the column decoder module 15 through the contact CC provided in the lead-out area HA1.

The planar layout of the block BLK1 in the lead-out area HA1 is, for example, the same as the layout in which the planar layout of the block BLK0 is inverted with the X direction as the symmetry axis and the contact CC is omitted.

In this case, the select gate line SGS, the word lines WL0 to WL11, and the select gate line SGD of the block BLK1 are electrically connected to the column decoder module 15 through the contact CC provided in the lead-out area HA2, respectively .

Specifically, the planar layout of the blocks BLK0 and BLK1 in the lead-out area HA2 corresponds to the wiring in the block BLK1 by inverting the planar layout of the blocks BLK0 and BLK1 in the lead-out area HA1 with the Y direction as the axis of symmetry. The ground is provided with the same plane layout of the contact CC.

FIG. 8 is a cross-sectional view of the memory cell array 10 along the line VIII-VIII of FIG. 7, showing an example of the cross-sectional structure of the block BLK in the lead-out area HA. In addition, in FIG. 8, the arrangement of the slit SHE provided in the depth direction of the cross-sectional view is indicated by a broken line.

As shown in FIG. 8, the area corresponding to the block BLK0 in the lead-out area HA1 includes, for example, the conductors 21-24, the conductors 40 and 41, and the contacts CC and V1.

In the lead-out area HA1, the end portion of the conductor 21 corresponding to the source line SL is provided, for example, on the inner side of the conductor 22. The conductor 21 only needs to be provided in at least the cell area CA. The respective ends of the conductor 22, the conductor 23, and the conductor 24 respectively corresponding to the select gate line SGS, the word line WL, and the select gate line SGD are not connected to the conductor 23 or 24 overlapping parts.

The slit SHE is provided in such a way that the conductor 24 corresponding to the selection gate line SGD is disconnected. Each contact CC is formed in a columnar shape extending along the Z direction. The contact CC includes, for example, a conductor formed in a columnar shape.

The conductors 40 and 41 are wirings for connecting the conductors 22 to 24 drawn from the cell area CA to the lead area HA1 and the column decoder module 15 respectively. The plurality of conductors 40 are respectively arranged on the plurality of contacts CC.

A plurality of contacts V1 are respectively provided on the plurality of conductors 40. A plurality of conductors 41 are respectively provided on the plurality of contacts V1. The conductors 40 and 41 may be connected via a plurality of contacts, or different wirings may be connected between the plurality of contacts.

In the structure of the block BLK0 in the lead-out area HA1 described above, the wiring drawn through the contact CC is electrically connected to the circuit under the memory cell array 10 through, for example, a region outside the lead-out area HA1.

It is not limited to this. The wiring led out via the contact CC can also be electrically connected to the circuit under the memory cell array 10, for example via a contact that penetrates a dummy block provided in the lead-out area HA1, or via a through hole. The contacts provided on the wider stepped surface portion of the lead-out area HA1 are electrically connected.

As described above, in the semiconductor memory 1 of the first embodiment, a voltage is applied to the word line WL (conductor 23) via the contact CC connected to one side in the X direction. According to the structure of the character line WL, the influence of the RC delay of the wiring cannot be ignored in the part of the character line WL far from the connection part of the contact CC.

In this specification, the term "RC delay" means the length of the RC delay time, which is the time after the voltage is applied to the wiring until the voltage of the wiring rises to the target value. In addition, in the following description, the part of the character line WL far away from the connection part of the contact CC is referred to as the "distal end of the character line WL", and the part of the character line WL close to the connection part of the contact CC It is called the "near end of the character line WL".

Furthermore, in the structure of the memory cell array 10 described above, the number of conductors 23 is designed based on the number of word lines WL. In the selection gate line SGS, a plurality of conductors 22 arranged on a plurality of layers can also be allocated. When the gate line SGS is selected to be arranged in multiple layers, a conductor different from the conductor 22 can also be used. In the selection gate line SGD, a plurality of conductors 24 arranged on a plurality of layers can also be allocated. [1-1-4] Circuit composition of column decoder module 15

FIG. 9 shows an example of the circuit configuration of the column decoder module 15 included in the semiconductor memory 1 of the first embodiment.

As shown in FIG. 9, the column decoder module 15 includes, for example, column decoders RD0 to RDn. The column decoder RD is used for the selection of the block BLK. The column decoders RD0-RDn are respectively associated with the blocks BLK0-BLKn.

Hereinafter, focusing on the column decoder RD0 corresponding to the block BLK0, the detailed circuit configuration of the column decoder RD will be described.

The column decoder RD includes, for example, a block decoder BD and high voltage n-channel MOS (metal oxide semiconductor) transistors TR1 to TR13.

The block decoder BD decodes the block address BA. Furthermore, the block decoder BD applies a specific voltage to the transfer gate line TG based on the decoding result. The transmission gate line TG is commonly connected to the gates of the transistors TR1 to TR13. Transistors TR1 to TR13 are connected between various signal lines wired from the driver module 14 and various wirings of the block BLK to be associated.

Specifically, the driver module 14 is connected to the signal lines SGDD0 to SGDD3, the signal lines CG0 to CG7, and the signal line SGSD. The signal lines SGDD0 to SGDD3 correspond to the selection gate lines SGD0 to SGD3, respectively. The signal lines CG0 to CG7 correspond to the word lines WL0 to WL7, respectively. The signal line SGSD corresponds to the selection gate line SGS.

One end of the transistor TR1 is connected to the signal line SGSD. The other end of the transistor TR1 is connected to the select gate line SGS. One end of the transistors TR2 to TR9 is respectively connected to the signal lines CG0 to CG7. The other ends of the transistors TR2 to TR9 are respectively connected to the word lines WL0 to WL7. One end of the transistors TR10 to TR13 is connected to the signal lines SGDD0 to SGDD3. The other ends of the transistors TR10 to TR13 are connected to the selection gate lines SGD0 to SGD3.

According to the above structure, the column decoder module 15 can select the block BLK that performs various actions.

Specifically, during various actions, the block decoder BD corresponding to the selected block BLK applies the voltage of the "H" level to the transfer gate line TG, which corresponds to the block corresponding to the non-selected block BLK The decoder BD applies the voltage of the "L" level to the transmission gate line TG.

In this specification, the "H" level is the voltage at which the n-channel MOS transistor becomes the on state and the p-channel MOS transistor becomes the off state. The "L" level is the voltage at which the n-channel MOS transistor becomes the off state and the p-channel MOS transistor becomes the on state.

For example, when the block BLK0 is selected, the transistors TR1 to TR13 included in the column decoder RD0 are in the on state, and the transistors TR1 to TR13 included in the other column decoders RD are in the off state. In this case, the current paths between the various wirings provided in the block BLK0 and the corresponding signal lines are formed, and the current paths between the various wirings provided in the other blocks BLK and the corresponding signal lines are blocked.

As a result, the voltage applied to each signal line by the driver module 14 is applied to various wirings provided in the selected block BLK0 via the column decoder RD0. The column decoder module 15 can also operate in the same way when selecting other blocks BLK. [1-1-5] Circuit composition of sense amplifier module 16

FIG. 10 shows an example of the circuit configuration of the sense amplifier module 16 included in the semiconductor memory 1 of the first embodiment.

As shown in FIG. 10, the sense amplifier module 16 includes, for example, sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are respectively associated with the bit lines BL0 to BLm.

Each sense amplifier unit SAU includes, for example, a sense amplifier section SA and latch circuits SDL, ADL, BDL, and XDL. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, and XDL are connected in a manner that can send and receive data to and from each other.

The sense amplifier section SA determines whether the read data is "0" or "1" based on the voltage of the corresponding bit line BL during a read operation, for example. In other words, the sense amplifier section SA senses the data read to the corresponding bit line BL, and determines the data memorized by the selected memory cell.

The latch circuits SDL, ADL, BDL, and XDL respectively temporarily store read data or write data. The latch circuit XDL is connected to an input/output circuit not shown, and can be used for the input/output of data between the sense amplifier unit SAU and the input/output circuit.

The latch circuit XDL can also function as a cache memory of the semiconductor memory 1. For example, even when the latch circuits SDL, ADL, and BDL are in use, the semiconductor memory 1 can be in a ready state as long as the latch circuit XDL is idle.

FIG. 11 is a more detailed view of the sense amplifier module 16 included in the semiconductor memory of the first embodiment by extracting one of the sense amplifier units SAU among the plurality of sense amplifier units SAU included in the sense amplifier module 16 An example of the circuit configuration.

As shown in FIG. 11, the sense amplifier section SA includes, for example, transistors 50 to 60 and a capacitor 61. The latch circuit SDL includes, for example, transistors 70 and 71, and inverters 72 and 73.

For example, the transistors 50 and 52 are p-channel MOS transistors, respectively. Transistors 51, 53-56, 58-60, 70, and 71 are n-channel MOS transistors, respectively. Transistor 57 is an n-channel MOS transistor with high withstand voltage.

One end of the transistor 50 is connected to the power cord. The gate of the transistor 50 is connected to the node INV(SDL) of the latch circuit SDL. For example, a power supply voltage Vdd is applied to a power line connected to one end of the transistor 50.

One end of the transistor 51 is connected to the other end of the transistor 50. The other end of the transistor 51 is connected to the node ND1. The control signal BLX is input to the gate of the transistor 51.

One end of each of transistors 52 and 53 is connected to node ND1. The respective gates of the transistors 52 and 53 are connected to the node INV (ADL) of the latch circuit ADL.

One ends of transistors 54 and 55 are connected to the other ends of transistors 52 and 53 respectively. The other ends of the transistors 54 and 55 are connected to the node ND2. Control signals BLC1 and BLC2 are input to the gates of transistors 54 and 55, respectively.

One end of the transistor 56 is connected to the node ND2. The other end of the transistor 56 is connected to the node SRC. The gate of the transistor 56 is connected to the node INV(SDL) of the latch circuit SDL. For example, the ground voltage VSS is applied to the node SRC.

One end of the transistor 57 is connected to the node ND2. The other end of the transistor 57 is connected to the corresponding bit line BL. The control signal BLS is input to the gate of the transistor 57.

One end of the transistor 58 is connected to the node ND1. The other end of the transistor 58 is connected to the node SEN. The control signal XXL is input to the gate of the transistor 58. One end of the transistor 59 is grounded. The gate of transistor 59 is connected to node SEN.

One end of the transistor 60 is connected to the other end of the transistor 59. The other end of the transistor 60 is connected to the bus LBUS. The control signal STB is input to the gate of the transistor 60. One end of the capacitor 61 is connected to the node SEN. The clock CLK is input to the other end of the capacitor 61.

In the latch circuit SDL, one end of each of the transistors 70 and 71 is connected to the bus LBUS. The other ends of transistors 70 and 71 are connected to nodes INV and LAT, respectively. The control signals STI and STL are respectively input to the gates of the transistors 70 and 71.

The input node of the inverter 72 and the output node of the inverter 73 are respectively connected to the node LAT. The output node of the inverter 72 and the input node of the inverter 73 are respectively connected to the node INV.

The circuit configuration of the latch circuits ADL, BDL, and XDL is, for example, the same as the circuit configuration of the latch circuit SDL. For example, in the latch circuit ADL, the control signals ATI and ATL are input to the gates of the transistors 70 and 71, respectively. In each of the latch circuits BDL and XDL, control signals different from the latch circuit SDL are input to the transistors 70 and 71, respectively. In addition, the nodes INV and LAT of the latch circuits SDL, ADL, BDL, and XDL are independently set for each latch circuit.

Each of the control signals BLX, BLC1, BLC2, BLS, XXL, STB, STI, STL, ATI, and ATL described above is generated by the sequencer 13, for example. For example, the sequencer 13 can independently control the latch circuits SDL, ADL, BDL, and XDL.

The sense amplifier section SA determines that the timing of the data read to the bit line BL is based on the timing of the sequencer 13 enabling the control signal STB. In the following description, the so-called "enable the control signal STB" corresponds to the sequencer 13 temporarily changing the control signal STB from the "L" level to the "H" level. [1-1-6]About the distribution of data

FIG. 12 shows an example of the threshold distribution, readout voltage, and verification voltage of the memory cell transistor MT in the semiconductor memory 1 of the first embodiment. The vertical axis of the threshold distribution shown in FIG. 12 corresponds to the number of memory cell transistors MT, and the horizontal axis corresponds to the threshold voltage Vth of the memory cell transistor MT.

As shown in FIG. 12, in the semiconductor memory 1 of the first embodiment, for example, the threshold voltages of a plurality of memory cell transistors MT included in one cell CU can form 8 threshold distributions.

In this manual, the above 8 threshold distributions (write levels) are called "ER" level, "A" level, "B" level, and "C" level in order of threshold voltage from low to high. , "D" level, "E" level, "F" level, "G" level.

Between adjacent threshold distributions, the readout voltages used in the readout operation are respectively set. For example, the readout voltage AR is set between the largest threshold voltage in the "ER" level and the smallest threshold voltage in the "A" level.

Similarly, the read voltage BR is set between the "A" level and the "B" level. Set the read voltage CR between the "B" level and the "C" level. Set the read voltage DR between the "C" level and the "D" level. Set the read voltage ER between the "D" level and the "E" level. Set the read voltage FR between the "E" level and the "F" level. Set the read voltage GR between the "F" level and the "G" level.

For example, when the readout voltage AR is applied to the gate electrode, the memory cell transistor MT becomes the on state when the threshold voltage is distributed at the "ER" level, and becomes off when the threshold voltage is distributed above the "A" level. Open state.

Similarly, when the readout voltage BR is applied to the gate, the memory cell transistor MT becomes an on state when the threshold voltage is included below the "A" level, and when it is included above the "B" level Become a disconnected state. When other readout voltages are applied to the gate, the memory cell transistor MT also becomes an on state or an off state according to the threshold voltage.

Read the set path voltage Vread for voltages higher than the highest threshold distribution. Specifically, the read channel voltage Vread is set to a voltage higher than the maximum threshold voltage in the "G" level. When the memory cell transistor MT applies the read path voltage Vread to the gate, it becomes in an on state regardless of the data stored.

In addition, between adjacent threshold distributions, the verification voltages used in the write operation are respectively set. Specifically, corresponding to the "A" level, "B" level, "C" level, "D" level, "E" level, "F" level and "G" level, respectively Set the verification voltage AV, BV, CV, DV, EV, FV and GV.

The verification voltage AV is set between the largest threshold voltage in the "ER" level and the smallest threshold voltage in the "A" level, and near the "A" level. The verification voltage BV is set between the largest threshold voltage in the "A" level and the smallest threshold voltage in the "B" level, and near the "B" level. The other verification voltages are also set in the vicinity of the corresponding write level. That is, the verification voltages AV, BV, CV, DV, EV, FV, and GV are set to be higher than the readout voltages AR, BR, CR, DR, ER, FR, and GR, respectively.

In the writing operation, the semiconductor memory 1 completes the program of the memory cell transistor MT when it detects that the threshold voltage of the memory cell transistor MT storing a certain data exceeds the verification voltage corresponding to the data.

In the threshold distribution of the 8 types of memory cell transistors MT described above, different 3-bit data are allocated respectively. Below, an example of the distribution of data relative to the threshold distribution is listed. "ER" level: "111 (upper bit/middle bit/lower bit)" data "A" level: "110" data "B" level: "100" data "C" level: "000" data "D" level: "010" data "E" level: "011" data "F" level: "001" data "G" level: "101" data.

In the case of applying this kind of data allocation, one page of data (lower page data) composed of lower bits is determined by a read process using read voltages AR and ER. One page of data (middle page data) composed of middle bits is determined by a read process using read voltages BR, DR, and FR. One page of data (upper page data) composed of upper bits is determined by each read process using read voltages CR and GR.

That is, the lower page data, the middle page data, and the upper page data are respectively determined by the read processing using 2, 3, and 2 read voltages. The distribution of such data is called "2-3-2 code", for example. In this manual, the application of the "2-3-2 code" for the distribution of the data of the memory cell transistor MT is taken as an example for description. [1-2] Reading action of semiconductor memory 1

In the semiconductor memory 1 of the first embodiment, in the read operation, the bit line BL performing the kick operation and the bit line BL not performing the kick operation are mixed.

The so-called kick action refers to an application method of temporarily setting the driving voltage of the driver module 14 to a value higher than the target voltage value, and then reducing it to the target voltage value after a fixed time has elapsed. The kick action is performed, for example, on the signal line CG or the control signal BLC.

For example, when a kick action is performed on the signal line CG, the voltage in the distal end of the word line WL can be made to reach the target voltage value in advance. When a kick action is performed on the control signal BLC, the amount of current supplied to the bit line BL by the transistor inputting the control signal BLC to the gate increases, and the bit line BL is charged.

The case of performing a kick action on the signal line CG is synonymous with the case of performing a kick action on the word line WL. The case of performing a kick action on the control signal BLC is synonymous with the case of performing a kick action on the bit line BL.

Therefore, in this specification, the case of the kick action for the signal line CG is also referred to as the kick action for the word line WL. The sudden jump action for the control signal BLC is also called the sudden jump action for the bit line BL

In addition, in the following description, the voltage higher than the target voltage applied before the target voltage during the kick action is referred to as the kick voltage. The difference between the voltage of the kick action target and the kick voltage is called the kick amount. The memory cell transistor MT contained in the cell CU of the read target is called a selected memory cell. The word line WL connected to the selected memory cell is called the selected word line WLsel. The signal line CG connected to the selection word line WLsel is called a selection signal line CGsel.

Hereinafter, an example of the reading operation of the semiconductor memory 1 of the first embodiment will be described by taking the reading operation of the lower page data in the reading operation of the page unit as a representative.

FIG. 13 shows an example of a timing chart in the reading operation of the lower bit page data in the semiconductor memory 1 of the first embodiment.

Furthermore, in the read operation described below, it is defined as applying a voltage to the selection signal line CGsel using the driver module 14 and the column decoder module 15. The node SEN is appropriately charged during the period in which each sense voltage is applied.

The voltage of the bit line BL shown in the timing chart referred to below indicates that a voltage based on the voltage is applied to the bit line BL. The voltage applied to the gate of the transistor that clamps the voltage of the bit line BL and the voltage based on the threshold voltage of the transistor are applied to the bit line BL.

In addition, the voltage of the node INV (SDL) defined as the latch circuit SDL is set to the "L" level. That is, during the period in which the read operation is performed, the transistor 50 is in an on state, and a voltage is supplied to the transistor 51. In addition, the transistor 56 is in an off state, and blocks the current path between the nodes ND2 and SRC.

As shown in FIG. 13, at the beginning of the read operation, the respective voltages of the selection signal line CGsel, the selection word line WLsel, the control signals BLX, BLC1, BLC2, and XXL, and the bit line BL are, for example, the ground voltage Vss. The respective voltages of the node INV (ADL) and the control signal STB are, for example, the "L" level.

When the voltage of the node INV (ADL) is at the "L" level, the transistor 52 is in the on state, and the transistor 53 is in the off state. That is, the current path between the nodes ND1 and ND2 is set as a path through the transistors 52 and 54.

When the reading operation of the lower page data is started, for example, during the period from time t0 to t1, the sequencer 13 performs the operation of removing residual electrons in the channel. During the period from time t1 to t4, the sequencer 13 executes the read process using the read voltage AR. During the period from time t4 to t7, the sequencer 13 executes the read process using the read voltage ER.

Specifically, at time t0, for example, the read path voltage Vread is applied to the selection signal line CGsel. In this case, the voltage of the selected word line WLsel rises based on the voltage applied to the select signal line CGsel.

For example, the voltage in the near end of the selected word line WLsel (Figure 13, "Near (near)") rises to the read path voltage Vread in the same manner as the select signal line CGsel, and the far end of the selected word line WLsel The voltage ("Far" in FIG. 13) is delayed from the selection signal line CGsel and rises to the read path voltage Vread.

In addition, at time t0, the sequencer 13 increases the voltage of the control signal BLX from Vss to VblxL, and increases the voltage of the control signals BLC1 and BLC2 from Vss to VblcL, for example. The voltage value of VblcL is lower than VblxL, for example.

At this time, since the voltage of the node INV (ADL) is at the "L" level, the voltage clamped by the transistors 52 and 54 is applied to the bit line BL. Then, the voltage of the bit line BL rises from Vss to VblcL in the same way as the control signal BLC1, for example.

When the voltage of the selected word line WLsel rises to Vread, and the respective voltages of the control signals BLC1 and BLC2 rise from Vss to VblcL, the transistors in the NAND string NS are turned on, and the residual electrons in the channel of the NAND string NS Is removed.

Next, at time t1, the read voltage AR is applied to the selection signal line CGsel. Then, the voltage of the selected word line WLsel drops based on the voltage applied to the select signal line CGsel. Specifically, for example, the voltage at the near end of the selected word line WLsel drops to the readout voltage AR the same as the select signal line CGsel, and the voltage at the far end of the selected word line WLsel drops later than the select signal line CGsel. Until the voltage AR is read.

Furthermore, at time t1, the sequencer 13 increases the voltage of the control signal BLX, for example, from VblxL to Vblx, and sets the voltage of the node INV (ADL) to the "H" level. Then, the voltage at the node ND1 rises to the voltage clamped by the transistor 51. When the voltage of the node INV (ADL) is at the "H" level, the transistor 52 is in the off state, and the transistor 53 is in the on state. That is, the current path between the nodes ND1 and ND2 is set as a path through the transistors 53 and 55, and a voltage based on the control signal BLC2 is applied to the bit line BL, for example.

Next, at time t2, the sequencer 13 increases the voltages of the control signals BLC1 and BLC2 from VblcL to Vblc. At this time, the sequencer 13 performs a kick action on the control signal BLC1. The voltage value of Vblc is lower than Vblx, for example.

Specifically, the kick voltage Vblk is first applied to the signal line supplied with the control signal BLC1, and Vblc is applied after the kick voltage Vblk is applied for a short time. The kick voltage Vblk is a voltage higher than Vblc, and the difference between Vblk and Vblc corresponds to the kick amount Dblk.

At time t2, since the voltage of the node INV (ADL) is at the "H" level, the voltage clamped by the transistors 53 and 55 is applied to the bit line BL. Therefore, the voltage of the bit line BL, for example, corresponding to the control signal BLC2, does not apply the voltage based on the kick voltage Vblk, and rises to the voltage based on Vblc.

In addition, during the period in which the read voltage AR is applied to the selected word line WLsel, the voltage of the bit line BL changes according to the state of the selected memory cell. Specifically, the selected memory cell is turned into an on state or an off state according to its threshold voltage and read voltage.

For example, when the selected memory cell is in the on state, the voltage of the bit line BL is lower than the voltage of the bit line BL of the off cell (FIG. 13, the on cell). When the selected memory cell is in the off state, the voltage of the bit line BL maintains the voltage based on Vblc (FIG. 13, the off cell).

Secondly, at time t3, the sequencer 13 increases the voltage of the control signal XXL from Vss to Vxxl. When the voltage of the control signal XXL rises to Vxxl, the transistor 58 is turned on. Thus, the voltage of the node SEN changes according to the voltage of the bit line BL.

Moreover, the sequencer 13 reduces the voltage of the control signal XXL from Vxx1 to Vss after the voltage of the bit line BL is reflected to the node SEN. When the voltage of the control signal XXL drops to Vss, the transistor 58 is turned off, and the voltage of the node SEN is fixed.

Then, the sequencer 13 activates the control signal STB, and decides to select the data stored in the memory cell. Specifically, the sense amplifier unit SAU determines whether the threshold voltage of the corresponding selected memory cell is higher than the read voltage AR, and stores the determination result in the latch circuit BDL, for example.

Then, the sequencer 13 changes the voltage of the node INV (ADL) in the latch circuit ADL based on the data stored in the latch circuit BDL. In other words, the sequencer 13 sets the current path between the nodes ND1 and ND2 based on the read result of the read voltage AR.

For example, when the latch circuit BDL saves the data corresponding to the disconnected cell, the sequencer 13 sets the voltage of the node INV (ADL) to the "L" level. When the latch circuit BDL saves the data corresponding to the turned-on cell, the sequencer 13 sets the voltage of the node INV (ADL) to the "H" level.

That is, in the sense amplifier unit SAU corresponding to the selected memory cell maintained in the off state by the read voltage AR, the current path between the nodes ND1 and ND2 is set to the path through the transistors 52 and 54. In the sense amplifier unit SAU corresponding to the selected memory cell turned on by the read voltage AR, the current path between the nodes ND1 and ND2 is set to the path through the transistors 53 and 55.

Next, at time t4, the read voltage ER is applied to the selection signal line CGsel. At this time, the sequencer 13 performs a kick action on the selection signal line CGsel. Specifically, a kick voltage is applied to the selection signal line CGsel shortly before the read voltage ER is applied. The kick voltage for the selection signal line CGsel is equivalent to, for example, the voltage obtained by adding the kick amount Dcgk for the selection signal line CGsel to the read voltage of the object.

Then, the voltage of the selected word line WLsel rises based on the voltage applied to the select signal line CGsel. Specifically, for example, the voltage at the proximal end of the selected word line WLsel is the same as the select signal line CGsel, and reaches the read voltage ER after the kick voltage is applied. The voltage at the far end of the selected word line WLsel is affected by the RC delay of the wiring, for example, does not exceed the read voltage ER and reaches the read voltage ER.

Next, at time t5, the sequencer performs a kick action on the control signal BLC1. Specifically, the kick voltage Vblk is first applied to the signal line supplied with the control signal BLC1, and Vblc is applied after the kick voltage Vblk is applied for a short time.

At time t5, when the voltage of the node INV (ADL) is at the "L" level, the voltage clamped by the transistors 52 and 54 is applied to the bit line BL. Then, the voltage of the bit line BL corresponds to the control signal BLC1, and after a voltage based on the kick voltage Vblk is applied for a short time, it changes to a voltage based on Vblc (FIG. 13, "BLC1").

At time t5, when the voltage of the node INV (ADL) is at the "H" level, the voltage clamped by the transistors 53 and 55 is applied to the bit line BL. Then, the voltage of the bit line BL maintains the voltage based on Vblc (FIG. 13, "BLC2") corresponding to the control signal BLC2, for example.

Then, the voltage of the bit line BL changes according to the state of the selected memory cell to which the read voltage ER is applied. Since the voltage change of the bit line BL is the same as the read process of the read voltage AR explained at the time t2, the explanation is omitted.

Secondly, at time t6, the sequencer 13 increases the voltage of the control signal XXL from Vss to Vxxl. When the voltage of the control signal XXL rises to Vxxl, the transistor 58 is turned on. Thus, the voltage of the node SEN changes according to the voltage of the bit line BL.

Moreover, the sequencer 13 reduces the voltage of the control signal XXL from Vxx1 to Vss after the voltage of the bit line BL is reflected to the node SEN. When the voltage of the control signal XXL drops to Vss, the transistor 58 is turned off, and the voltage of the node SEN is fixed.

Then, the sequencer 13 activates the control signal STB, and decides to select the data stored in the memory cell. Specifically, the sense amplifier unit SAU determines whether the threshold voltage of the corresponding selected memory cell is higher than the read voltage ER.

Furthermore, the sequencer 13 determines the lower page data based on the determination result and the read result of the read voltage AR stored in the latch circuit BDL, and stores the determined lower page data in the latch circuit XDL, for example.

Next, at time t7, the sequencer 13 returns each of the selection signal line CGsel, the control signals BLX, BLC1, BLC2, and XXL to the state before the read operation, and ends the read operation of the lower page data. Moreover, the memory controller 2 outputs the lower page data to the semiconductor memory 1 when detecting that the semiconductor memory 1 finishes the reading operation of the lower page data.

As described above, the semiconductor memory 1 of the first embodiment can perform the reading operation of the lower page data. Furthermore, the semiconductor memory 1 of the first embodiment is the same as the reading operation of the lower page data in the respective read operation of the middle page data and the upper page data, and can appropriately perform a kick operation according to the read result. . [1-3] Effects of the first embodiment

According to the semiconductor memory 1 of the first embodiment described above, the read operation of the semiconductor memory 1 can be speeded up. Hereinafter, the details of the effects of the semiconductor memory 1 of the first embodiment will be described.

In a semiconductor memory in which memory cells are stacked three-dimensionally, electrical conductors (character lines WL) used as gate electrodes of memory cells and interlayer insulating films are alternately stacked to increase the number of stacked layers to achieve high capacity.

The layered word line WL is, for example, drawn out stepwise from the end of the memory cell array, and a voltage is applied through the contact point connected to the step surface portion of the step formed. However, the word line WL with this structure tends to increase the RC delay when a voltage is applied.

For example, it can be assumed that the voltage rise speed is different between the area close to the driver (the near end of the word line WL) and the area far away from the driver (the far end of the word line WL). The voltage in the far end of the word line WL Compared with the voltage in the near end of the word line WL, it reaches the target voltage with a large delay.

Therefore, in the semiconductor memory, for example, in order to assist the voltage rise in the distal end of the word line WL, a kick operation for the word line WL is performed. When the kick action for the word line WL is performed, the voltage in the far end of the word line WL reaches the target voltage earlier than when the kick action is not performed.

On the other hand, when a sudden jump operation to the word line WL is performed, overdischarge is generated in the bit line BL connected to the NAND string NS corresponding to the near end portion of the word line WL, which will result in overdischarge. In order to make the voltage of the bit line BL stable for a longer time.

As a countermeasure against the overdischarge of the bit line BL, it is considered to charge the overdischarged bit line BL by performing a kick action on the bit line BL. As a result, it is possible to assist the charging of the over-discharged bit line BL, and to stabilize the voltage of the bit line BL in a short time.

In addition, it can be assumed that the kick action for the bit line BL is in the read process for executing the kick action, and the effect of the memory cell is changed according to the on or off state when the read voltage is applied.

For example, when the threshold voltage of the memory cell to which the sense voltage is applied is greater than the sense voltage, when the sequencer 13 reflects the voltage of the bit line BL to the node SEN, the voltage of the bit line BL must be "H "The level of the voltage. In other words, when the memory cell to which the read voltage is applied becomes the off state, it is preferable that the voltage of the bit line BL is maintained in a higher state.

That is, in each read process, in the bit line BL connected to the off-state memory cell (hereinafter referred to as the off cell), the effect caused by the overdischarge of the bit line BL is greater. Will become the cause of misreading. Therefore, it is preferable to perform a kick action on the bit line BL connected to the memory cell that is clearly in the disconnected state.

On the other hand, when the threshold voltage of the memory cell to which the read voltage is applied is below the read voltage, when the voltage of the bit line BL is reflected to the node SEN, the voltage of the bit line BL must be "L" Level of voltage. In other words, when the memory cell to which the read voltage is applied becomes the ON state, it is preferable that the voltage of the bit line BL transition to a lower state.

That is, in each read process, in the bit line BL connected to the on-state memory cell (hereinafter referred to as the on cell), the influence caused by the overdischarge of the bit line BL is small. Therefore, it is preferable to omit the kick action for the bit line BL connected to the memory cell that is clearly in the on state.

In addition, in each read process, when a kick operation is performed on the bit line BL connected to the turned-on cell, the voltage of the bit line BL changes greatly. In this case, it can be assumed that the voltage of the bit line BL adjacent to the bit line BL connected to the turned-on cell is depressed by capacitive coupling. For example, when the bit line BL connected to the turned-on cell is adjacent to the bit line BL connected to the turned-off cell, the voltage of the bit line BL connected to the off cell is depressed, and it will be connected to An erroneous reading occurs in the bit line BL of the disconnected cell.

Therefore, in the semiconductor memory 1 of the first embodiment, in the read operation, the kick operation for the bit line BL, which can be determined in advance as the ON state, is omitted.

This operation can be realized, for example, by using the circuit configuration of the sense amplifier unit SAU described in FIG. 11. Specifically, the state of the memory cell transistor MT in the previous read process is stored, for example, by the node INV (ADL) of the latch circuit ADL.

For example, when the read process is performed in the order of the read voltage AR and ER, it is clear that the memory cell transistor MT that is turned on by the read voltage AR is turned on by the read voltage ER. At this time, the sequencer 13 sets the voltage of the node INV (ADL) to, for example, the "H" level.

On the other hand, it is uncertain whether the memory cell transistor MT that is turned off by the read voltage AR is turned on or off by the read voltage ER. At this time, the sequencer 13 sets the voltage of the node INV (ADL) to, for example, the "L" level.

The node INV (ADL) is, for example, connected to the gate of the p-channel MOS transistor 52 and the gate of the n-channel MOS transistor 53. The transistor 52 is included in a current path that performs a kick action, for example, and the transistor 53 is included in a current path that does not perform a kick action, for example. That is, based on the voltage of the node INV (ADL), one of the transistors 52 and 53 is in the on state, and the other is in the off state.

Thereby, the semiconductor memory 1 of the first embodiment can selectively omit the kick operation for the bit line BL that can be determined to be in the on state in advance.

As a result, the semiconductor memory 1 of the first embodiment can suppress erroneous reading caused by the kick operation performed on the bit line BL connected to the ON cell. Furthermore, in the semiconductor memory 1 of the first embodiment, by appropriately performing the kick operation for the bit line BL, the stabilization time of the bit line BL can be shortened, and therefore, the read operation can be speeded up.

Furthermore, it is considered that when the readout voltage is applied sequentially from the lower one, the number of memory cell transistors MT that are turned on from the readout voltage initially applied is less than that of the readout voltage applied later. The number of memory cell transistors MT in the on state.

In other words, it can be assumed that in the sensing process in the initially applied sensing voltage, the number of OFF cells is greater than the number of ON cells. Furthermore, it can be assumed that because the number of disconnected cells is large, the number of disconnected cells affected by the noise caused by the bit line BL connected to the turned-on cell increases. Therefore, in the semiconductor memory 1 of the first embodiment, for example, in the first read process, the kick operation is omitted for all the bit lines BL. Furthermore, in the semiconductor memory 1 of the first embodiment, in the second and subsequent read processing, the bit line BL corresponding to the memory cell transistor MT that is not clearly in the on state is, for example, The read process is the same to omit the kick action.

Thereby, the semiconductor memory 1 of the first embodiment can suppress the number of error bits, thereby improving the reliability of data.

Furthermore, it can also be assumed that, for example, in the second and subsequent read processing, when the read voltage is higher than a specific voltage, the number of turned-on cells becomes an advantage. Therefore, in the second and subsequent read processing in the read operation, the sequencer 13 can also perform the read operation on the bit line BL corresponding to the memory cell transistor MT that is not clearly turned on. The output voltage performs a sudden jump action. [1-4] Variations of the first embodiment

In the semiconductor memory 1 of the first embodiment described above, the read operation in which the read voltage is sequentially applied from the lower is exemplified, but it is not limited to this. For example, even when the read voltage is applied from the higher one in the read operation, the operation described in the first embodiment can be applied.

Hereinafter, an example of the read operation in the modified example of the first embodiment will be described.

Fig. 14 shows an example of a timing chart in the reading operation of the lower page data in the modified example of the first embodiment.

As shown in FIG. 14, in the read operation in the modified example of the first embodiment, the read operation in the first embodiment described using FIG. 13 is changed in the order of applying the read voltage.

That is, in the read operation in the modified example of the first embodiment, the read voltage ER is applied to the selection signal line CGsel at time t1. At time t4, the read voltage AR is applied to the selection signal line CGsel. When each readout voltage is applied to the selection signal line CGsel, the voltage at the near end of the selected word line WLsel ("Near" in FIG. 14) drops the same as the selection signal line CGsel, and the word line WLsel is selected The voltage in the far end (Figure 14, "Far (far)") decreases with a delay in comparison with the selection signal line CGsel.

Furthermore, in the read operation in the modified example of the first embodiment, in the first kick operation, the kick operation for all the bit lines BL is performed.

Specifically, at time t1, the sequencer 13 sets the voltage of the node INV(ADL) to the "L" level. When the voltage of the node INV (ADL) is at the "L" level, the transistor 52 is in the on state, and the transistor 53 is in the off state. That is, the current path between the nodes ND1 and ND2 is set as a path through the transistors 52 and 54, and a voltage based on the control signal BLC1 is applied to the bit line BL, for example.

Therefore, at time t2, a voltage corresponding to the control signal BLC1 for performing the kick action is applied to the bit line BL. That is, at time t2, the voltage of the bit line BL changes to a voltage based on Vblc after applying a voltage based on the kick voltage Vblk for a short time in response to, for example, the control signal BLC1.

Since the other operations of the read operation in the modified example of the first embodiment are the same as the read operation in the first embodiment, the description is omitted. Furthermore, as a modification of the first embodiment, the reading operation of the lower page data is exemplified, but the same operation can be performed for the respective reading operations of the middle page data and the upper page data.

As described above, in the read operation in the modified example of the first embodiment, the kick operation is performed on the bit line BL that can be determined in advance to be in the off state.

For example, when the read process is performed in the order of the read voltage ER and AR, it is clear that the memory cell transistor MT that is turned off by the read voltage ER is turned off by the read voltage AR. At this time, the sequencer 13 sets the voltage of the node INV (ADL) to, for example, the "L" level.

On the other hand, it is uncertain whether the memory cell transistor MT that is turned on by the read voltage ER is turned on or off by the read voltage AR. At this time, the sequencer 13 sets the voltage of the node INV (ADL) to, for example, the "H" level.

Also, in the read operation in the modified example of the first embodiment, as in the first embodiment, it can be set whether or not to perform a kick operation on the bit line BL based on the voltage of the node INV (ADL).

Thereby, in the read operation in the modified example of the first embodiment, the kick operation can be selectively performed on the bit line BL that can be determined in advance to be in the off state.

As a result, in the read operation in the modified example of the first embodiment, it is possible to suppress erroneous reading caused by not performing a kick operation on the bit line BL connected to the disconnected cell. Furthermore, in the read operation in the modified example of the first embodiment, by appropriately performing the kick operation for the bit line BL, the stabilization time of the bit line BL is shortened, and the read operation can be speeded up.

Furthermore, it is considered that when the readout voltage is applied sequentially from the higher one, the number of memory cell transistors MT that are turned on from the first applied readout voltage is greater than that of the readout voltage applied later. The number of memory cell transistors MT in the on state.

In other words, it can be assumed that in the sensing process in the initially applied sensing voltage, the number of ON cells is greater than the number of OFF cells. Furthermore, it can be assumed that since the number of ON cells is larger, the number of OFF cells affected by the noise caused by the bit line BL connected to the ON cells is reduced.

Therefore, in the read operation in the modified example of the first embodiment, for example, the first kick operation is performed on all the bit lines BL. In the read operation in the modified example of the first embodiment, in the second and subsequent read processing, for the bit line BL corresponding to the memory cell transistor MT that is not clearly in the off state, For example, the kick action is executed in the same way as the first reading action.

Thereby, in the read operation in the modification of the first embodiment, the number of error bits can be suppressed, and the reliability of the data can be improved.

Furthermore, it can be assumed that, for example, in the second and subsequent read processing, when the read voltage is lower than a certain voltage, the number of disconnected cells becomes an advantage. Therefore, in the second and subsequent read processing during the read operation, the sequencer 13 can also perform the read operation on the bit line BL corresponding to the memory cell transistor MT that is not clearly in the off state according to the applied read The output voltage skips the sudden jump action. [2] The second embodiment

The semiconductor memory 1 of the second embodiment uses a sense amplifier module 16 different from that of the first embodiment, and performs the same read operation as that of the first embodiment. Hereinafter, regarding the semiconductor memory 1 of the second embodiment, differences from the first embodiment will be described. [2-1] Circuit composition of the sense amplifier module 16

FIG. 15 is a circuit configuration of the sense amplifier module 16 included in the semiconductor memory of the second embodiment by extracting one of the sense amplifier units SAU among the plurality of sense amplifier units SAU included in the sense amplifier module 16 An example.

As shown in FIG. 15, the sense amplifier section SA in the second embodiment has transistors 51 to 55 and 58 that are omitted and transistor 80 is added to the sense amplifier section SA explained using FIG. 11 in the first embodiment. The composition of ~ 84.

For example, the transistors 80-82 and 84 are n-channel MOS transistors, respectively. Transistor 83 is a p-channel MOS transistor.

One end of the transistor 80 is connected to the other end of the transistor 50. The other end of the transistor 80 is connected to the node ND2. The control signal BLX1 is input to the gate of the transistor 80.

The transistor 81 is connected between one end of the transistor 57 and the node ND2. Specifically, one end of the transistor 81 is connected to the node ND2, and the other end of the transistor 81 is connected to one end of the transistor 57. The control signal BLC1 is input to the gate of the transistor 81.

One end of the transistor 82 is connected to the node ND2. The other end of the transistor 82 is connected to the node SEN. The control signal BLC2 is input to the gate of the transistor 82.

One end of the transistor 83 is connected to the power cord. The gate of the transistor 83 is connected to the bus LBUS. For example, a power supply voltage Vdd is applied to a power line connected to one end of the transistor 83.

One end of the transistor 84 is connected to the other end of the transistor 83. The other end of the transistor 84 is connected to the node SEN. The control signal BLX2 is input to the gate of the transistor 84.

The other structure of the semiconductor memory 1 of the second embodiment is, for example, the same as the semiconductor memory 1 of the first embodiment, so the description will be omitted. [2-2] Reading action of semiconductor memory 1

FIG. 16 shows an example of a timing chart in the reading operation of the lower bit page data in the semiconductor memory 1 of the second embodiment. In addition, it is defined that in the read operation in the second embodiment, the transistor 50 is in the ON state as in the first embodiment, and a voltage is supplied to the transistor 80.

As shown in FIG. 16, at the beginning of the read operation, the respective voltages of the selection signal line CGsel, the selection word line WLsel, the control signals BLX1, BLX2, BLC1 and BLC2, and the bit line BL are, for example, the ground voltage Vss. The voltage of the control signal STB is, for example, the "L" level.

When starting the reading operation of the lower page data, for example, during the period from time t0 to t1, the sequencer 13 executes the operation of removing residual electrons in the channel in the same way as in the first embodiment. During the period from time t1 to time t5, the sequencer 13 executes the read process using the read voltage AR. During the period from time t5 to t9, the sequencer 13 executes the read process using the read voltage ER.

Specifically, at time t0, for example, the read path voltage Vread is applied to the selection signal line CGsel. Then, the voltage of the selected word line WLsel rises based on the voltage applied to the select signal line CGsel.

In addition, at time t0, the sequencer 13 increases the voltage of the control signals BLX1, BLC1, and BLC2 from Vss to VblcL, and increases the voltage of the control signal BLX2 from Vss to VblxL, for example.

At this time, for example, a voltage clamped by the transistors 80 and 81 is applied to the bit line BL. Then, the voltage of the bit line BL rises from Vss to a voltage based on VblcL, for example, corresponding to the control signal BLC1.

Next, at time t1, the read voltage AR is applied to the selection signal line CGsel. Then, the voltage of the selected word line WLsel drops based on the voltage applied to the select signal line CGsel.

In addition, at time t1, the sequencer 13 sets the voltage of the bus LBUS to the "H" level, so that the voltage of the control signal BLX1 rises, for example, from VblcL to Vblc, and the voltage of the control signal BLX2 rises, for example, from VblxL to Vblx.

When the voltage of the bus LBUS is set to the "H" level, the transistor 83 is turned off, and the voltage supply to the transistor 84 is interrupted. In addition, the voltage at the node ND2 rises to the voltage clamped by the transistor 80.

Next, at time t2, the sequencer 13 performs a kick action on each of the control signals BLC1 and BLC2, for example. Specifically, the sequencer 13 increases the voltage of the control signal BLC1 to the kick voltage VblkH, and increases the voltage of the control signal BLC2 to the kick voltage Vblk. The kick voltage VblkH is higher than Vblk.

During the period when the kick action is performed on each of the control signals BLC1 and BLC2, the bit line BL is applied with a voltage passing through the path of the transistors 50, 80, and 81. Then, a voltage based on Vblc is applied to the bit line BL for a short time corresponding to the control signal BLX1, for example.

Furthermore, after the sequencer 13 performs a kick action on each of the control signals BLC1 and BLC2, the voltage of the control signal BLC1 drops to Vblc, and the voltage of the control signal BLC2 drops to Vss. When the voltage of the control signal BLC2 becomes Vss, the transistor 82 is turned off.

Next, at time t3, the sequencer 13 increases the voltage of the control signal BLX1 from Vblc to Vblx, and decreases the voltage of the control signal BLX2 from Vblx to Vss, for example. When the voltage of the control signal BLC2 becomes Vss, the transistor 84 is turned off.

At this time, a voltage passing through the path of transistors 50, 80, and 81 is applied to the bit line BL. Then, a voltage based on Vblc is applied to the bit line BL in response to, for example, the control signal BLC1.

Also, during the period in which the read voltage AR is applied to the selected word line WLsel, the voltage of the bit line BL changes according to the state of the selected memory cell as in the first embodiment.

Next, at time t4, the sequencer 13 increases the voltage of the control signal BLC2 to, for example, Vxx1. When the voltage of the control signal BLC2 rises to Vxxl, the transistor 82 is turned on. Thus, the voltage of the node SEN changes according to the voltage of the bit line BL.

Moreover, the sequencer 13 reduces the voltage of the control signal BLC2 to Vss after the voltage of the bit line BL is reflected to the node SEN. When the voltage of the control signal XXL drops to Vss, the transistor 82 is turned off, and the voltage of the node SEN is fixed.

Then, the sequencer 13 activates the control signal STB, and decides to select the data stored in the memory cell. Specifically, the sense amplifier unit SAU determines whether the threshold voltage of the corresponding selected memory cell is higher than the read voltage AR, and stores the determination result in, for example, the latch circuit ADL.

Next, at time t5, the read voltage ER is applied to the selection signal line CGsel. At this time, the sequencer 13 performs a kick operation on the selection signal line CGsel, as in the first embodiment. Then, the voltage of the selected word line WLsel is based on the increase of the voltage applied to the select signal line CGsel, as in the first embodiment.

Furthermore, at time t5, the sequencer 13 reduces the voltage of the control signal BLX1 from Vblx to Vblc, raises the voltage of the control signal BLX2 from Vss to Vblx, and raises the voltage of the control signal BLC2 from Vss to Vblc. When the voltage of the control signal BLX2 becomes Vblx, the transistor 84 becomes an ON state, and when the voltage of the control signal BLC2 becomes Vblc, the transistor 82 becomes an ON state.

Furthermore, at time t5, the sequencer 13 controls the voltage of the bus LBUS based on the data stored in the latch circuit ADL. For example, when the latch circuit ADL saves the data corresponding to the disconnected unit, the sequencer 13 sets the voltage of the bus LBUS to the "L" level. When the latch circuit ADL saves the data corresponding to the turned-on unit, the sequencer 13 sets the voltage of the bus LBUS to the "H" level.

Then, the sense amplifier unit SAU corresponding to the selected memory cell maintained in the off state by the read voltage AR applies the voltage of the path through the transistors 50, 80 and 81 and the voltage through the transistors 83, 83 to the corresponding bit line BL. The voltages of the paths 84, 82, and 81.

The sense amplifier unit SAU corresponding to the selected memory cell that is turned on by the read voltage AR applies the voltage through the path of the transistors 50, 80, and 81. In this way, in the read operation in the second embodiment, based on the previous read result, the number of paths for applying voltage to the bit line BL changes.

Next, at time t6, the sequencer, for example, performs a kick action on each of the control signals BLC1 and BLC2. Specifically, the sequencer 13 increases the voltage of the control signal BLC1 to the kick voltage VblkH, and increases the voltage of the control signal BLC2 to the kick voltage Vblk, as at the time t2.

At time t6, when the voltage of the bus LBUS is at the "H" level, the voltage of the path through the transistors 50, 80, and 81 is applied to the bit line BL. Then, a voltage based on Vblc is applied to the bit line BL in response to, for example, the control signal BLX1 ("BLC1" in FIG. 16).

At time t6, when the voltage of the bus LBUS is at the "L" level, apply the voltage of the path through the transistors 50, 80, and 81 and the voltage through the path of the transistors 83, 84, 82, and 81 to the bit line BL. The voltage of the path. Then, a voltage based on the kick voltage Vblk is applied to the bit line BL for a short time in response to, for example, the control signal BLC2 ("BLC2" in FIG. 16).

Next, at time t7, the sequencer 13 increases the voltage of the control signal BLX1 from Vblc to Vblx, and decreases the voltage of the control signal BLX2 from Vblx to Vss, for example. When the voltage of the control signal BLC2 becomes Vss, the transistor 84 is turned off.

At this time, a voltage passing through the path of the transistors 50, 80, and 81 is applied to the bit line BL. Then, a voltage based on Vblc is applied to the bit line BL in response to, for example, the control signal BLC1.

Also, during the period in which the read voltage ER is applied to the selected word line WLsel, the voltage of the bit line BL changes according to the state of the selected memory cell as in the first embodiment.

Next, at time t8, the sequencer 13 increases the voltage of the control signal BLC2, for example, from Vss to Vxx1. When the voltage of the control signal BLC2 rises to Vxx1, the transistor 82 is turned on. Therefore, the voltage of the node SEN changes according to the voltage of the bit line BL, that is, the state of the selected memory cell.

Furthermore, after the voltage of the bit line BL is reflected to the node SEN, the sequencer 13 reduces the voltage of the control signal BLC2, for example, from Vxx1 to Vss. When the voltage of the control signal BLC2 drops to Vss, the transistor 82 is turned off, and the voltage of the node SEN is fixed.

Then, the sequencer 13 activates the control signal STB, and decides to select the data stored in the memory cell. Specifically, the sense amplifier unit SAU determines whether the threshold voltage of the corresponding selected memory cell is higher than the read voltage ER.

Then, the sequencer 13 determines the lower page data based on the determination result and the read result of the read voltage AR stored in the latch circuit ADL, so that the determined lower page data is stored in the latch circuit XDL, for example.

Next, at time t9, the sequencer 13 returns the selection signal line CGsel and the control signals BLX1, BLX2, BLC1, and BLC2 to the state before the read operation, and ends the read operation of the lower page data. Moreover, the memory controller 2 outputs the lower page data to the semiconductor memory 1 when detecting that the semiconductor memory 1 has finished the reading operation of the lower page data.

As described above, the semiconductor memory 1 of the second embodiment can perform the reading operation of the lower page data. Furthermore, the semiconductor memory 1 of the second embodiment is the same as the reading operation of the lower page data in the respective read operation of the middle page data and the upper page data, and can appropriately perform a kick operation according to the read result. . [2-3] Effects of the second embodiment

In the semiconductor memory 1 of the second embodiment, in the read operation, as in the first embodiment, the kick operation for the bit line BL that can be determined in advance to be in the on state can be omitted. As a result, the semiconductor memory 1 of the second embodiment can obtain the same effects as those of the first embodiment.

In addition, in the semiconductor memory 1 of the second embodiment, the functions of the two transistors 54 and 58 in the first embodiment are realized by one transistor 82.

As a result, in the semiconductor memory 1 of the second embodiment, the number of elements of the sense amplifier unit SAU can be made smaller than that of the first embodiment. Therefore, the semiconductor memory 1 of the second embodiment can reduce the circuit area of the sense amplifier unit SAU as compared with the first embodiment, thereby reducing the chip area of the semiconductor memory 1.

In addition, in the semiconductor memory 1 of the second embodiment, as in the first embodiment, the kick operation in the initial read process is omitted for all bit lines BL. Thereby, the semiconductor memory 1 of the second embodiment can suppress the number of error bits as in the first embodiment, and can improve the reliability of data.

Also, in the semiconductor memory 1 of the second embodiment, the sequencer 13 may be the same as that of the first embodiment, and it is also possible to compare the memory cells that are not clearly in the ON state in the second and subsequent read processing. The bit line BL corresponding to the transistor MT performs a kick action according to the applied readout voltage. [2-4] Variations of the second embodiment

In the semiconductor memory 1 of the second embodiment described above, the read operation in which the read voltage is sequentially applied from the lower one is exemplified, but it is not limited to this. For example, as in the modification of the first embodiment, even when the read voltage is applied from the higher one in the read operation, the operation described in the second embodiment can be applied.

Hereinafter, an example of the read operation in the modified example of the second embodiment will be described.

Fig. 17 shows an example of a timing chart in the reading operation of the lower page data in the modification of the second embodiment.

As shown in FIG. 17, in the read operation in the modified example of the first embodiment, the order in which the read voltage is applied is changed to the read operation in the first embodiment described using FIG. 16.

That is, in the read operation in the modified example of the second embodiment, the read voltage ER is applied to the selection signal line CGsel at time t1. At time t5, the read voltage AR is applied to the selection signal line CGsel. Then, as in the modified example of the first embodiment, the voltage of the selected word line WLsel drops based on the voltage of the select signal line CGsel.

Also, in the read operation in the modified example of the second embodiment, as in the modified example of the first embodiment, in the first kick operation, a kick operation for all bit lines BL is performed.

Specifically, at time t1, the sequencer 13 sets the voltage of the bus LBUS to the "L" level. When the voltage of the bus LBUS is at the "L" level, the transistor 83 is turned on. That is, the voltages of the paths passing through the transistors 50, 80, and 81 and the voltages of the paths passing through the transistors 83, 84, 82, and 81 are applied to the bit line BL. Therefore, at time t2, a voltage based on the kick voltage Vblk is applied to the bit line BL, for example, corresponding to the control signal BLC2.

The other operations of the read operation in the modified example of the second embodiment are the same as the read operation in the second embodiment, so the description will be omitted. Furthermore, as a modification of the second embodiment, the reading operation of the lower page data is exemplified, but the same operation can be performed for the respective reading operation of the middle page data and the upper page data.

According to the semiconductor memory 1 in the modified example of the second embodiment described above, in the read operation, the same as the modified example of the first embodiment, the bit line BL that can be determined to be in the off state can be detected in advance. Perform a sudden jump. As a result, the read operation in the modified example of the second embodiment can obtain the same effect as the modified example of the first embodiment.

In addition, the read operation in the modified example of the second embodiment is the same as the modified example of the first embodiment, and the kick operation in the initial read process is performed on all bit lines BL. Thereby, the read operation in the modified example of the second embodiment can suppress the number of error bits in the same way as the modified example of the first embodiment, and the reliability of the data can be improved.

In addition, in the read operation in the modified example of the second embodiment, similar to the modified example of the first embodiment, it is also possible to check whether it is in the off state during the second and subsequent read processing. The bit line BL corresponding to the memory cell transistor MT omits the kick action according to the applied readout voltage. [3] The third embodiment

The semiconductor memory 1 of the third embodiment has a circuit configuration of the sense amplifier module 16 different from that of the first and second embodiments. In the semiconductor memory 1 of the third embodiment, in the read operation, it is set whether or not to perform a kick operation for each read voltage. Hereinafter, regarding the semiconductor memory 1 of the third embodiment, differences from the first and second embodiments will be described. [3-1] Circuit composition of the sense amplifier module 16

FIG. 18 is a circuit configuration of the sense amplifier module 16 included in the semiconductor memory of the third embodiment by extracting one of the sense amplifier units SAU among the plurality of sense amplifier units SAU included in the sense amplifier module 16 An example.

As shown in FIG. 18, the sense amplifier section SA in the third embodiment has the sense amplifier section SA explained using FIG. 11 in the first embodiment. Transistors 51 to 55 and 58 are omitted and transistor 90 is added. The composition of ~93.

Each of the transistors 90 to 93 is, for example, an n-channel MOS transistor.

One end of the transistor 90 is connected to the other end of the transistor 50. The other end of the transistor 90 is connected to the node ND2. The control signal BLX is input to the gate of the transistor 90.

Transistor 91 is connected between one end of transistor 57 and node ND2. Specifically, one end of the transistor 91 is connected to the node ND2, and the other end of the transistor 91 is connected to one end of the transistor 57. The control signal BLC is input to the gate of the transistor 91.

One end of the transistor 92 is connected to the other end of the transistor 50. The other end of the transistor 92 is connected to the node SEN. The control signal HLL is input to the gate of the transistor 92.

One end of the transistor 93 is connected to the node SEN. The other end of the transistor 93 is connected to the node ND2. The control signal XXL is input to the gate of the transistor 93.

The other configuration of the semiconductor memory 1 of the third embodiment is, for example, the same as the semiconductor memory 1 of the first embodiment, and therefore description thereof will be omitted. [3-2] Reading action of semiconductor memory 1

(Reading operation in the comparative example of the third embodiment)

Before describing the read operation of the semiconductor memory 1 of the third embodiment, the read operation in the comparative example of the third embodiment will be described. In the read operation in the comparative example of the third embodiment, in the read process corresponding to all the read voltages, a kick operation with respect to the control signal BLC is performed.

FIG. 19 shows an example of a timing chart in the reading operation of bit page data in the comparative example of the third embodiment. In addition, it is defined that in the read operation in the comparative example of the third embodiment, the transistor 50 is in the ON state as in the first embodiment, and voltage is supplied to the transistors 90 and 92.

In addition, in the comparative example of the third embodiment, the transistor 92 uses the sequencer 13 to appropriately control the control signal HLL to appropriately charge the node SEN. As in the first embodiment, the voltages of the selected word line WLsel and the bit line BL vary according to the voltages of the select signal line CGsel and the control signal BLC, respectively.

As shown in FIG. 19, at the beginning of the read operation, the respective voltages of the selection signal line CGsel, the selection word line WLsel, and the control signals BLX, BLC, and XXL are, for example, the ground voltage Vss. The voltage of the control signal STB is, for example, the "L" level.

When starting the reading operation of the middle page data, for example, during the period from time t0 to t1, the sequencer 13 executes the operation of removing residual electrons in the channel in the same manner as in the first embodiment. During the period from time t1 to t4, the sequencer 13 executes the read process using the read voltage BR. During the period from time t4 to t7, the sequencer 13 executes the read process using the read voltage DR. During the period from time t7 to t10, the sequencer 13 executes the read process using the read voltage FR.

Specifically, at time t0, for example, the read path voltage Vread is applied to the selection signal line CGsel. Then, the voltage of the selected word line WLsel rises based on the voltage applied to the select signal line CGsel.

In addition, at time t0, the sequencer 13 increases the voltage of the control signal BLX from Vss to VblxL, and increases the voltage of the control signal BLC from Vss to VblcL, for example. At this time, for example, a voltage clamped by transistors 90 and 91 is applied to bit line BL.

Next, at time t1, the read voltage BR is applied to the selection signal line CGsel. Then, the voltage of the selected word line WLsel drops based on the voltage applied to the select signal line CGsel. Furthermore, at time t1, the sequencer 13 increases the voltage of the control signal BLX, for example, from VblxL to Vblc.

Next, at time t2, the sequencer 13 performs a kick action on the control signal BLC. Specifically, the kick voltage Vblk is first applied to the signal line supplied with the control signal BLC, and then Vblc is applied after the kick voltage Vblk is applied for a short time.

Also, during the period in which the read voltage BR is applied to the selected word line WLsel, the voltage of the bit line BL changes according to the state of the selected memory cell as in the first embodiment.

Secondly, at time t3, the sequencer 13 increases the voltage of the control signal XXL from Vss to Vxxl. When the voltage of the control signal XXL rises to Vxxl, the transistor 93 is turned on. Therefore, the voltage of the node SEN changes according to the voltage of the bit line BL, that is, the state of the selected memory cell.

Moreover, the sequencer 13 reduces the voltage of the control signal XXL from Vxx1 to Vss after the voltage of the bit line BL is reflected to the node SEN. When the voltage of the control signal XXL drops to Vss, the transistor 93 is turned off, and the voltage of the node SEN is fixed.

Then, the sequencer 13 activates the control signal STB, and decides to select the data stored in the memory cell. Specifically, the sense amplifier unit SAU determines whether the threshold voltage of the corresponding selected memory cell is higher than the read voltage BR, and stores the determination result in, for example, the latch circuit ADL.

Next, at time t4, the read voltage DR is applied to the selection signal line CGsel. At this time, the sequencer 13 performs a kick operation on the selection signal line CGsel, as in the first embodiment. Then, the voltage of the selected word line WLsel is based on the increase of the voltage applied to the select signal line CGsel, as in the first embodiment.

Next, at time t5, the sequencer 13 performs a kick action on the control signal BLC. Since the operation of the semiconductor memory 1 at time t5 is the same as the operation at time t2, the description is omitted. During the period when the read voltage DR is applied to the selected word line WLsel, the voltage of the bit line BL changes according to the state of the selected memory cell.

Next, at time t6, the sequencer 13 controls the control signal XXL in the same way as at time t3, so that the voltage of the bit line BL is reflected to the voltage of the node SEN. Then, the sequencer 13 activates the control signal STB to determine the data stored in the selected memory cell.

Specifically, the sense amplifier unit SAU determines whether the threshold voltage of the corresponding selected memory cell is higher than the read voltage ER. Then, the sequencer 13 performs an operation based on the determination result and the determination result in the read voltage BR stored in the latch circuit ADL, and the operation result is stored in the latch circuit BDL, for example.

Next, at time t7, the read voltage FR is applied to the selection signal line CGsel. At this time, the sequencer 13 performs a kick operation on the selection signal line CGsel, as in the first embodiment. Then, the voltage of the selected word line WLsel is based on the increase of the voltage applied to the select signal line CGsel, as in the first embodiment.

Next, at time t8, the sequencer 13 performs a kick action on the control signal BLC. Since the operation of the semiconductor memory 1 at time t8 is the same as the operation at time t2, the description is omitted. During the period when the read voltage FR is applied to the selected word line WLsel, the voltage of the bit line BL changes according to the state of the selected memory cell.

Next, at time t9, the sequencer 13 controls the control signal XXL in the same way as at time t3, so that the voltage of the bit line BL is reflected to the voltage of the node SEN. Then, the sequencer 13 activates the control signal STB to determine the data stored in the selected memory cell.

Specifically, the sense amplifier unit SAU determines whether the threshold voltage of the corresponding selected memory cell is higher than the read voltage FR. Furthermore, the sequencer 13 determines the middle page data based on the determination result and the determination result in the read voltages BR and DR stored in the latch circuit BDL, so that the determined middle page data is stored in the latch circuit XDL, for example. in.

Next, at time t10, the sequencer 13 returns the selection signal line CGsel, the control signals BLX, BLC, and XXL to the state before the read operation, respectively, and ends the read operation of the middle page data. Moreover, the memory controller 2 outputs the lower page data to the semiconductor memory 1 when detecting that the semiconductor memory 1 finishes the reading operation of the middle page data.

(Reading operation in the third embodiment)

In contrast to the read operation in the comparative example of the third embodiment described above, in the read operation in the third embodiment, it is set whether to perform a kick operation for the control signal BLC for each read voltage.

FIG. 20 shows an example of the conditions of the kick operation in the read operation of the semiconductor memory of the third embodiment.

As shown in FIG. 20, the sequencer 13 omits the kick operation for the control signal BLC in each of the read processing corresponding to the read voltages AR, BR, and CR, for example. In addition, the sequencer 13 performs a kick operation with respect to the control signal BLC in each of the read processing corresponding to the read voltages DR, ER, FR, and GR, for example.

In other words, in the semiconductor memory 1 of the third embodiment, for example, it is classified into a group with lower read voltage (for example, read voltage AR, BR, and CR) and a group with higher read voltage (for example, read voltage DR, ER, FR and GR) 2 groups. Moreover, the sequencer 13 omits the kick action for the control signal BLC in the group with a lower sense voltage, and executes it in the group with a higher sense voltage.

Furthermore, the setting of whether to perform the kick action for the control signal BLC in the read operation is not limited to the group classification described above, and can be changed to arbitrary settings.

FIG. 21 shows an example of a timing chart in the read operation of bit page data in the semiconductor memory 1 of the third embodiment.

As shown in FIG. 21, in the read operation in the third embodiment, compared to the read operation in the comparative example of the third embodiment described using FIG. 19, the kick operation corresponding to the read voltage BR is changed Omitted.

Specifically, at time t2, the sequencer 13 causes the voltage of the control signal BLC not to rise to the kick voltage Vblk but to Vblc. Therefore, at time t2, a voltage based on Vblc is applied to the bit line BL in response to, for example, the control signal BLC. Since the other operations of the reading operation in the third embodiment are the same as the reading operation in the comparative example of the third embodiment, the description is omitted.

In this way, the semiconductor memory 1 of the third embodiment can perform the read operation of the middle page data. Furthermore, in the semiconductor memory 1 of the third embodiment, the respective read operations of the lower page data and the upper page data are the same as the read operation of the middle page data, and can be appropriately executed for each read voltage Sudden action. [3-3] Effects of the third embodiment

For example, it is considered that the number of memory cell transistors MT that are turned on by a lower reading voltage is less than the number of memory cell transistors MT that are turned on by a higher reading voltage.

In other words, it is considered that the number of memory cell transistors MT that are turned off by a lower reading voltage is more than the number of memory cell transistors MT that are turned off by a higher reading voltage.

In this way, in the read operation, which one of the number of ON cells and the number of OFF cells is superior can be estimated by the value of the read voltage. That is, based on the relationship between the number of ON cells and the number of OFF cells, the number of OFF cells affected by the noise caused by the bit line BL connected to the ON cells can be assumed.

Therefore, in the semiconductor memory 1 of the third embodiment, it is set whether to perform a kick operation for the bit line BL for each read voltage. Specifically, the sequencer 13 omits the kick action in the group with lower read voltage (for example, read voltage AR, BR, and CR), and in the group with higher read voltage (for example, read voltage DR, ER). , FR and GR).

That is, the sequencer 13 omits the kick action in the read process of the group in which it is estimated that the number of disconnected cells is the advantage and the number of memory cells that can be misread by the kick action is larger. On the other hand, the sequencer 13 performs a kick action in the read process of a group in which it is estimated that the number of turn-on cells is superior and the number of memory cells that can be misread by the kick action is small.

In this way, the semiconductor memory 1 of the third embodiment can perform appropriate read processing in each of the group with a higher read voltage and the group with a lower read voltage. As a result, the semiconductor memory 1 of the third embodiment can suppress the number of error bits in the same manner as in the first embodiment, and can improve the reliability of data. [3-4] Variations of the third embodiment

In the semiconductor memory 1 of the third embodiment described above, the read operation in which the read voltage is sequentially applied from the lower one is exemplified, but it is not limited to this. For example, as in the modification of the first embodiment, even when the read voltage is applied from the higher one during the read operation, the operation described in the third embodiment can be applied.

Hereinafter, an example of the read operation in the modified example of the third embodiment will be described.

Fig. 22 shows an example of a timing chart in the readout operation of bit page data in the modified example of the third embodiment.

As shown in FIG. 22, in the read operation in the modified example of the third embodiment, the order in which the read voltage is applied is changed from the read operation in the third embodiment described using FIG. 21.

That is, in the read operation in the modified example of the third embodiment, the read voltage FR is applied to the selection signal line CGsel at time t1. At time t4, the read voltage DR is applied to the selection signal line CGsel. At time t7, the read voltage BR is applied to the selection signal line CGsel. Then, similarly to the modification of the first embodiment, the voltage of the selected word line WLsel drops based on the voltage of the select signal line CGsel.

In addition, in the modified example of the third embodiment, the sequencer 13 executes the read operation based on the setting of the kick operation for the control signal BLC shown in FIG. 20 in the same way as the read operation in the third embodiment.

Specifically, for example, in the read operation of the middle page, the sequencer 13 executes the kick operation in each read process using the read voltages FR and DR, and performs one of the read processes in the read process using the read voltage BR The kick action is omitted.

The other operations of the read operation in the modified example of the third embodiment are the same as the read operation in the third embodiment, so the description will be omitted. Furthermore, as a modification of the third embodiment, the reading operation of the middle page data is exemplified, but the same operation can be performed for the respective reading operations of the lower page data and the upper page data.

As described above, in the read operation in the modified example of the third embodiment, similarly to the third embodiment, in each of the group with a higher read voltage and the group with a lower read voltage, an appropriate operation can be performed. The read processing. As a result, in the read operation in the modified example of the third embodiment, the same effect as the third embodiment can be obtained. [4] Fourth Embodiment

The semiconductor memory 1 of the fourth embodiment has the same configuration as that of the third embodiment. Furthermore, in the semiconductor memory 1 of the fourth embodiment, in the read operation, the kick amount is changed for each read voltage. Hereinafter, regarding the semiconductor memory 1 of the fourth embodiment, differences from the first to third embodiments will be described. [4-1] Reading action of semiconductor memory 1

FIG. 23 shows an example of the conditions of the kick operation in the read operation of the semiconductor memory of the fourth embodiment.

As shown in FIG. 23, the sequencer 13 omits the kick operation for the control signal BLC in each of the read processing corresponding to the read voltages AR, BR, and CR in the same manner as in the third embodiment. In each of the read processing corresponding to the read voltages DR, ER, FR, and GR, a kick operation with respect to the control signal BLC is performed.

In addition, in the fourth embodiment, the sequencer 13 applies a small amount of kick in response to the control signal BLC, for example, corresponding to each of the read voltages DR and ER, and the read voltages FR and GR Each of them corresponds to a larger jump amount of the application.

Furthermore, whether to perform the setting of the kick action for the control signal BLC and the setting of the kick amount in the read operation can be changed to arbitrary settings. The setting of the kick amount is not limited to two types of "large" or "small", and more than three settings can also be used.

FIG. 24 shows an example of a timing chart in the readout operation of bit page data in the semiconductor memory 1 of the fourth embodiment.

As shown in FIG. 24, in the reading operation in the fourth embodiment, the reading operation of the reading voltage FR at time t2 is the same as the reading operation in the third embodiment described using FIG. 21. The sudden jump action of the out processing is omitted.

Moreover, in the read operation in the fourth embodiment, compared to the read operation in the third embodiment, there is a jump between the read process using the read voltage DR and the read process using the read voltage FR. The voltage is different.

Specifically, at time t5, the sequencer 13 performs a kick operation corresponding to the read voltage DR. At this time, the kick voltage Vblk1 is first applied to the signal line supplying the control signal BLC, and then Vblc is applied after the kick voltage Vblk1 is applied for a short time. The kick voltage Vblk1 is a voltage higher than Vblc, and the difference between Vblk1 and Vblc corresponds to the kick amount Dblk1.

At time t8, the sequencer 13 performs a kick action corresponding to the read voltage FR. At this time, the kick voltage Vblk2 is first applied to the signal line supplying the control signal BLC, and then Vblc is applied after the kick voltage Vblk2 is applied for a short time. The kick voltage Vblk2 is a voltage higher than Vblk1, and the difference between Vblk2 and Vblc corresponds to the kick amount Dblk2.

In this way, in the fourth embodiment, the kick amount Dblk2 of the kick voltage Vblk2 is set to be larger than the kick amount Dblk1 of the kick voltage Vblk1. Therefore, the voltage applied to the bit line BL by the kick action at time t8 is higher than the voltage applied to the bit line BL by the kick action at time t5. The other operations of the reading operation in the fourth embodiment are the same as the reading operation in the third embodiment, so the description is omitted.

As described above, the semiconductor memory 1 of the fourth embodiment can perform the read operation of the middle page data. Furthermore, in the semiconductor memory 1 of the fourth embodiment, the respective read operation of the lower page data and the upper page data is the same as the read operation of the middle page data, and can be appropriately executed for each read voltage Kick action, and the amount of kick is appropriately changed for each read voltage. [4-2] Effects of the fourth embodiment

It can be inferred that the appropriate kick amount in the read operation differs according to the read voltage of the read process that performs the kick operation.

For example, it can be inferred that memory cells with a higher threshold voltage tend to be difficult to be turned on. Therefore, it is better to apply a higher kick amount when a kick action is applied. On the other hand, it can be inferred that memory cells with a lower threshold voltage tend to be in an on state relatively easily, so it is better to apply a lower kick amount when a kick action is applied.

Therefore, in the semiconductor memory 1 of the fourth embodiment, as in the third embodiment, it is set whether or not to perform the kick operation for the bit line BL for each read voltage. Furthermore, in the fourth embodiment, when a kick operation with respect to the bit line BL is performed, the kick amount is changed based on the corresponding read voltage.

Thereby, the semiconductor memory 1 of the fourth embodiment can apply an appropriate kick amount for each read process. That is, the semiconductor memory 1 of the fourth embodiment can suppress the increase in the number of error bits caused by the kick operation performed on the bit line BL connected to the ON cell. As a result, the semiconductor memory 1 of the fourth embodiment can suppress the number of error bits compared with the third embodiment, and can improve the reliability of data. [4-3] Variations of the fourth embodiment

In the semiconductor memory 1 of the fourth embodiment described above, the read operation in which the read voltage is sequentially applied from the lower one is exemplified, but it is not limited to this. For example, as in the modification of the first embodiment, even when the read voltage is applied from the higher one during the read operation, it can be applied to the operation described in the fourth embodiment.

Hereinafter, an example of the read operation in the modified example of the fourth embodiment will be described.

FIG. 25 shows an example of a timing chart in the readout operation of bit page data in the modification of the fourth embodiment.

As shown in FIG. 25, in the read operation in the modified example of the fourth embodiment, the order in which the read voltage is applied is changed from the read operation in the fourth embodiment described using FIG. 24.

That is, in the read operation in the modified example of the fourth embodiment, the read voltage FR is applied to the selection signal line CGsel at time t1. At time t4, the read voltage DR is applied to the selection signal line CGsel. At time t7, the read voltage BR is applied to the selection signal line CGsel. Then, similarly to the modification of the first embodiment, the voltage of the selected word line WLsel drops based on the voltage of the select signal line CGsel.

In addition, in the modified example of the fourth embodiment, the sequencer 13 executes the read operation based on the setting of the kick operation for the control signal BLC shown in FIG. 23 in the same way as the read operation in the fourth embodiment.

Specifically, for example, in the read operation of the middle page, the sequencer 13 performs the kick operation of applying the kick amount Dblk2 in the read process using the read voltage FR. In the read process using the read voltage DR, the sequencer 13 performs a kick action of applying the kick amount Dblk1. In the read process using the read voltage BR, the sequencer 13 omits the kick action.

The other operations of the read operation in the modified example of the fourth embodiment are the same as the read operation in the fourth embodiment, so the description will be omitted. Furthermore, as a modification of the fourth embodiment, the reading operation of the middle page data is exemplified, but the same operation can be performed with respect to the respective reading operations of the lower page data and the upper page data.

As described above, in the read operation in the modified example of the fourth embodiment, similar to the fourth embodiment, in each of the group with higher read voltage and the group with lower read voltage, appropriate The read processing. As a result, in the read operation in the modified example of the fourth embodiment, the same effect as that of the fourth embodiment can be obtained. [5] Other changes

The semiconductor memory of the embodiment includes first and second memory cells, word lines, first and second bit lines, first and second sense amplifiers, and a controller. The first and second memory cells respectively store multiple bits of data based on the threshold voltage. The character line is connected to the respective gates of the first and second memory cells. The first and second bit lines are connected to the first and second memory cells, respectively. The first and second sense amplifiers are connected to the first and second bit lines, respectively. The first and second sense amplifiers respectively include a first transistor, a second transistor, and a third transistor. One end of the third transistor is electrically connected to the first transistor and the second transistor, and the other end is connected to the corresponding bit line. In the read operation of the first and second memory cells, the controller applies the first read voltage to the word line. In the first time included in the first period in which the controller applies the first readout voltage <for example, FIG. 13, t5>, the controller applies a first voltage higher than the ground voltage to the first transistor <for example, FIG. 13, Vblk>, a second voltage different from the first voltage is applied to the second transistor <for example, Vblc in FIG. 13,>. At the first moment, the first sense amplifier applies voltage to the first bit line via the first transistor and the third transistor, and the second sense amplifier applies voltage to the second bit line via the second transistor and the third transistor. Apply voltage. Thereby, in the semiconductor memory of the embodiment, the read operation can be speeded up.

In the first embodiment, the case where the kick amount in the kick action is uniform is exemplified, but it is not limited to this. For example, in the read operation of the semiconductor memory 1 of the first embodiment, as in the fourth embodiment, a different kick amount may be applied for each corresponding read voltage. The case of such a reading operation is referred to as a first modification example, and will be described below.

FIG. 26 shows an example of a timing chart of the reading operation of the lower page data in the first modification. As shown in FIG. 26, the readout operation in the first modified example is compared with the readout operation described in FIG. 13 in the first embodiment. The amount of kick of the control signal BLC at time t2 and the control at time t5 The amount of sudden jump of the signal BLC is different.

Specifically, in the read operation in the first modified example, the kick amount Dblk1 is applied in the kick operation at time t2, and the voltage of the control signal BLC1 temporarily rises to Vblk1. In the kick action at time t5, a kick amount Dblk2 greater than the kick amount Dblk1 is applied, and the voltage of the control signal BLC1 temporarily rises to Vblk2.

As a result, in the read operation in the first modified example, as in the fourth embodiment, an appropriate kick amount can be applied for each read process. Furthermore, as in the modified example of the first embodiment, even when the read voltage is applied from the higher one, as in the fourth embodiment, an appropriate kick amount can be applied for each read process. .

In addition, in the second embodiment, the case where the kick amount in the kick operation is uniform is exemplified, but as in the fourth embodiment, a different kick amount may be applied to each corresponding read voltage. The case of such a reading operation is referred to as a second modification example, and will be described below.

FIG. 27 shows an example of a timing chart of the reading operation of the lower page data in the second modification. As shown in FIG. 27, the readout operation in the second modification example is compared with the readout operation described in FIG. 16 in the second embodiment. The kick amount of the control signal BLC2 at time t2 and the control at time t6 The amount of sudden jump of signal BLC2 is different.

Specifically, in the read operation in the second modified example, in the kick operation at time t2, the voltage of the control signal BLC2 temporarily rises to Vblk1. In the kick action at time t6, a kick amount greater than the kick amount at time t2 is applied, and the voltage of the control signal BLC1 temporarily rises to Vblk2.

As a result, in the read operation in the second modified example, as in the fourth embodiment, an appropriate kick amount can be applied for each read process. Furthermore, as in the modified example of the second embodiment, even when the read voltage is applied from the higher one, as in the fourth embodiment, an appropriate kick amount can be applied for each read process. .

Furthermore, in the above embodiment, the case where the kick amount applied to the kick action for the selection signal line CGsel is fixed is explained, but it is not limited to this. For example, the amount of kick corresponding to the selection signal line CGsel can also be changed for each sense voltage.

The timing chart used in the description of the read operation in the above embodiment is just an example. For example, the timing of the respective voltages of the control signal and wiring at each time can also be staggered. In the reading operation, it is sufficient that at least the relationship between the front and back of the operation at each time is not changed.

In the read operation described in the above-mentioned embodiment, the case where the operation of removing residual electrons in the channel is inserted before executing the read processing is exemplified, but it is not limited to this. In the readout operation, the removal of residual electrons in the channel can also be omitted.

The read operation described in the above embodiment can also be applied to verify read in the write operation. Even when the above-mentioned embodiment is applied to the verification and readout, the semiconductor memory 1 can obtain the same effect as the above-mentioned embodiment.

In the first embodiment, the case in which whether to apply the kick operation to the bit line BL is controlled by the node INV (ADL) of the latch circuit ADL is illustrated, but it is not limited to this. For example, as in the second embodiment, the bus LBUS can also be used. In this case, the bus bar LBUS is connected to the respective gates of the transistor 52 and the transistor 53.

Similarly, in the second embodiment, the case where whether to apply a kick operation to the bit line BL is controlled by the bus LBUS is illustrated, but it is not limited to this. For example, as in the first embodiment, the node INV (ADL) of the latch circuit ADL can also be used. In this case, the gate of the transistor 83 is connected to the node INV (ADL).

In the above embodiment, the case where the voltage of the selected word line WLsel becomes the same voltage as the voltage of the select signal line CGsel has been exemplified, but it is not limited to this. The voltage of the selection word line WLsel may also be different from the voltage of the selection signal line CGsel, as long as it changes based on the change of the selection signal line CGsel.

In the above embodiment, a case where TLC (Triple-Level Cell) is applied as a data memory method is illustrated, but it is not limited to this. For example, even when the memory cell transistor MT stores data of 2 bits or more than 4 bits, the semiconductor memory 1 can also perform the read operation described in the above-mentioned embodiment.

In the above-mentioned embodiment, the timing at which the kick action starts can be set to any timing. The timing for the start of the kick action only needs to be included at least in the period from the start of the application of the corresponding sense voltage to the stabilization of the sense voltage.

In the modified example of the foregoing embodiment, when the read voltage transitions from a higher to a lower, the case where the kick operation for the selection signal line CGsel is omitted, but it is not limited to this. For example, when the sense voltage transitions from a higher one to a lower one, a kick action for the selection signal line CGsel can also be performed. In this case, the kick amount in the kick action can be set to a negative value, for example.

In the above-mentioned embodiment, the case where the end of the character line WL is formed in three rows of steps in the lead-out area HA is illustrated, but it is not limited to this. The end of the character line WL may also have a stepped structure with two rows or more than four rows, for example.

In the above-mentioned embodiment, a case where the direction of applying voltage to the blocks BLK arranged in the Y direction is different between the even-numbered block BLK and the odd-numbered block BLK is illustrated, but it is not limited to this. For example, the lead-out area HA may have a structure provided only on one side of the X direction with respect to the unit area CA. In this case, voltage is applied from the same direction to the build-up wiring corresponding to each block BLK.

In the above-mentioned embodiment, the structure in which a voltage is applied to the build-up wiring such as the word line WL from one side in the X direction is exemplified, but it is not limited to this. For example, a contact CC may be provided in each of the lead-out areas HA1 and HA2 in a certain block BLK, and a voltage may be applied to the word line WL etc. from both sides of the X direction. Even in this case, for example, the effect of RC delay will be generated in the central part of the word line WL, so the same effect can be obtained by applying any one of the above-mentioned embodiments.

In the above embodiment, the circuit configuration of the sense amplifier module 16 can be variously changed. For example, the number of latch circuits included in the sense amplifier unit SAU can be appropriately changed based on the number of bits memorized by one memory cell transistor MT. There is also the following situation: according to the configuration of the sense amplifier module 16, the action of "enable the control signal STB" corresponds to the sequencer 13 temporarily changing the control signal STB from the "H" level to the "L" level.

In the above embodiment, the memory pillar MP may also be a structure in which a plurality of pillars are connected in the Z direction. For example, the memory pillar MP may also be a structure in which a pillar passing through the conductor 24 (selection gate line SGD) and a pillar passing through a plurality of conductors 23 (character line WL) are connected. In addition, the memory pillar MP may also have a structure in which a plurality of pillars penetrating a plurality of conductors 23 are connected in the Z direction.

In the above-mentioned embodiment, the structure in which the slit SLT and SLTa divide the conductor 24 has been exemplified, but the slit SLT and SLTa may not divide the conductor 24. In this case, the memory pillar MP has a structure in which a plurality of pillars are connected in the Z direction. For example, the pillars arranged below pass through the conductors 22 and 23, and the pillars arranged above pass through the conductor 24. Furthermore, the conductor 24 is divided by a slit different from the slit SLT and SLTa, for example, and each of the divided conductors 24 functions as a selective gate line SGD.

In the semiconductor memory 1 of the above embodiment, for example, by performing a replacement process using slits SLT, SLTa, and SLTb, the conductors 23 and 24 can be formed. In this case, for example, a plurality of supporting pillars can be formed between adjacent slits SLT and SLTb, each of which is formed of an insulator and penetrates the laminated structure forming the conductors 23 and 24.

In the above-mentioned embodiment, the semiconductor memory 1 has a structure in which circuits such as the sense amplifier module 16 are provided under the memory cell array 10, but it is not limited to this. For example, the semiconductor memory 1 may also have a structure in which the memory cell array 10 is formed on the semiconductor substrate 20. In this case, the memory pillar MP is electrically connected to the semiconductor 31 and the source line SL via the bottom surface of the memory pillar MP, for example.

In the above embodiment, the structure of the memory cell array 10 can also be other structures. Regarding the structure of other memory cell arrays 10, for example, it is described in US Patent Application No. 12/407,403 filed on March 19, 2009 of "Three-dimensional multilayer non-volatile semiconductor memory". U.S. Patent Application No. 12/406,524 filed on March 18, 2009, and filed on March 25, 2010 for "Non-Volatile Semiconductor Memory Device and Its Manufacturing Method" The US Patent Application No. 12/679,991 is pending. It is described in US Patent Application No. 12/532,030 filed on March 23, 2009 in "Semiconductor Memory and Its Manufacturing Method". The entirety of these patent applications is cited in the specification of this application by reference.

In the above embodiment, the block BLK may not be a deletion unit. Regarding other deletion actions, they are recorded in the US Patent Application No. 13/235,389 filed on September 18, 2011 for "Non-Volatile Semiconductor Memory Device" and the application on January 27, 2010 for "Non-Volatile Semiconductor Memory Device". The US Patent Application No. 12/694,690 is pending. The entirety of these patent applications is cited in the specification of this application by reference.

In the above-mentioned embodiment, the case of the three-dimensionally laminated structure of the memory cell transistor MT provided in the memory cell array 10 has been described as an example, but it is not limited to this. For example, the structure of the memory cell array 10 can also be a planar NAND flash memory in which the memory cell transistors MT are two-dimensionally arranged.

In this specification, the so-called “connected” refers to electrical connection, for example, the case where other components are not interposed therebetween is excluded. In addition, in this specification, the so-called "off state" means that a voltage that does not reach the threshold voltage of the transistor is applied to the gate of the corresponding transistor, for example, the current is not as small as the leakage current of the transistor. Except in the case of circulation.

In this specification, "the period during which the controller applies the read voltage" is, for example, in FIG. 13, and corresponds to the period from the time t1 corresponding to the read voltage AR to the time t4 and from the time t4 corresponding to the read voltage ER. The period until time t7. That is, in this specification, the period includes the time point of starting the application of the read voltage and the period during which the kick operation is performed.

In this specification, the term "conductivity type" is used to distinguish between n-channel MOS transistors and p-channel MOS transistors. For example, a transistor of the first conductivity type corresponds to an n-channel MOS transistor, and a transistor of the second conductivity type different from the first conductivity type corresponds to a p-channel MOS transistor.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments or their changes are included in the scope or spirit of the invention, and are included in the invention described in the scope of the patent application and its equivalent scope. [Related application cases]

This application enjoys the priority of the basic application based on Japanese Patent Application No. 2018-151665 (application date: August 10, 2018). This application includes all the contents of the basic application by referring to the basic application.

1: Semiconductor memory 2: Memory controller 10: Memory cell array 11: Command register 12: Address register 13: Sequencer 14: drive module 15: Column decoder module 16: Sense amplifier module 20: Semiconductor substrate 21~25: Conductor 30: core components 31: Semiconductor 32: Laminated film 33: Tunnel oxide film 34: Insulating film 35: barrier insulating film 40, 41: Conductor 50~60: Transistor 61: Capacitor 70, 71: Transistor 72, 73: inverter 80~84: Transistor 90~93: Transistor ADD: address information ADL: latch circuit ALE: address latch enable signal AR: Read voltage ATL: Control signal AV: Verify voltage BD: Block decoder BDL: latch circuit BL: bit line BL0~BLm: bit line BLC1: control signal BLC2: control signal BLK: block BLK0~BLKn: block BLS: control signal BLX: control signal BR: Read voltage BV: verification voltage CA: unit area CG0~CG7: signal line CGsel: Select the signal line CLE: instruction latch enable signal CMD: Command CP, V1, CC: contact CR: Read voltage CU: unit CV: verification voltage DAT: write data Dblk: sudden jump Dcgk: sudden jump DJ: slit dividing part DMP: Dummy column DR: Read voltage DV: Verification voltage ER: Read voltage EV: verification voltage FR: Read voltage FV: verification voltage GR: Read voltage GV: verification voltage HA1: Leading area HA2: Leading area INV: Node I/O: Input and output signals LAT: Node LBUS: bus MP: Memory column MT: Memory cell transistor MT0~MT11: memory cell transistor ND1: Node ND2: Node RBn: ready busy signal RD0~RDn: column decoder Ren: Read out the enabling signal SAU0~SAUm: Sense amplifier unit SEN: Node SDL: latch circuit SGD: select gate line SGD0~SGD3: select gate line SGDD0~SGDD3: signal line SGS: Select gate line SHE: slit SL: source line SLT, SLTa, SLTb: slit ST1, ST2: select transistor STB: control signal STI: Control signal STL: control signal SU: String unit SU0~SU3: string unit TG: Transmission gate line TR1~TR13: Transistor Vblc: voltage VblcL: Voltage Vblk: kick voltage Vblx: Voltage VblxL: Voltage Vdd: power supply voltage Vread: Channel voltage Vss: Ground voltage Vxxl: voltage Wen: Write enabling signal WL: Character line WL0~WL11: Character line WLsel: select character line XDL: latch circuit XXL: Control signal

FIG. 1 is a block diagram showing a configuration example of the semiconductor memory of the first embodiment. Fig. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array included in the semiconductor memory of the first embodiment. FIG. 3 is a plan view showing an example of the planar layout of the memory cell array included in the semiconductor memory of the first embodiment. FIG. 4 is a plan view showing an example of the planar layout in the cell area of the memory cell array included in the semiconductor memory of the first embodiment. FIG. 5 is a cross-sectional view showing an example of the cross-sectional structure in the cell region of the memory cell array included in the semiconductor memory of the first embodiment. FIG. 6 is a cross-sectional view showing an example of the cross-sectional structure of the memory pillar in the semiconductor memory of the first embodiment. FIG. 7 is a top view showing an example of the planar layout in the lead-out area of the memory cell array included in the semiconductor memory of the first embodiment. FIG. 8 is a cross-sectional view showing an example of the cross-sectional structure in the lead-out area of the memory cell array included in the semiconductor memory of the first embodiment. FIG. 9 is a circuit diagram showing an example of the circuit configuration of the column decoder module included in the semiconductor memory of the first embodiment. FIG. 10 is a circuit diagram showing an example of the circuit configuration of the sense amplifier module included in the semiconductor memory of the first embodiment. FIG. 11 is a circuit diagram showing an example of a more detailed circuit configuration of the sense amplifier module included in the semiconductor memory of the first embodiment. Fig. 12 is a diagram showing an example of the threshold distribution, data distribution, and read voltage of the memory cell transistor in the semiconductor memory of the first embodiment. FIG. 13 is a timing chart showing an example of the read operation of the semiconductor memory in the first embodiment. Fig. 14 is a timing chart showing an example of the read operation in the modification of the first embodiment. FIG. 15 is a circuit diagram showing an example of the circuit configuration of the sense amplifier module included in the semiconductor memory of the second embodiment. FIG. 16 is a timing chart showing an example of the read operation of the semiconductor memory of the second embodiment. Fig. 17 is a timing chart showing an example of the read operation in the modified example of the second embodiment. FIG. 18 is a circuit diagram showing an example of the circuit configuration of the sense amplifier module included in the semiconductor memory of the third embodiment. Fig. 19 is a timing chart showing an example of the read operation in the comparative example of the third embodiment. FIG. 20 is a table showing an example of the setting of the kick action in the read operation of the semiconductor memory of the third embodiment. FIG. 21 is a timing chart showing an example of the read operation of the semiconductor memory of the third embodiment. Fig. 22 is a timing chart showing an example of the read operation in the modified example of the third embodiment. FIG. 23 is a table showing an example of the setting of the kick action in the read operation of the semiconductor memory of the fourth embodiment. FIG. 24 is a timing chart showing an example of the read operation of the semiconductor memory of the fourth embodiment. Fig. 25 is a timing chart showing an example of the read operation in the modification of the fourth embodiment. Fig. 26 is a timing chart showing an example of the read operation in the first modification example. FIG. 27 is a timing chart showing an example of the read operation in the second modification example.

ADL: latch circuit

AR: Read voltage

BL: bit line

BLC1: control signal

BLC2: control signal

BLX: control signal

CGsel: Select the signal line

Dblk: sudden jump

Dcgk: sudden jump

ER: Read voltage

INV: Node

STB: control signal

Vblc: voltage

VblcL: Voltage

Vblk: kick voltage

Vblx: Voltage

VblxL: Voltage

Vread: Channel voltage

Vss: Ground voltage

Vxxl: voltage

WLsel: select character line

XXL: Control signal

Claims (20)

A semiconductor memory, which has: first and second memory cells, which respectively store data of multiple bits based on the threshold voltage; character lines, which are connected to the respective gates of the first and second memory cells; The first and second bit lines are connected to the first and second memory cells mentioned above; the first and second sense amplifiers are connected to the first and second bit lines mentioned above respectively; and the controller; In addition, the first and second sense amplifiers include a first transistor, a second transistor, and a third transistor, and one end of the third transistor is electrically connected to the first transistor and the second transistor. Transistor, and the other end is connected to the corresponding bit line. During the read operation of the first and second memory cells, the controller applies the first read voltage to the word line, and the controller applies the For the first time included in the first period of the first read voltage, the controller applies a first voltage higher than the ground voltage to the first transistor, and applies a second voltage that is different from the first voltage to the second transistor. 2 Voltage. At the above first moment, the first sense amplifier applies a voltage to the first bit line via the first transistor and the third transistor, and the second sense amplifier is connected to the first bit line via the second transistor. The third transistor applies a voltage to the second bit line. For example, the semiconductor memory of claim 1, wherein the first and second memory cells respectively store the first data based on the first threshold voltage, and store the second data based on the second threshold voltage higher than the first threshold voltage. In the read operation, the first memory cell has the second threshold voltage, and the second memory cell has the first threshold voltage. For example, the semiconductor memory of claim 1, wherein the first and second sense amplifiers respectively further include: a fourth transistor, one end of which is connected to the first node, and the other end is connected to the first transistor; the fifth transistor One end is connected to the first node, the other end is connected to the second transistor, the gate is connected to the gate of the fourth transistor, and the conductivity type is different from the fourth transistor; and the sixth transistor, It is connected between the power line and the first node; in each of the first and second sense amplifiers, the other end of the first transistor, the other end of the second transistor, and the third One end of the crystal is respectively connected to the second node, and the second voltage is the voltage between the ground voltage and the first voltage. For example, in the semiconductor memory of claim 3, in the second time included in the first period and later than the first time, the controller applies the second transistor to the first transistor and the second transistor, respectively. Voltage. For example, the semiconductor memory of claim 3, wherein in the read operation, the controller applies the initially applied read voltage and is lower than the first read voltage before applying the first read voltage to the word line. The second sense voltage of the output voltage is at the third time included in the second period in which the controller applies the second sense voltage, and the controller applies a third voltage higher than the second voltage to the first transistor. Voltage, apply the second voltage to the second transistor, and at the third moment, the first sense amplifier applies the voltage to the first bit line via the second transistor and the third transistor, and the voltage is applied to the first bit line through the second transistor and the third transistor. 2 The sense amplifier applies a voltage to the second bit line via the second transistor and the third transistor. For example, the semiconductor memory of claim 5, wherein the above-mentioned first voltage is higher than the above-mentioned third voltage. For example, in the semiconductor memory of claim 3, in the above-mentioned read operation, the controller applies the initially applied readout voltage and is higher than the first readout voltage before applying the first readout voltage to the word line. The second sense voltage of the output voltage is at the third time included in the second period in which the controller applies the second sense voltage, and the controller applies a third voltage higher than the second voltage to the first transistor. Voltage, the second voltage is applied to the second transistor, and at the third moment, the first sense amplifier applies voltage to the first bit line via the first transistor and the third transistor, 2 The sense amplifier applies a voltage to the second bit line via the first transistor and the third transistor. Such as the semiconductor memory of claim 7, wherein the above-mentioned first voltage is lower than the above-mentioned third voltage. For example, the semiconductor memory of any one of claims 5 to 8, wherein the first and second sense amplifiers have a plurality of latch circuits respectively, and the latch circuits include gates and gates respectively connected to the fourth transistors. For the first latch circuit of the gate of the fifth transistor, in the read operation, the controller updates the information stored in the first latch circuit based on the read result of the second read voltage. For example, the semiconductor memory of claim 1, wherein the first and second sense amplifiers respectively further include: a fourth transistor, one end of which is supplied with a power supply voltage; a fifth transistor, one end of which is connected to the fourth transistor The other end, the other end is connected to one end of the first transistor; the sixth transistor, one end of which is supplied with a power supply voltage; and the seventh transistor, one end of which is connected to the other end of the sixth transistor, and the other end is connected to One end of the second transistor; In each of the first and second sense amplifiers, the other end of the first transistor is connected to one end of the third transistor, and the other end of the second transistor is connected to On the one end of the first transistor, at the first time, the controller applies a third voltage to the fifth transistor, applies a fourth voltage higher than the third voltage to the seventh transistor, and applies a fourth voltage higher than the third voltage to the seventh transistor. 1 The sixth transistor of the sense amplifier applies a voltage of a first logic level, and the sixth transistor of the second sense amplifier applies a voltage of a second logic level that is different from the first logic level, The second voltage is lower than the first voltage. For example, the semiconductor memory of claim 10, in which the controller applies the third voltage to the first transistor and applies the third voltage to the first transistor at the second time that is included in the first period and is later than the first time. A fifth voltage lower than the third voltage is applied to the crystal, the fourth voltage is applied to the fifth transistor, and a sixth voltage lower than the third voltage is applied to the seventh transistor. For example, the semiconductor memory of claim 10, wherein in the read operation, the controller applies the initially applied read voltage and is lower than the first read voltage before applying the first read voltage to the word line. The second sense voltage of the output voltage is at the third time included in the second period in which the controller applies the second sense voltage. The controller applies the first voltage to the first transistor, and applies the first voltage to the second transistor. The transistor applies a seventh voltage lower than the first voltage. At the third moment, the controller applies the third voltage to the fifth transistor, applies the fourth voltage to the seventh transistor, and applies the fourth voltage to the seventh transistor. 1. The sixth transistor of the sense amplifier applies the voltage of the second logic level, and the voltage of the second logic level is applied to the sixth transistor of the second sense amplifier. For example, the semiconductor memory of claim 12, wherein the above-mentioned second voltage is higher than the above-mentioned seventh voltage. For example, in the semiconductor memory of claim 10, in the above-mentioned read operation, the controller applies the initially applied readout voltage and is higher than the first readout voltage before applying the first readout voltage to the word line. The second sense voltage of the output voltage is at the third time included in the period during which the controller applies the second sense voltage. The controller applies the first voltage to the first transistor, and applies the first voltage to the second transistor. A seventh voltage lower than the first voltage is applied. At the third time, the controller applies the third voltage to the fifth transistor, applies the fourth voltage to the seventh transistor, and responds to the first inductor. The sixth transistor of the sense amplifier applies the voltage of the first logic level, and the voltage of the first logic level is applied to the sixth transistor of the second sense amplifier. For example, the semiconductor memory of claim 14, wherein the above-mentioned second voltage is lower than the above-mentioned seventh voltage. Such as the semiconductor memory of any one of claims 12 to 15, wherein the controller changes the voltage applied to the sixth transistor at the first time based on the reading result of the second reading voltage. A semiconductor memory, which has: a memory cell, which stores data of a plurality of bits based on a threshold voltage; a character line, which is connected to the gate of the above-mentioned memory cell; a bit line, which is connected to the above-mentioned memory cell; a sense amplifier , Which includes a first transistor with one end supplied with a power supply voltage, a second transistor with one end connected to the other end of the first transistor, a third transistor with one end connected to the other end of the second transistor, and one end The fourth transistor connected to the other end of the third transistor and the other end to the bit line; and the controller, which applies the first read voltage and the AND to the word line during the read operation. A second readout voltage different from the first readout voltage; during the first period in which the controller applies the first readout voltage, the controller applies a first voltage higher than the ground voltage to the second transistor, A second voltage higher than the ground voltage is applied to the third transistor, and after the second voltage is applied to the third transistor, a voltage higher than the ground and lower than the second voltage is applied to the third transistor For the third voltage, during the second period in which the controller applies the second readout voltage, the controller applies the first voltage to the second transistor, and the third voltage to the third transistor. The third transistor does not apply a voltage higher than the third voltage. For example, the semiconductor memory of claim 17, wherein the controller sets whether to apply a voltage higher than the third voltage to the third transistor for each read voltage during the period in which the read voltage is applied to the word line. Voltage. For example, the semiconductor memory of claim 17 or 18, wherein the first read voltage is higher than the second read voltage. For example, the semiconductor memory of claim 17 or 18, wherein the controller can apply a third readout voltage different from the first readout voltage and the second readout voltage to the word line, and apply it to the controller In the third period of the third read voltage, the controller applies the first voltage to the second transistor, and applies a fourth voltage higher than the third voltage and different from the third voltage to the third transistor. Voltage.

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