TW202113463A - Multi-layer alignment mark and a method for appliyinf the same - Google Patents

Abstract

A multi-layer alignment mark includes a plurality of first pattern elements and a plurality of second pattern elements. The plurality of first pattern elements are disposed on a surface of a substrate and arranged along a first direction with a first periodic pitch. The plurality of second pattern elements are disposed on the surface of the substrate and arranged along the first direction with a second periodic pitch. The plurality of first pattern elements and the plurality of second pattern elements are arranged in a staggered manner.

Description

Multi-layer alignment mark and alignment method

The present invention relates to an alignment mark and its alignment method, and more particularly to a multi-layer alignment mark and its alignment method.

A typical semiconductor and integrated circuit component is a multilayer structure including a size less than 1 micron. In the process of manufacturing semiconductors and integrated circuit components, the multilayer structure must undergo various processing steps, such as providing photomasks, coating photoresist, etching and deposition processes. In some steps, the material at a specific location in the current processing layer needs to be removed or overlapped with another layer underneath. Proper alignment between the different layers is necessary. Therefore, overlay measurements need to be performed frequently to verify the correctness of the alignment. The lack of correct alignment will usually lead to incorrect specification measurements, failing to meet process requirements, and causing failures of semiconductors and integrated circuit components.

A typical coverage measurement uses optical methods to measure the relative positions of alignment marks on different layers of the semiconductor structure. More specifically, alignment marks need to be formed on each material layer of the semiconductor structure. When two alignment marks of two material layers stacked on top of each other overlap and are centered relative to each other, it can be determined that the two material layers are properly aligned with each other. In order to save space, the alignment mark is generally formed at the position of the scribe line of the semiconductor structure.

However, with the shrinking of key dimensions of modern integrated circuits and the gradual increase in component density, the number of stacks of semiconductors and integrated circuit component structures is more and more complicated. If each material layer is formed, a separate alignment mark must be added and a layer coverage measurement must be performed, which not only wastes the manufacturing process and measurement time, but also easily leads to the problem of insufficient cutting channel space.

Therefore, it is necessary to provide an advanced manufacturing method and application of the dielectric layer to solve the problems faced by the conventional technology.

An embodiment of this specification discloses a multi-layer alignment mark, including: a plurality of first pattern units and a plurality of second pattern units. The first pattern units are located on the surface of the substrate, have a first periodic pitch, and are arranged in parallel along the first direction. The second pattern unit is located on the surface of the substrate, has a second periodic interval, and is staggered with the first pattern unit along the first direction.

Another embodiment of this specification discloses a multi-layer alignment method, which includes the following steps: first, a multi-layer alignment mark is provided, which includes a plurality of first pattern units and a plurality of second pattern units. Wherein, the first pattern units are located on the surface of the substrate, have a first periodic interval, and are arranged in parallel along the first direction. The second pattern unit is located on the surface of the substrate, has a second periodic interval, and is staggered with the first pattern unit along the first direction. Then, simultaneously measure the alignment error of the multi-layer alignment mark with the first target pattern on the first material layer above the surface of the substrate and the second target pattern on the second material layer above the surface of the substrate.

Based on the above, the embodiment of this specification proposes a multi-layer alignment mark and an alignment method thereof. It accommodates at least two groups of alignment pattern groups arranged alternately with each other and covering overlapping areas on the surface of the substrate. Among them, different alignment pattern groups respectively have a plurality of individual case units, and various different plurality of pattern units are respectively arranged in the same direction at different periodic intervals to form a composite alignment mark. By using different alignment pattern groups to correspond to different target patterns on different material layers stacked on the surface of the substrate, the coverage measurement can be performed by using the scattering measurement technology (Diffraction-Based-Overlay, DBO), which can simultaneously judge the difference The alignment error between the material layer and the substrate. Compared with the traditional independent alignment mark, it has the technical advantages of reducing and saving semiconductor device manufacturing process space and alignment process.

This specification provides a multi-layer alignment mark and alignment method, which has the technical advantages of saving space in the manufacturing process of semiconductor devices and reducing alignment procedures. In order to make the above-mentioned embodiments and other purposes, features and advantages of this specification more comprehensible, several alignment marks and their alignment methods are specifically listed below as preferred embodiments, and are described in detail in conjunction with the accompanying drawings. as follows.

However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The preferred embodiments are only used to illustrate the technical features of the present invention, and not to limit the scope of the patent application of the present invention. Those with ordinary knowledge in this technical field will be able to make equivalent modifications and changes based on the description in the following specification without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

Please refer to FIG. 1A and FIG. 1B. FIG. 1A and FIG. 1B are cross-sectional views of a partial process structure of a multilayer alignment mark 100 according to an embodiment of the present specification. In this embodiment, the multi-layer alignment mark 100 may be a patterned material layer formed on the surface 101 a of the semiconductor substrate 101. The formation of the multi-layer alignment mark 100 includes the following steps: first, a semiconductor substrate 101 (as shown in FIG. 1A) is provided. In some embodiments of this specification, the semiconductor substrate 101 may be made of a semiconductor material, such as silicon (Si), germanium (Ge), or a compound semiconductor material, such as gallium arsenide (GaAs), Constituted. However, in other embodiments, the semiconductor substrate 101 may also be a silicon on insulator (SOI) substrate. In this embodiment, the semiconductor substrate 101 is preferably a silicon substrate, such as a silicon wafer.

Then, a deposition process, such as a Low-pressure Chemical Vapor Deposition (LPCVD) process, an evaporation process, or a sputtering process, forms a metal material layer 102 on the surface 101a of the substrate 101. After that, the metal material layer 102 is patterned by the etching process 103 to form a plurality of metal protrusions 100a on the semiconductor substrate 101 (for example, the dicing lane of a silicon wafer (not shown)). Among them, the multi-layer alignment mark 100 is a pattern mark formed by a plurality of metal protrusions 100a (as shown in FIG. 1B).

However, the material of the multi-layer registration mark 100 is not limited to this. In other embodiments of this specification, the multi-layer alignment mark 100 can also be patterned with other material layers on the surface 101a of the substrate 101 by the etching process 103, such as a dielectric layer, a silicide layer, or a semiconductor layer. Material layer to form.

Please refer to FIG. 2. FIG. 2 is a cross-sectional view of a partial process structure of a multilayer alignment mark 200 according to another embodiment of the present specification. In this embodiment, the multi-layer alignment mark 200 can be directly patterned on the substrate 201 by the etching process 203 to form a pattern mark with a plurality of recesses 200a on the surface 201a of the substrate 201.

Please refer to FIG. 3. FIG. 3 is a top view of a multilayer alignment mark 300 according to an embodiment of the present specification. The multi-layer alignment mark 300 is located on the surface 101 a of the substrate 101 and has a first alignment pattern group 310 and a second alignment pattern group 320. The first alignment pattern group 310 includes a plurality of first pattern units 310A, 310B, 310C, 310D, and 310E, which are arranged in parallel along the first direction L1 with a first periodic pitch P1. The second alignment pattern group 320 includes a plurality of second pattern units 320A, 320B, 320C, 320D, and 320E, which are arranged in parallel along the first direction L1 at a second periodic pitch P2. And the first pattern units 310A, 310B, 310C, 310D, and 310E and the second pattern units 320A, 320B, 320C, 320D, and 320E are arranged staggered.

In detail, in this embodiment, each of the first pattern units 310A, 310B, 310C, 310D, and 310E has a short rod-shaped structure with the same size; each short rod-shaped structure has a short axis with a width of W1 and One has a length of H1 long axis and is parallel to each other. The long axes of the first pattern units 310A, 310B, 310C, 310D, and 310E are all perpendicular to the first direction L1. Any two adjacent first pattern units 310A and 310B (310B and 310C, 310C and 310D) are separated by a first periodic pitch P1. Each of the second pattern units 320A, 320B, 320C, 320D, and 320E has a short rod-like structure with the same size. Each short rod-like structure has a short axis with a width of W2 and a long axis with a length of H2, which are parallel to each other. The long axes of the second pattern units 320A, 320B, 320C, 320D, and 320E are all perpendicular to the first direction L1. Any two adjacent second pattern units 320A and 320B (320B and 320C; 320C and 320D; 320D and 320E) are separated by a second periodic pitch P2.

Between any two adjacent first pattern units, a second pattern unit is interspersed. For example, the second pattern unit 320B is interspersed between the first pattern units 310A and 310B; the second pattern unit 320C is interspersed between the first pattern units 310B and 310C; the second pattern unit is interspersed between the first pattern units 310C and 310D Unit 320D; and a second pattern unit 320E is interspersed between the first pattern units 310D and 310E. In other words, within the area A1 covered by the first alignment pattern group 310 (the first pattern units 310A, 310B, 310C, 310D, and 310E), the second alignment pattern group 320 (the second pattern unit 320A) can be accommodated at the same time. , 320B, 320C, 320D and 320E).

The first periodic pitch P1 of the first pattern units 310A, 310B, 310C, 310D, and 310E is at least larger than the width W2 of the short rod-shaped structures of the second pattern units 320A, 320B, 320C, 320D, and 320E. The second periodic pitch P2 of the second pattern units 320A, 320B, 320C, 320D, and 320E is also at least larger than the width W1 of the short rod-shaped structures of the first pattern units 310A, 310B, 310C, 310D, and 310E. In this embodiment, the major axis length H1 of the first pattern units 310A, 310B, 310C, 310D, and 310E may be substantially equal to (but not limited to) the second pattern units 320A, 320B, 320C, 320D, and 320E The long axis length H2. The minor axis width W1 of the first pattern units 310A, 310B, 310C, 310D, and 310E may be substantially larger (but not limited to) the minor axis width W2 of the second pattern units 320A, 320B, 320C, 320D, and 320E.

It is also worth noting that although in this embodiment the first pattern units 310A, 310B, 310C, 310D and 310E and the second pattern units 320A, 320B, 320C, 320D and 320E are in a one-to-one manner (arbitrarily adjacent Between the two first pattern units, one second pattern unit is interspersed with each other in a staggered arrangement. However, the staggered arrangement of the first pattern units 310A, 310B, 310C, 310D, and 310E and the second pattern units 320A, 320B, 320C, 320D, and 320E is not limited to this. For example, in some embodiments of this specification, a plurality of second pattern units (not shown) can be interspersed between any two adjacent first pattern units. In other embodiments, a plurality of first pattern units (not shown) can be interspersed between any two adjacent second pattern units.

Please refer to Figure 4, Figure 4 is based on an embodiment of the present specification, using the multi-layer alignment mark 300 of Figure 3 and the first material layer 402 and the second material layer 403 stacked on the surface 101a of the substrate 101. Schematic diagram of the alignment operation structure. Among them, the first alignment pattern group 310 in the multi-layer alignment mark 300 corresponds to the first target pattern 410 on the first material layer 402; the second alignment pattern group 320 in the multi-layer alignment mark 300 corresponds to It corresponds to the second target pattern 420 on the second material layer 403.

Wherein, the first target pattern 410 has a plurality of first target units 410A, 410B, 410C, and 410D with the same size and arrangement as the first pattern units 310A, 310B, 310C, 310D, and 310E of the first alignment pattern group 310. And 410E. The second target pattern 420 has a plurality of second target units 420A, 420B, 420C, 420D, and 420E with the same size and arrangement as the second pattern units 320A, 320B, 320C, 320D, and 320E of the second alignment pattern group 320 . In some embodiments of this specification, the first target pattern 410 and the first target pattern 410 and the first target pattern 410 and the first target pattern 410 are formed on the first material layer 402 and the second material layer 403, respectively, in the manner shown in FIG. 1A to FIG. 1B or FIG. Two target patterns 420. Since the similar method of forming the pattern has been described in detail above, it will not be repeated here.

When the first material layer 402 is formed on the surface 101a of the substrate 101, the first alignment pattern group 310 and the first target pattern 410 will be stacked on top of each other. If the first pattern units 310A and 310B in the first alignment pattern group 310 , 310C, 310D, and 310E and the first target unit 410A, 410B, 410C, 410D, and 410E in the first target pattern 410 are centered on each other in the direction perpendicular to the surface 101a of the substrate 101, and the first material layer can be determined 402 and substrate 101 are properly aligned with each other. Similarly, when the second material layer 403 is formed on the surface 101a of the substrate 101, the second alignment pattern group 320 and the second mark pattern 420 are stacked on top of each other. If the second pattern unit in the second alignment pattern group 320 is 320A, 320B, 320C, 320D, and 320E correspond to the second target units 420A, 420B, 420C, 420D, and 420E in the second target pattern 420, which correspond to each other in the vertical projection direction on the surface 101a of the substrate 101, and it can be determined The second material layer 402 and the substrate 101 are properly aligned with each other.

In some embodiments of this specification, when aligning the first material layer 402 with the substrate 101, a scattering measurement technique may be used to measure the first pattern units 310A and 310A in the first alignment pattern group 310. A first overly error between 310B, 310C, 310D, and 310E and the first target cells 410A, 410B, 410C, 410D, and 410E in the first target pattern 410. When aligning the second material layer 403 with the substrate 101, scattering measurement technology can also be used to measure the second pattern units 320A, 320B, 320C, 320D, and 320E in the second alignment pattern group 320 The second coverage error with the second target cells 420A, 420B, 420C, 420D, and 420E in the second target pattern 420.

Since the first material layer 402 is formed on the surface 101a of the substrate 101 before the second material layer 403, the alignment operation between the first material layer 402 and the substrate 101 can be earlier than the second material layer 403 and the substrate 101. Alignment operation between materials 101. However, in some embodiments, after the first material layer 402 and the second material layer 403 have been formed on the surface 101a of the substrate 101, the alignment operation can be performed again, and the first material layer 402 and the substrate can be measured at the same time. The first covering error between 101 and the second covering error between the second material layer 403 and the substrate 101, thereby reducing/saving one alignment process. In addition, since the first alignment pattern group 310 and the second alignment pattern group 320, which are used to align the first material layer 402 and the second material layer 403, respectively, can be formed on the surface of the substrate 101 at the same time by a single process 101a can also reduce the process of making alignment marks in the manufacturing process of semiconductors and integrated circuit components.

Please refer to FIG. 5. FIG. 5 is a top view of the multi-layer alignment mark 500 on the surface 501 a of the substrate 501 according to another embodiment of the present specification. The structure of the multi-layer alignment mark 500 is roughly similar to that of the multi-layer alignment mark 300 depicted in FIG. 3, except that the multi-layer alignment mark 500 includes a first alignment pattern group 310 and a second alignment pattern group 320, It also includes a plurality of alignment pattern groups in which the pattern units are located in different regions and whose shapes, sizes, and arrangements are different from or the same as the first alignment pattern group 310 and the second alignment pattern group 320, respectively.

For example, in this embodiment, the multi-layer alignment mark 500 further includes the first alignment mark 500 located in the area A2, and the shape, size, and arrangement of the pattern units are the same as those of the first alignment pattern group 310 and the second alignment pattern group 320, respectively. The third pattern group 530 and the fourth pattern group 540; located in the area A3, and the shape, size and arrangement of the pattern units are respectively different from the first alignment pattern group 310 and the second alignment pattern group 320, the fifth pattern group 550 And the sixth pattern group 560; and the seventh pattern group 570 and the eighth pattern group 570 and the eighth pattern group located in the area A4, and the shape, size, and arrangement of the pattern units are different from the first alignment pattern group 310 and the second alignment pattern group 320, respectively Pattern group 580.

In detail, the third pattern group 530 of the multi-layer alignment mark 500 includes a plurality of third pattern units 530A, 530B, 530C, 530D, and 530E; the fourth pattern group 540 of the alignment mark 500 includes a plurality of fourth pattern units 540A , 540B, 540C, 540D and 540E. The third pattern units 530A, 530B, 530C, 530D, and 530E are arranged in parallel along the first direction L1 at a third periodic pitch P3; the fourth pattern units 540A, 540B, 540C, 540D, and 540E are arranged at a fourth periodic pitch P4 , Arranged in parallel along the first direction L1; and the third pattern units 530A, 530B, 530C, 530D, and 530E and the fourth pattern units 540A, 540B, 540C, 540D, and 540E are interspersed with each other in the area A2 and arranged in a staggered manner. The areas A1 are adjacent to each other (that is, they are located diagonally opposite to the area A1).

In this embodiment, the basic structure (shape, size) and arrangement of the third pattern units 530A, 530B, 530C, 530D, and 530E are the same as those of the first pattern units 310A, 310B, 310C, 310D, and 310E; the fourth pattern unit The basic structures of 540A, 540B, 540C, 540D, and 540E are the same as the second pattern units 320A, 320B, 320C, 320D, and 320E. The third periodic interval P3 is equal to the first periodic interval P1; and the fourth periodic interval P4 is equal to the second periodic interval P3.

The fifth pattern group 550 of the multi-layer alignment mark 500 includes a plurality of fifth pattern units 550A, 550B, 550C, 550D, and 550E; the sixth pattern group 560 of the alignment mark 500 includes a plurality of sixth pattern units 560A, 560B, 560C , 560D and 560E. The fifth pattern units 550A, 550B, 550C, 550D, and 550E are arranged in parallel along the second direction L2 at a fifth periodic pitch P5; the sixth pattern units 560A, 560B, 560C, 560D, and 560E are arranged at a sixth periodic pitch P6 , Arranged in parallel along the second direction L2; and the fifth pattern units 550A, 550B, 550C, 550D, and 550E and the sixth pattern units 560A, 560B, 560C, 560D, and 560E are interspersed with each other and arranged in a staggered arrangement in the area A3, and are arranged with Area A1 is adjacent to each other (located to the right of area A1). The second direction L2 and the first direction L1 form a non-flat angle (that is, a non-180° angle) θ.

In this embodiment, the basic structure (shape and size) of the five pattern units 550A, 550B, 550C, 550D, and 550E is the same as the first pattern units 310A, 310B, 310C, 310D, and 310E, but the arrangement direction is different; the sixth pattern The basic structure of the units 560A, 560B, 560C, 560D, and 560E is the same as the second pattern units 320A, 320B, 320C, 320D, and 320E, but the arrangement direction is different. The fifth period interval P5 is equal to the first period interval P1; and the sixth period interval P6 is equal to the second period interval P3. The second direction L2 is perpendicular to the first direction L1 (that is, at an angle of 90°).

The seventh pattern group 570 of the multi-layer alignment mark 500 includes a plurality of seventh pattern units 570A, 570B, 570C, 570D, and 570E; the eighth pattern group 580 of the alignment mark 500 includes a plurality of eighth pattern units 580A, 580B, 580C , 580D and 580E. The seventh pattern units 570A, 570B, 570C, 570D, and 570E are arranged in parallel along the second direction L2 at a seventh periodic pitch P7; the eighth pattern units 580A, 580B, 580C, 580D, and 580E are arranged at an eighth periodic pitch P8 , Arranged in parallel along the second direction L2; and the seventh pattern units 570A, 570B, 570C, 570D, and 570E and the eighth pattern units 580A, 580B, 580C, 580D, and 580E are interspersed with each other in the area A4 and arranged in a staggered manner. The areas A1 are adjacent to each other (located below the area A1).

In this embodiment, the basic structure (shape and size) of the seventh pattern units 570A, 570B, 570C, 570D, and 570E is the same as the first pattern units 310A, 310B, 310C, 310D, and 310E, but the arrangement direction is different; The basic structure of the pattern units 580A, 580B, 580C, 580D, and 580E is the same as the second pattern units 320A, 320B, 320C, 320D, and 320E, but the arrangement direction is different. The seventh period interval P7 is equal to the first period interval P1; and the eighth period interval P8 is equal to the second period interval P3.

It should be noted that the structural arrangement of the alignment mark 500 is not limited to this. In other embodiments, the multi-layer alignment mark may also include other pattern groups whose shapes, sizes, arrangement angles, and periodic intervals of other pattern units are the same as or different from the above-mentioned pattern units.

Please refer to FIGS. 6A and 6B. FIG. 6A is a top view of a partial structure of the first material layer 602 stacked on the surface 501a of the substrate 501 according to an embodiment of the present specification. FIG. 6B is a top view of a partial structure of the second material layer 603 stacked on the surface 501a of the substrate 501 according to an embodiment of the present specification. When the multi-layer alignment mark 500 is aligned with the first material layer 602 and the second material layer 603 located above the substrate 101 by the method described in Fig. 4, the first pair of the multi-layer alignment mark 500 The alignment pattern formed by the alignment pattern group 310, the third alignment pattern set 530, the fifth alignment pattern set 550, and the seventh alignment pattern set 570 will be the same as the first target pattern 610 located on the first material layer 501 Corresponding to each other; the alignment patterns formed by the second alignment pattern group 320, the fourth alignment pattern group 540, the sixth alignment pattern group 560, and the eighth alignment pattern group 580 in the multilayer alignment mark 500 will be It corresponds to the second target pattern 620 on the second material layer 602.

And when the first target pattern 410 and the alignment pattern constituted by the first alignment pattern group 310, the third alignment pattern group 530, the fifth alignment pattern group 550, and the seventh alignment pattern group 570, the alignment pattern The vertical projection of the surface 101a of the material 101 corresponds to each other in the center, and it can be determined that the first material layer 501 and the substrate 101 are properly aligned with each other. When the second target pattern 620 and the alignment pattern composed of the second alignment pattern group 320, the fourth alignment pattern group 540, the sixth alignment pattern group 560, and the eighth alignment pattern group 580 are applied to the substrate The vertical projection of the surface 101a of the surface 101 corresponds to each other in the center, and it can be determined that the second material layer 602 and the substrate 101 are properly aligned with each other.

Because, the alignment pattern composed of the first alignment pattern group 310, the third alignment pattern group 530, the fifth alignment pattern group 550, and the seventh alignment pattern group 570, and the second alignment pattern group 320 , The alignment patterns formed by the fourth alignment pattern group 540, the sixth alignment pattern group 560, and the eighth alignment pattern group 580 each have at least four sets of regions with different positions (regions A1, A2, A3, and A4) , Respectively, the pattern units arranged along two different directions (for example, directions L1 and L2). Therefore, the measured variation of the first coverage error and the second coverage error will be greatly reduced; the difference between the first material layer 602 and the substrate 101 and the second material layer 603 and the substrate 101 can be improved. The accuracy of the alignment.

Based on the above, the embodiment of this specification proposes a multi-layer alignment mark and an alignment method thereof. It accommodates at least two groups of alignment pattern groups arranged alternately with each other and covering overlapping areas on the surface of the substrate. Among them, different alignment pattern groups respectively have a plurality of individual case units, and various different plurality of pattern units are respectively arranged in the same direction at different periodic intervals to form a composite alignment mark. By using different alignment pattern groups to correspond to different target patterns on different material layers stacked on the surface of the substrate, the scattering measurement technology is used for coverage measurement, which can simultaneously determine the contrast between different material layers and the substrate. Bit error. Compared with the traditional independent alignment mark, it has the technical advantages of saving the space of the semiconductor device manufacturing process and reducing the alignment process.

Although the present invention has been disclosed as above in the preferred embodiment, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100, 200, 300, 500: Multi-layer registration mark 101, 201: base material 101a, 201a: substrate surface 102: metal material layer 103, 203: etching process 200a: Depressed part 310: The first alignment pattern group 320: The second alignment pattern group 310A, 310B, 310C, 310D, 310E: the first pattern unit 320A, 320B, 320C, 320D, 320E: the second pattern unit 402, 602: the first material layer 410, 610: The first target pattern 410A, 410B, 410C, 410D, 410E: the first target unit 403, 603: second material layer 420, 620: second second target pattern 420A, 420B, 420C, 420D, 420E: second target unit 530: The third pattern group 530A, 530B, 530C, 530D, 530E: the third pattern unit 540: The fourth pattern group 540A, 540B, 540C, 540D, 540E: the fourth pattern unit 550: The fifth pattern group 550A, 550B, 550C, 550D, 550E: the fifth pattern unit 560: The sixth pattern group 560A, 560B, 560C, 560D, 560E: sixth pattern unit 570: Seventh Pattern Group 570A, 570B, 570C, 570D, 570E: seventh pattern unit 580; The eighth pattern group 580 580A, 580B, 580C, 580D, 580E: the eighth pattern unit A1, A2, A3, A4: area L1; first direction L2: second direction P1: first period pitch P2: second period interval P1: third period interval P4: The fourth period interval W1, W2: the width of the short axis of the short rod structure H1, H2: the length of the long axis of the short rod structure Θ: non-flat angle

In order to make the above-mentioned embodiments and other objectives, features and advantages of the present invention more comprehensible, a few preferred embodiments are listed in conjunction with the accompanying drawings, which are described in detail as follows: Figures 1A and 1B are cross-sectional views of a partial process structure of a multi-layer alignment mark according to an embodiment of this specification; Figure 2 is a cross-sectional view of a part of the process structure of a multilayer alignment mark according to another embodiment of the present specification; Figure 3 is a top view of the multi-layer alignment mark drawn according to an embodiment of this specification; Fig. 4 is a schematic diagram of an operation structure for aligning the first material layer and the second material layer stacked on the surface of the substrate using the multilayer alignment mark of Fig. 3 according to an embodiment of the present specification; Figure 5 is a top view of a multilayer alignment mark on the surface of the substrate according to another embodiment of the present specification; FIG. 6A is a top view of a partial structure of the first material layer stacked on the surface of the substrate according to an embodiment of the present specification; and FIG. 6B is a top view of a partial structure of the second material layer stacked on the surface of the substrate according to an embodiment of the present specification.

100: Multi-layer registration mark

101: Substrate

101a, 201a: substrate surface

310: The first alignment pattern group

320: The second alignment pattern group

310A, 310B, 310C, 310D, 310E: the first pattern unit

320A, 320B, 320C, 320D, 320E: the second pattern unit

402: First Material Layer

410: The first target pattern

410A, 410B, 410C, 410D, 410E: the first target unit

403: Second Material Layer

420: second target pattern

420A, 420B, 420C, 420D, 420E: second target unit

L1: first direction

Claims (11)

A multi-layer alignment mark, including: A plurality of first pattern units are located on a surface of a substrate, have a first periodic pitch (periodic pitch), and are arranged in parallel along a first direction; and A plurality of second pattern units are located on the surface of the substrate, have a second periodic interval, and are alternately arranged with the plurality of first pattern units along the first direction. The multi-layer alignment mark described in item 1 of the scope of the patent application, wherein the plurality of first pattern units constitute a first alignment pattern group, which is used to interact with a first material layer located above the surface of the substrate. The first target pattern corresponds; the plurality of second pattern units constitute a second alignment pattern group for corresponding to a second target pattern on a second material layer above the surface of the substrate. According to the multi-layer alignment mark described in item 1 of the scope of patent application, the first alignment pattern group and the second alignment pattern group are located in a first area on the surface of the substrate. The multi-layer alignment mark described in item 1 of the scope of patent application further includes: a plurality of third pattern units located on the surface of the substrate, having a third periodic interval, and being connected to the plurality of third pattern units along the first direction The first pattern unit and the plurality of second pattern units are arranged alternately. The multi-layer alignment mark described in item 1 of the scope of patent application includes: A plurality of fourth pattern units are located on the surface of the substrate, have a fourth periodic interval, and are arranged in parallel along a second direction; and A plurality of fifth pattern units are located on the surface of the substrate, have a fifth periodic interval, and are alternately arranged with the fourth pattern units along the second direction. The multi-layer alignment mark described in item 5 of the scope of patent application, wherein the first direction and the second direction have a non-flat angle (non-180° angle). The multi-layer alignment mark according to item 1 of the scope of patent application, wherein at least one of the plurality of first pattern units and the plurality of second pattern units is included in a pattern formed on the surface of the substrate In the metal layer. The multi-layer alignment mark described in item 1 of the scope of patent application, wherein at least one of the plurality of first pattern units and the plurality of second pattern units is formed by a plurality of depressions formed on the surface of the substrate Constituted. A method of multi-layer alignment, including: Provide a multi-layer registration mark, including: A plurality of first pattern units are located on the surface of a substrate, have a first periodic pitch, and are arranged in parallel along a first direction; and A plurality of second pattern units are located on the surface of the substrate, have a second periodic interval, and are arranged staggered with the plurality of first pattern units along the first direction; and Simultaneously measure the multi-layer alignment mark and a first target pattern on a first material layer above the surface of the substrate, and a second target pattern on a second material layer above the surface of the substrate. Alignment error. The multi-layer alignment method according to item 9 of the scope of patent application, wherein the step of simultaneously measuring the alignment error of the multi-layer alignment mark with the first target pattern and the second target pattern includes: Calculating a first overly error between the plurality of first pattern units and the first target pattern; and Calculate a second coverage error between the plurality of second pattern units and the second target pattern. The multi-layer alignment method described in item 9 of the scope of patent application, wherein the step of calculating the first coverage error and the second coverage error includes a scattering measurement technology (Diffraction-Based-Overlay, DBO).

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