TW202111978A - Display panel and method of manufacturing the same - Google Patents
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- 239000002184 metal Substances 0.000 claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000059 patterning Methods 0.000 claims abstract description 11
- 238000002513 implantation Methods 0.000 claims abstract description 9
- 239000010409 thin film Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 22
- 229920005591 polysilicon Polymers 0.000 description 22
- 238000005530 etching Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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Abstract
Description
本發明是有關於一種顯示面板及其製造方法,且特別是有關於一種具有低濃度摻雜區域薄膜電晶體的顯示面板及其製造方法。 The present invention relates to a display panel and a manufacturing method thereof, and more particularly to a display panel with a low-concentration doped region thin film transistor and a manufacturing method thereof.
隨著科技的發展,顯示裝置被廣泛應用在許多電子產品上,如手機、平板電腦、手錶等。為了提高顯示質量,大尺寸、高解析度、高亮度的低溫多晶矽薄膜電晶體顯示面板應運而生。 With the development of technology, display devices are widely used in many electronic products, such as mobile phones, tablet computers, watches and so on. In order to improve display quality, large-size, high-resolution, and high-brightness low-temperature polysilicon thin-film transistor display panels have emerged.
現有的低溫多晶矽薄膜電晶體顯示面板,一般在進行低濃度離子摻雜形成低濃度摻雜區域(LDD lightly doped drain)時,通常採用如下兩種方法:1、使用栅極金屬層作為掩模進行高濃度摻雜,再對栅極金屬層進行二次蝕刻,進一步縮減栅極金屬層的綫寬,以栅極金屬層作為掩模進行低濃度摻雜,形成低濃度摻雜區域;2、使用專用的光罩製作掩模層從而定義高濃度摻雜區域,去除掩模層後,使用栅極金屬層作為掩模進行低濃度摻雜,形成低濃度摻雜區域。上述的第一種方法會對所有的栅極金屬層造成影響,設計時需對所有的栅極金屬層走綫都要進行加粗以防止斷 綫,使得數據及移位寄存器扇出部分走綫的綫寬和綫距所占空間增大,越來越難以實現客戶未來更窄邊框的要求,嚴重影響產品競爭力,而且二次蝕刻使得對於有不同圖形密度的栅極金屬層有不同的蝕刻速率,因此需要針對不同部位進行分區補償,降低了出圖效率且增加了出錯概率;第二種方法需要額外增加一層光罩,成本較高。 Existing low-temperature polysilicon thin-film transistor display panels generally use the following two methods when low-concentration ion doping is performed to form a low-concentration doped drain (LDD lightly doped drain): 1. Use the gate metal layer as a mask. High-concentration doping, and then second etching the gate metal layer to further reduce the line width of the gate metal layer, using the gate metal layer as a mask for low-concentration doping to form a low-concentration doped area; 2. Use A special photomask is used to make a mask layer to define high-concentration doped regions. After removing the mask layer, use the gate metal layer as a mask to perform low-concentration doping to form low-concentration doped regions. The first method mentioned above will affect all the gate metal layers. During design, all gate metal layer traces must be thickened to prevent disconnection. The line width and line spacing of the fan-out part of the data and shift registers occupy more space, making it more and more difficult to meet the requirements of customers for a narrower frame in the future, which seriously affects the competitiveness of products, and the secondary etching makes it difficult to Gate metal layers with different pattern densities have different etching rates, so it is necessary to perform partition compensation for different parts, which reduces the drawing efficiency and increases the error probability; the second method requires an additional layer of photomask, which is costly.
因此,如何能在不增加專用光罩的基礎上,形成低濃度摻雜區域,且避免因使用二次蝕刻而帶來的弊端,增加產品競爭力。實為需要解决的問題之一。 Therefore, how to form a low-concentration doped area without adding a dedicated photomask, avoid the disadvantages caused by the use of secondary etching, and increase product competitiveness. It is one of the problems that needs to be solved.
為解决上述問題,本發明提供一種顯示面板及其製造方法,可以利用顯示面板製作流程中其他層別的光罩,定義薄膜電晶體中的低濃度摻雜區域,獲得更小綫寬和/或綫距的栅極金屬層,增加薄膜電晶體對側向光和正向光的光漏電保護,簡化出圖流程,提高效率,降低出錯概率。 In order to solve the above-mentioned problems, the present invention provides a display panel and a manufacturing method thereof, which can use photomasks of other layers in the display panel manufacturing process to define low-concentration doped regions in thin film transistors to obtain smaller line widths and/or The gate metal layer of the line pitch increases the light leakage protection of the thin film transistor to the side light and the forward light, which simplifies the drawing process, improves the efficiency, and reduces the error probability.
本發明一實施例的顯示面板的製造方法,包括提供一基板;形成一第一遮光層於所述基板,且圖案化所述第一遮光層,以形成一第一圖案化遮光層;設置一緩衝層於所述基板,且所述緩衝層覆蓋所述第一圖案化遮光層;形成一半導體層於所述緩衝層,且圖案化所述半導體層,以形成一圖案化半導體層;設置一第一絕緣層於所述基板,且所述第一絕緣層覆蓋所述圖案化半導體層;設置一第一金屬層於所述第一絕緣層,且圖案化所述第一金屬層,以形成一第一 圖案化金屬層;以所述第一圖案化金屬層為掩模而進行一第一離子濃度注入,形成一輕摻雜區與一溝道區於所述半導體層;設置一遮光材料層於所述第一圖案化金屬層上,且圖案化所述遮光材料層以形成一圖案化遮光材料層;以及以所述圖案化遮光材料層為掩模而進行一第二離子濃度注入,形成一重摻雜區於所述半導體層。 A method of manufacturing a display panel according to an embodiment of the present invention includes providing a substrate; forming a first light-shielding layer on the substrate, and patterning the first light-shielding layer to form a first patterned light-shielding layer; A buffer layer is on the substrate, and the buffer layer covers the first patterned light-shielding layer; a semiconductor layer is formed on the buffer layer, and the semiconductor layer is patterned to form a patterned semiconductor layer; A first insulating layer is on the substrate, and the first insulating layer covers the patterned semiconductor layer; a first metal layer is disposed on the first insulating layer, and the first metal layer is patterned to form One first A patterned metal layer; using the first patterned metal layer as a mask to perform a first ion concentration implantation to form a lightly doped region and a channel region on the semiconductor layer; and a light-shielding material layer is placed on the On the first patterned metal layer, and patterning the shading material layer to form a patterned shading material layer; and using the patterned shading material layer as a mask to perform a second ion concentration implantation to form a heavy doping The miscellaneous region is in the semiconductor layer.
本發明一實施例的一種顯示面板,具有多個薄膜電晶體,其中,所述薄膜電晶體包括一基板;一第一圖案化遮光層,設置於所述基板;一緩衝層,覆蓋所述第一圖案化遮光層;一半導體層,設置於所述緩衝層上方,使得所述緩衝層位於所述半導體層與所述第一圖案化遮光層之間,且所述半導體層具有一第一重摻雜區、一第一輕摻雜區、一第二重摻雜區、一第二輕摻雜區與一溝道區,所述溝道區位於所述第一輕摻雜區與所述第二輕摻雜區之間,且所述第一輕摻雜區分別鄰近於所述第一重摻雜區與所述溝道區,所述第二輕摻雜區分別鄰近於所述第二重摻雜區與所述溝道區;一第一絕緣層,設置於所述半導體層上方;一第一圖案化金屬層,設置於所述第一絕緣層上方,且所述第一圖案化金屬層與所述溝道區在所述基板的垂直投影面積彼此重叠;以及一第二圖案化遮光層,設置於所述第一圖案化金屬層上方,其中,所述第二圖案化遮光層於所述基板的投影面積的部分外輪廓與所述第一輕摻雜區鄰接於所述第一重摻雜區的交界處對齊;其中,所述第二圖案化遮光層於所述基板的投影面 積的另一部分外輪廓與所述第二輕摻雜區鄰接於所述第二重摻雜區的交界處對齊。 A display panel according to an embodiment of the present invention has a plurality of thin film transistors, wherein the thin film transistors include a substrate; a first patterned light-shielding layer disposed on the substrate; and a buffer layer covering the first A patterned light-shielding layer; a semiconductor layer disposed above the buffer layer so that the buffer layer is located between the semiconductor layer and the first patterned light-shielding layer, and the semiconductor layer has a first layer Doped region, a first lightly doped region, a second heavily doped region, a second lightly doped region and a channel region, the channel region is located between the first lightly doped region and the Between the second lightly doped regions, and the first lightly doped regions are respectively adjacent to the first heavily doped region and the channel region, and the second lightly doped regions are respectively adjacent to the first heavily doped region A double-doped region and the channel region; a first insulating layer disposed above the semiconductor layer; a first patterned metal layer disposed above the first insulating layer, and the first pattern The metallized metal layer and the channel region overlap each other on the vertical projection area of the substrate; and a second patterned light-shielding layer is disposed above the first patterned metal layer, wherein the second patterned light-shielding layer A part of the outer contour of the projected area of the layer on the substrate is aligned with the junction of the first lightly doped region adjacent to the first heavily doped region; wherein, the second patterned light-shielding layer is on the substrate Projection surface Another part of the outer contour of the product is aligned with the junction where the second lightly doped region is adjacent to the second heavily doped region.
以下結合附圖和具體實施例對本發明進行詳細描述,但不作為對本發明的限定。 The following describes the present invention in detail with reference to the accompanying drawings and specific embodiments, but it is not intended to limit the present invention.
100‧‧‧顯示面板 100‧‧‧Display Panel
101‧‧‧基板 101‧‧‧Substrate
102‧‧‧第一遮光層 102‧‧‧First shading layer
103‧‧‧緩衝層 103‧‧‧Buffer layer
104‧‧‧半導體層 104‧‧‧Semiconductor layer
105‧‧‧第一絕緣層 105‧‧‧First insulation layer
106‧‧‧第一金屬層 106‧‧‧First metal layer
107‧‧‧第二絕緣層 107‧‧‧Second insulating layer
108‧‧‧遮光材料層 108‧‧‧Shading material layer
N+‧‧‧重摻雜區 N+‧‧‧Heavy doped area
N-‧‧‧輕摻雜區 N-‧‧‧Lightly doped area
CH‧‧‧溝道區 CH‧‧‧Channel area
圖1A-圖1F是本發明一實施例低溫多晶矽薄膜電晶體製造方法的流程圖。 1A-1F are flowcharts of a method for manufacturing low-temperature polysilicon thin-film transistors according to an embodiment of the present invention.
圖2是本發明一實施例低溫多晶矽薄膜電晶體的結構俯視示意圖。 2 is a schematic top view of the structure of a low temperature polysilicon thin film transistor according to an embodiment of the present invention.
圖3是本發明另一實施例低溫多晶矽薄膜電晶體製造方法的流程圖。 FIG. 3 is a flowchart of another embodiment of the manufacturing method of low-temperature polysilicon thin film transistors of the present invention.
圖4是本發明另一實施例低溫多晶矽薄膜電晶體的結構俯視示意圖。 4 is a schematic top view of the structure of a low temperature polysilicon thin film transistor according to another embodiment of the present invention.
圖5A-圖5E是本發明又一實施例低溫多晶矽薄膜電晶體製造方法的流程圖。 5A-5E are flowcharts of a method for manufacturing a low-temperature polysilicon thin-film transistor according to another embodiment of the present invention.
圖6是本發明又一實施例低溫多晶矽薄膜電晶體的結構俯視示意圖。 FIG. 6 is a schematic top view of the structure of a low temperature polysilicon thin film transistor according to another embodiment of the present invention.
圖7A-圖7E是本發明再一實施例低溫多晶矽薄膜電晶體製造方法的流程圖。 7A-7E are flowcharts of a method for manufacturing a low-temperature polysilicon thin-film transistor according to another embodiment of the present invention.
圖8A-圖8B是本發明再一實施例低溫多晶矽薄膜電晶體的結構俯視示意圖。 8A-8B are schematic top views of the structure of a low-temperature polysilicon thin film transistor according to another embodiment of the present invention.
下面結合附圖對本發明的結構原理和工作原理作具體的描述。 The structural principle and working principle of the present invention will be described in detail below in conjunction with the accompanying drawings.
本發明提供一種顯示面板的製造方法,特別是顯示面板中低溫多晶矽薄膜電晶體的製造方法,對於本領域技術人員而言,其他結構採用熟知的製造方法。 The present invention provides a method for manufacturing a display panel, particularly a method for manufacturing a low-temperature polysilicon thin film transistor in a display panel. For those skilled in the art, other structures adopt well-known manufacturing methods.
第一實施例The first embodiment
圖1A-圖1F是本發明一實施例低溫多晶矽薄膜電晶體製造方法的流程圖。本實施例中的低溫多晶矽薄膜電晶體100的製造方法包括以下步驟。
1A-1F are flowcharts of a method for manufacturing low-temperature polysilicon thin-film transistors according to an embodiment of the present invention. The manufacturing method of the low temperature polysilicon
如圖1A所示,首先提供一基板101,在基板101上形成一第一遮光層102,並對第一遮光層102進行圖案化,形成圖案化的第一遮光層102。其中,第一遮光層例如為遮光金屬層,可以為鈦、鉬、鉻、銥、鋁、銅、銀、金或上述的任意組合。
As shown in FIG. 1A, a
接下來,如圖1B所示,在基板101上形成一緩衝層103,緩衝層103覆蓋圖案化的第一遮光層102以及基板101。然後,在緩衝層103上形成一半導體層104,並圖案化半導體層104,形成一圖案化的半導體層104。其中,半導體層104可以採用非晶矽、多晶矽等半導體材料製成,本發明並不以此為限。
Next, as shown in FIG. 1B, a
如圖1C所示,在半導體層104上形成一第一絕緣層105,第一絕緣層105覆蓋圖案化的半導體層104。再
在第一絕緣層105上形成一第一金屬層106,並且圖案化第一金屬層106,以形成一圖案化的第一金屬層106。
As shown in FIG. 1C, a first
下一步,如圖1D所示,以圖案化的第一金屬層106作為掩模,對半導體層104進行低濃度離子注入,在半導體層104中形成一溝道區CH以及輕摻雜區N-。其中,輕摻雜區N-位於溝道區CH兩側,溝道區CH的位置與圖案化的第一金屬層106的位置相對應。
Next, as shown in FIG. 1D, using the patterned
然後,如圖1E所示,形成一第二絕緣層107,第二絕緣層107覆蓋圖案化的第一金屬層106以及第一絕緣層105,再在第二絕緣層107上形成一遮光材料層108,並且對遮光材料層108進行圖案化,形成圖案化的遮光材料層108。其中,在本實施例中,遮光材料層108採用與第一遮光層102相同的膜層製成,並採用相同的光罩進行圖案化,使得圖案化的遮光材料層108與圖案化的第一遮光層102的位置相對應。
Then, as shown in FIG. 1E, a second
最後,如圖1F所示,採用圖案化的遮光材料層108作為掩模,對半導體層104進行高濃度離子注入,在半導體層104中的溝道區CH與輕摻雜區N-之間形成重摻雜區N+。
Finally, as shown in FIG. 1F, using the patterned light-shielding
當然,形成低溫多晶矽薄膜電晶體100以及顯示面板還有很多其他的層,本發明僅示例性的進行描述,並不以此為限。
Of course, there are many other layers for forming the low-temperature polysilicon
圖2是本發明一實施例低溫多晶矽薄膜電晶體的結構俯視示意圖。由圖2可以看出,由於採用遮光材料層
108作為離子注入掩模,因此,在第一金屬層106的上方還形成有一遮光材料層,可以進一步增加薄膜電晶體對側向光和正向光的光漏電保護。需要說明的是,圖1A-圖1F是沿圖2中剖面綫A-A’所示的剖面結構示意圖。
2 is a schematic top view of the structure of a low temperature polysilicon thin film transistor according to an embodiment of the present invention. As can be seen from Figure 2, due to the use of light-shielding
第二實施例Second embodiment
圖3是本發明另一實施例低溫多晶矽薄膜電晶體製造方法的流程圖。結合圖1A-1F以及圖3,與第一實施例不同的是,在對遮光材料層108進行圖案化的過程中,採用過度蝕刻或過度曝光的方式進行,使得圖案化的遮光材料層108較圖案化的第一遮光層102的寬度小。然後,採用圖案化的遮光材料層108作為掩模,對半導體層104進行高濃度離子注入,在半導體層104中輕摻雜區N-的兩側形成重摻雜區N+。採用過度蝕刻或過度曝光方式對遮光材料層108進行圖案化,可以調整輕摻雜區N-的寬度,使得輕摻雜區N-的寬度較第一實施例中輕摻雜區N-的寬度更小。
FIG. 3 is a flowchart of another embodiment of the manufacturing method of low-temperature polysilicon thin film transistors of the present invention. With reference to FIGS. 1A-1F and FIG. 3, the difference from the first embodiment is that in the process of patterning the light-shielding
圖4是本發明另一實施例低溫多晶矽薄膜電晶體的結構俯視示意圖。由圖4可以看出,遮光材料層108的寬度較第一遮光層102的寬度更小。需要說明的是,圖3是沿圖4中剖面綫B-B’所示的剖面結構示意圖。
4 is a schematic top view of the structure of a low temperature polysilicon thin film transistor according to another embodiment of the present invention. It can be seen from FIG. 4 that the width of the light-shielding
第三實施例The third embodiment
圖5A-圖5E是本發明又一實施例低溫多晶矽薄膜電晶體製造方法的流程圖。圖5A-圖5C的步驟與第一實施例中的步驟相同,在此不再贅述。 5A-5E are flowcharts of a method for manufacturing a low-temperature polysilicon thin-film transistor according to another embodiment of the present invention. The steps in FIG. 5A to FIG. 5C are the same as the steps in the first embodiment, and will not be repeated here.
具體的,如圖5D所示,形成一第二絕緣層107,第二絕緣層107覆蓋圖案化的第一金屬層106以及第一絕緣層105,再在第二絕緣層107上形成一遮光材料層108,並且對遮光材料層108進行圖案化,形成圖案化的遮光材料層108。其中,在本實施例中,遮光材料層108採用光阻材料層,採用與第一遮光層相同的光罩進行圖案化,使得圖案化的遮光材料層108與圖案化的第一遮光層102的位置相對應。採用圖案化的遮光材料層108作為掩模,對半導體層104進行高濃度離子注入,在半導體層104中形成一溝道區CH與重摻雜區N+。其中,重摻雜區N+位於溝道區CH兩側,溝道區CH的位置與圖案化的遮光材料層108的位置相對應。另外,也可以對遮光材料層108進行過度蝕刻或過度曝光,使得圖案化的遮光材料層108的尺寸小於圖案化的第一遮光層102。
Specifically, as shown in FIG. 5D, a second insulating
下一步,如圖5E所示,在進行高濃度離子注入步驟之後,將圖案化的遮光材料層108移除,然後,以圖案化的第一金屬層106作為掩模,對半導體層104進行低濃度離子注入。由此,在半導體層104中的溝道區CH兩側形成輕摻雜區N-。其中,輕摻雜區N-位於溝道區CH兩側,溝道區CH的位置與圖案化的第一金屬層106的位置相對應,重摻雜區N+位於輕摻雜區N-的兩側,且輕摻雜區N-位於溝道區CH與重摻雜區N+之間。
Next, as shown in FIG. 5E, after the high-concentration ion implantation step is performed, the patterned light-shielding
圖6是本發明又一實施例低溫多晶矽薄膜電晶體的結構俯視示意圖。由圖6可以看出,與第一實施例或第
二實施例不同的是,由於將遮光材料層108進行移除,本實施例中薄膜電晶體100中並不存在遮光材料層108,其結構與熟知的薄膜電晶體的結構相同。需要說明的是,圖5A-圖5E是沿圖6中剖面綫C-C’所示的剖面結構示意圖。
FIG. 6 is a schematic top view of the structure of a low temperature polysilicon thin film transistor according to another embodiment of the present invention. It can be seen from Fig. 6 that, compared with the first embodiment or the first
The difference between the two embodiments is that since the light-shielding
第四實施例Fourth embodiment
圖7A-圖7E是本發明再一實施例低溫多晶矽薄膜電晶體製造方法的流程圖。圖7A-圖7D的步驟與第一實施例中的步驟相同,在此不再贅述。 7A-7E are flowcharts of a method for manufacturing a low-temperature polysilicon thin-film transistor according to another embodiment of the present invention. The steps in FIGS. 7A-7D are the same as the steps in the first embodiment, and will not be repeated here.
具體的,如圖7E所示,在圖案化的第一金屬層106上直接形成一遮光材料層108,並且對遮光材料層108進行圖案化,形成圖案化的遮光材料層108,圖案化的遮光材料層108覆蓋圖案化的第一金屬層106的上表面、兩側表面以及第一絕緣層105。其中,在本實施例中,遮光材料層108採用與第一遮光層102相同的膜層製成,或採用光阻材料層製成,並採用與第一遮光層102相同的光罩進行圖案化,在對遮光材料層108進行圖案化的過程中,採用過度蝕刻或過度曝光的方式進行。使得圖案化的遮光材料層108較圖案化的第一遮光層102的寬度小。然後,採用圖案化的遮光材料層108作為掩模,對半導體層104進行高濃度離子注入,在半導體層104中輕摻雜區N-兩側形成重摻雜區N+。其中,當遮光材料層108採用光阻材料層時,在進行高濃度離子注入步驟之後,需移除圖案化的遮光材料層108。
Specifically, as shown in FIG. 7E, a light-shielding
圖8A-圖8B是本發明再一實施例低溫多晶矽薄膜電晶體的結構俯視示意圖。當遮光材料層108採用遮光金
屬層時,由圖8A可以看出,薄膜電晶體100中,不僅包括第一遮光層102,也包括遮光材料層108,且遮光材料層108的寬度較第一遮光層102的寬度更小。當遮光材料層108採用光阻材料層時,由圖8B可以看出,薄膜電晶體100中,僅包括第一遮光層102,並不包括遮光材料層108。需要說明的是,圖7A-圖7E是沿圖8中剖面綫D-D’所示的剖面結構示意圖。
8A-8B are schematic top views of the structure of a low-temperature polysilicon thin film transistor according to another embodiment of the present invention. When the
綜上,依照本發明的實施例,可以利用顯示面板製作流程中其他層別的光罩,定義薄膜電晶體中的低濃度摻雜區域,獲得更小綫寬和/或綫距的栅極金屬層,增加薄膜電晶體對側向光和正向光的光漏電保護,簡化出圖流程,提高效率,降低出錯概率。 In summary, according to the embodiments of the present invention, other layers of photomasks in the display panel manufacturing process can be used to define low-concentration doped regions in thin-film transistors to obtain gate metal with smaller line width and/or line spacing. Layer, increase the light leakage protection of thin film transistors for side light and forward light, simplify the drawing process, improve efficiency, and reduce the probability of error.
當然,本發明還可有其它多種實施例,在不背離本發明精神及其實質的情况下,熟悉本領域的技術人員當可根據本發明作出各種相應的改變和變形,但這些相應的改變和變形都應屬於本發明所附的申請專利範圍的保護範圍。 Of course, the present invention can also have various other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and All the deformations shall fall within the protection scope of the attached patent application of the present invention.
100‧‧‧顯示面板 100‧‧‧Display Panel
102‧‧‧第一遮光層 102‧‧‧First shading layer
104‧‧‧半導體層 104‧‧‧Semiconductor layer
107‧‧‧第二絕緣層 107‧‧‧Second insulating layer
108‧‧‧遮光材料層 108‧‧‧Shading material layer
N+‧‧‧重摻雜區 N+‧‧‧Heavy doped area
N-‧‧‧輕摻雜區 N-‧‧‧Lightly doped area
CH‧‧‧溝道區 CH‧‧‧Channel area
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