TW202111538A - Memory device, writing method, and reading method - Google Patents

Abstract

A memory device includes a memory array and a memory controller. The memory array includes a first memory bank, a second memory bank, and a third memory bank. The first memory bank includes a first sub memory bank. The second memory bank includes a second sub memory bank. The memory controller, according to a write command from a host, writes first data from the host to the first memory bank and second data to the second memory bank at the same time, and writes a first hamming weight of the first data to the third memory bank. The second data is an inverse of the first data.

Description

Memory device, writing method and reading method

The present invention relates to a memory device and its writing method and reading method, and more particularly to a memory device with data security and its writing method and reading method.

Since the power consumption of static random access memory (SRAM) for writing or reading logic 0 and logic 1 may be different, hackers know that static random access memory reads and writes logic 0 and logic 1 In the case of power consumption of 1, the actual read and write data content can be known through the change of power consumption and permutation and combination. Therefore, for the handling of confidential information, we need a more efficient way to maintain the security of the information.

In view of this, the present invention provides a memory device including a memory array and a memory controller. The memory array includes a first memory bank, a second memory bank, and a third memory bank. The above-mentioned first memory bank includes a first sub-memory bank. The above-mentioned second memory bank includes a second sub-memory bank. The memory controller sends a write command from a host, and simultaneously writes a first data sent by the host to the first memory bank and writes the second data to the second sub-memory bank at the same time , And write the first Hamming weight, one of the first data, into the third database, wherein the second data is the inverse of the first data.

According to an embodiment of the present invention, the above-mentioned memory array further includes a fourth memory bank. The fourth memory bank is used to store a second Hamming weight, wherein the second Hamming weight is the inverse of the first Hamming weight, and the memory controller writes the first Hamming weight at the same time Enter the third memory bank and write the second Hamming weight into the fourth memory bank.

According to an embodiment of the present invention, the aforementioned memory controller further includes a Hamming weight encoder. The Hamming weight encoder is used to count that the first data has a first bit number and a first logic, and generates the first Hamming weight according to the first bit number, and generates the first hamming weight Reverse the above second Hamming weight.

According to an embodiment of the present invention, when the memory controller receives a read command sent by the host to read the first data in the first memory bank, the memory controller reads the first data at the same time The first Hamming weight of the three memory banks and the second Hamming weight of the fourth memory bank, wherein the memory controller generates a first dummy data according to the first Hamming weight, and the first Dummy data is written into the first sub-memory bank and a second dummy data is written into the second sub-memory bank, wherein the second dummy data is the inverse of the first dummy data, and the memory controls The device reads the first data and the second fake data at the same time, and transmits the first data to the host.

According to an embodiment of the present invention, the aforementioned memory controller further includes a Hamming weight decoder. The Hamming weight decoder generates the first fake data having the first Hamming weight, and generates the second fake data that is the inverse of the first fake data, wherein the first data and the first fake data are both There is a first logic with a first bit number and a second logic with a second bit number.

The present invention further provides a writing method suitable for a memory array, wherein the memory array includes a first memory bank and a second memory bank, wherein the first memory bank includes a first sub-memory The second memory bank includes a second sub-memory bank. The writing method includes: receiving a writing command and a first data sent by a host; writing the first data to the first memory bank, and simultaneously writing a second data to the second sub A memory bank, wherein the second data is the inverse of the first data; and a first Hamming weight of the first data is written into a third memory bank of the memory array.

According to an embodiment of the present invention, the writing method further includes: generating a second Hamming weight, wherein the second Hamming weight is the inverse of the first Hamming weight; During the step of writing the first Hamming weight of the data to the third memory bank of the memory array, the second Hamming weight is written to the fourth memory bank of the memory array at the same time.

The present invention further provides a reading method suitable for a memory array, wherein the memory array includes a first memory bank storing a first data, a second memory bank, and a second memory bank storing the first data. A third memory bank with a Hamming weight, wherein the first memory bank includes a first sub-memory bank, and the second memory bank includes a second sub-memory bank. The reading method includes: receiving a reading command sent by the host to read the first data in the first memory library; reading the first Hamming weight, wherein the first Hamming weight represents The first data has a first logic with a first bit number and a second logic with a second bit number; a first fake data is generated according to the first Hamming weight, wherein the first fake data has One of the second logic of the first bit number and the first logic of the second bit number; writing the first dummy data into the second sub-memory library; and simultaneously reading the first data and the The first fake information.

According to an embodiment of the present invention, the above-mentioned reading method further includes: when reading the above-mentioned first Hamming weight, simultaneously reading one of the second Hamming weights of one of the fourth memory banks of the memory array, and The second Hamming weight is the inverse of the first Hamming weight; and after the step of simultaneously reading the first data and the first fake data, only the first data is sent to the host.

According to an embodiment of the present invention, the step of generating the first fake data based on the first Hamming weight further includes: generating a second fake data based on the first Hamming weight, wherein the second fake data has the first fake data. The first logic of one bit and the second logic of the second bit; and inverting the second fake data to generate the first fake data.

The following description is an embodiment of the present invention. Its purpose is to exemplify the general principles of the present invention and should not be regarded as a limitation of the present invention. The scope of the present invention shall be subject to the scope of the patent application.

It should be noted that the content disclosed below can provide multiple embodiments or examples for practicing the different features of the present invention. The specific component examples and arrangements described below are only used to briefly illustrate the spirit of the present invention, and are not used to limit the scope of the present invention. In addition, the following description may reuse the same component symbols or words in multiple examples. However, the purpose of repeated use is only to provide a simplified and clear description, and is not used to limit the relationship between the multiple embodiments and/or configurations discussed below. In addition, the description of one feature connected to, coupled to, and/or formed on another feature described in the following specification may actually include a plurality of different embodiments, including direct contact of these features, or other additional features. The features of are formed between these features, etc., so that these features are not in direct contact.

FIG. 1 shows a block diagram of a memory device according to an embodiment of the invention. As shown in FIG. 1, the memory device 100 includes a memory controller 110 and a memory array 120. The memory controller 110 performs a write operation or a read operation on the memory array 120 according to the operation command CMD issued by the host 10. The memory array 120 includes a first memory bank 121 and a second memory bank 122. According to an embodiment of the present invention, the memory array 120 is a static random access memory. According to many embodiments of the present invention, the host 10 is a central processing unit or other data access device. According to other embodiments of the present invention, a microcontroller includes a host 10 and a memory device 100, wherein the host 10 is a central processing unit.

According to an embodiment of the present invention, when the operation command CMD is a write command, the memory controller 110 writes the data DT sent by the host 10 into the first memory bank 121, and at the same time writes the inverted data DTB Into the second memory bank 122, the reverse data DTB is the reverse of the data DT. According to another embodiment of the present invention, when the operation command CMD is a read command, the memory controller 110 reads the data of the first memory bank 121 and the inverted data DTB of the second memory bank 122 at the same time, and Only the data DT is sent to the host 10.

According to an embodiment of the present invention, the data DT is confidential data. Since the memory controller 110 performs a write operation and/or a write operation, the number of bits of logic 0 and the number of bits of logic 1 to be written and/or read are the same, so that each write operation and And/or the power consumption during the read operation is the same, thereby improving the data security. However, in order to improve data security, half of the space in the memory array 120 needs to be used to store reversed data, so that the utilization rate of the memory array 120 is thus halved. According to an embodiment of the present invention, the memory space utilization rate of the memory device 100 is 50%. In order to improve the storage efficiency of the memory array, we need other methods to achieve data security.

FIG. 2 shows a block diagram of a writing device according to another embodiment of the present invention. As shown in FIG. 2, the memory device 200 includes a memory controller 210 and a memory array 220. The memory controller 210 performs a write operation on the memory array 220 according to a write command CMDW issued by the host 10 . According to an embodiment of the present invention, the memory array 220 is a static random access memory. According to many embodiments of the present invention, the host 10 is a central processing unit or other data access device. According to other embodiments of the present invention, a microcontroller includes a host 10 and a memory device 200, wherein the host 10 is a central processing unit.

As shown in Figure 2, the memory array 220 includes a first memory bank 221, a second memory bank 222, a third memory bank 223, and a fourth memory bank 224. The first memory bank 221 includes a first memory bank 221. A sub-memory bank 221A, and the second memory bank 222 includes a second sub-memory bank 222A.

As shown in the embodiment shown in Figure 2, when the memory controller 210 receives the write command CMDW sent by the host 10, the memory controller 210 writes the write data DW sent by the host 10 into the write command CMDW according to the write command CMDW. To one of the first memory bank 221 or the second memory bank 222, and simultaneously write the inverted write data DWB to one of the second sub-memory bank 222A and the first sub-memory bank 221A, wherein The reverse write data DWB is the reverse data of the write data DW.

In other words, when the memory controller 210 writes the write data DW into the first memory bank 221, the memory controller 210 writes the inverted write data DWB into the second sub-memory bank 222A at the same time; When the memory controller 210 writes the write data DW into the second memory bank 222, the memory controller 210 simultaneously writes the inverted write data DW into the first sub-memory bank 221A. Since the memory controller 210 simultaneously writes the write data DW and the reverse write data DWB to the memory array 220, the number of bits of the written logic 1 and the number of bits of the written logic 0 are the same, so Improve data security.

According to many embodiments of the present invention, when the memory controller 210 writes another write data (not shown in Figure 2) into the first memory bank 221/the second memory bank 222, the memory controller 210 simultaneously Invert another write data to the second sub-memory bank 222A/first sub-memory bank 221A. Therefore, compared with the memory device 100 in Fig. 1, the space of the second sub-memory bank 222A/the first sub-memory bank 221A can be reduced to the size of the inverted write data. The memory device 200 in Fig. 2 is It can increase the memory space that can be written, thereby greatly improving the space utilization of the memory array.

As shown in FIG. 2, the memory controller 210 further includes a Hamming weight encoder 211. According to an embodiment of the present invention, when the memory controller 210 receives the written data DW, the Hamming weight encoder 211 counts the number of bits of logic 1 in the written data DW to generate a hamming weight (hamming weight) HW . According to another embodiment of the present invention, when the memory controller 210 receives the written data DW, the Hamming weight encoder 211 can also be used to count the number of logic 0 bits in the written data DW to generate the Hamming weight ( hamming weight) HW.

After the Hamming weight encoder 211 generates the Hamming weight HW, the Hamming weight encoder 2111 further generates the inverted Hamming weight HWB of the Hamming weight HW. Then, the memory controller 210 simultaneously writes the Hamming weight HW and the inverted Hamming weight HWB to the third memory bank 223 and the fourth memory bank 224 to balance the number of bits of logic 1 written and The bit number of logic 0, where the reverse Hamming weight HWB is the inverse of the Hamming weight HW.

According to an embodiment of the present invention, when the memory controller 210 writes the write data DW into the first memory bank 221 and simultaneously writes the inverted write data DWB to the second sub-memory bank 222A, the memory The controller 210 further writes the Hamming weight HW to the third memory bank 223, and at the same time writes the inverted Hamming weight HWB to the fourth memory bank 224.

According to another embodiment of the present invention, when the memory controller 210 writes the write data into the second memory bank 222 and simultaneously writes the inverted write data DWB to the first sub-memory bank 221A, the memory The controller 210 also writes the Hamming weight HW to the third memory bank 223 and writes the inverted Hamming weight HWB to the fourth memory bank 224 at the same time.

位元。由於第1圖之記憶體裝置100非用以儲存寫入資料的記憶體空間係為K*N位元，第2圖之記憶體裝置200非用以儲存寫入資料的記憶體空間(即，第一子記憶體庫221A、第二子記憶體庫222A、第三記憶體庫223以及第四記憶體庫224)係為

位元。當N以及K皆遠大於1時，因此第2圖之記憶體裝置200之記憶體空間的利用率係趨近於100%，遠大於第1圖之記憶體裝置100之50%的記憶體空間利用率。According to an embodiment of the present invention, the memory spaces of the first memory bank 121 and the second memory bank 122 in FIG. 1 are K*N bits, respectively; the first memory bank 221 and the second memory bank 221 in FIG. The memory spaces of the two memory banks 222 are K*N bits respectively, the memory spaces of the first sub-memory bank 221A and the second sub-memory bank 222A are 1*N bits respectively, and the third memory bank 223 And the memory space of the fourth memory bank 224 are

Bit. Since the memory space of the memory device 100 in FIG. 1 not used to store written data is K*N bits, the memory device 200 in FIG. 2 is not used to store write data in the memory space (ie, The first sub-memory bank 221A, the second sub-memory bank 222A, the third memory bank 223, and the fourth memory bank 224) are

Bit. When N and K are both far greater than 1, the utilization rate of the memory space of the memory device 200 in Figure 2 approaches 100%, which is much larger than the 50% memory space of the memory device 100 in Figure 1 Utilization rate.

FIG. 3 shows a flowchart of the writing method according to an embodiment of the invention. The following description of the flowchart of the writing method 300 shown in FIG. 3 will be combined with the block diagram of FIG. 2 for detailed description.

First, the memory controller 210 is used to receive the write command CMDW and the first data (ie, the write data DW) sent by the host 10 (step S31). Then, according to an embodiment of the present invention, the memory controller 210 is used to write the first data (ie, the write data DW) into the first memory bank 221 (step S32), and at the same time, the second data ( That is, the inverted write data DWB) is written to the second sub-bank 222A (step S33). According to another embodiment of the present invention, the memory controller 210 is used to write the first data (that is, the write data DW) into the second memory bank 222 (step S32), and at the same time, the second data (that is, , The inverted write data DWB) is written to the first sub-memory bank 221A (step S33).

According to an embodiment of the present invention, simultaneously writing the first data (ie, the write data DW) and the second data (ie, the inverted write data DWB) is used to balance the written logic 1 and logic 0 bits Yuan number.

Subsequently, the Hamming weight encoder 211 of the memory controller 210 is used to count the number of bits of the first logic in the first data (ie, the written data DW) (step S34), and the memory controller 210 is used to, According to the number of bits in the first logic, a first Hamming weight (ie, Hamming weight HW) and a second Hamming weight (ie, inverted Hamming weight HWB) are generated (step S35). According to an embodiment of the present invention, the memory controller 210 generates a first Hamming weight (ie, Hamming weight HW) according to the number of bits in the first logic, and then inverts the first Hamming weight to generate a second Hamming weight. Hamming weight (ie, inverted Hamming weight HWB). According to an embodiment of the present invention, the first logic may be logic 1. According to another embodiment of the present invention, the first logic may be logic 0.

Next, the memory controller 210 is used to write the first Hamming weight (ie, the Hamming weight HW) to the third memory bank 223 of the memory array 220 (step S36), and at the same time, the second Hamming weight (Ie, the inverted Hamming weight HWB) is written into the fourth memory bank 224 of the memory array 220 (step S37), where the second Hamming weight is the inverse of the first Hamming weight.

FIG. 4 shows a flowchart of a writing method according to another embodiment of the present invention. As shown in Fig. 4, steps S31 to S37 are the same as steps S31 to S37 in Fig. 3, in which step S34 in Fig. 4 (ie, counting the first data (ie, writing data DW) is the first The number of bits in a logic) and step S35 (ie, using the memory controller 210 to generate the first Hamming weight (ie, the Hamming weight HW) based on the number of bits in the first logic) are the same as step S32 and step S33 is executed in parallel to improve the writing speed.

FIG. 5 shows a block diagram of a memory device according to another embodiment of the invention. As shown in FIG. 5, the memory device 500 includes a memory controller 510 and a memory array 520. The memory controller 510 performs a read operation on the memory array 520 according to the read command CMDR issued by the host 10 . The memory array 520 corresponds to the memory array 220 in FIG. 2 and includes a first memory bank 521, a second memory bank 522, a third memory bank 523, and a fourth memory bank 524, and the first memory bank The bank 521 includes a first sub-memory bank 521A, and the second memory bank 522 includes a second sub-memory bank 522A.

As in the embodiment shown in FIG. 5, when the memory controller 510 reads the read data DR stored in the first memory bank 521 according to the read command CMDR, the memory controller 510 reads the read data DR stored in the first memory bank 521 Three memory banks 523 correspond to the Hamming weight HW of the read data DR, and at the same time read the inverted Hamming weight HWB stored in the fourth memory bank 524, where the inverted Hamming weight HWB is the Hamming weight The reverse of HW.

After the memory controller 510 generates the fake data FD with the Hamming weight HW, the memory controller 510 writes the fake data FD into the first sub-memory bank 521A, and at the same time reverses the reverse of the fake data FD The fake data FDB is written into the second sub-memory bank 522A. Then, the memory controller 510 simultaneously reads the read data DR of the first memory bank 521 and the inverted dummy data FDB of the second sub-memory bank 522A.

According to another embodiment of the present invention, when the memory controller 510 reads the read data DR (not shown in Figure 5) stored in the second memory bank 522 according to the read command CMDR, the memory controls The device 510 reads the Hamming weight HW stored in the third memory bank 523 and corresponding to the read data DR, and reads the inverted Hamming weight HWB stored in the fourth memory bank 524 at the same time. After the memory controller 510 generates the fake data FD with the Hamming weight HW, the memory controller 510 writes the fake data FD into the second sub-memory bank 522A, and at the same time reverses the reverse of the fake data FD The fake data FDB is written into the first sub-memory bank 521A. Then, the memory controller 510 simultaneously reads the read data DR of the second memory bank 522 and the inverted dummy data FDB of the first sub-memory bank 521A.

According to an embodiment of the present invention, since the Hamming weight HW and the inverted Hamming weight HWB are inverse to each other, reading the Hamming weight HW and the inverted Hamming weight HWB at the same time helps to balance the logic 1 of the reading. The number of bits and the number of bits of logic 0 read to facilitate data security. According to an embodiment of the present invention, since the read data DR and the fake data FD have the same Hamming weight HW, the memory controller 510 simultaneously reads the read data DB and the reverse fake data FDB for balanced reading The number of bits of logic 1 and the number of bits of logic 0 are used to improve data security.

According to many embodiments of the present invention, when the memory controller 510 reads another read data from the first memory bank 521/the second memory bank 522 (not shown in Figure 5), the memory controller 510 corresponds to Another read data generates another inverted dummy data to be written to the second sub-memory bank 522A/first sub-memory bank 521A. Therefore, the space of the second sub-memory bank 522A/first sub-memory bank 521A only needs to reverse the size of the dummy data. Compared with the memory device 100 in FIG. 1, the memory device 500 in FIG. 5 can increase the readable storage space, thereby greatly improving the space utilization of the memory array.

According to an embodiment of the present invention, the memory controller 510 includes a Hamming weight decoder 511, wherein the Hamming weight decoder 511 is used to generate a fake data FD with a Hamming weight HW according to the Hamming weight HW, and to combine the fake data FD with the Hamming weight HW. The data FD is inverted to generate inverted fake data FDB. According to some embodiments of the present invention, since the read data DR and the fake data FD both have a Hamming weight HW, it means that the read data DR and the fake data FD have the same bit number of logic 1 or the same bit number of logic 0. According to some embodiments of the present invention, although both the read data DR and the fake data FD have a Hamming weight HW, the read data DR may be exactly the same as or different from the fake data FD.

位元。由於第1圖之記憶體裝置100非用以儲存讀取資料的記憶體空間係為K*N位元，第5圖之記憶體裝置500非用以儲存讀取資料的記憶體空間(即，第一子記憶體庫521A、第二子記憶體庫522A、第三記憶體庫523以及第四記憶體庫524)係為

位元。當N以及K皆遠大於1時，因此第5圖之記憶體裝置500之記憶體空間的利用率係趨近於100%，大於第1圖之記憶體裝置100之50%的記憶體空間利用率。According to an embodiment of the present invention, the memory spaces of the first memory bank 121 and the second memory bank 122 in FIG. 1 are K*N bits, respectively; the first memory bank 521 and the second memory bank in FIG. 5 The memory space of the second memory bank 522 is K*N bits, the memory space of the first sub-memory bank 521A and the second sub-memory bank 522A are 1*N bits respectively, and the third memory bank 523 And the memory space of the fourth memory bank 524 are

Bit. Since the memory space of the memory device 100 in FIG. 1 not used to store read data is K*N bits, the memory device 500 in FIG. 5 is not the memory space used to store read data (ie, The first sub-memory bank 521A, the second sub-memory bank 522A, the third memory bank 523, and the fourth memory bank 524) are

Bit. When N and K are both far greater than 1, the utilization rate of the memory space of the memory device 500 in Figure 5 approaches 100%, which is greater than the 50% memory space utilization of the memory device 100 in Figure 1 rate.

Fig. 6 shows a flowchart of the reading method according to an embodiment of the present invention. The following description of the flowchart of the writing method 600 shown in FIG. 6 will be combined with the block diagram of FIG. 5 for detailed description.

First, the memory controller 510 is used to receive the read command CMDR sent by the host 10 (step S61) to read the first data of the first memory bank 521 of the memory array 520 (ie, read the data DR). Next, the memory controller 510 is used to read the first Hamming weight (ie, Hamming weight HW) of the third memory bank 523 (step S62), where the first Hamming weight (ie, Hamming weight HW) It means that the first data (ie, the read data DR) has the first logic of the first bit number and the second logic of the second bit number. According to an embodiment of the present invention, the first logic system is logic 1, and the second logic system is logic 0. According to another embodiment of the present invention, the first logic system is logic 0, and the second logic system is logic 1.

When the first Hamming weight is read (step S62), the memory controller 510 is used to read the second Hamming weight of the fourth memory bank 524 of the memory array 520 (ie, the inverted Hamming weight HWB). ) (Step S63). According to an embodiment of the present invention, the first Hamming weight (ie, Hamming weight HW) and the second Hamming weight (ie, inverted Hamming weight HWB) are read at the same time, so that the bit of logic 1 is read The number of bits and the number of bits of logic 0 are equal, thereby increasing data security.

After step S62, the Hamming weight decoder 511 is used to generate the first fake data (that is, the inverted fake data FDB) and the second fake data (that is, the fake data) according to the first Hamming weight (ie, the Hamming weight HW). Data FD) (step S64), wherein the first dummy data (ie, the inverted dummy data FDB) has the first logic of the second bit number and the second logic of the first bit number, and the second dummy data (ie, The dummy data FD) has a first logic with a first bit number and a second logic with a second bit number. In other words, the first data (that is, the read data DR) and the second dummy data (that is, the dummy data FD) have the same number of bits of logic 1 and/or the same number of bits of logic 0, and the first false The data system and the second fake data are opposite to each other.

According to an embodiment of the present invention, the Hamming weight decoder 511 generates the second fake data (ie, the fake data FD) with the first Hamming weight (ie, the Hamming weight HW), and combines the second fake data ( That is, the fake data FD) is inverted to generate the first fake data (ie, the inverted fake data FDB).

Next, the memory controller 510 is used to write the first dummy data (that is, the inverted dummy data FDB) into the second sub-memory bank 522A (step S65), and at the same time, the second dummy data (that is, the dummy data FD) Write to the first sub-memory bank 521A (step S66). According to an embodiment of the present invention, since the first fake data (ie, inverted fake data FDB) has the first logic of the second bit number and the second logic of the first bit number, the second fake data (ie, Fake data FD) has the first logic of the first bit number and the second logic of the second bit number. Performing step S65 and step S66 at the same time means writing the first bit number plus the second bit number at the same time The first logic and the second logic, thereby enhancing the security of the data.

Subsequently, the memory controller 510 is used to simultaneously read the first data (ie, read data DR) and the first dummy data (ie, inverted fake data FDB) (step S67) to balance the read logic 1 and logic The number of bits of 0. Finally, the memory controller 510 is used to transmit only the first data (ie, the read data DR) to the host 10 (step S68), and the reading method 600 is completed.

According to another embodiment of the present invention, when the read command CMDW received in step S61 is used to read the first data of the second memory bank 522 of the memory array 520 (ie, read the data DR), Step S62 also reads the first Hamming weight of the third memory bank 5232 (ie, Hamming weight HW), and reads the second Hamming weight of the fourth memory bank 524 of the memory array 520 (ie, reverse Phase Hamming weight (HWB) (step S63). Next, in step S65, the memory controller 510 is used to write the first dummy data (that is, the reversed dummy data FDB) into the first sub-memory bank 521A, and in step S66, the second dummy data (that is, The dummy data FD) is written into the second sub-memory bank 522A.

Although the embodiments of the present disclosure and their advantages have been disclosed as above, it should be understood that anyone with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the manufacturing processes, machines, manufacturing, material composition, devices, methods, and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can implement some implementations from this disclosure. The disclosed content of the examples understands the current or future developed processes, machines, manufacturing, material composition, devices, methods, and steps, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. The present disclosure uses some embodiments. Therefore, the protection scope of the present disclosure includes the above-mentioned manufacturing processes, machines, manufacturing, material composition, devices, methods, and steps. In addition, each patent application scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes each patent application scope and a combination of embodiments.

10: host 100, 200, 500: memory device 110, 210, 510: memory controller 120, 220, 520: memory array 121, 221, 521: the first memory bank 122, 222, 522: second memory bank 211: Hamming weight encoder 223, 523: third memory bank 224, 524: fourth memory bank 221A, 521A: the first sub-memory bank 222A, 522A: the second sub-memory bank DT: Information DTB: Reversed data CMD: Operation instruction CMDW: write command CMDR: Read command DW: write data DR: Read data DWB: Write data in reverse phase HW: Hamming weight HWB: Inverted Hamming Weight FD: Fake data FDB: reverse fake data S31～S37, S61～S68: step flow

Figure 1 shows a block diagram of a memory device according to an embodiment of the present invention; Figure 2 shows a block diagram of a writing device according to another embodiment of the present invention; Figure 3 is a flow chart showing the writing method according to an embodiment of the present invention; FIG. 4 shows a flowchart of a writing method according to another embodiment of the present invention; Figure 5 shows a block diagram of a memory device according to another embodiment of the present invention; and Fig. 6 shows a flowchart of the reading method according to an embodiment of the present invention.

10: host

200: Memory device

210: Memory Controller

220: memory array

221: first memory bank

222: second memory bank

211: Hamming weight encoder

223: third memory bank

224: The fourth memory bank

221A: The first sub-memory bank

222A: The second sub-memory bank

CMDW: write command

DW: write data

DWB: Write data in reverse phase

HW: Hamming weight

HWB: Inverted Hamming Weight

Claims (10)

A memory device includes: A memory array, including: A first memory bank, including a first sub-memory bank; A second memory bank, including a second sub-memory bank; and A third memory bank; and A memory controller, according to a write command sent by a host, simultaneously writes a first data sent from the host to the first memory bank and writes the second data to the second sub-memory at the same time And write the first Hamming weight of one of the first data into the third database, wherein the second data is the inverse of the first data. The memory device described in the first item of the scope of patent application, wherein the above-mentioned memory array further includes: A fourth memory bank for storing a second Hamming weight, wherein the second Hamming weight is the inverse of the first Hamming weight, and the memory controller simultaneously stores the first Hamming weight Write the third memory bank and write the second Hamming weight into the fourth memory bank. The memory device described in item 2 of the scope of patent application, wherein the memory controller further includes: A Hamming weight encoder for counting that the first data has a first logic with a first bit number, and generating the first Hamming weight according to the first bit number, and generating the first Hamming The above-mentioned second Hamming weight is the inverse of the weight. The memory device described in item 2 of the scope of patent application, wherein when the memory controller receives a read command sent by the host to read the first data in the first memory bank, the memory The controller reads the first Hamming weight of the third memory bank and the second Hamming weight of the fourth memory bank at the same time, wherein the memory controller generates a first Hamming weight based on the first Hamming weight. Fake data, write the first dummy data into the first sub-memory bank and write a second dummy data into the second sub-memory bank, wherein the second dummy data is the inverse of the first dummy data Phase, wherein the memory controller reads the first data and the second dummy data at the same time, and transmits the first data to the host. The memory device described in item 4 of the scope of patent application, wherein the above-mentioned memory controller further includes: A Hamming weight decoder that generates the first fake data having the first Hamming weight, and generates the second fake data that is the inverse of the first fake data, wherein the first data and the first fake data Each has a first logic with a first bit number and a second logic with a second bit number. A writing method is suitable for a memory array, wherein the memory array includes a first memory bank and a second memory bank, wherein the first memory bank includes a first sub-memory bank, and the The second memory bank includes a second sub-memory bank, and the above-mentioned writing method includes: Receiving a write command and a first data sent by a host; Writing the first data to the first memory bank, and at the same time writing a second data to the second sub-memory bank, wherein the second data is the inverse of the first data; and The first Hamming weight of one of the first data is written into a third memory bank of the memory array. The writing method described in item 6 of the scope of patent application includes: Generating a second Hamming weight, wherein the second Hamming weight is the inverse of the first Hamming weight; and When the step of writing the first Hamming weight of the first data to the third memory bank of the memory array is performed, the second Hamming weight is written to the memory array of the memory array at the same time. The fourth memory bank. A reading method suitable for a memory array, wherein the memory array includes a first memory bank that stores a first data, a second memory bank, and a first Hamming weight that stores the first data A third memory bank, wherein the first memory bank includes a first sub-memory bank, the second memory bank includes a second sub-memory bank, and the reading method includes: Receiving a read command sent by the host to read the first data in the first memory bank; Read the first Hamming weight, where the first Hamming weight represents that the first data has a first logic of a first digit and a second logic of a second digit; Generating a first fake data according to the first Hamming weight, wherein the first fake data has a second logic of the first bit number and a first logic of the second bit number; Write the first dummy data into the second sub-memory bank; and Read the above-mentioned first data and the above-mentioned first fake data at the same time. The reading method described in item 8 of the scope of patent application includes: When the first Hamming weight is read, the second Hamming weight of one of the fourth memory banks in the memory array is read at the same time, wherein the second Hamming weight is the opposite of the first Hamming weight. Phase; and After the step of simultaneously reading the first data and the first fake data, only the first data is sent to the host. The reading method described in item 8 of the scope of patent application, wherein the step of generating the first fake data according to the first Hamming weight further includes: Generating a second fake data according to the first Hamming weight, wherein the second fake data has the first logic of the first bit number and the second logic of the second bit number; and The above-mentioned second fake data is inverted to generate the above-mentioned first fake data.

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