TW202108815A - Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film - Google Patents

Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film Download PDF

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TW202108815A
TW202108815A TW109127904A TW109127904A TW202108815A TW 202108815 A TW202108815 A TW 202108815A TW 109127904 A TW109127904 A TW 109127904A TW 109127904 A TW109127904 A TW 109127904A TW 202108815 A TW202108815 A TW 202108815A
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nitride film
molybdenum nitride
molybdenum
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substrate
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艾瑞克 克里斯多福 史帝芬斯
布尚 洛波
香卡 斯瓦米那森
查理斯 德茲拉
謝琦
吉賽佩 亞雷西歐 維爾尼
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荷蘭商Asm Ip私人控股有限公司
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Abstract

Methods for depositing a molybdenum nitride film on a surface of a substrate are disclosed. The methods may include: providing a substrate into a reaction chamber; and depositing a molybdenum nitride film directly on the surface of the substrate by performing one or more unit deposition cycles of cyclical deposition process, wherein a unit deposition cycle may include, contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, and contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor. Semiconductor device structures including a molybdenum nitride film are also disclosed.

Description

用於藉由循環沉積製程將氮化鉬膜沉積於基板表面上之方法及包括氮化鉬膜之相關半導體裝置結構Method for depositing molybdenum nitride film on substrate surface by cyclic deposition process and related semiconductor device structure including molybdenum nitride film

[[ 相關申請案之交叉參考Cross reference of related applications ]]

本申請案主張於2019年8月23日申請且標題為「用於藉由循環沉積製程將氮化鉬膜沉積於基板表面上之方法及包括氮化鉬膜之相關半導體裝置結構(METHODS FOR DEPOSITING A MOLYBDENUM NITRIDE FILM ON A SURFACE OF A SUBSTRATE BY A CYCLICAL DEPOSITION PROCESS AND RELATED SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A MOLYBDENUM NITRIDE FILM)」之美國臨時專利申請案第62/891,254號之優先權,該申請案特此以引用之方式併入本文中。本申請案係關於2019年8月23日申請的標題為「用於在基板表面上形成多晶鉬膜之方法及包括多晶鉬膜之相關結構(METHODS FOR FORMING A POLYCRYSTALLINE MOLYBDENUM FILM OVER A SURFACE OF A SUBSTRATE AND RELATED STRUCTURES INCLUDING A POLYCRYSTALLINE MOLYBDENUM FILM)」之美國臨時專利申請案第62/891,247號,該申請案之全部內容以引用之方式併入本文中。This application claims to be filed on August 23, 2019 and is titled ``Methods for depositing molybdenum nitride films on the surface of substrates by a cyclic deposition process and related semiconductor device structures including molybdenum nitride films (METHODS FOR DEPOSITING) A MOLYBDENUM NITRIDE FILM ON A SURFACE OF A SUBSTRATE BY A CYCLICAL DEPOSITION PROCESS AND RELATED SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A MOLYBDENUM NITRIDE FILM), which is hereby incorporated by reference Incorporated into this article. This application is related to the application on August 23, 2019, titled ``Methods for forming polycrystalline molybdenum films on the surface of substrates and related structures including polycrystalline molybdenum films (METHODS FOR FORMING A POLYCRYSTALLINE MOLYBDENUM FILM OVER A SURFACE OF A SUBSTRATE AND RELATED STRUCTURES INCLUDING A POLYCRYSTALLINE MOLYBDENUM FILM)" US Provisional Patent Application No. 62/891,247, the entire content of which is incorporated herein by reference.

本發明大體上係關於用於將氮化鉬膜沉積於基板表面上之方法及用於藉由循環沉積製程沉積氮化鉬膜之特定方法。本發明大體上亦係關於包括氮化鉬膜之半導體裝置結構。The present invention generally relates to a method for depositing a molybdenum nitride film on the surface of a substrate and a specific method for depositing a molybdenum nitride film by a cyclic deposition process. The present invention also generally relates to a semiconductor device structure including a molybdenum nitride film.

互補金屬氧化物半導體(complementary metal-oxide-semiconductor;CMOS)技術習知地利用n型及p型多晶矽作為閘電極材料。然而,摻雜多晶矽可能並非用於先進技術節點之理想閘電極材料。舉例而言,儘管摻雜多晶矽為導電的,但仍可能存在可在偏壓下耗乏載流子之表面區域。此耗乏區可呈現為額外閘極絕緣體厚度,通常稱作閘極耗乏,且可增加等效氧化物厚度。儘管閘極耗乏區可能極薄,呈約數埃(Å),但在閘極氧化物厚度在先進技術節點中減小時,其可能變得顯著。另外,對於NMOS及PMOS裝置兩者而言,多晶矽並未展現理想的有效功函數(effective work function, eWF)。為克服摻雜多晶矽之非理想有效功函數,可利用臨限電壓調整植入。然而,隨著裝置幾何形狀在先進技術節點中減小,臨限電壓調整植入過程可能變得愈來愈複雜。Complementary metal-oxide-semiconductor (CMOS) technology conventionally uses n-type and p-type polysilicon as gate electrode materials. However, doped polysilicon may not be an ideal gate electrode material for advanced technology nodes. For example, although doped polysilicon is conductive, there may still be surface areas that can be depleted of carriers under bias. This depletion region can appear as an additional gate insulator thickness, commonly referred to as gate depletion, and can increase the equivalent oxide thickness. Although the gate depletion region may be extremely thin, on the order of a few angstroms (Å), it may become significant when the gate oxide thickness is reduced in advanced technology nodes. In addition, for both NMOS and PMOS devices, polysilicon does not exhibit an ideal effective work function (eWF). In order to overcome the non-ideal effective work function of doped polysilicon, a threshold voltage can be used to adjust the implantation. However, as device geometries decrease in advanced technology nodes, the threshold voltage adjustment implantation process may become more and more complicated.

為克服與摻雜多晶矽閘電極相關聯之問題,非理想摻雜多晶矽閘極材料可用替代材料替換,諸如金屬、金屬氮化物及金屬碳化物。舉例而言,金屬氮化物膜之特性可用以為NMOS及PMOS裝置兩者提供更理想的有效功函數,其中閘電極之有效功函數,亦即提取電子所需之能量,可與半導體材料之障高相容。舉例而言,在PMOS裝置之情況下,有效功函數為約5.0-5.2 eV,且在NMOS裝置之情況下,有效功函數為約4.1-4.3 eV。To overcome the problems associated with doped polysilicon gate electrodes, non-ideal doped polysilicon gate materials can be replaced with alternative materials, such as metals, metal nitrides, and metal carbides. For example, the characteristics of the metal nitride film can be used to provide a more ideal effective work function for both NMOS and PMOS devices. The effective work function of the gate electrode, that is, the energy required to extract electrons, can be compatible with the barrier height of semiconductor materials . For example, in the case of a PMOS device, the effective work function is about 5.0-5.2 eV, and in the case of an NMOS device, the effective work function is about 4.1-4.3 eV.

因此,需要用於形成具有較佳有效功函數之NMOS裝置及PMOS裝置兩者之低電阻率閘電極的方法。Therefore, there is a need for a method for forming low-resistivity gate electrodes for both NMOS devices and PMOS devices with better effective work functions.

提供本發明內容來以簡化形式介紹一系列概念。此等概念在以下揭示內容之例示性具體例之詳細描述中加以進一步詳述。本發明內容並不意欲鑑別所主張之主題的關鍵特徵或基本特徵,亦不意欲用以限制所主張之主題的範疇。The summary of the present invention is provided to introduce a series of concepts in a simplified form. These concepts are further detailed in the detailed description of illustrative specific examples of the following disclosure. This summary is not intended to identify the key features or basic features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

在一些具體例中,提供用於藉由循環沉積製程將氮化鉬膜沉積於基板表面上之方法。方法可包含:將基板提供至反應室中;且藉由執行循環沉積製程之一或多個單元沉積循環而將氮化鉬膜直接沉積於基板表面上,其中單元沉積循環包含:使基板與包含鹵化鉬前驅物之第一氣相反應物接觸;且使基板與包含氮前驅物之第二氣相反應物接觸。In some embodiments, a method for depositing a molybdenum nitride film on the surface of a substrate by a cyclic deposition process is provided. The method may include: providing the substrate into the reaction chamber; and directly depositing the molybdenum nitride film on the surface of the substrate by performing one or more unit deposition cycles of the cyclic deposition process, wherein the unit deposition cycle includes: The first gas phase reactant of the molybdenum halide precursor is contacted; and the substrate is contacted with the second gas phase reactant containing the nitrogen precursor.

在本發明之一些具體例中,提供包括氮化鉬膜之半導體裝置結構。本發明之半導體裝置結構可包含:半導體通道區;及直接安置於半導體通道區上之閘極堆疊結構,其中閘極堆疊結構包含:直接安置於半導體通道區上之閘極介電質;及直接安置於閘極介電質上之氮化鉬膜。In some embodiments of the present invention, a semiconductor device structure including a molybdenum nitride film is provided. The semiconductor device structure of the present invention may include: a semiconductor channel region; and a gate stack structure directly disposed on the semiconductor channel region, wherein the gate stack structure includes: a gate dielectric directly disposed on the semiconductor channel region; and directly Molybdenum nitride film placed on the gate dielectric.

出於概述本發明及所達成之優於先前技術之優點的目的,已在上文中描述本發明之某些目標及優點。當然,應理解,可無須根據本發明之任何特定具體例來達成所有此類目標或優點。因此,舉例而言,熟悉本技藝者應認識到,本發明可以如本文所教示或建議達成或最佳化一個優點或一組優點而無須達成如本文可能教示或建議之其他目標或優點的方式實施或執行。For the purpose of summarizing the present invention and the advantages achieved over the prior art, certain objectives and advantages of the present invention have been described above. Of course, it should be understood that all such goals or advantages may not be achieved according to any specific embodiment of the present invention. Therefore, for example, those familiar with the art should realize that the present invention can achieve or optimize an advantage or a set of advantages as taught or suggested herein without the need to achieve other goals or advantages as might be taught or suggested herein. Implement or execute.

所有此等具體例皆意欲在本文所揭示之本發明之範疇內。此等及其他具體例將自以下參見附圖的某些具體例之詳細描述而對熟悉本技藝者變得顯而易見,但本發明並不受限於所揭示之任何一或多個特定具體例。All these specific examples are intended to be within the scope of the invention disclosed herein. These and other specific examples will become apparent to those familiar with the art from the detailed description of some specific examples below with reference to the accompanying drawings, but the present invention is not limited to any one or more specific examples disclosed.

儘管在下文中揭示某些具體例及實施例,但熟悉本技藝者將理解,本發明延伸超出本發明所具體揭示之具體例及/或用途以及其明顯修改及等效物。因此,希望所揭示之本發明之範疇不應受下文所描述之特定揭示之具體例限制。Although some specific examples and embodiments are disclosed below, those skilled in the art will understand that the present invention extends beyond the specific examples and/or uses specifically disclosed in the present invention, as well as obvious modifications and equivalents thereof. Therefore, it is hoped that the scope of the present invention disclosed should not be limited by the specific examples of the specific disclosure described below.

本文所呈現之圖示並不意欲為任何特定材料、結構或裝置之實際視圖,而僅為用於描述本發明之具體例的理想化表示。The illustrations presented herein are not intended to be actual views of any specific materials, structures or devices, but are merely idealized representations for describing specific examples of the present invention.

如本文所用,術語「基板」可指任何底層材料或可使用其或在其上可形成裝置、電路或膜之材料。As used herein, the term "substrate" can refer to any underlying material or material on which a device, circuit, or film can be formed or used.

如本文所用,術語「循環沉積(cyclical deposition)」可指將兩種或更多種前驅物(反應物)依序引入反應室中以在基板上方沉積膜且包括諸如原子層沉積(atomic layer deposition, ALD)及循環化學氣相沉積(cyclical chemical vapor deposition, 循環CVD)之沉積技術。As used herein, the term "cyclical deposition" may refer to the sequential introduction of two or more precursors (reactants) into the reaction chamber to deposit a film on the substrate and includes such as atomic layer deposition (atomic layer deposition). , ALD) and cyclic chemical vapor deposition (cyclical chemical vapor deposition, cyclic CVD) deposition technology.

如本文所用,術語「循環化學氣相沉積(cyclical chemical vapor deposition)」可指任何製程,其中基板依序暴露於兩種或更多種揮發性前驅物,該等前驅物在基板上反應及/或分解以沉積膜。As used herein, the term "cyclical chemical vapor deposition" can refer to any process in which a substrate is sequentially exposed to two or more volatile precursors, which react on the substrate and/ Or decompose to deposit the film.

如本文所用,術語「原子層沉積」(ALD)可指氣相沉積製程,其中在反應室中進行沉積循環,較佳複數個連續沉積循環。通常,在各單元沉積循環期間,將前驅物化學吸附於沉積表面(例如,基板表面或先前沉積之底層表面,諸如來自先前ALD循環之材料),形成不容易與額外前驅物反應(亦即,自限反應(self-limiting reaction))之單層或次單層。其後,若需要,可隨後將反應物(例如,另一前驅物或反應氣體)引入反應室中以用於將化學吸附之前驅物轉化為沉積表面上之所需材料。通常,此反應物能夠進一步與前驅物反應。此外,在各單元沉積循環期間,亦可利用吹掃步驟,以在化學吸附之前驅物轉化之後,自反應室移除過量前驅物及/或自反應室移除過量反應物及/或反應副產物。此外,當用一或多種前驅物組成物、反應氣體及吹掃氣體(例如,惰性運載氣體)之交替脈衝執行時,如本文所用之術語「原子層沉積」亦意謂包括由相關術語所表示之製程,諸如「化學氣相原子層沉積」、「原子層磊晶(atomic layer epitaxy;ALE)」、分子束磊晶(molecular beam epitaxy;MBE)、氣體源MBE、有機金屬MBE及化學束磊晶。As used herein, the term "atomic layer deposition" (ALD) may refer to a vapor deposition process in which a deposition cycle is performed in a reaction chamber, preferably a plurality of continuous deposition cycles. Generally, during the deposition cycle of each unit, the precursor is chemically adsorbed on the deposition surface (for example, the substrate surface or the previously deposited underlying surface, such as the material from the previous ALD cycle), and the formation is not easy to react with the additional precursor (that is, Self-limiting reaction (self-limiting reaction)) monolayer or sub-monolayer. Thereafter, if necessary, a reactant (for example, another precursor or reaction gas) can be subsequently introduced into the reaction chamber for conversion of the chemically adsorbed precursor to the desired material on the deposition surface. Generally, this reactant can further react with the precursor. In addition, during the deposition cycle of each unit, a purge step can also be used to remove excess precursors from the reaction chamber and/or remove excess reactants and/or reaction side effects from the reaction chamber after the chemical adsorption precursors are converted. product. In addition, when performed with alternating pulses of one or more precursor components, reactive gas, and purge gas (for example, inert carrier gas), the term "atomic layer deposition" as used herein also means to include those represented by related terms Processes such as "chemical vapor atomic layer deposition", "atomic layer epitaxy (ALE)", molecular beam epitaxy (MBE), gas source MBE, organic metal MBE, and chemical beam epitaxy crystal.

如本文所用,術語「膜」可指藉由本文所揭示之方法形成之任何物理上連續或物理上不連續的結構及材料。舉例而言,「膜」可包括2D材料、奈米層合物、奈米棒、奈米管、奈米粒子、或甚至部分或全部分子層、或部分或全部原子層或原子及/或分子之群集。「膜」可包含具有針孔但仍至少部分地物理上連續的材料或層。As used herein, the term "film" can refer to any physically continuous or physically discontinuous structure and material formed by the methods disclosed herein. For example, "film" may include 2D materials, nano laminates, nano rods, nano tubes, nanoparticles, or even part or all of molecular layers, or part or all of atomic layers or atoms and/or molecules Of clusters. A "film" can include a material or layer that has pinholes but is still at least partially physically continuous.

如本文所用,術語「氮化鉬膜」可指包含至少鉬組分及氮組分之膜。As used herein, the term "molybdenum nitride film" may refer to a film including at least a molybdenum component and a nitrogen component.

如本文所用,術語「鹵化鉬前驅物」可指包含至少鉬組分及鹵化物組分之反應物,其中該鹵化物組分可包括氯組分、碘組分或溴組分中之一或多者。As used herein, the term "molybdenum halide precursor" may refer to a reactant comprising at least a molybdenum component and a halide component, wherein the halide component may include one of a chlorine component, an iodine component, or a bromine component or More.

如本文所用,術語「硫化鉬鹵化物」可指包含至少鉬組分、鹵化物組分及硫族元素組分之反應物,其中硫族元素為元素週期表之第IV族之元素,包括氧(O)、硫(S)、硒(Se)及碲(Te)。As used herein, the term "molybdenum sulfide halide" may refer to a reactant containing at least a molybdenum component, a halide component, and a chalcogen component, where the chalcogen element is an element of group IV of the periodic table, including oxygen (O), sulfur (S), selenium (Se) and tellurium (Te).

如本文所用,術語「鹵氧化鉬」可指至少包含鉬組分、氧組分及鹵化物組分之反應物。As used herein, the term "molybdenum oxyhalide" may refer to a reactant containing at least a molybdenum component, an oxygen component, and a halide component.

如本文所用,術語「還原劑」可指在氧化還原化學反應中將電子供給另一物種之反應物。As used herein, the term "reducing agent" can refer to a reactant that donates electrons to another species in a redox chemical reaction.

如本文所用,術語「結晶膜」可指顯示至少短程有序或甚至長程有序之結晶結構的膜,且包括單晶膜以及多晶膜。As used herein, the term "crystalline film" may refer to a film showing a crystalline structure of at least short-range order or even long-range order, and includes single crystal films and polycrystalline films.

如本文所使用,術語「非晶形膜」可指實質上不顯示如在結晶膜中觀測到之有序結晶結構的膜。As used herein, the term "amorphous film" may refer to a film that does not substantially show an ordered crystalline structure as observed in a crystalline film.

如本文所用,術語「氣體」可指蒸氣或汽化固體及/或汽化液體,且可由單一氣體或氣體混合物構成。As used herein, the term "gas" may refer to vapor or vaporized solid and/or vaporized liquid, and may be composed of a single gas or a mixture of gases.

本發明之具體例包括可用以沉積氮化鉬膜之方法及包括根據本發明之具體例沉積之氮化鉬膜的相關半導體裝置結構。在本發明之一些具體例中,舉例而言,氮化鉬膜可形成閘極堆疊之一部分,諸如電晶體裝置結構之閘電極之至少一部分。基於氮化鉬膜之閘電極可為PMOS及NMOS裝置兩者提供具有較佳有效功函數之閘極堆疊。Specific examples of the present invention include methods that can be used to deposit molybdenum nitride films and related semiconductor device structures including molybdenum nitride films deposited according to specific examples of the present invention. In some embodiments of the present invention, for example, the molybdenum nitride film may form a part of the gate stack, such as at least a part of the gate electrode of the transistor device structure. Molybdenum nitride film-based gate electrodes can provide gate stacks with better effective work functions for both PMOS and NMOS devices.

用於形成閘電極之現有功函數金屬可歸因於其不合適的有效功函數值而具有侷限性。舉例而言,已知材料之有效功函數可隨其厚度而變化。因此,隨著裝置幾何形狀在先進技術節點中減小,對應裝置膜(諸如閘電極之功函數金屬)的厚度亦可隨著總體閘極堆疊之有效功函數之值的關聯改變而減小厚度。閘極堆疊之有效功函數之此類改變可產生對於NMOS及PMOS裝置結構兩者非理想的有效功函數。Existing work function metals used to form gate electrodes have limitations due to their improper effective work function values. For example, the effective work function of a known material can vary with its thickness. Therefore, as the device geometry is reduced in advanced technology nodes, the thickness of the corresponding device film (such as the work function metal of the gate electrode) can also be reduced as the value of the effective work function of the overall gate stack changes. . Such changes in the effective work function of the gate stack can produce effective work functions that are not ideal for both NMOS and PMOS device structures.

在本發明之一些具體例中,所沉積之氮化鉬膜之電阻率可為改良半導體裝置效率之重要參數,諸如在其中氮化鉬膜可用作閘電極、襯料(例如,在記憶體應用中)、障壁層材料、罩蓋材料(capping material)或接觸層之一部分的應用中。如上文所論述,下一代技術節點可能需要不斷減小的膜厚度。然而,隨著導電膜之膜厚度減小,導電膜之電阻率可能增加,從而導致相關聯半導體裝置結構中之效率出現損耗。作為一非限制性實施例,本發明之氮化鉬膜可用作半導體裝置結構中當前採用之常見氮化鈦膜的替代物。因此,與在可比厚度之氮化鈦膜中通常達成之電阻率相比,本發明之氮化鉬膜可具有較低電阻率。In some specific examples of the present invention, the resistivity of the deposited molybdenum nitride film can be an important parameter for improving the efficiency of semiconductor devices, such as where the molybdenum nitride film can be used as a gate electrode, a liner (for example, in a memory In application), barrier layer material, capping material or part of the contact layer. As discussed above, next-generation technology nodes may require ever-decreasing film thicknesses. However, as the film thickness of the conductive film decreases, the resistivity of the conductive film may increase, resulting in loss of efficiency in the structure of the associated semiconductor device. As a non-limiting example, the molybdenum nitride film of the present invention can be used as a substitute for the common titanium nitride film currently used in semiconductor device structures. Therefore, the molybdenum nitride film of the present invention can have a lower resistivity than the resistivity usually achieved in a titanium nitride film of comparable thickness.

因此,本發明之具體例可包括用於藉由循環沉積製程將氮化鉬膜沉積於基板表面上之方法。方法可包含:將基板提供至反應室中;且藉由執行循環沉積製程之一或多個單元沉積循環而將氮化鉬膜直接沉積於基板表面上,其中單元沉積循環包含:使基板與包含鹵化鉬前驅物之第一氣相反應物接觸;且使基板與包含氮前驅物之第二氣相反應物接觸。Therefore, specific examples of the present invention may include a method for depositing a molybdenum nitride film on the surface of a substrate by a cyclic deposition process. The method may include: providing the substrate into the reaction chamber; and directly depositing the molybdenum nitride film on the surface of the substrate by performing one or more unit deposition cycles of the cyclic deposition process, wherein the unit deposition cycle includes: The first gas phase reactant of the molybdenum halide precursor is contacted; and the substrate is contacted with the second gas phase reactant containing the nitrogen precursor.

本文所揭示之將氮化鉬膜直接沉積於基板表面上之方法可包含循環沉積製程,諸如原子層沉積(ALD)或循環化學氣相沉積(循環CVD)。The method of directly depositing a molybdenum nitride film on the surface of a substrate disclosed herein may include a cyclic deposition process, such as atomic layer deposition (ALD) or cyclic chemical vapor deposition (cyclic CVD).

循環沉積方法之非限制性例示性具體例可包括原子層沉積(ALD),其中ALD通常係基於自限反應,由此依序及交替反應物脈衝用以每單元沉積循環沉積約一個原子(或分子)材料單層。沉積條件及前驅物通常經選擇以提供自飽和反應,使得一個反應物之吸收層留下不與相同反應物之氣相反應物反應的表面終止。隨後使基板與不同反應物接觸,該反應物與先前終止反應以使得繼續沉積。因此,交替脈衝之各循環通常留下不超過約一個所需材料之單層。然而,如上文所提及,熟悉本技藝者將認識到,在一或多個ALD循環中,可沉積超過一個材料單層,例如在不管製程之交替性質如何發生某些氣相反應的情況下。Non-limiting illustrative examples of cyclic deposition methods may include atomic layer deposition (ALD), where ALD is usually based on a self-limiting reaction, whereby sequential and alternating reactant pulses are used to deposit about one atom (or Molecule) single layer of material. The deposition conditions and precursors are usually selected to provide a self-saturating reaction so that the absorber layer of one reactant leaves a surface termination that does not react with the gas phase reactant of the same reactant. The substrate is then brought into contact with a different reactant, which reacts with the previous termination to allow the deposition to continue. Therefore, each cycle of alternating pulses usually leaves no more than about one monolayer of the desired material. However, as mentioned above, those skilled in the art will recognize that in one or more ALD cycles, more than one single layer of material can be deposited, for example, in the case of unregulated alternate nature of how certain gas phase reactions occur .

在用於直接在基板表面上沉積氮化鉬膜之例示性ALD製程中,單元沉積循環可包含:使基板暴露於第一氣相反應物,自反應室移除任何未反應之第一反應物及反應副產物,且使基板暴露於第二氣相反應物,隨後進行第二移除步驟。在本發明之一些具體例中,第一氣相反應物可包含鹵化鉬前驅物且第二氣相反應物可包含氮前驅物。In an exemplary ALD process for directly depositing a molybdenum nitride film on the surface of a substrate, the unit deposition cycle may include exposing the substrate to the first gas phase reactant, and removing any unreacted first reactant from the reaction chamber And reaction by-products, and exposing the substrate to the second gas phase reactant, followed by a second removal step. In some embodiments of the present invention, the first gas phase reactant may include a molybdenum halide precursor and the second gas phase reactant may include a nitrogen precursor.

前驅物可藉由惰性氣體(諸如氬氣(Ar)或氮氣(N2 ))分離,以防止反應物之間發生氣相反應且能夠進行自飽和表面反應。然而,在一些具體例中,可移動基板以與第一氣相反應物及第二氣相反應物分別接觸。由於反應自飽和,所以可能不需要對基板進行嚴格溫度控制且對前驅物進行精確劑量控制。然而,基板溫度較佳使得送入的氣體物種不會冷凝成單層,亦不會在表面上分解。在使基板與下一反應性化學物質接觸之前,諸如藉由吹掃反應空間或藉由移動基板,自基板表面移除過剩化學物質及反應副產物(若存在)。藉助於惰性吹掃氣體,非所需氣態分子可有效地自反應空間排出。真空泵可用以輔助吹掃。The precursor can be separated by an inert gas (such as argon (Ar) or nitrogen (N 2 )) to prevent gas phase reactions between the reactants and enable self-saturating surface reactions. However, in some embodiments, the substrate can be moved to contact the first gas phase reactant and the second gas phase reactant respectively. Due to the self-saturation of the reaction, there may be no need for strict temperature control of the substrate and precise dose control of the precursor. However, the substrate temperature is preferably such that the gas species introduced will not condense into a single layer, nor decompose on the surface. Before contacting the substrate with the next reactive chemical species, such as by purging the reaction space or by moving the substrate, the excess chemical species and reaction byproducts (if any) are removed from the substrate surface. With the help of inert purge gas, undesired gaseous molecules can be effectively discharged from the reaction space. A vacuum pump can be used to assist in purging.

能夠進行循環沉積製程之反應器可用以沉積如本文所描述之氮化鉬膜。此類反應器包括經組態以提供前驅物之ALD反應器以及CVD反應器。根據一些具體例,可使用簇射頭式反應器(showerhead reactor)。根據一些具體例,可使用叉流式、分批式、小型分批式或空間式ALD反應器。A reactor capable of a cyclic deposition process can be used to deposit the molybdenum nitride film as described herein. Such reactors include ALD reactors and CVD reactors configured to provide precursors. According to some specific examples, a showerhead reactor can be used. According to some specific examples, cross-flow, batch, small batch, or space ALD reactors can be used.

在本發明之一些具體例中,可使用分批式反應器。在一些具體例中,可使用垂直分批式反應器。舉例而言,垂直分批式反應器可包含反應室及升降機,升降機經構造及佈置以將經組態用於支撐10至200個之間的基板之批次的舟皿移入或移出反應室。在其他具體例中,分批式反應器包含經組態以(configured to)容納10個或更少晶圓、8個或更少晶圓、6個或更少晶圓、4個或更少晶圓或2個或更少晶圓之小型分批式反應器。在使用分批式反應器之一些具體例中,晶圓間之不一致性小於3% (1σ)、小於2%、小於1%或甚至小於0.5%。In some embodiments of the present invention, a batch reactor can be used. In some specific examples, a vertical batch reactor can be used. For example, a vertical batch reactor may include a reaction chamber and an elevator that is constructed and arranged to move boats configured to support batches of between 10 and 200 substrates into or out of the reaction chamber. In other specific examples, the batch reactor includes configured to accommodate 10 or fewer wafers, 8 or fewer wafers, 6 or fewer wafers, 4 or fewer wafers. Wafers or small batch reactors with 2 or less wafers. In some specific examples using batch reactors, the inconsistency between wafers is less than 3% (1σ), less than 2%, less than 1%, or even less than 0.5%.

本文所描述之例示性循環沉積製程可選擇地在反應器及連接至群集工具之一或多個相關反應室中進行。在群集工具中,因為各反應室專用於一種類型之製程,所以各模組中之反應室之溫度可保持恆定,其相較於在各輪次前將基板加熱至製程溫度的反應器可提高處理量。另外,在群集工具中,可減少將反應室泵至基板之間所需的製程壓力之時間。在本發明之一些具體例中,本文所揭示之用於沉積氮化鉬膜之例示性循環沉積製程可在包含多個反應室之群集工具中進行,其中各個別反應室可用以將基板暴露於個別前驅氣體且基板可在不同反應室之間轉移以用於暴露於多種前驅物,基板轉移係在受控環境下進行以防止基板污染。在本發明之一些具體例中,本文所描述之循環沉積製程可在包含多個反應室之群集工具中進行,其中各個別反應室可經組態以將基板加熱至不同溫度。The exemplary cyclic deposition process described herein can optionally be performed in one or more related reaction chambers in the reactor and connected to the cluster tool. In the cluster tool, because each reaction chamber is dedicated to one type of process, the temperature of the reaction chamber in each module can be kept constant, which is higher than that of a reactor that heats the substrate to the process temperature before each round Processing capacity. In addition, in the cluster tool, the process pressure time required to pump the reaction chamber to the substrate can be reduced. In some specific examples of the present invention, the exemplary cyclic deposition process for depositing molybdenum nitride films disclosed herein can be performed in a cluster tool containing multiple reaction chambers, wherein each individual reaction chamber can be used to expose the substrate to Individual precursor gases and substrates can be transferred between different reaction chambers for exposure to multiple precursors. The substrate transfer is performed in a controlled environment to prevent substrate contamination. In some embodiments of the present invention, the cyclic deposition process described herein can be performed in a cluster tool containing multiple reaction chambers, where each individual reaction chamber can be configured to heat the substrate to different temperatures.

獨立式反應器可配備有負載鎖定件(load-lock)。在彼情況下,在各輪次之間無須冷卻反應室。The free-standing reactor may be equipped with a load-lock. In that case, there is no need to cool the reaction chamber between rounds.

根據本發明之一些非限制性具體例,ALD製程可用以將氮化鉬膜直接沉積於基板表面上。在本發明之一些具體例中,各ALD單元沉積循環可包含兩個不同沉積步驟或階段。在單元沉積循環之第一階段(「鉬階段」)中,可使需要沉積之基板表面與包含化學吸附至基板表面上之鉬前驅物的第一氣相反應物接觸,從而在基板表面上形成不超過約一個反應物物種單層。在單元沉積循環之第二階段(「氮階段」)中,可使需要沉積之基板表面與包含氮前驅物之第二氣相反應物接觸。According to some non-limiting examples of the present invention, the ALD process can be used to directly deposit the molybdenum nitride film on the surface of the substrate. In some embodiments of the present invention, each ALD unit deposition cycle may include two different deposition steps or stages. In the first stage of the unit deposition cycle (the "molybdenum stage"), the surface of the substrate to be deposited can be brought into contact with the first gas phase reactant containing the molybdenum precursor chemically adsorbed on the surface of the substrate, thereby forming on the surface of the substrate No more than about one reactant species monolayer. In the second stage ("nitrogen stage") of the unit deposition cycle, the surface of the substrate to be deposited can be brought into contact with a second gas phase reactant containing a nitrogen precursor.

參看圖1,可理解用於將氮化鉬膜直接沉積於基板表面上之例示性循環沉積製程,其繪示用於將氮化鉬膜沉積於基板表面上之例示性原子層沉積製程100。Referring to FIG. 1, an exemplary cyclic deposition process for directly depositing a molybdenum nitride film on the surface of a substrate can be understood, which illustrates an exemplary atomic layer deposition process 100 for depositing a molybdenum nitride film on the surface of a substrate.

更詳細而言,圖1繪示包括循環沉積階段105之例示性氮化鉬沉積製程100。例示性原子層沉積製程100可開始於製程框110,其包含將基板提供至反應室中且將基板加熱至所需沉積溫度。In more detail, FIG. 1 shows an exemplary molybdenum nitride deposition process 100 including a cyclic deposition stage 105. The exemplary atomic layer deposition process 100 may begin at process block 110, which includes providing a substrate into a reaction chamber and heating the substrate to a desired deposition temperature.

在本發明之一些具體例中,基板可包含平面基板或經圖案化基板,其包括高縱橫比特徵,諸如垂直溝槽、水平溝槽、垂直間隙特徵、水平間隙特徵及/或鰭結構。基板可包含一或多種材料,包括(但不限於)半導體材料、介電材料及金屬材料。基板亦可包含一或多個暴露表面,包括(但不限於)半導體表面、介電質表面及金屬表面。In some embodiments of the present invention, the substrate may include a planar substrate or a patterned substrate, which includes high aspect ratio features, such as vertical trenches, horizontal trenches, vertical gap features, horizontal gap features, and/or fin structures. The substrate may include one or more materials, including but not limited to semiconductor materials, dielectric materials, and metal materials. The substrate may also include one or more exposed surfaces, including but not limited to semiconductor surfaces, dielectric surfaces, and metal surfaces.

在一些具體例中,基板可包括半導體材料,諸如但不限於矽(Si)、鍺(Ge)、鍺錫(GeSn)、矽鍺(SiGe)、矽鍺錫(SiGeSn)、碳化矽(SiC)或第III-V族半導體材料。In some specific examples, the substrate may include semiconductor materials, such as but not limited to silicon (Si), germanium (Ge), germanium tin (GeSn), silicon germanium (SiGe), silicon germanium tin (SiGeSn), silicon carbide (SiC) Or group III-V semiconductor materials.

在一些具體例中,基板可包括介電材料,諸如但不限於含矽介電材料及金屬氧化物介電材料。在一些具體例中,基板可包含一或多種含矽介電材料/表面,諸如但不限於二氧化矽(SiO2 )、亞氧化矽、氮化矽(Si3 N4 )、氮氧化矽(SiON)、碳氧化矽(SiOC)、氮化碳氧化矽(SiOCN)、氮化碳矽(SiCN)。在一些具體例中,基板可為一或多種金屬氧化物材料/表面,諸如但不限於氧化鋁(Al2 O3 )、氧化鉿(HfO2 )、氧化鉭(Ta2 O5 )、氧化鋯(ZrO2 )、氧化鈦(TiO2 )、矽酸鉿(HfSiOx )及氧化鑭(La2 O3 )。In some embodiments, the substrate may include dielectric materials, such as but not limited to silicon-containing dielectric materials and metal oxide dielectric materials. In some embodiments, the substrate may include one or more silicon-containing dielectric materials/surfaces, such as, but not limited to , silicon dioxide (SiO 2 ), silicon suboxide, silicon nitride (Si 3 N 4 ), silicon oxynitride ( SiON), silicon carbide (SiOC), silicon carbide nitride (SiOCN), silicon carbide nitride (SiCN). In some specific examples, the substrate may be one or more metal oxide materials/surfaces, such as but not limited to aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), hafnium silicate (HfSiO x ), and lanthanum oxide (La 2 O 3 ).

在一些具體例中,基板可包含經工程改造之基板,其中表面半導體層安置於本體支撐件上方,伴隨中間內埋氧化物(buried oxide, BOX)安置於其之間。In some embodiments, the substrate may include an engineered substrate, in which a surface semiconductor layer is disposed above the body support, with an intermediate buried oxide (BOX) disposed therebetween.

經圖案化基板可包含可包括形成於基板之表面中或形成至基板之表面上之半導體裝置結構的基板。舉例而言,半導體裝置結構可包含部分製造之半導體裝置結構,諸如電晶體及/或記憶體元件。在一些具體例中,基板可含有單晶表面及/或可包含非單晶表面之一或多個次表面,諸如多晶表面及/或非晶形表面。The patterned substrate may include a substrate that may include semiconductor device structures formed in or onto the surface of the substrate. For example, the semiconductor device structure may include a partially manufactured semiconductor device structure, such as a transistor and/or a memory device. In some embodiments, the substrate may include a single crystal surface and/or may include one or more sub-surfaces of a non-single crystal surface, such as a polycrystalline surface and/or an amorphous surface.

用於沉積之反應室可為原子層沉積反應室,或化學氣相沉積反應室,或如本文先前所描述之反應室中之任一者。The reaction chamber used for deposition can be an atomic layer deposition reaction chamber, or a chemical vapor deposition reaction chamber, or any of the reaction chambers as previously described herein.

在製程框110(圖1)之一些具體例中,可將基板加熱至沉積溫度以用於後續循環沉積階段105。舉例而言,基板可加熱至低於約700 ℃、或低於約600 ℃、或低於約500 ℃、或低於約400 ℃、或低於約300 ℃、或甚至低於約200 ℃之基板溫度。在一些具體例中,在循環沉積製程100期間之基板溫度可在約200℃與700 ℃之間、或在約350 ℃與600 ℃之間、或在約450 ℃與550 ℃之間。In some specific examples of the process block 110 (FIG. 1 ), the substrate may be heated to the deposition temperature for the subsequent cycle deposition stage 105. For example, the substrate can be heated to temperatures below about 700°C, or below about 600°C, or below about 500°C, or below about 400°C, or below about 300°C, or even below about 200°C. Substrate temperature. In some embodiments, the substrate temperature during the cyclic deposition process 100 may be between about 200°C and 700°C, or between about 350°C and 600°C, or between about 450°C and 550°C.

除了達成所需沉積溫度,亦即所需基板溫度之外,例示性循環沉積製程100亦可在膜沉積期間調節反應室內之壓力。舉例而言,在一些具體例中,例示性循環沉積製程100可在調節至低於300托、或低於200托、或低於100托、或低於50托、或低於30托、或低於10托、或低於5托、或甚至低於2托之壓力的反應室內進行。在一些具體例中,沉積期間反應室內之壓力可在約2托與300托之間、或在約30托與80托之間的壓力下調節。In addition to achieving the desired deposition temperature, that is, the desired substrate temperature, the exemplary cyclic deposition process 100 can also adjust the pressure in the reaction chamber during film deposition. For example, in some specific examples, the exemplary cyclic deposition process 100 can be adjusted to less than 300 Torr, or less than 200 Torr, or less than 100 Torr, or less than 50 Torr, or less than 30 Torr, or It is carried out in a reaction chamber with a pressure of less than 10 Torr, or less than 5 Torr, or even less than 2 Torr. In some embodiments, the pressure in the reaction chamber during deposition can be adjusted between about 2 Torr and 300 Torr, or between about 30 Torr and 80 Torr.

一旦將基板加熱至所需沉積溫度且調節反應室內之壓力,則例示性循環沉積製程100(例如,ALD製程)可藉助於製程框120以循環沉積階段105繼續,該製程框包含使基板與包含鹵化鉬前驅物(亦即,鉬前驅物)之第一氣相反應物接觸。Once the substrate is heated to the desired deposition temperature and the pressure in the reaction chamber is adjusted, the exemplary cyclic deposition process 100 (for example, an ALD process) can be continued with the cyclic deposition stage 105 by means of a process block 120, which includes making the substrate and containing The first gas phase reactant of the molybdenum halide precursor (ie, the molybdenum precursor) contacts.

在本發明之一些具體例中,鹵化鉬前驅物可包含氯化鉬前驅物、溴化鉬前驅物或碘化鉬前驅物。舉例而言,作為一非限制性實施例,氯化鉬可包含以下中之一或多者:五氯化鉬(MoCl5 )或六氯化鉬(MoCl6 )。In some embodiments of the present invention, the molybdenum halide precursor may include a molybdenum chloride precursor, a molybdenum bromide precursor, or a molybdenum iodide precursor. For example, as a non-limiting embodiment, molybdenum chloride may include one or more of the following: molybdenum pentachloride (MoCl 5 ) or molybdenum hexachloride (MoCl 6 ).

在一些具體例中,鹵化鉬前驅物可包含硫化鉬鹵化物前驅物,諸如選自由包含以下之群的鹵氧化鉬前驅物:氯氧化鉬、碘氧化鉬及/或溴氧化鉬。在一些具體例中,鉬前驅物可包含氯氧化鉬,其包含以下中之一或多者:三氯氧化鉬(V) (MoOCl3 )、四氯氧化鉬(VI) (MoOCl4 )或二氯二氧化鉬(IV) (MoO2 Cl2 )。In some embodiments, the molybdenum halide precursor may include a molybdenum sulfide halide precursor, such as a molybdenum oxyhalide precursor selected from the group consisting of molybdenum oxychloride, molybdenum oxyiodide, and/or molybdenum oxybromide. In some specific examples, the molybdenum precursor may include molybdenum oxychloride, which includes one or more of the following: molybdenum trichloride (V) (MoOCl 3 ), molybdenum tetrachloride (VI) (MoOCl 4 ), or two Chlorinated molybdenum (IV) dioxide (MoO 2 Cl 2 ).

在替代性具體例中,第一氣相反應物,亦即鉬前驅物可包含金屬有機鉬前驅物,諸如Mo(NMe2 )4 、Mo(NEt2 )4 、Mo2 (NMe2 )6 、Mo(tBuN)2 (NMe2 )2 、Mo(tBuN)2 (NEt2 )2 、Mo(NEtMe)4 、Mo(NtBu)2 (StBu)2 、Mo(NtBu)2 (iPr2 AMD)2 Mo(thd)3 、MoO2 (acac)­、MoO2 (thd)2 及/或MoO2 (iPr2 AMD)2 第一氣相反應物可包含有機金屬鉬化合物,其包括(但不限於)含有環戊二烯基(Cp)配位體、η6 -芳烴配位體及羰基配位體,諸如Mo(CO)6 Mo(Cp)2 H2 、Mo(iPrCp)2 H2 、Mo(η6 -乙苯)2 、MoCp(CO)23 -烯丙基)、MoCp(CO)2 (NO)、Mo(苯)2 、MoCp2 Cl2 及NMe)3 ,以及其變體。In an alternative embodiment, the first gas phase reactant, that is, the molybdenum precursor may include a metal organic molybdenum precursor, such as Mo(NMe 2 ) 4 , Mo(NEt 2 ) 4 , Mo 2 (NMe 2 ) 6 , Mo(tBuN) 2 (NMe 2 ) 2 , Mo(tBuN) 2 (NEt 2 ) 2 , Mo(NEtMe) 4 , Mo(NtBu) 2 (StBu) 2 , Mo(NtBu) 2 (iPr 2 AMD) 2 Mo (thd) 3 , MoO 2 (acac), MoO 2 (thd) 2 and/or MoO 2 (iPr 2 AMD) 2 The first gas phase reactant may include an organometallic molybdenum compound, including (but not limited to) containing ring Pentadienyl (Cp) ligands, η 6 -arene ligands and carbonyl ligands, such as Mo(CO) 6 , Mo(Cp) 2 H 2 , Mo(iPrCp) 2 H 2 , Mo(η 6 -Ethylbenzene) 2 , MoCp(CO) 23 -allyl), MoCp(CO) 2 (NO), Mo(benzene) 2 , MoCp 2 Cl 2 and NMe) 3 , and variants thereof.

在本發明之至少一個具體例中,第一氣相反應物可包含雙(第三丁基亞胺基)雙(二甲胺基)鉬(VI)。第一氣相反應物可與第二氣相反應物反應,其中第二氣相反應物可包含氨氣。所得氮化鉬膜可具有適用於pMOS功函數金屬應用之功函數值、電阻率及平帶位移(flatband shift)。舉例而言,此可部分歸因於相比於鈦或釩,鉬之較高電負性。另外,氮化鉬之較低電阻率使得有效功函數較高。In at least one embodiment of the present invention, the first gas phase reactant may include bis(tertiary butylimino) bis(dimethylamino) molybdenum (VI). The first gas phase reactant may react with the second gas phase reactant, where the second gas phase reactant may include ammonia gas. The resulting molybdenum nitride film can have work function values, resistivity and flatband shift suitable for pMOS work function metal applications. For example, this can be partly attributed to the higher electronegativity of molybdenum compared to titanium or vanadium. In addition, the lower resistivity of molybdenum nitride makes the effective work function higher.

在本發明之一些具體例中,使基板與鹵化鉬前驅物接觸可包含在約0.1秒與約60秒之間、或在約0.1秒與約10秒之間、或甚至在約0.5秒與約5.0秒之間的接觸時段。另外,在基板與鹵化鉬前驅物接觸期間,鹵化鉬前驅物之流動速率可小於1000 sccm、或小於500 sccm、或小於100 sccm、或小於10 sccm、或甚至小於1 sccm。另外,在基板與鹵化鉬前驅物接觸期間,鉬前驅物之流動速率可在約1 sccm至2000 sccm、約5 sccm至1000 sccm或約10 sccm至約500 sccm範圍內。In some embodiments of the present invention, contacting the substrate with the molybdenum halide precursor may comprise between about 0.1 seconds and about 60 seconds, or between about 0.1 seconds and about 10 seconds, or even between about 0.5 seconds and about 0.5 seconds. The contact period between 5.0 seconds. In addition, during the contact between the substrate and the molybdenum halide precursor, the flow rate of the molybdenum halide precursor may be less than 1000 sccm, or less than 500 sccm, or less than 100 sccm, or less than 10 sccm, or even less than 1 sccm. In addition, during the contact between the substrate and the molybdenum halide precursor, the flow rate of the molybdenum precursor may be in the range of about 1 sccm to 2000 sccm, about 5 sccm to 1000 sccm, or about 10 sccm to about 500 sccm.

用於如藉由圖1之製程100沉積氮化鉬膜之例示性循環沉積製程可藉由吹掃反應室而繼續。舉例而言,過量鹵化鉬前驅物及反應副產物(若存在)可例如藉由用惰性氣體抽汲自基板表面移除。在本發明之一些具體例中,吹掃製程可包含吹掃循環,其中將基板表面吹掃持續小於約5秒、或小於約3秒、或小於約2秒,在約2至5秒之間的時段。過量鹵化鉬前驅物及任何可能的反應副產物可藉助於由與反應室流體連通之抽汲系統產生之真空來移除。在本發明之一些具體例中,可省略在使基板與第一氣相反應物接觸之後的吹掃循環。An exemplary cyclic deposition process for depositing a molybdenum nitride film as by process 100 of FIG. 1 can be continued by purging the reaction chamber. For example, excess molybdenum halide precursors and reaction byproducts (if present) can be removed from the substrate surface, for example, by pumping with an inert gas. In some embodiments of the present invention, the purge process may include a purge cycle, wherein the substrate surface is purged for less than about 5 seconds, or less than about 3 seconds, or less than about 2 seconds, between about 2 to 5 seconds Time period. The excess molybdenum halide precursor and any possible reaction by-products can be removed by means of a vacuum created by a pumping system in fluid communication with the reaction chamber. In some embodiments of the present invention, the purge cycle after contacting the substrate with the first gas phase reactant may be omitted.

例示性循環沉積製程100可藉助於製程框130以循環沉積階段105之第二階段繼續,該製程框包含使基板與第二氣相反應物接觸,且特定言之使基板與包含氮前驅物之第二氣相反應物接觸(「氮階段」)。The exemplary cyclic deposition process 100 can be continued with the second stage of the cyclic deposition stage 105 by means of a process block 130, which includes contacting a substrate with a second gas phase reactant, and in particular, contacting the substrate with a nitrogen precursor. The second gas phase reactant contact ("nitrogen stage").

在本發明之一些具體例中,氮前驅物可包含以下中之至少一者:分子氮(N2 )、氨氣(NH3 )、肼(N2 H4 )、肼衍生物或氮基電漿。在一些具體例中,肼衍生物可包含烷基-肼,其包括以下中之至少一者:第三丁肼(C4 H9 N2 H3 )、甲肼(CH3 NHNH2 )、1,1-二甲肼((CH3 )2 N2 H2 )、1,2-二甲肼、乙肼、1,1-二乙肼、1-乙基-1-甲肼、異丙肼、苯肼、1,1-二苯肼、1,2-二苯肼、N-胺基哌啶、N-胺基吡咯、N-胺基吡咯啶、N-甲基-N-苯肼、1-胺基-1,2,3,4-四氫喹啉、N-胺基哌𠯤、1,1-二苯肼、1,2-二苯肼、1-乙基-1-苯肼、1-胺基吖𠰢、1-甲基-1-(間甲苯基)肼、1-乙基-1-(對甲苯基)肼、1-胺基咪唑、1-胺基-2,6-二甲基哌啶、N-胺基氮丙啶或偶氮基-第三丁烷。在一些具體例中,氮基電漿可藉由將RF功率施加至含氮氣體而產生,且氮基電漿可包含原子氮(N)、氮離子、氮自由基及氮之激發物種。在一些具體例中,氮基電漿可進一步包含額外反應性物種,諸如藉由添加另一氣體。In some embodiments of the present invention, the nitrogen precursor may include at least one of the following: molecular nitrogen (N 2 ), ammonia (NH 3 ), hydrazine (N 2 H 4 ), hydrazine derivatives, or nitrogen-based electricity Pulp. In some specific examples, the hydrazine derivative may include an alkyl-hydrazine, which includes at least one of the following: tertiary butylhydrazine (C 4 H 9 N 2 H 3 ), methylhydrazine (CH 3 NHNH 2 ), 1 ,1-Dimethylhydrazine ((CH 3 ) 2 N 2 H 2 ), 1,2-Dimethylhydrazine, ethylhydrazine, 1,1-diethylhydrazine, 1-ethyl-1-methylhydrazine, isopropylhydrazine , Phenylhydrazine, 1,1-diphenylhydrazine, 1,2-diphenylhydrazine, N-aminopiperidine, N-aminopyrrole, N-aminopyrrolidine, N-methyl-N-phenylhydrazine, 1-amino-1,2,3,4-tetrahydroquinoline, N-aminopiper, 1,1-diphenylhydrazine, 1,2-diphenylhydrazine, 1-ethyl-1-phenylhydrazine , 1-amino acridine, 1-methyl-1-(m-tolyl)hydrazine, 1-ethyl-1-(p-tolyl)hydrazine, 1-aminoimidazole, 1-amino-2,6 -Dimethylpiperidine, N-aminoaziridine or azo-tert-butane. In some embodiments, the nitrogen-based plasma can be generated by applying RF power to a nitrogen-containing gas, and the nitrogen-based plasma can include atomic nitrogen (N), nitrogen ions, nitrogen radicals, and nitrogen excited species. In some embodiments, the nitrogen-based plasma may further include additional reactive species, such as by adding another gas.

在本發明之一些具體例中,使基板與氮前驅物接觸可包含在約0.01秒與約180秒之間、或在約0.05秒與約60秒之間、或甚至在約0.1秒與約10.0秒之間的接觸時段。在一些具體例中,可使基板暴露於氮前驅物持續小於60秒、或小於30秒、或小於15秒、或甚至小於5秒之時段。在一些具體例中,可使基板暴露於氮前驅物持續5秒與60秒之間或5秒與30秒之間的時段。另外,在基板與氮前驅物接觸期間,氮前驅物之流動速率可為小於30 slm、或小於15 slm、或小於10 slm、或小於5 slm、或小於2 slm、或甚至小於1 slm。另外,在基板與氮前驅物接觸期間,氮前驅物之流動速率可在約0.1 slm至30 slm、約2 slm至15 slm或等於或大於2 slm範圍內。In some embodiments of the present invention, contacting the substrate with the nitrogen precursor may be comprised between about 0.01 second and about 180 seconds, or between about 0.05 second and about 60 seconds, or even between about 0.1 second and about 10.0 seconds. The contact period between seconds. In some embodiments, the substrate can be exposed to the nitrogen precursor for a period of less than 60 seconds, or less than 30 seconds, or less than 15 seconds, or even less than 5 seconds. In some embodiments, the substrate may be exposed to the nitrogen precursor for a period of between 5 seconds and 60 seconds or between 5 seconds and 30 seconds. In addition, during the contact between the substrate and the nitrogen precursor, the flow rate of the nitrogen precursor may be less than 30 slm, or less than 15 slm, or less than 10 slm, or less than 5 slm, or less than 2 slm, or even less than 1 slm. In addition, during the contact between the substrate and the nitrogen precursor, the flow rate of the nitrogen precursor may be in the range of about 0.1 slm to 30 slm, about 2 slm to 15 slm, or equal to or greater than 2 slm.

一旦使基板與氮前驅物接觸,則例示性循環沉積製程100可藉由吹掃反應室進行,如本文先前所描述。在本發明之一些具體例中,可省略在使基板與氮前驅物接觸之後的吹掃循環。Once the substrate is brought into contact with the nitrogen precursor, the exemplary cyclic deposition process 100 can be performed by purging the reaction chamber, as previously described herein. In some embodiments of the present invention, the purge cycle after contacting the substrate with the nitrogen precursor can be omitted.

例示性循環沉積製程100之循環沉積階段105可利用決策閘140繼續,其中決策閘140視所沉積之氮化鉬膜之平均膜厚度而定。舉例而言,若所沉積之氮化鉬膜之平均膜厚度不足以用於所需裝置應用,則可藉由返回至製程框120且繼續通過另一單元沉積循環來重複循環沉積階段105,其中單元沉積循環可包含使基板與鹵化鉬前驅物接觸(製程框120)、吹掃反應室、使基板與氮前驅物接觸(製程框130)及再次吹掃反應室。在一些具體例中,循環沉積階段105之單元沉積循環可在引入前驅物之後省略吹掃循環。The cyclic deposition stage 105 of the exemplary cyclic deposition process 100 can be continued with the decision gate 140, wherein the decision gate 140 depends on the average film thickness of the deposited molybdenum nitride film. For example, if the average film thickness of the deposited molybdenum nitride film is not sufficient for the desired device application, the cyclic deposition stage 105 can be repeated by returning to the process block 120 and continuing through another unit deposition cycle, where The unit deposition cycle may include contacting the substrate with the molybdenum halide precursor (process block 120), purging the reaction chamber, contacting the substrate with the nitrogen precursor (process block 130), and purging the reaction chamber again. In some embodiments, the unit deposition cycle of the cyclic deposition stage 105 can omit the purge cycle after introducing the precursor.

循環沉積階段105之單元沉積循環可重複一或多次,直至所需平均膜厚度之氮化鉬膜沉積於基板上。一旦氮化鉬膜已沉積至所需平均膜厚度,則例示性循環沉積製程100可經由製程框150結束,且具有沉積於其上之氮化鉬膜的基板可經受進一步處理以用於形成例如半導體裝置結構。The unit deposition cycle of the cyclic deposition stage 105 can be repeated one or more times until the molybdenum nitride film with the desired average film thickness is deposited on the substrate. Once the molybdenum nitride film has been deposited to the desired average film thickness, the exemplary cyclic deposition process 100 can be completed via process block 150, and the substrate with the molybdenum nitride film deposited thereon can undergo further processing for forming, for example, Semiconductor device structure.

應瞭解,在本發明之一些具體例中,基板與第一氣相反應物(例如,鉬前驅物)及第二氣相反應物(例如,氮前驅物)接觸之次序可使得基板首先與第二氣相反應物接觸,隨後與第一氣相反應物接觸。另外,在一些具體例中,例示性循環沉積製程100之循環沉積階段105可包含在使基板與第二氣相反應物接觸一或多次之前使基板與第一氣相反應物接觸一或多次。另外,在一些具體例中,例示性循環沉積製程100之循環沉積階段105可包含在使基板與第一氣相反應物接觸一或多次之前使基板與第二氣相反應物接觸一或多次。It should be understood that, in some embodiments of the present invention, the order of contacting the substrate with the first gas phase reactant (for example, a molybdenum precursor) and the second gas phase reactant (for example, a nitrogen precursor) may be such that the substrate first contacts with the second gas phase reactant. The two gas phase reactants are contacted, followed by contact with the first gas phase reactant. In addition, in some embodiments, the cyclic deposition stage 105 of the exemplary cyclic deposition process 100 may include contacting the substrate with the first gas phase reactant one or more times before contacting the substrate with the second gas phase reactant one or more times. Times. In addition, in some embodiments, the cyclic deposition stage 105 of the exemplary cyclic deposition process 100 may include contacting the substrate with the second gas phase reactant one or more times before contacting the substrate with the first gas phase reactant one or more times. Times.

在一些具體例中,本文所描述之循環沉積製程可包含混合ALD/CVD或循環CVD製程。舉例而言,在一些具體例中,與CVD製程相比,ALD製程之生長速率可較低。一種提高生長速率之方法可為在比ALD製程中通常採用之溫度更高的基板溫度下操作,產生化學氣相沉積製程之一些部分,但仍利用前驅物之依序引入,此類製程可稱為循環CVD。在一些具體例中,循環CVD製程可包含將兩種或更多種前驅物引入反應室中,其中在反應室中在兩種或更多種前驅物之間可能存在一定重疊時段,從而產生沉積的ALD組分及沉積的CVD組分。舉例而言,循環CVD製程可包含第一前驅物連續流動至反應室中及第二前驅物週期性脈衝至反應室中。In some specific examples, the cyclic deposition process described herein may include a hybrid ALD/CVD or cyclic CVD process. For example, in some embodiments, the growth rate of the ALD process may be lower than that of the CVD process. One way to increase the growth rate can be to operate at a higher substrate temperature than the ALD process is usually used to produce some parts of the chemical vapor deposition process, but still use the sequential introduction of precursors. This type of process can be called It is cyclic CVD. In some specific examples, the cyclic CVD process may include introducing two or more precursors into the reaction chamber, where there may be a certain overlap period between the two or more precursors in the reaction chamber, resulting in deposition. ALD composition and deposited CVD composition. For example, the cyclic CVD process may include the continuous flow of the first precursor into the reaction chamber and the periodic pulse of the second precursor into the reaction chamber.

在一些具體例中,用於沉積氮化鉬膜之循環沉積製程可包含單元沉積,其進一步包括使基板與包含還原劑之第三氣相反應物接觸。作為一非限制性實施例,在一些具體例中,氮前驅物及還原劑可共流至反應室中,亦即,使基板同時與氮前驅物及還原劑接觸。作為另一非限制性實施例,在一些具體例中,可將氮前驅物及還原劑以單獨氣體脈衝引入至反應室中,例如可在使基板與氮前驅物接觸與使基板與還原劑接觸之製程之間執行吹掃循環。In some embodiments, the cyclic deposition process for depositing the molybdenum nitride film may include unit deposition, which further includes contacting the substrate with a third gas phase reactant containing a reducing agent. As a non-limiting example, in some specific examples, the nitrogen precursor and the reducing agent can be co-flowed into the reaction chamber, that is, the substrate is brought into contact with the nitrogen precursor and the reducing agent at the same time. As another non-limiting example, in some specific examples, the nitrogen precursor and the reducing agent can be introduced into the reaction chamber by separate gas pulses. For example, the substrate can be contacted with the nitrogen precursor and the substrate can be contacted with the reducing agent. Perform a purge cycle between the processes.

更詳細而言,圖2繪示用於氮化鉬沉積之例示性循環沉積製程200。例示性製程200可包括循環沉積階段205,該循環沉積期包含製程框230,其中基板與包含氮前驅物及還原劑前驅物之氣體接觸,亦即,將氮前驅物及還原劑前驅物同時暴露於基板。In more detail, FIG. 2 shows an exemplary cyclic deposition process 200 for molybdenum nitride deposition. The exemplary process 200 may include a cyclic deposition stage 205 including a process block 230 in which the substrate is contacted with a gas including a nitrogen precursor and a reducing agent precursor, that is, the nitrogen precursor and the reducing agent precursor are exposed at the same time于substrate.

例示性循環沉積製程200可開始於製程框210,其包含將基板提供至反應室中且將基板加熱至所需沉積溫度。製程框210可與圖1之製程框110實質上相同,且因此,為簡潔起見,不重複對製程框210之描述。The exemplary cyclic deposition process 200 may begin at process block 210, which includes providing a substrate into a reaction chamber and heating the substrate to a desired deposition temperature. The process block 210 may be substantially the same as the process block 110 of FIG. 1, and therefore, for the sake of brevity, the description of the process block 210 is not repeated.

例示性循環沉積製程200可藉由循環沉積階段205繼續,該循環沉積期可藉助於製程框220開始,該製程框包含使基板與鹵化鉬前驅物接觸。製程框220可與圖1之製程框120實質上相同,且因此,為簡潔起見,不重複對製程框220之描述。The exemplary cyclic deposition process 200 can be continued by the cyclic deposition stage 205, which can begin with a process block 220, which includes contacting a substrate with a molybdenum halide precursor. The process block 220 may be substantially the same as the process block 120 of FIG. 1, and therefore, for the sake of brevity, the description of the process block 220 is not repeated.

例示性循環沉積製程200(圖2)可藉由如先前相對於圖1之例示性製程100所論述吹掃反應室而繼續。在本發明之一些具體例中,可省略在使基板與鹵化鉬前驅物接觸之後的吹掃循環。The exemplary cyclic deposition process 200 (FIG. 2) can be continued by purging the reaction chamber as previously discussed with respect to the exemplary process 100 of FIG. 1. In some embodiments of the present invention, the purge cycle after contacting the substrate with the molybdenum halide precursor can be omitted.

例示性循環沉積製程200可藉助於製程框230以循環沉積階段205之第二階段繼續,該製程框包含使基板與包含氮前驅物及還原劑之氣體接觸。換言之,基板可與包含氮前驅物及還原劑兩者之氣體接觸。在本發明之至少一個具體例中,接觸基板之單一氣體可為氮前驅物與還原劑兩者。The exemplary cyclic deposition process 200 can be continued with the second stage of the cyclic deposition stage 205 by means of a process block 230, which includes contacting a substrate with a gas containing a nitrogen precursor and a reducing agent. In other words, the substrate can be in contact with a gas including both the nitrogen precursor and the reducing agent. In at least one embodiment of the present invention, the single gas contacting the substrate can be both the nitrogen precursor and the reducing agent.

在一些具體例中,氮前驅物可包含先前相對於圖1之製程框130所描述的氮前驅物中之一或多者,且因此,為簡潔起見,可用於例示性製程200中之一或多種氮前驅物未第二次描述。In some embodiments, the nitrogen precursor may include one or more of the nitrogen precursors previously described with respect to the process block 130 of FIG. 1, and therefore, for the sake of brevity, may be used in one of the exemplary process 200 Or more nitrogen precursors are not described a second time.

在本發明之一些具體例中,可使基板與包含氮前驅物及還原劑之氣體接觸約0.01秒與約180秒之間、約0.05秒與約60秒之間或約0.1秒與約10.0秒之間的時段,或持續小於60秒、或小於30秒、或小於15秒、或甚至小於5秒之時段。在一些具體例中,基板可暴露於包含氮前驅物及還原劑之氣體持續約5秒與60秒之間或約5秒與30秒之間的時段。另外,在基板與包含氮前驅物及還原劑兩者之氣體接觸期間,氮前驅物之流動速率可為小於30 slm、或小於15 slm、或小於10 slm、或小於5 slm、或小於2 slm、或小於1 slm,或甚至在約1 slm與30 slm之間。另外,還原劑之流動速率可小於30 slm、或小於15 slm、或小於10 slm、或小於5 slm、或小於2 slm,甚至在約2 slm與30 slm之間。In some embodiments of the present invention, the substrate can be contacted with a gas containing a nitrogen precursor and a reducing agent for between about 0.01 seconds and about 180 seconds, between about 0.05 seconds and about 60 seconds, or between about 0.1 seconds and about 10.0 seconds The period between, or lasts less than 60 seconds, or less than 30 seconds, or less than 15 seconds, or even less than 5 seconds. In some embodiments, the substrate may be exposed to the gas including the nitrogen precursor and the reducing agent for a period of between about 5 seconds and 60 seconds or between about 5 seconds and 30 seconds. In addition, during the contact between the substrate and the gas containing both the nitrogen precursor and the reducing agent, the flow rate of the nitrogen precursor can be less than 30 slm, or less than 15 slm, or less than 10 slm, or less than 5 slm, or less than 2 slm , Or less than 1 slm, or even between about 1 slm and 30 slm. In addition, the flow rate of the reducing agent can be less than 30 slm, or less than 15 slm, or less than 10 slm, or less than 5 slm, or less than 2 slm, or even between about 2 slm and 30 slm.

例示性循環沉積製程200可藉由吹掃反應室進行,如先前在本文中所描述。在本發明之一些具體例中,可省略在使基板與氮前驅物/還原劑接觸之後的吹掃循環。The exemplary cyclic deposition process 200 can be performed by purging the reaction chamber, as previously described herein. In some embodiments of the present invention, the purge cycle after contacting the substrate with the nitrogen precursor/reducing agent can be omitted.

例示性循環沉積製程200之循環沉積階段205可以決策閘240繼續,其中決策閘240視所沉積之氮化鉬膜之平均膜厚度而定。舉例而言,若所沉積之氮化鉬膜之平均膜厚度不足以用於特定裝置應用,則可藉由返回至製程框220且繼續通過另一單元沉積循環來重複循環沉積階段205,其中單元沉積循環可包含使基板與鹵化鉬前驅物接觸(製程框220)、吹掃反應室、使基板與包含氮前驅物及還原劑之氣體接觸(製程框230)及再次吹掃反應室。在一些具體例中,循環沉積階段205之單元沉積循環可在引入前驅物之後省略吹掃循環。The cyclic deposition stage 205 of the exemplary cyclic deposition process 200 can be continued with a decision gate 240, wherein the decision gate 240 depends on the average film thickness of the deposited molybdenum nitride film. For example, if the average film thickness of the deposited molybdenum nitride film is not sufficient for a specific device application, the cyclic deposition stage 205 can be repeated by returning to the process block 220 and continuing through another unit deposition cycle, where the unit The deposition cycle may include contacting the substrate with a molybdenum halide precursor (process block 220), purging the reaction chamber, contacting the substrate with a gas containing a nitrogen precursor and a reducing agent (process block 230), and purging the reaction chamber again. In some embodiments, the unit deposition cycle of the cyclic deposition stage 205 can omit the purge cycle after introducing the precursor.

循環沉積階段205之單元沉積循環可重複一或多次,直至所需平均膜厚度之氮化鉬膜沉積於基板上。一旦氮化鉬膜已沉積至所需平均膜厚度,則例示性循環沉積製程200可經由製程框250結束,且具有沉積於其上之氮化鉬膜的基板可經受進一步處理以用於形成例如裝置結構。The unit deposition cycle of the cyclic deposition stage 205 can be repeated one or more times until a molybdenum nitride film with a desired average film thickness is deposited on the substrate. Once the molybdenum nitride film has been deposited to the desired average film thickness, the exemplary cyclic deposition process 200 may end through process block 250, and the substrate with the molybdenum nitride film deposited thereon may undergo further processing for forming, for example,装置结构。 Device structure.

應瞭解,在本發明之一些具體例中,基板與鹵化鉬前驅物及包含氮前驅物及還原劑之氣體接觸之次序可使得基板首先與包含氮前驅物及還原劑之氣體接觸,隨後與鹵化鉬前驅物接觸。另外,在一些具體例中,例示性製程200之循環沉積階段205可包含在使基板與包含氮前驅物及還原劑兩者之氣體接觸之前使基板與鹵化鉬前驅物接觸一或多次。另外,在一些具體例中,例示性製程200之循環沉積階段205可包含在使基板與鹵化鉬前驅物接觸一或多次之前使基板與包含氮前驅物及還原劑之氣體接觸一或多次。It should be understood that, in some embodiments of the present invention, the sequence of contacting the substrate with the molybdenum halide precursor and the gas containing the nitrogen precursor and reducing agent can be such that the substrate is first contacted with the gas containing the nitrogen precursor and reducing agent, and then with the halogenated gas. Molybdenum precursor contact. Additionally, in some embodiments, the cyclic deposition stage 205 of the exemplary process 200 may include contacting the substrate with the molybdenum halide precursor one or more times before contacting the substrate with the gas containing both the nitrogen precursor and the reducing agent. In addition, in some embodiments, the cyclic deposition stage 205 of the exemplary process 200 may include contacting the substrate with a gas containing a nitrogen precursor and a reducing agent one or more times before contacting the substrate with the molybdenum halide precursor one or more times. .

在一些具體例中,用於沉積氮化鉬膜之例示性循環沉積製程可包含氮前驅物及還原劑之單獨脈衝,例如吹掃循環可在使基板與氮前驅物接觸與使基板與還原劑接觸之間進行。In some embodiments, the exemplary cyclic deposition process for depositing molybdenum nitride films may include separate pulses of the nitrogen precursor and the reducing agent. For example, the purge cycle may be used to contact the substrate with the nitrogen precursor and the substrate with the reducing agent. Between contacts.

更詳細而言,圖3繪示包括循環沉積階段305之例示性循環沉積製程300。在一些具體例中,循環沉積階段305可包含用於使基板與氮前驅物接觸之製程框330,及用於使基板與還原劑接觸之製程框340,亦即,基板可分別暴露於氮前驅物及還原劑。In more detail, FIG. 3 shows an exemplary cyclic deposition process 300 including a cyclic deposition stage 305. In some embodiments, the cyclic deposition stage 305 may include a process block 330 for contacting the substrate with a nitrogen precursor, and a process block 340 for contacting the substrate with a reducing agent, that is, the substrate may be exposed to the nitrogen precursor, respectively. Material and reducing agent.

例示性循環沉積製程300可開始於製程框310,其包含將基板提供至反應室中且將基板加熱至所需沉積溫度。製程框310可與圖1之製程框110實質上相同,且因此,為簡潔起見,不重複對製程框310之描述。The exemplary cyclic deposition process 300 may begin at process block 310, which includes providing a substrate into a reaction chamber and heating the substrate to a desired deposition temperature. The process block 310 may be substantially the same as the process block 110 of FIG. 1, and therefore, for the sake of brevity, the description of the process block 310 is not repeated.

例示性循環沉積製程300可藉由循環沉積階段305繼續,該循環沉積期可藉助於製程框320開始,該製程框包含使基板與鹵化鉬前驅物接觸。製程框320可與圖1之製程框120實質上相同,且因此,為簡潔起見,不重複對製程框320之描述。The exemplary cyclic deposition process 300 can be continued by the cyclic deposition stage 305, which can begin with a process block 320, which includes contacting a substrate with a molybdenum halide precursor. The process block 320 may be substantially the same as the process block 120 of FIG. 1, and therefore, for the sake of brevity, the description of the process block 320 is not repeated.

例示性循環沉積製程300(圖3)之例示性循環沉積階段305可藉由如先前相對於圖1之例示性製程100所論述吹掃反應室而繼續。在本發明之一些具體例中,可省略在使基板與鹵化鉬前驅物接觸之後的吹掃循環。The exemplary cyclic deposition stage 305 of the exemplary cyclic deposition process 300 (FIG. 3) can be continued by purging the reaction chamber as previously discussed with respect to the exemplary process 100 of FIG. 1. In some embodiments of the present invention, the purge cycle after contacting the substrate with the molybdenum halide precursor can be omitted.

例示性循環沉積製程300(圖3)可藉助於製程框330以循環沉積階段305之第二階段繼續,該製程框包含使基板與氮前驅物接觸。製程框330可與圖1之製程框130實質上相同,且因此,為簡潔起見,不重複對製程框330之描述。The exemplary cyclic deposition process 300 (FIG. 3) can be continued with the second stage of the cyclic deposition stage 305 by means of a process block 330, which includes contacting a substrate with a nitrogen precursor. The process block 330 may be substantially the same as the process block 130 of FIG. 1, and therefore, for the sake of brevity, the description of the process block 330 is not repeated.

製程300(圖3)之例示性循環沉積階段305可藉由如先前相對於圖1之例示性製程100所論述吹掃反應室而繼續。在本發明之一些具體例中,可省略在使基板與氮前驅物接觸之後的吹掃循環。The exemplary cyclic deposition stage 305 of process 300 (FIG. 3) can be continued by purging the reaction chamber as previously discussed with respect to exemplary process 100 of FIG. 1. In some embodiments of the present invention, the purge cycle after contacting the substrate with the nitrogen precursor can be omitted.

例示性循環沉積製程300可藉助於製程框340以循環沉積階段305之第三階段繼續,該製程框包含使基板與還原劑接觸。在本發明之一些具體例中,還原劑前驅物可選自先前相對於製程框230所描述之彼等,且因此,為簡潔起見,用於製程220之一或多種還原劑不重複。The exemplary cyclic deposition process 300 may continue with the third stage of the cyclic deposition stage 305 by means of a process block 340, which includes contacting a substrate with a reducing agent. In some embodiments of the present invention, the reducing agent precursor may be selected from those previously described with respect to the process block 230, and therefore, for the sake of brevity, one or more reducing agents used in the process 220 are not repeated.

在本發明之一些具體例中,可使基板與還原劑接觸約0.01秒與約180秒之間、約0.05秒與約60秒之間或約0.1秒與約10.0秒之間的時段,或小於60秒、或小於30秒、或小於15秒、或甚至小於5秒之時段。在一些具體例中,可使基板暴露於還原劑前驅物持續5秒與60秒之間或5秒與30秒之間的時段。另外,在基板與還原劑接觸期間,還原劑前驅物之流動速率可小於100 slm、或小於50 slm、或小於25 slm、或小於10 slm、或小於5 slm,或甚至在約5 slm與100 slm之間。In some embodiments of the present invention, the substrate can be contacted with the reducing agent for a period of time between about 0.01 second and about 180 seconds, between about 0.05 second and about 60 seconds, or between about 0.1 second and about 10.0 seconds, or less than A period of 60 seconds, or less than 30 seconds, or less than 15 seconds, or even less than 5 seconds. In some embodiments, the substrate may be exposed to the reducing agent precursor for a period of between 5 seconds and 60 seconds or between 5 seconds and 30 seconds. In addition, during the contact between the substrate and the reducing agent, the flow rate of the reducing agent precursor can be less than 100 slm, or less than 50 slm, or less than 25 slm, or less than 10 slm, or less than 5 slm, or even between about 5 slm and 100 slm. between slm.

例示性循環沉積製程300(圖3)可藉由如先前相對於圖1之例示性製程100所論述吹掃反應室而繼續。在本發明之一些具體例中,可省略在使基板與還原劑接觸之後的吹掃循環。The exemplary cyclic deposition process 300 (FIG. 3) can be continued by purging the reaction chamber as previously discussed with respect to the exemplary process 100 of FIG. 1. In some specific examples of the present invention, the purge cycle after contacting the substrate with the reducing agent may be omitted.

例示性製程300 (圖3)之循環沉積階段305可以決策閘350繼續,其中決策閘350視所沉積之氮化鉬膜之平均膜厚度而定。舉例而言,若所沉積之氮化鉬膜之平均膜厚度不足以用於所需裝置應用,則可藉由返回至製程框320且繼續通過另一單元沉積循環來重複循環沉積階段305,其中單元沉積循環可包含使基板與鹵化鉬前驅物接觸(製程框320)、吹掃反應室、使基板氮前驅物接觸(製程框330)、吹掃反應室、使基板與還原劑接觸(製程框340)及再次吹掃反應室。在一些具體例中,循環沉積階段305之單元沉積循環可在引入前驅物之後省略吹掃循環。The cyclic deposition stage 305 of the exemplary process 300 (FIG. 3) can be continued by the decision gate 350, where the decision gate 350 depends on the average film thickness of the deposited molybdenum nitride film. For example, if the average film thickness of the deposited molybdenum nitride film is not sufficient for the desired device application, the cyclic deposition stage 305 can be repeated by returning to the process block 320 and continuing through another unit deposition cycle, where The unit deposition cycle may include contacting the substrate with the molybdenum halide precursor (process block 320), purging the reaction chamber, contacting the substrate nitrogen precursor (process block 330), purging the reaction chamber, and contacting the substrate with the reducing agent (process block 340) and purge the reaction chamber again. In some embodiments, the unit deposition cycle of the cyclic deposition stage 305 can omit the purge cycle after introducing the precursor.

循環沉積階段305之單元沉積循環可重複一或多次,直至所需平均膜厚度之氮化鉬膜沉積於基板上。一旦氮化鉬膜已沉積至所需平均膜厚度,則例示性循環沉積製程300可經由製程框360結束,且具有沉積於其上之氮化鉬膜的基板可經受進一步處理以用於形成例如裝置結構。The unit deposition cycle of the cyclic deposition stage 305 can be repeated one or more times until the molybdenum nitride film with the desired average film thickness is deposited on the substrate. Once the molybdenum nitride film has been deposited to the desired average film thickness, the exemplary cyclic deposition process 300 may end through process block 360, and the substrate with the molybdenum nitride film deposited thereon may undergo further processing for forming, for example,装置结构。 Device structure.

應瞭解,在本發明之一些具體例中,基板與鹵化鉬前驅物、氮前驅物及還原劑之接觸次序可以任何可設想之順序進行且不受圖3中所示之順序限制。另外,基板與特定前驅物(諸如鹵化鉬前驅物、氮前驅物或還原劑)之接觸可在執行循環沉積階段305之後續製程框之前重複一或多次。It should be understood that, in some specific examples of the present invention, the contact sequence of the substrate and the molybdenum halide precursor, the nitrogen precursor, and the reducing agent can be performed in any conceivable sequence and is not limited by the sequence shown in FIG. 3. In addition, the contact of the substrate with a specific precursor (such as a molybdenum halide precursor, a nitrogen precursor, or a reducing agent) can be repeated one or more times before the subsequent process blocks of the cyclic deposition stage 305 are performed.

本文中之例示性沉積製程揭示內容可以約0.05 Å/循環至約10 Å/循環、約0.5 Å/循環至約5 Å/循環,或甚至約0.5 Å/循環至約2 Å/循環之生長速率將氮化鉬膜直接沉積於基板表面上。在一些具體例中,直接沉積於基板表面上之氮化鉬膜之生長速率大於約0.5 Å/循環、大於約1 Å/循環或甚至大於約2 Å/循環。在本發明之一些具體例中,氮化鉬膜可在沉積溫度,亦即基板溫度,在300 ℃與700 ℃之間、或在400 ℃與500 ℃之間、或甚至低於450 ℃下,以0.5 Å/循環與1 Å/循環之間、或0.8 Å/循環與1 Å/循環之間的生長速率沉積。The exemplary deposition process disclosed herein can be about 0.05 Å/cycle to about 10 Å/cycle, about 0.5 Å/cycle to about 5 Å/cycle, or even about 0.5 Å/cycle to about 2 Å/cycle growth rate The molybdenum nitride film is deposited directly on the surface of the substrate. In some embodiments, the growth rate of the molybdenum nitride film directly deposited on the surface of the substrate is greater than about 0.5 Å/cycle, greater than about 1 Å/cycle, or even greater than about 2 Å/cycle. In some specific examples of the present invention, the molybdenum nitride film can be deposited at a temperature, that is, the substrate temperature, between 300°C and 700°C, or between 400°C and 500°C, or even lower than 450°C, Deposit at a growth rate between 0.5 Å/cycle and 1 Å/cycle, or between 0.8 Å/cycle and 1 Å/cycle.

藉由本文所揭示之方法沉積之氮化鉬膜可為物理上連續的膜。在一些具體例中,氮化鉬膜可在低於約100 Å、或低於約60 Å、或低於約50 Å、或低於約40 Å、或低於約30 Å、或約20 Å、甚至在約20 Å與100 Å之間的平均膜厚度下為物理上連續的。The molybdenum nitride film deposited by the method disclosed herein may be a physically continuous film. In some specific examples, the molybdenum nitride film may be less than about 100 Å, or less than about 60 Å, or less than about 50 Å, or less than about 40 Å, or less than about 30 Å, or about 20 Å. , It is physically continuous even at an average film thickness between about 20 Å and 100 Å.

在一些具體例中,膜可物理上連續之平均膜厚度可能不會與膜電學上連續之平均膜厚度相同,且反之亦然。In some embodiments, the average film thickness of the film that can be physically continuous may not be the same as the average film thickness of the film that is electrically continuous, and vice versa.

在一些具體例中,根據本文所揭露之方法沉積之氮化鉬膜可在低於40 Å、或低於30 Å、或低於20 Å、或低於10 Å,或甚至在約10 Å至40 Å之間的平均膜厚度下為物理上連續的。換言之,氮化鉬膜可具有小於40 Å、或小於30 Å、或小於20 Å、小於10 Å、或甚至在約10 Å與40 Å之間的平均膜閉合厚度。膜變得呈物理上連續之厚度可利用低能量離子散射(low-energy ion scattering;LEIS)來確定。In some specific examples, the molybdenum nitride film deposited according to the method disclosed herein can be below 40 Å, or below 30 Å, or below 20 Å, or below 10 Å, or even at about 10 Å to The average film thickness between 40 Å is physically continuous. In other words, the molybdenum nitride film may have an average film closure thickness of less than 40 Å, or less than 30 Å, or less than 20 Å, less than 10 Å, or even between about 10 Å and 40 Å. The thickness at which the film becomes physically continuous can be determined using low-energy ion scattering (LEIS).

在一些具體例中,本發明之氮化鉬膜可具有約20 Å至250 Å、或約50 Å至200 Å、或甚至約100 Å至150 Å之平均膜厚度。在一些具體例中,本發明之氮化鉬膜可具有大於約20 Å、或大於約30 Å、或大於約40 Å、或大於約50 Å、或大於約60 Å、或大於約100 Å、或大於約250 Å、或大於約500 Å、或甚至在約20 Å與500 Å之間的平均膜厚度。在一些具體例中,本發明之氮化鉬膜可具有小於約250 Å、或小於約100 Å、或小於約50 Å、或小於約25 Å、或小於約10 Å、或小於約5 Å、或甚至約5 Å及250 Å之平均膜厚度。In some specific examples, the molybdenum nitride film of the present invention may have an average film thickness of about 20 Å to 250 Å, or about 50 Å to 200 Å, or even about 100 Å to 150 Å. In some specific examples, the molybdenum nitride film of the present invention may have a thickness greater than about 20 Å, or greater than about 30 Å, or greater than about 40 Å, or greater than about 50 Å, or greater than about 60 Å, or greater than about 100 Å, Or greater than about 250 Å, or greater than about 500 Å, or even an average film thickness between about 20 Å and 500 Å. In some specific examples, the molybdenum nitride film of the present invention may have a thickness of less than about 250 Å, or less than about 100 Å, or less than about 50 Å, or less than about 25 Å, or less than about 10 Å, or less than about 5 Å, Or even an average film thickness of about 5 Å and 250 Å.

在一些具體例中,根據本文所揭示之製程沉積之氮化鉬膜可包含低電阻率之氮化鉬膜。更詳細而言,圖4繪示根據本發明之具體例沉積之呈各種厚度之多個氮化鉬膜的電阻率,其中標記為400之資料包含藉由循環沉積製程100(圖1)沉積之氮化鉬膜,標記為410之資料包含藉由循環沉積製程200(圖2)沉積之氮化鉬膜,且標記為420之資料包含藉由循環沉積製程300(圖3)沉積之氮化鉬膜。圖4之電阻率資料之檢查清楚地繪示在製程200(標記為410之資料)及製程300(標記為420之資料)兩者中添加之還原劑降低氮化鉬膜之電阻率。另外,圖4之進一步檢查清楚地繪示相比於利用氮前驅物及還原劑之共流(製程200/標記為410之資料)沉積之氮化鉬膜,分別引入氮前驅物及還原劑之脈衝(製程300/標記為420之資料)進一步降低所沉積之氮化鉬膜之電阻率。In some embodiments, the molybdenum nitride film deposited according to the process disclosed herein may include a low-resistivity molybdenum nitride film. In more detail, FIG. 4 shows the resistivity of a plurality of molybdenum nitride films of various thicknesses deposited according to a specific example of the present invention, wherein the data marked 400 includes those deposited by the cyclic deposition process 100 (FIG. 1) Molybdenum nitride film, the data labeled 410 includes the molybdenum nitride film deposited by the cyclic deposition process 200 (FIG. 2), and the data labeled 420 includes the molybdenum nitride deposited by the cyclic deposition process 300 (FIG. 3) membrane. The inspection of the resistivity data in FIG. 4 clearly shows that the reducing agent added in both process 200 (data marked 410) and process 300 (data marked 420) reduces the resistivity of the molybdenum nitride film. In addition, the further inspection of Fig. 4 clearly shows that compared to the molybdenum nitride film deposited by the co-flow of nitrogen precursor and reducing agent (process 200/data marked as 410), the introduction of nitrogen precursor and reducing agent respectively The pulse (process 300/data labeled 420) further reduces the resistivity of the deposited molybdenum nitride film.

作為一非限制性實施例,根據本發明之具體例沉積之氮化鉬膜在小於200 Å之平均膜厚度下可具有小於750 μΩ-cm之電阻率、或在小於100 Å之平均膜厚度下可具有小於750 μΩ-cm之電阻率、或在小於25 Å之平均膜厚度下可具有小於1300 μΩ-cm之電阻率。As a non-limiting example, the molybdenum nitride film deposited according to a specific example of the present invention may have a resistivity of less than 750 μΩ-cm at an average film thickness of less than 200 Å, or an average film thickness of less than 100 Å It can have a resistivity of less than 750 μΩ-cm, or can have a resistivity of less than 1300 μΩ-cm with an average film thickness of less than 25 Å.

作為另一非限制性實施例,根據本發明之具體例沉積之氮化鉬膜在小於200 Å之平均膜厚度下可具有小於550 μΩ-cm之電阻率或在小於100 Å之平均膜厚度下可具有小於550 μΩ-cm之電阻率、或在小於25 Å之平均膜厚度下可具有小於950 μΩ-cm之電阻率。As another non-limiting example, the molybdenum nitride film deposited according to a specific example of the present invention may have a resistivity of less than 550 μΩ-cm at an average film thickness of less than 200 Å or an average film thickness of less than 100 Å It can have a resistivity of less than 550 μΩ-cm, or can have a resistivity of less than 950 μΩ-cm with an average film thickness of less than 25 Å.

作為另一非限制性實施例,根據本發明之具體例沉積之氮化鉬膜在小於200 Å之平均膜厚度下可具有小於250 μΩ-cm之電阻率、或在小於100 Å之平均膜厚度下可具有小於250 μΩ-cm之電阻率、或在小於25 Å之平均膜厚度下可具有小於600 μΩ-cm之電阻率。As another non-limiting example, the molybdenum nitride film deposited according to a specific example of the present invention may have a resistivity of less than 250 μΩ-cm at an average film thickness of less than 200 Å, or an average film thickness of less than 100 Å It can have a resistivity of less than 250 μΩ-cm, or can have a resistivity of less than 600 μΩ-cm with an average film thickness of less than 25 Å.

在一些具體例中,對於具有約10 Å與200 Å之間、或約20 Å與100 Å之間、或甚至約20 Å與50 Å之間的平均膜厚度的氮化鉬膜,根據本發明之具體例沉積之氮化鉬膜可具有250 μΩ-cm與1000 μΩ-cm之間、或250 μΩ-cm與750 μΩ-cm之間、或甚至250 μΩ-cm與500 μΩ-cm之間的電阻率。In some specific examples, for a molybdenum nitride film having an average film thickness between about 10 Å and 200 Å, or between about 20 Å and 100 Å, or even between about 20 Å and 50 Å, according to the present invention The deposited molybdenum nitride film may have a thickness between 250 μΩ-cm and 1000 μΩ-cm, or between 250 μΩ-cm and 750 μΩ-cm, or even between 250 μΩ-cm and 500 μΩ-cm. Resistivity.

藉由本發明之具體例沉積之氮化鉬膜之優良電阻率進一步展示於圖5中,其繪示根據本發明之具體例沉積於介電基板上之呈各種厚度之多個氮化鉬膜的電阻率。另外,圖5亦比較本發明之電阻率鉬膜與利用四氯化鈦前驅物沉積之不同厚度之先前技術氮化鈦膜。標記為500之資料對應於採用四氯化鈦(TiCl4 )作為金屬前驅物沉積之氮化鈦膜。圖5中所繪示之所有膜均沉積於介電材料之暴露表面上。The excellent resistivity of the molybdenum nitride film deposited by the specific example of the present invention is further shown in FIG. 5, which shows the various thicknesses of the molybdenum nitride film deposited on the dielectric substrate according to the specific example of the present invention. Resistivity. In addition, FIG. 5 also compares the resistivity molybdenum film of the present invention and the prior art titanium nitride film of different thicknesses deposited using the titanium tetrachloride precursor. The data marked 500 corresponds to a titanium nitride film deposited using titanium tetrachloride (TiCl 4 ) as the metal precursor. All the films depicted in Figure 5 are deposited on the exposed surface of the dielectric material.

更詳細而言,標記為510之資料對應於沉積於氧化矽基板上之氮化鉬膜,且標記為520之資料對應於沉積於氧化鉿(HfO2 )基板上之氮化鉬膜。圖5中所繪示之例示性氮化鉬膜係在小於約500 ℃之沉積溫度(亦即,基板溫度)下,利用二氯化鉬(IV) (MoO2 Cl2 )作為鹵化鉬前驅物、氨氣(NH3 )作為氮前驅物且氫氣(H2 )作為還原劑來沉積。In more detail, the data labeled 510 corresponds to the molybdenum nitride film deposited on the silicon oxide substrate, and the data labeled 520 corresponds to the molybdenum nitride film deposited on the hafnium oxide (HfO 2 ) substrate. The exemplary molybdenum nitride film depicted in FIG. 5 uses molybdenum (IV) chloride (MoO 2 Cl 2 ) as a molybdenum halide precursor at a deposition temperature (ie, substrate temperature) of less than about 500°C , Ammonia (NH 3 ) is used as the nitrogen precursor and hydrogen (H 2 ) is deposited as a reducing agent.

圖5中之電阻率資料之檢查清晰地表明,當與先前技術可比厚度之氮化鈦膜之電阻率比較時,本發明之氮化鉬膜在減小的平均膜厚度下具有減小的電阻率。The inspection of the resistivity data in FIG. 5 clearly shows that when compared with the resistivity of the titanium nitride film of comparable thickness in the prior art, the molybdenum nitride film of the present invention has a reduced resistance at a reduced average film thickness. rate.

作為一非限制性實施例,本發明之氮化鉬膜在小於50 Å之平均膜厚度下可具有小於250 μΩ-cm之電阻率、或在小於40 Å之平均膜厚度下可具有小於300 μΩ-cm之電阻率、或在小於25 Å之平均膜厚度下可具有400 μΩ-cm之電阻率。在一些具體例中,本發明之氮化鉬膜在小於50 Å之平均膜厚度下可具有約250 μΩ-cm與400 μΩ-cm之間的電阻率。As a non-limiting example, the molybdenum nitride film of the present invention may have a resistivity of less than 250 μΩ-cm at an average film thickness of less than 50 Å, or may have a resistivity of less than 300 μΩ at an average film thickness of less than 40 Å. -cm resistivity, or 400 μΩ-cm resistivity at an average film thickness of less than 25 Å. In some specific examples, the molybdenum nitride film of the present invention may have a resistivity between about 250 μΩ-cm and 400 μΩ-cm at an average film thickness of less than 50 Å.

在一些具體例中,根據本文所揭示之具體例沉積之氮化鉬膜可包含結晶膜或非晶形膜。在特定具體例中,其中氮化鉬膜為結晶的,氮化鉬膜可包含MoN相或Mo2 N相。在一些具體例中,氮化鉬膜可包含MoN相及Mo2 N相。In some specific examples, the molybdenum nitride film deposited according to the specific examples disclosed herein may include a crystalline film or an amorphous film. In a specific example, where the molybdenum nitride film is crystalline, the molybdenum nitride film may include a MoN phase or a Mo 2 N phase. In some specific examples, the molybdenum nitride film may include a MoN phase and a Mo 2 N phase.

更詳細而言,圖6繪示自根據本發明之具體例沉積之例示性氮化鉬膜獲得的x射線繞射(XRD)資料,其中標記為600之XRD資料包含藉由循環沉積製程100 (圖1)沉積之氮化鉬膜、標記為610之XRD資料包含藉由循環沉積方法200 (圖2)沉積之氮化鉬膜及標記為620之XRD資料包含藉由循環沉積製程300 (圖3)沉積之氮化鉬膜。圖6之XRD資料之檢查繪示在藉由製程100、200或300沉積之氮化鉬膜之XRD資料之間不存在顯著差異。然而,圖6之XRD資料之進一步檢查繪示XRD資料中的標記為630、640、650及660之四個主峰。標記為630之XRD峰對應於具有(200)結晶定向之MoN相及具有(111)結晶定向之Mo2 N相(200)。標記為640之XRD峰對應於具有(200)結晶定向之Mo2 N相。標記為650之XRD峰對應於具有(220)結晶定向之MoN相及具有(200)結晶定向之Mo2 N相。標記為660之XRD峰對應於具有(222)結晶定向之MoN相及具有(311)結晶定向之Mo2N相。In more detail, FIG. 6 shows x-ray diffraction (XRD) data obtained from an exemplary molybdenum nitride film deposited according to a specific example of the present invention, wherein the XRD data marked as 600 includes a cyclic deposition process 100 ( Figure 1) The deposited molybdenum nitride film, the XRD data labeled 610 include the molybdenum nitride film deposited by the cyclic deposition method 200 (Figure 2) and the XRD data labeled 620 include the XRD data of the cyclic deposition process 300 (Figure 3). ) Deposited molybdenum nitride film. The inspection of the XRD data of FIG. 6 shows that there is no significant difference between the XRD data of the molybdenum nitride film deposited by the process 100, 200, or 300. However, further examination of the XRD data in Figure 6 shows the four main peaks marked 630, 640, 650, and 660 in the XRD data. The XRD peak labeled 630 corresponds to the MoN phase with (200) crystal orientation and the Mo 2 N phase (200) with (111) crystal orientation. The XRD peak labeled 640 corresponds to the Mo 2 N phase with (200) crystal orientation. The XRD peak labeled 650 corresponds to the MoN phase with (220) crystal orientation and the Mo 2 N phase with (200) crystal orientation. The XRD peak labeled 660 corresponds to the MoN phase with (222) crystal orientation and the Mo2N phase with (311) crystal orientation.

在具體例中,其中所沉積之氮化鉬膜之組成包含至少MoN相及Mo2 N相,存在於氮化鉬膜內之MoN相相比於存在於氮化鉬膜內之Mo2 N相之比率(MoN:Mo2 N)可在本發明之循環沉積製程期間受控制。舉例而言,MoN:Mo2 N比率可藉由改變用於氮化鉬沉積之循環沉積參數來改變,包括(但不限於)沉積溫度、反應室壓力、前驅物濃度或另一氣體物種之添加。In a specific example, the composition of the deposited molybdenum nitride film includes at least MoN phase and Mo 2 N phase, and the MoN phase existing in the molybdenum nitride film is compared with the Mo 2 N phase existing in the molybdenum nitride film. The ratio (MoN:Mo 2 N) can be controlled during the cyclic deposition process of the present invention. For example, the MoN:Mo 2 N ratio can be changed by changing the cyclic deposition parameters for molybdenum nitride deposition, including (but not limited to) deposition temperature, reaction chamber pressure, precursor concentration or addition of another gas species .

在一些具體例中,氮化鉬之MoN相可優於氮化鉬之Mo2 N相,亦即,MoN:Mo2 N比率增加。作為一非限制性實施例,相對於Mo2 N相,MoN相可較佳藉由將還原劑添加至沉積製程中來沉積。In some specific examples, the MoN phase of molybdenum nitride may be better than the Mo 2 N phase of molybdenum nitride, that is, the ratio of MoN:Mo 2 N increases. As a non-limiting example, compared to the Mo 2 N phase, the MoN phase can be deposited preferably by adding a reducing agent to the deposition process.

本文所揭示之例示性循環沉積方法亦可沉積具有改良之平均r.m.s.表面粗糙度之氮化鉬膜。舉例而言,在一些具體例中,氮化鉬膜可具有小於0.30奈米、或小於0.25奈米、或小於0.20奈米、或小於0.10奈米、或甚至在0.10奈米與0.30奈米之間的平均r.m.s.表面粗糙度(Ra ) (沉積後)。沉積後之氮化鉬膜之平均r.m.s.表面粗糙度(Ra )可採用原子力顯微法(atomic force microscopy;AFM),例如藉由掃描約100 μm×100 μm之表面積來測定。The exemplary cyclic deposition method disclosed herein can also deposit molybdenum nitride films with improved average rms surface roughness. For example, in some specific examples, the molybdenum nitride film may have a thickness of less than 0.30 nanometers, or less than 0.25 nanometers, or less than 0.20 nanometers, or less than 0.10 nanometers, or even between 0.10 nanometers and 0.30 nanometers. Average rms surface roughness (R a ) between (after deposition). The average rms surface roughness (R a ) of the deposited molybdenum nitride film can be measured by atomic force microscopy (AFM), for example, by scanning a surface area of about 100 μm×100 μm.

在一些具體例中,氮化鉬膜之表面粗糙度可表示為氮化鉬膜之平均總厚度之百分比粗糙度。舉例而言,本發明之氮化鉬膜之百分比表面粗糙度可小於10%、或小於5%、或小於3%、或小於2%、或小於1.5%、或甚至小於1%。作為一非限制性實施例,根據本發明之具體例沉積之氮化鉬膜可具有約100 Å之平均膜厚度,其中氮化鉬膜具有小於4 Å之r.m.s.表面粗糙度(Ra )及小於4%之對應百分比表面粗糙度。In some specific examples, the surface roughness of the molybdenum nitride film can be expressed as the percentage roughness of the average total thickness of the molybdenum nitride film. For example, the percentage surface roughness of the molybdenum nitride film of the present invention can be less than 10%, or less than 5%, or less than 3%, or less than 2%, or less than 1.5%, or even less than 1%. As a non-limiting example, the molybdenum nitride film deposited according to a specific example of the present invention may have an average film thickness of about 100 Å, wherein the molybdenum nitride film has an rms surface roughness (R a ) less than 4 Å and less than 4% corresponds to the percentage surface roughness.

在一些具體例中,基板可包含介電質表面、半導體表面或金屬表面中之至少一者。如本文所用,術語「介電質表面」可指介電材料之表面,包括(但不限於)含矽介電材料(諸如,氧化矽、氮化矽、氮氧化矽、碳氧化矽以及其混合物)以及例如金屬氧化物。如本文所用,術語「金屬表面」可指包括金屬組分之表面,包括(但不限於)金屬表面、金屬氧化物表面、金屬矽化物表面、金屬氮化物表面及金屬碳化物表面。在一些具體例中,基板可包含介電質表面及金屬表面兩者,且本發明之循環沉積製程可用以將氮化鉬膜直接沉積於介電質表面及金屬表面兩者上,亦即在不使用介入晶核層之情況下。In some embodiments, the substrate may include at least one of a dielectric surface, a semiconductor surface, or a metal surface. As used herein, the term "dielectric surface" can refer to the surface of a dielectric material, including (but not limited to) silicon-containing dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and mixtures thereof ) And, for example, metal oxides. As used herein, the term "metal surface" may refer to a surface including a metal component, including but not limited to a metal surface, a metal oxide surface, a metal silicide surface, a metal nitride surface, and a metal carbide surface. In some embodiments, the substrate may include both a dielectric surface and a metal surface, and the cyclic deposition process of the present invention can be used to directly deposit a molybdenum nitride film on both the dielectric surface and the metal surface. Without using the intervening nucleus layer.

根據本發明之具體例沉積之氮化鉬膜可用於多種應用中。舉例而言,氮化鉬膜可用作障壁層材料以防止金屬物種擴散至層間介電質中,或用作襯料,或用作形成於半導體裝置結構上之閘極堆疊之一部分。The molybdenum nitride film deposited according to specific examples of the present invention can be used in a variety of applications. For example, the molybdenum nitride film can be used as a barrier layer material to prevent metal species from diffusing into the interlayer dielectric, or as a liner, or as a part of a gate stack formed on a semiconductor device structure.

作為一非限制性例示性具體例,根據本發明之具體例沉積之氮化鉬膜可用作後段製程(back-end-of-line;BEOL)金屬化應用中之障壁層,如圖7中所示。更詳細而言,圖7繪示部分製造之半導體裝置結構700,其包含基板702,基板可包括部分製造及/或製造之半導體裝置結構,諸如電晶體及記憶體元件(未圖示)。部分製造之半導體裝置結構700可包括形成於基板702上之介電材料704,材料可包含低介電常數材料,亦即低k介電質,諸如含矽介電質或金屬氧化物介電質。溝槽可形成於介電材料704中且障壁層706可安置於溝槽之表面上,此防止或實質上防止金屬互連材料708擴散至周圍介電材料704中。在本發明之一些具體例中,障壁層706可包含藉由本文所描述之沉積製程沉積之氮化鉬膜。As a non-limiting illustrative specific example, the molybdenum nitride film deposited according to the specific example of the present invention can be used as a barrier layer in back-end-of-line (BEOL) metallization applications, as shown in FIG. 7 Shown. In more detail, FIG. 7 shows a partially manufactured semiconductor device structure 700, which includes a substrate 702, which may include partially manufactured and/or manufactured semiconductor device structures, such as transistors and memory devices (not shown). The partially manufactured semiconductor device structure 700 may include a dielectric material 704 formed on the substrate 702. The material may include a low-k dielectric material, such as a silicon-containing dielectric material or a metal oxide dielectric material. . The trench may be formed in the dielectric material 704 and the barrier layer 706 may be disposed on the surface of the trench, which prevents or substantially prevents the metal interconnect material 708 from diffusing into the surrounding dielectric material 704. In some embodiments of the present invention, the barrier layer 706 may include a molybdenum nitride film deposited by the deposition process described herein.

部分製造之半導體結構700亦可包含用於電學上互連安置於基板702中/上之複數個裝置結構的金屬互連材料708。在一些具體例中,金屬互連材料708可包含銅或鈷。另外,罩蓋層710可安置於金屬互連材料708之上表面上。因此,參看圖7,半導體裝置結構700亦可包括直接安置於金屬互連材料708之上表面上的罩蓋層710。罩蓋層710可用以防止金屬互連材料708氧化,且重要地係防止金屬互連材料708擴散至在後續製造製程中(亦即,對於多層互連結構)形成於部分製造之半導體結構700上之額外介電材料中。在一些具體例中,金屬互連材料708、氮化鉬障壁層706及罩蓋層710可共同地形成用於安置於基板702中/上之複數個半導體裝置之電氣互連的電極。在一些具體例中,罩蓋層710可包含根據本發明之具體例沉積之氮化鉬膜。The partially fabricated semiconductor structure 700 may also include a metal interconnection material 708 for electrically interconnecting a plurality of device structures disposed in/on the substrate 702. In some embodiments, the metal interconnect material 708 may include copper or cobalt. In addition, the capping layer 710 may be disposed on the upper surface of the metal interconnect material 708. Therefore, referring to FIG. 7, the semiconductor device structure 700 may also include a cap layer 710 directly disposed on the upper surface of the metal interconnect material 708. The capping layer 710 can be used to prevent the metal interconnect material 708 from oxidizing, and it is important to prevent the metal interconnect material 708 from diffusing to be formed on the partially manufactured semiconductor structure 700 in the subsequent manufacturing process (ie, for the multilayer interconnect structure) The additional dielectric materials. In some embodiments, the metal interconnection material 708, the molybdenum nitride barrier layer 706, and the cap layer 710 can collectively form electrodes for electrical interconnection of a plurality of semiconductor devices disposed in/on the substrate 702. In some embodiments, the capping layer 710 may include a molybdenum nitride film deposited according to embodiments of the present invention.

作為另一非限制性實施例,本發明之氮化鉬膜可包含形成於半導體通道區上之閘極堆疊中之閘電極之至少一部分。更詳細而言,圖8繪示包括根據本發明之具體例沉積之氮化鉬膜的半導體裝置結構之橫剖面示意圖。半導體裝置結構800可包含電晶體結構,電晶體結構包括半導體主體816,半導體主體包括源極區802、汲極區804及安置於源極區802與汲極區804之間的半導體通道區806。As another non-limiting embodiment, the molybdenum nitride film of the present invention may include at least a part of the gate electrode in the gate stack formed on the semiconductor channel region. In more detail, FIG. 8 shows a schematic cross-sectional view of a semiconductor device structure including a molybdenum nitride film deposited according to a specific example of the present invention. The semiconductor device structure 800 may include a transistor structure including a semiconductor body 816 that includes a source region 802, a drain region 804, and a semiconductor channel region 806 disposed between the source region 802 and the drain region 804.

在一些具體例中,半導體裝置結構800可包含NMOS裝置,且半導體主體816及半導體通道區806兩者可為摻雜p型,且源極區802及汲極區804兩者可為摻雜n型。在替代性具體例中,半導體裝置結構800可包含PMOS裝置,且半導體主體816及半導體通道區806兩者可為摻雜n型,且源極區802及汲極區804兩者可為摻雜p型。在一些具體例中,半導體主體816可包含實質上單晶矽。In some embodiments, the semiconductor device structure 800 may include an NMOS device, and the semiconductor body 816 and the semiconductor channel region 806 may both be doped p-type, and both the source region 802 and the drain region 804 may be doped n type. In an alternative embodiment, the semiconductor device structure 800 may include a PMOS device, and both the semiconductor body 816 and the semiconductor channel region 806 may be doped n-type, and both the source region 802 and the drain region 804 may be doped p-type. In some embodiments, the semiconductor body 816 may include substantially single crystal silicon.

安置於半導體通道區806上方的為閘極堆疊808,其可包括閘極介電質809及閘電極811。在一些具體例中,閘極介電質可包含直接安置於半導體通道區806上之氧化矽中間層816及直接安置於中間層816上之高k介電層812。在本發明之一些具體例中,高k電介質層812可包含以下中之至少一者:氧化鉿(HfO2 )、氧化鉭(Ta2 O5 )、氧化鋯(ZrO2 )、氧化鈦(TiO2 )、矽酸鉿(HfSiOx )、氧化鑭(La2 O3 )或其混合物/層合物。Disposed above the semiconductor channel region 806 is a gate stack 808, which may include a gate dielectric 809 and a gate electrode 811. In some embodiments, the gate dielectric may include a silicon oxide intermediate layer 816 directly disposed on the semiconductor channel region 806 and a high-k dielectric layer 812 directly disposed on the intermediate layer 816. In some embodiments of the present invention, the high-k dielectric layer 812 may include at least one of the following: hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), hafnium silicate (HfSiO x ), lanthanum oxide (La 2 O 3 ) or a mixture/laminate thereof.

安置於閘極介電質809上方且在一些具體例中,直接安置於閘極介電質809上方的為閘電極811,閘電極可包含根據本發明之具體例沉積之氮化鉬膜810。直接安置於氮化鉬膜810上方的可為另一金屬膜814以使閘電極811完整,舉例而言,另一金屬膜814可包含過渡碳化物(例如,碳化鈦)或過渡氮化物(例如,氮化鈦)。The gate electrode 811 is arranged above the gate dielectric 809 and in some embodiments, the gate electrode 811 is arranged directly above the gate dielectric 809. The gate electrode may include a molybdenum nitride film 810 deposited according to an embodiment of the present invention. Directly disposed above the molybdenum nitride film 810 may be another metal film 814 to complete the gate electrode 811. For example, the other metal film 814 may include a transition carbide (e.g., titanium carbide) or a transition nitride (e.g., titanium carbide). , Titanium nitride).

在本發明之一些具體例中,安置於半導體通道區806上方之閘極堆疊808之有效功函數可藉由用以沉積氮化鉬膜810之沉積方法及氮化鉬膜810之平均膜厚度來調整。舉例而言,對於平均氮化鉬膜厚度小於50 Å、小於40 Å、小於30 Å、或小於20 Å、或小於15 Å,或在15 Å與50 Å之間而言,包含氮化鉬膜之閘極堆疊808之有效功函數可在約4 eV至約5 eV範圍內、或大於4 eV、或大於4.5 eV、或大於4.75 eV。In some embodiments of the present invention, the effective work function of the gate stack 808 disposed above the semiconductor channel region 806 can be determined by the deposition method used to deposit the molybdenum nitride film 810 and the average film thickness of the molybdenum nitride film 810 Adjustment. For example, for an average molybdenum nitride film thickness of less than 50 Å, less than 40 Å, less than 30 Å, or less than 20 Å, or less than 15 Å, or between 15 Å and 50 Å, the molybdenum nitride film is included The effective work function of the gate stack 808 can be in the range of about 4 eV to about 5 eV, or greater than 4 eV, or greater than 4.5 eV, or greater than 4.75 eV.

因此,在一些具體例中,氮化鉬膜包含形成於半導體通道區之閘極堆疊之一部分,其中在平均氮化鉬膜厚度小於50 Å、或小於40 Å、或小於30 Å、或小於20 Å、或小於20 Å、或小於15 Å、或在15 Å與50 Å之間下,閘極堆疊具有大於4.0 eV、或大於4.5 eV、或大於4.75 eV、或甚至大於4.9 eV、或在4 eV與5 eV之間的有效功函數。Therefore, in some specific examples, the molybdenum nitride film includes a portion of the gate stack formed in the semiconductor channel region, wherein the average thickness of the molybdenum nitride film is less than 50 Å, or less than 40 Å, or less than 30 Å, or less than 20 Å. Å, or less than 20 Å, or less than 15 Å, or between 15 Å and 50 Å, the gate stack has greater than 4.0 eV, or greater than 4.5 eV, or greater than 4.75 eV, or even greater than 4.9 eV, or less than 4 Effective work function between eV and 5 eV.

作為一非限制性實施例,圖9繪示包含根據本發明之具體例沉積之各種平均膜厚度之氮化鉬膜之閘極堆疊(安置於半導體通道區上方)的有效功函數。圖9之檢查表明,隨著氮化鉬層之平均膜厚度自約50 Å減小至15 Å,包括氮化鉬膜之閘極堆疊的對應有效功函數僅自約4.75 eV略微減小至約4.6 eV。因此,在本發明之一些具體例中,在平均氮化鉬膜厚度小於50 Å、或小於40 Å、或小於30 Å、或小於20 Å、或小於15 Å、或在15 Å與50 Å之間下,本發明之氮化鉬膜可包含具有大於4 eV、或大於4.25 eV、或大於4.5 eV、或大於4.75 eV、或大於4.8 eV、或在4 eV與4.8 eV之間、或在4.6 eV與4.75 eV之間的有效功函數的閘極堆疊之一部分。在一些具體例中,在平均氮化鉬膜厚度等於或小於50 Å下,安置於半導體通道區上方且包含氮化鉬膜之閘極堆疊具有大於4.75 eV之有效功函數。As a non-limiting example, FIG. 9 illustrates the effective work function of a gate stack (disposed above the semiconductor channel region) of a molybdenum nitride film of various average film thicknesses deposited according to a specific example of the present invention. The inspection of Figure 9 shows that as the average film thickness of the molybdenum nitride layer decreases from about 50 Å to 15 Å, the corresponding effective work function of the gate stack including the molybdenum nitride film only slightly decreases from about 4.75 eV to about 4.6 eV. Therefore, in some specific examples of the present invention, the average molybdenum nitride film thickness is less than 50 Å, or less than 40 Å, or less than 30 Å, or less than 20 Å, or less than 15 Å, or between 15 Å and 50 Å. From time to time, the molybdenum nitride film of the present invention may include a molybdenum nitride film having a temperature greater than 4 eV, or greater than 4.25 eV, or greater than 4.5 eV, or greater than 4.75 eV, or greater than 4.8 eV, or between 4 eV and 4.8 eV, or within 4.6 Part of the gate stack with an effective work function between eV and 4.75 eV. In some specific examples, when the average molybdenum nitride film thickness is equal to or less than 50 Å, the gate stack containing the molybdenum nitride film disposed above the semiconductor channel region has an effective work function greater than 4.75 eV.

作為另一非限制性實施例,圖10繪示包含利用例示性循環沉積製程300(圖3)沉積之不同平均膜厚度之氮化鉬膜之閘極堆疊的有效功函數。圖10之檢閱表明,隨著氮化鉬膜之平均膜厚度自約45 Å減小至15 Å,包括氮化鉬膜之閘極堆疊的對應有效功函數在約4.75 eV之值下保持實質上不變。因此,在一些具體例中,在平均氮化鉬膜厚度小於50 Å、或小於40 Å、或小於30 Å、或小於20 Å、或小於15 Å、或甚至在約15 Å與50 Å之間下,本發明之氮化鉬可包含具有大於4.6 eV、或大於4.75 eV、或大於4.8 eV、或大於4.9 eV、或大於5.0 eV、或在4.6 eV與4.9 eV之間、或甚至在4.75 eV與4.8 eV之間的閘極堆疊之一部分。As another non-limiting example, FIG. 10 illustrates the effective work function of a gate stack including molybdenum nitride films of different average film thicknesses deposited using an exemplary cyclic deposition process 300 (FIG. 3 ). The review of Figure 10 shows that as the average film thickness of the molybdenum nitride film decreases from about 45 Å to 15 Å, the corresponding effective work function of the gate stack including the molybdenum nitride film remains substantially at a value of about 4.75 eV constant. Therefore, in some specific examples, the average molybdenum nitride film thickness is less than 50 Å, or less than 40 Å, or less than 30 Å, or less than 20 Å, or less than 15 Å, or even between about 15 Å and 50 Å. Next, the molybdenum nitride of the present invention may include a molybdenum nitride having a value greater than 4.6 eV, or greater than 4.75 eV, or greater than 4.8 eV, or greater than 4.9 eV, or greater than 5.0 eV, or between 4.6 eV and 4.9 eV, or even 4.75 eV Part of the gate stack between 4.8 eV and 4.8 eV.

在一些裝置應用中,例如對於PMOS裝置結構,形成包含氮化鉬膜之閘極堆疊的能力可為合乎需要的,其中閘極堆疊之有效功函數實質上與氮化鉬膜之平均膜厚度無關。In some device applications, such as PMOS device structures, the ability to form gate stacks containing molybdenum nitride films may be desirable, where the effective work function of the gate stacks is substantially independent of the average film thickness of the molybdenum nitride film .

因此,在一些具體例中,閘極堆疊可包含平均膜厚度在約15 Å與45 Å之間的氮化鉬膜,其中閘極堆疊之有效功函數可具有實質上與氮化鉬膜之平均膜厚度無關的有效功函數。另外,對於平均膜厚度在約15 Å與45 Å之間,包含氮化鉬膜之閘極堆疊可包含約4.8 eV之實質上恆定的有效功函數。此外,閘極堆疊可包含藉由包含以下之循環沉積製程沉積之氮化鉬膜:使基板與鹵化鉬前驅物、氮前驅物及還原劑依序接觸,其中對於平均氮化鉬膜厚度在約15 Å與45 Å之間,該閘極堆疊包含約4.8 eV之實質上恆定的有效功函數。Therefore, in some specific examples, the gate stack may include a molybdenum nitride film with an average film thickness between about 15 Å and 45 Å, and the effective work function of the gate stack may be substantially equal to that of the molybdenum nitride film. Effective work function independent of film thickness. In addition, for an average film thickness between about 15 Å and 45 Å, the gate stack including the molybdenum nitride film may include a substantially constant effective work function of about 4.8 eV. In addition, the gate stack may include a molybdenum nitride film deposited by a cyclic deposition process including the following: contacting the substrate with a molybdenum halide precursor, a nitrogen precursor, and a reducing agent in sequence, wherein the average thickness of the molybdenum nitride film is about Between 15 Å and 45 Å, the gate stack contains a substantially constant effective work function of approximately 4.8 eV.

作為本發明之氮化鉬膜之另一非限制性應用,圖11繪示例示性半導體裝置結構之另一橫剖面示意圖,半導體裝置結構包括根據本發明之具體例沉積之氮化鉬膜,且尤其繪示FinFet半導體裝置結構。As another non-limiting application of the molybdenum nitride film of the present invention, FIG. 11 is another cross-sectional schematic diagram of an exemplary semiconductor device structure. The semiconductor device structure includes a molybdenum nitride film deposited according to a specific example of the present invention, and In particular, the structure of the FinFet semiconductor device is shown.

更詳細而言,圖11繪示包含例示性FinFET裝置結構的半導體裝置結構1100的非限制性實施例。半導體裝置結構1100可包含基板1102,基板可包含本體矽(Si)基板。基板1102可摻雜有p型摻雜物(對於NMOS型FinFET裝置)及/或摻雜有n型摻雜物(對於PMOS型FinFET裝置)。In more detail, FIG. 11 illustrates a non-limiting embodiment of a semiconductor device structure 1100 including an exemplary FinFET device structure. The semiconductor device structure 1100 may include a substrate 1102, and the substrate may include a bulk silicon (Si) substrate. The substrate 1102 may be doped with p-type dopants (for NMOS-type FinFET devices) and/or with n-type dopants (for PMOS-type FinFET devices).

半導體裝置結構1100亦可包含隔離區1104,隔離區可包含淺溝槽隔離(shallow trench isolation;STI)區。半導體裝置結構1100亦可包含在隔離區1104之頂表面上方延伸之鰭結構1106,鰭結構1106之一部分埋入包含半導體通道區之閘極堆疊1108下方。閘極介電質1110可安置於鰭結構1106之側壁上方且閘極介電質1110可包含氧化矽及/或高k介電材料。The semiconductor device structure 1100 may also include an isolation region 1104, and the isolation region may include a shallow trench isolation (STI) region. The semiconductor device structure 1100 may also include a fin structure 1106 extending above the top surface of the isolation region 1104, and a portion of the fin structure 1106 is buried under the gate stack 1108 including the semiconductor channel region. The gate dielectric 1110 may be disposed above the sidewall of the fin structure 1106 and the gate dielectric 1110 may include silicon oxide and/or high-k dielectric materials.

閘電極可安置於閘極介電質1110上以提供與半導體通道區之電接觸,且閘電極可包含根據本發明之具體例沉積之氮化鉬膜1112,以及可包含過渡金屬碳化物或過渡金屬氮化物之額外金屬膜1114。在本發明之一些具體例中,半導體裝置結構1100可進一步包含鄰近於半導體通道區之源極/汲極區1116。The gate electrode may be disposed on the gate dielectric 1110 to provide electrical contact with the semiconductor channel region, and the gate electrode may include the molybdenum nitride film 1112 deposited according to the embodiment of the present invention, and may include transition metal carbide or transition metal carbide. Additional metal film 1114 of metal nitride. In some embodiments of the present invention, the semiconductor device structure 1100 may further include a source/drain region 1116 adjacent to the semiconductor channel region.

作為本發明之氮化鉬膜之另一非限制性應用,圖12繪示例示性半導體裝置結構之另一示意圖,半導體裝置結構包括根據本發明之具體例沉積之氮化鉬膜,且尤其繪示環繞式閘極(GAA)半導體裝置結構。As another non-limiting application of the molybdenum nitride film of the present invention, FIG. 12 shows another schematic diagram of an exemplary semiconductor device structure. The semiconductor device structure includes a molybdenum nitride film deposited according to a specific example of the present invention, and particularly depicts Shows the structure of a surround gate (GAA) semiconductor device.

更詳細而言,半導體裝置結構1200可包含半導體基板1202及安置於基板1202上方之介電質膜1204。另外,GAA裝置結構可包含半導體線1206 (摻雜p型或n型),其中閘極介電質1208圍繞且包圍半導體線1206安置。閘電極可圍繞半導體線1206之區域安置,且可包含根據本發明之具體例沉積之氮化鉬膜1210。另外,閘電極可包含另一金屬膜1212,諸如過渡金屬碳化物或過渡金屬氮化物。In more detail, the semiconductor device structure 1200 may include a semiconductor substrate 1202 and a dielectric film 1204 disposed on the substrate 1202. In addition, the GAA device structure may include a semiconductor line 1206 (doped p-type or n-type), in which a gate dielectric 1208 is arranged around and surrounding the semiconductor line 1206. The gate electrode may be disposed around the area of the semiconductor wire 1206, and may include a molybdenum nitride film 1210 deposited according to an embodiment of the present invention. In addition, the gate electrode may include another metal film 1212, such as transition metal carbide or transition metal nitride.

本發明之具體例亦提供包括氮化鉬膜之半導體裝置結構。在一些具體例中,半導體裝置結構可包含:半導體通道區;及直接安置於半導體通道區上之閘極堆疊,其中閘極堆疊包含:直接安置於半導體通道區上之閘極介電質及包含直接安置於閘極介電質上之氮化鉬膜的閘電極。A specific example of the present invention also provides a semiconductor device structure including a molybdenum nitride film. In some specific examples, the semiconductor device structure may include: a semiconductor channel region; and a gate stack directly disposed on the semiconductor channel region, wherein the gate stack includes: a gate dielectric directly disposed on the semiconductor channel region and including The gate electrode of the molybdenum nitride film directly placed on the gate dielectric.

在一些具體例中,在平均氮化鉬膜厚度小於100 Å、或小於50 Å、或小於20 Å、或小於10 Å、或在10 Å與50 Å之間下,半導體裝置結構可包含可具有小於1000 μΩ-cm、或小於500 μΩ-cm、或小於250 μΩ-cm、或在250 μΩ-cm與1000 μΩ-cm之間的電阻率的氮化鉬膜。在一些具體例中,在平均膜厚度小於100 Å下,半導體裝置結構可包含可具有小於250 μΩ-cm之電阻率的氮化鉬膜。在一些具體例中,在平均膜厚度小於25 Å下,半導體裝置結構可包含可具有小於500 μΩ-cm之電阻率的氮化鉬膜。In some specific examples, when the average molybdenum nitride film thickness is less than 100 Å, or less than 50 Å, or less than 20 Å, or less than 10 Å, or between 10 Å and 50 Å, the semiconductor device structure may include A molybdenum nitride film with a resistivity of less than 1000 μΩ-cm, or less than 500 μΩ-cm, or less than 250 μΩ-cm, or between 250 μΩ-cm and 1000 μΩ-cm. In some specific examples, with an average film thickness of less than 100 Å, the semiconductor device structure may include a molybdenum nitride film that may have a resistivity of less than 250 μΩ-cm. In some embodiments, with an average film thickness of less than 25 Å, the semiconductor device structure may include a molybdenum nitride film that may have a resistivity of less than 500 μΩ-cm.

在一些具體例中,包括氮化鉬膜之半導體裝置結構可包含MoN相及Mo2 N相兩者。在一些具體例中,半導體裝置結構包含平均膜厚度小於40 Å、或小於30 Å、或小於20 Å、或小於15 Å、或在15 Å與40 Å之間的物理上連續的氮化鉬膜。在一些具體例中,半導體裝置結構可包含可為非晶形或結晶之氮化鉬膜。In some embodiments, the semiconductor device structure including the molybdenum nitride film may include both the MoN phase and the Mo 2 N phase. In some specific examples, the semiconductor device structure includes a physically continuous molybdenum nitride film with an average film thickness of less than 40 Å, or less than 30 Å, or less than 20 Å, or less than 15 Å, or between 15 Å and 40 Å . In some embodiments, the semiconductor device structure may include a molybdenum nitride film that may be amorphous or crystalline.

在一些具體例中,包括氮化鉬膜之半導體裝置結構可包含PMOS功函數金屬裝置結構、FinFET半導體裝置結構或環繞式閘極半導體裝置結構。In some embodiments, the semiconductor device structure including the molybdenum nitride film may include a PMOS work function metal device structure, a FinFET semiconductor device structure, or a wrap-around gate semiconductor device structure.

本發明之具體例亦可包括經組態以用於沉積本發明之氮化鉬膜之反應系統。更詳細而言,圖13示意性地繪示反應系統1300,其包括反應室1302,反應室進一步包括用於在預定壓力、溫度及環境條件下保持基板(未圖示)且用於將基板選擇性地暴露於各種氣體的機構。前驅反應物源1304可藉由管道或其他適當構件1304A耦接至反應室1302,且可進一步耦接至歧管、閥控制系統、質量流量控制系統或用以控制源自前驅反應物源1304之氣態前驅物。藉由前驅反應物源1304供應之前驅物(未圖示),反應物(未圖示)在室溫及標準大氣壓條件下可為液體或固體。此類前驅物可在反應物源真空容器內汽化,反應物源真空容器可維持處於或高於前驅物源室內之汽化溫度。在此類具體例中,汽化前驅物可與運載氣體(例如不活動或惰性氣體)一起輸送,且隨後經由管道1304A饋入反應室1302中。在其他具體例中,前驅物在標準條件下可為蒸氣。在此類具體例中,前驅物並不需要汽化且可能不需要運載氣體。舉例而言,在一個具體例中,前驅物可儲存於貯氣缸中。反應系統1300亦可包括額外前驅反應物源,諸如前驅反應物源1306及1308,其亦可藉由如上文所描述之管道1306A及1308A耦接至反應室。在一些具體例中,前驅反應物源1304可包含鹵化鉬,前驅反應物源1306可包含氮前驅物,且前驅反應物源1308可包含還原劑。Specific examples of the present invention may also include a reaction system configured to deposit the molybdenum nitride film of the present invention. In more detail, FIG. 13 schematically illustrates a reaction system 1300, which includes a reaction chamber 1302, and the reaction chamber further includes a substrate for holding a substrate (not shown) under predetermined pressure, temperature and environmental conditions and for selecting a substrate Mechanisms that are sexually exposed to various gases. The precursor reactant source 1304 can be coupled to the reaction chamber 1302 by pipes or other suitable components 1304A, and can be further coupled to a manifold, a valve control system, a mass flow control system, or used to control the source of the precursor reactant 1304. Gaseous precursors. The precursor (not shown) is supplied by the precursor reactant source 1304, and the reactant (not shown) can be liquid or solid at room temperature and standard atmospheric pressure. Such precursors can be vaporized in the reactant source vacuum container, and the reactant source vacuum container can be maintained at or higher than the vaporization temperature in the precursor source chamber. In such a specific example, the vaporized precursor can be transported with a carrier gas (eg, inactive or inert gas), and then fed into the reaction chamber 1302 via the pipe 1304A. In other specific examples, the precursor may be vapor under standard conditions. In such specific cases, the precursor does not need to be vaporized and may not require a carrier gas. For example, in one specific example, the precursor can be stored in a storage cylinder. The reaction system 1300 may also include additional precursor reactant sources, such as precursor reactant sources 1306 and 1308, which may also be coupled to the reaction chamber through the pipes 1306A and 1308A as described above. In some embodiments, the precursor reactant source 1304 may include molybdenum halide, the precursor reactant source 1306 may include a nitrogen precursor, and the precursor reactant source 1308 may include a reducing agent.

吹掃氣體源1310亦可經由管道1310A耦接至反應室1302,且選擇性地將各種惰性或稀有氣體供應至反應室1302以輔助自反應室移除前驅氣體或廢氣。可供應之各種惰性或稀有氣體可來源於固體、液體或儲存之氣態形式。The purge gas source 1310 can also be coupled to the reaction chamber 1302 via a pipe 1310A, and can selectively supply various inert or rare gases to the reaction chamber 1302 to assist in removing the precursor gas or exhaust gas from the reaction chamber. Various inert or rare gases can be supplied from solid, liquid or stored gaseous forms.

圖13之反應系統1300亦可包含提供電子電路及機械組件以選擇性地操作閥、歧管、泵及反應系統1300中所包括之其他設備的系統操作及控制機構1312。此類電路及組件操作以自各別前驅物來源1304、1306、1308及吹掃氣體源1310引入前驅物、吹掃氣體。系統操作及控制機構1312亦控制氣體脈衝序列之時序、基板及反應室之溫度、反應室之壓力及提供反應系統1300之恰當操作所需的各種其他操作。操作及控制機構1312可包括控制軟體及電學上或氣動控制閥以控制前驅物、反應物及吹掃氣體流入反應室1302及流出該反應室。控制系統可包括執行某些任務之模組,諸如軟體或硬體組件,例如,FPGA或ASIC。模組可有利地經組態以駐留於控制系統之可定址儲存媒體上且經組態以執行一或多個程序。The reaction system 1300 of FIG. 13 may also include a system operation and control mechanism 1312 that provides electronic circuits and mechanical components to selectively operate valves, manifolds, pumps, and other equipment included in the reaction system 1300. Such circuits and components operate to introduce precursors and purge gas from respective precursor sources 1304, 1306, 1308 and purge gas source 1310. The system operation and control mechanism 1312 also controls the timing of the gas pulse sequence, the temperature of the substrate and the reaction chamber, the pressure of the reaction chamber, and provides various other operations required for the proper operation of the reaction system 1300. The operation and control mechanism 1312 may include control software and electrical or pneumatic control valves to control the flow of precursors, reactants, and purge gas into and out of the reaction chamber 1302. The control system may include modules that perform certain tasks, such as software or hardware components, for example, FPGA or ASIC. The module can advantageously be configured to reside on the addressable storage medium of the control system and configured to execute one or more programs.

熟習相關技術者瞭解,本發明反應系統之其他組態為可能的,包括不同數目及種類之前驅反應物源及吹掃氣體源。此外,此類人員亦將瞭解,存在閥、管道、前驅物源、吹掃氣體源之許多配置,其可用以實現將氣體選擇性地饋入反應室1302中之目標。此外,作為反應系統之示意性表示,為簡化圖示起見,已省略許多組件,且此類組件可包括例如各種閥、歧管、純化器、加熱器、容器、通風口及/或旁路。Those familiar with the relevant technology will understand that other configurations of the reaction system of the present invention are possible, including different numbers and types of precursor reactant sources and purge gas sources. In addition, such persons will also understand that there are many configurations of valves, pipes, precursor sources, and purge gas sources that can be used to achieve the goal of selectively feeding gas into the reaction chamber 1302. In addition, as a schematic representation of the reaction system, in order to simplify the illustration, many components have been omitted, and such components may include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and/or bypasses. .

上文所描述之本發明之例示性具體例並不限制本發明之範疇,因為此等具體例僅為本發明之具體例之實施例,本發明之範疇由所附申請專利範圍及其法定等效物定義。任何等效具體例意欲處於本發明之範疇內。實際上,除本文中所示及所描述之彼等之外,本發明之各種修改(諸如所描述之元件的替代性適用組合)根據描述對熟習本技藝者而言可變得顯而易見。此類修改及具體例亦意欲屬於所附申請專利範圍之範疇內。The illustrative specific examples of the present invention described above do not limit the scope of the present invention, because these specific examples are only examples of specific embodiments of the present invention, and the scope of the present invention is determined by the scope of the attached patent application and its statutory, etc. Definition of effect. Any equivalent specific examples are intended to be within the scope of the present invention. In fact, in addition to those shown and described herein, various modifications of the present invention (such as alternative applicable combinations of the described elements) may become apparent to those skilled in the art based on the description. Such modifications and specific examples are also intended to fall within the scope of the attached patent application.

100:例示性原子層沉積製程/例示性氮化鉬沉積製程/例示性循環沉積製程/循環沉積製程/例示性製程/製程 105:循環沉積階段 110、120、130、150:製程框 140:決策閘 200:例示性循環沉積製程/例示性製程/循環沉積製程/製程 205:循環沉積階段 210、220、230、250:製程框 240:決策閘 300:例示性循環沉積製程/例示性製程/循環沉積製程/製程 305:循環沉積階段 310、320、330、340、360:製程框 350:決策閘 400、410、420、500、510、520:資料 600、610、620:XRD資料 630、640、650、660:主峰/XRD峰 700:半導體裝置結構/半導體結構 702:基板 704:介電材料/周圍介電材料 706:障壁層/氮化鉬障壁層 708:金屬互連材料 710:罩蓋層 800:半導體裝置結構 802:源極區 804:汲極區 806:半導體通道區 808:閘極堆疊 809:閘極介電質 810:氮化鉬膜 811:閘電極 812:高k介電層 814:另一金屬膜 816:半導體主體/氧化矽介面層/介面層 1100:半導體裝置結構 1102:基板 1104:隔離區 1106:鰭結構 1108:閘極堆疊 1110:閘極介電質 1112:氮化鉬膜 1114:額外金屬膜 1116:源極/汲極區 1200:半導體裝置結構 1202:半導體基板/基板 1204:介電質膜 1206:半導體線 1208:閘極介電質 1210:氮化鉬膜 1212:另一金屬膜 1300:反應系統 1302:反應室 1304、1306、1308:前驅反應物源/前驅物源 1304A、1306A、1308A、1310A:管道 1310:吹掃氣體源 1312:系統操作及控制機構/操作及控制機構100: Exemplary Atomic Layer Deposition Process / Exemplary Molybdenum Nitride Deposition Process / Exemplary Cyclic Deposition Process / Cyclic Deposition Process / Exemplary Process / Process 105: cyclic deposition stage 110, 120, 130, 150: process frame 140: Decision Gate 200: Exemplary Cyclic Deposition Process/Exemplary Process/Cyclic Deposition Process/Process 205: Cyclic Deposition Stage 210, 220, 230, 250: process frame 240: Decision Gate 300: Exemplary Cyclic Deposition Process / Exemplary Process / Cyclic Deposition Process / Process 305: Cyclic Deposition Stage 310, 320, 330, 340, 360: process frame 350: Decision Gate 400, 410, 420, 500, 510, 520: data 600, 610, 620: XRD data 630, 640, 650, 660: main peak/XRD peak 700: semiconductor device structure/semiconductor structure 702: Substrate 704: Dielectric material/surrounding dielectric material 706: barrier layer/molybdenum nitride barrier layer 708: Metal Interconnect Materials 710: cover layer 800: Semiconductor device structure 802: Source Region 804: Drain Area 806: semiconductor channel area 808: gate stack 809: gate dielectric 810: Molybdenum Nitride Film 811: gate electrode 812: High-k dielectric layer 814: another metal film 816: semiconductor body/silicon oxide interface layer/interface layer 1100: Semiconductor device structure 1102: substrate 1104: Quarantine 1106: Fin structure 1108: gate stack 1110: gate dielectric 1112: Molybdenum nitride film 1114: Extra metal film 1116: source/drain region 1200: Semiconductor device structure 1202: Semiconductor substrate/substrate 1204: Dielectric film 1206: Semiconductor wire 1208: gate dielectric 1210: Molybdenum nitride film 1212: another metal film 1300: reaction system 1302: reaction chamber 1304, 1306, 1308: precursor source/precursor source 1304A, 1306A, 1308A, 1310A: pipeline 1310: purge gas source 1312: System operation and control mechanism/operation and control mechanism

儘管本說明書以特別指出且明確主張視為本發明之具體例的申請專利範圍作結,但在結合附圖理解時可自本發明之具體例之某些實施例的描述更容易地確定本發明之具體例的優點,在該等附圖中:Although this specification ends with the scope of the patent application that specifically points out and clearly claims to be regarded as specific examples of the present invention, the present invention can be more easily determined from the description of certain embodiments of the specific examples of the present invention when understood in conjunction with the accompanying drawings. The advantages of the specific examples are shown in the drawings:

圖1繪示例示性流程,其表明用於沉積根據本發明之具體例之氮化鉬膜的循環沉積製程;Figure 1 depicts an exemplary flow chart showing a cyclic deposition process for depositing a molybdenum nitride film according to a specific example of the present invention;

圖2繪示例示性流程,其表明用於沉積根據本發明之具體例之氮化鉬膜的額外循環沉積製程;FIG. 2 is an exemplary flow chart showing an additional cyclic deposition process for depositing a molybdenum nitride film according to a specific example of the present invention;

圖3繪示例示性流程,其表明用於沉積根據本發明之具體例之氮化鉬膜的另一循環沉積製程;FIG. 3 is an exemplary flow chart showing another cyclic deposition process for depositing a molybdenum nitride film according to a specific example of the present invention;

圖4繪示根據本發明之具體例沉積的呈各種厚度之多個氮化鉬膜的電阻率;4 shows the resistivity of a plurality of molybdenum nitride films of various thicknesses deposited according to a specific example of the present invention;

圖5繪示與採用四氯化鈦前驅物沉積之不同厚度之氮化鈦膜的電阻率相比,直接沉積於介電質上之不同厚度之多個氮化鉬膜的電阻率;FIG. 5 shows the resistivity of multiple molybdenum nitride films of different thicknesses deposited directly on the dielectric compared with the resistivities of titanium nitride films of different thicknesses deposited using a titanium tetrachloride precursor;

圖6繪示自根據本發明之具體例沉積之例示性氮化鉬膜獲得的x射線繞射(XRD)資料;Figure 6 shows x-ray diffraction (XRD) data obtained from an exemplary molybdenum nitride film deposited according to a specific example of the present invention;

圖7繪示根據本發明之具體例沉積的包括氮化鉬膜之例示性半導體裝置結構的橫剖面示意圖;7 is a schematic cross-sectional view of an exemplary semiconductor device structure including a molybdenum nitride film deposited according to a specific example of the present invention;

圖8繪示根據本發明之具體例的包括氮化鉬膜之額外半導體裝置結構的橫剖面示意圖;8 shows a schematic cross-sectional view of an additional semiconductor device structure including a molybdenum nitride film according to a specific example of the present invention;

圖9繪示根據本發明之具體例沉積的包括各種厚度之氮化鉬膜的各種閘極堆疊的有效功函數;9 illustrates the effective work functions of various gate stacks including various thicknesses of molybdenum nitride films deposited according to a specific example of the present invention;

圖10繪示根據本發明之具體例沉積的各種厚度之其他氮化鉬膜的有效功函數;FIG. 10 illustrates the effective work function of other molybdenum nitride films of various thicknesses deposited according to specific examples of the present invention;

圖11繪示根據本發明之具體例的包括氮化鉬膜之例示性半導體裝置結構的示意圖;11 is a schematic diagram showing the structure of an exemplary semiconductor device including a molybdenum nitride film according to a specific example of the present invention;

圖12繪示根據本發明之具體例的包括氮化鉬膜之例示性半導體裝置結構的另一示意圖;及FIG. 12 shows another schematic diagram of an exemplary semiconductor device structure including a molybdenum nitride film according to a specific example of the present invention; and

圖13繪示根據本發明之具體例的經組態用於沉積氮化鉬膜之反應系統的示意圖。FIG. 13 shows a schematic diagram of a reaction system configured for depositing a molybdenum nitride film according to a specific example of the present invention.

100:製程 100: Process

105:循環沉積階段 105: cyclic deposition stage

110、120、130、150:製程框 110, 120, 130, 150: process frame

140:決策閘 140: Decision Gate

Claims (39)

一種用於藉由循環沉積製程將氮化鉬膜沉積於基板表面上之方法,該方法包含: 將一基板提供至一反應室中;及 藉由執行循環沉積製程之一或多個單元沉積循環而將一氮化鉬膜直接沉積於該基板表面上,其中一單元沉積循環包含: 使該基板與包含一鉬前驅物之一第一氣相反應物接觸;及 使該基板與包含一氮前驅物之一第二氣相反應物接觸。A method for depositing a molybdenum nitride film on the surface of a substrate by a cyclic deposition process, the method comprising: Providing a substrate into a reaction chamber; and A molybdenum nitride film is deposited directly on the surface of the substrate by performing one or more unit deposition cycles of a cyclic deposition process, wherein a unit deposition cycle includes: Contacting the substrate with a first gas phase reactant containing a molybdenum precursor; and The substrate is contacted with a second gas phase reactant containing a nitrogen precursor. 如請求項1之方法,其中,該單元沉積循環進一步包含使該基板與包含一還原劑之一第三氣相反應物接觸。The method of claim 1, wherein the unit deposition cycle further comprises contacting the substrate with a third gas phase reactant containing a reducing agent. 如請求項2之方法,其中,該基板與該氮前驅物及該還原劑同時接觸。The method of claim 2, wherein the substrate is in contact with the nitrogen precursor and the reducing agent at the same time. 如請求項2之方法,其中,在使該基板與該氮前驅物接觸與使該基板與該還原劑接觸之該等製程之間執行吹掃循環。The method of claim 2, wherein a purge cycle is performed between the processes of contacting the substrate with the nitrogen precursor and contacting the substrate with the reducing agent. 如請求項2之方法,其中,該還原劑包含以下中之至少一者:分子氫(H2 )、原子氫(H)、合成氣體(H2 +N2 )、氨氣(NH3 )、肼(N2 H4 )、肼衍生物、氫基電漿、醇、醛、羧酸、硼烷、胺或矽烷。The method of claim 2, wherein the reducing agent includes at least one of the following: molecular hydrogen (H 2 ), atomic hydrogen (H), synthesis gas (H 2 +N 2 ), ammonia (NH 3 ), Hydrazine (N 2 H 4 ), hydrazine derivatives, hydrogen-based plasma, alcohol, aldehyde, carboxylic acid, borane, amine or silane. 如請求項1之方法,其中,該氮前驅物包含以下中之至少一者:分子氮(N2 )、氨氣(NH3 )、肼(N2 H4 )、肼衍生物或氮基電漿。The method of claim 1, wherein the nitrogen precursor comprises at least one of the following: molecular nitrogen (N 2 ), ammonia (NH 3 ), hydrazine (N 2 H 4 ), hydrazine derivatives, or nitrogen-based electricity Pulp. 如請求項1之方法,其進一步包含將該基板加熱至小於450℃之沉積溫度。The method of claim 1, further comprising heating the substrate to a deposition temperature of less than 450°C. 如請求項1之方法,其中,該鉬前驅物包含一鹵氧化鉬前驅物。The method of claim 1, wherein the molybdenum precursor comprises a molybdenum oxyhalide precursor. 如請求項8之方法,其中,該氯氧化鉬前驅物包含以下中之至少一者:三氯氧化鉬(V)(MoOCl3 )、四氯氧化鉬(VI)(MoOCl4 )或二氯二氧化鉬(IV)(MoO2 Cl2 )。The method of claim 8, wherein the molybdenum oxychloride precursor comprises at least one of the following: molybdenum trichloride (V) (MoOCl 3 ), molybdenum tetrachloride (VI) (MoOCl 4 ), or dichlorodichloride Molybdenum (IV) oxide (MoO 2 Cl 2 ). 如請求項1之方法,其中,該鉬前驅物包含以下中之至少一者:五氯化鉬(MoCl5 )或六氯化鉬(MoCl6 )。The method of claim 1, wherein the molybdenum precursor comprises at least one of the following: molybdenum pentachloride (MoCl 5 ) or molybdenum hexachloride (MoCl 6 ). 如請求項1之方法,其中,該鉬前驅物包含以下中之至少一者:Mo(NMe2 )4 、Mo(NEt2 )4 、Mo2 (NMe2 )6 、Mo(tBuN)2 (NMe2 )2 、Mo(tBuN)2 (NEt2 )2 、Mo(NEtMe)4 、Mo(NtBu)2 (StBu)2 、Mo(NtBu)2 (iPr2 AMD)2 Mo(thd)3 、MoO2 (acac)、MoO2 (thd)2 、MoO2 (iPr2 AMD)2 Mo(CO)6 Mo(Cp)2 H2 、Mo(iPrCp)2 H2 、Mo(η6 -乙苯)2 、MoCp(CO)23 -烯丙基)及MoCp(CO)2 (NO)。Such as the method of claim 1, wherein the molybdenum precursor contains at least one of the following: Mo(NMe 2 ) 4 , Mo(NEt 2 ) 4 , Mo 2 (NMe 2 ) 6 , Mo(tBuN) 2 (NMe 2 ) 2 , Mo(tBuN) 2 (NEt 2 ) 2 , Mo(NEtMe) 4 , Mo(NtBu) 2 (StBu) 2 , Mo(NtBu) 2 (iPr 2 AMD) 2 Mo(thd) 3 , MoO 2 (acac), MoO 2 (thd) 2 , MoO 2 (iPr 2 AMD) 2 Mo(CO) 6 , Mo(Cp) 2 H 2 , Mo(iPrCp) 2 H 2 , Mo(η 6 -ethylbenzene) 2 , MoCp(CO) 23 -allyl) and MoCp(CO) 2 (NO). 如請求項1之方法,其中,該氮化鉬膜在小於50 Å之平均氮化鉬膜厚度下具有小於750 μΩ-cm之電阻率。The method of claim 1, wherein the molybdenum nitride film has a resistivity of less than 750 μΩ-cm at an average molybdenum nitride film thickness of less than 50 Å. 如請求項1之方法,其中,該氮化鉬膜在小於100 Å之平均氮化鉬膜厚度下具有小於250 μΩ-cm之電阻率。The method of claim 1, wherein the molybdenum nitride film has a resistivity of less than 250 μΩ-cm at an average molybdenum nitride film thickness of less than 100 Å. 如請求項1之方法,其中,該氮化鉬膜在小於25 Å之平均氮化鉬膜厚度下具有小於400 μΩ-cm之電阻率。The method of claim 1, wherein the molybdenum nitride film has a resistivity of less than 400 μΩ-cm at an average molybdenum nitride film thickness of less than 25 Å. 如請求項1之方法,其中,該氮化鉬膜具有小於1.5%之百分比粗糙度。The method of claim 1, wherein the molybdenum nitride film has a percentage roughness of less than 1.5%. 如請求項1之方法,其中,該氮化鉬膜之組成包含一MoN相及一Mo2 N相兩者。The method of claim 1, wherein the composition of the molybdenum nitride film includes both a MoN phase and a Mo 2 N phase. 如請求項1之方法,其中,該氮化鉬膜直接沉積於一介電質表面上。The method of claim 1, wherein the molybdenum nitride film is directly deposited on a dielectric surface. 如請求項1之方法,其中,該氮化鉬膜在小於40 Å之平均膜厚度下為物理上連續的。The method of claim 1, wherein the molybdenum nitride film is physically continuous at an average film thickness of less than 40 Å. 如請求項1之方法,其中,該氮化鉬膜包含安置於一半導體通道區上方之一閘極堆疊之一部分,其中在小於50 Å之平均氮化鉬膜厚度下,該閘極堆疊具有大於4.6 eV之有效功函數。The method of claim 1, wherein the molybdenum nitride film includes a portion of a gate stack disposed above a semiconductor channel region, wherein at an average molybdenum nitride film thickness of less than 50 Å, the gate stack has a thickness greater than Effective work function of 4.6 eV. 如請求項1之方法,其中,該氮化鉬膜包含安置於一半導體通道區上方之一閘極堆疊之一部分,其中在小於50 Å之平均氮化鉬膜厚度下,該閘極堆疊具有大於4.75 eV之有效功函數。The method of claim 1, wherein the molybdenum nitride film includes a portion of a gate stack disposed above a semiconductor channel region, wherein at an average molybdenum nitride film thickness of less than 50 Å, the gate stack has a thickness greater than Effective work function of 4.75 eV. 如請求項1之方法,其中,該氮化鉬膜包含安置於一半導體通道區上方之一閘極堆疊之一部分,其中在約15 Å與50 Å之間的平均氮化鉬膜厚度下,該閘極堆疊具有在約4.6 eV與4.75 eV之間的有效功函數。The method of claim 1, wherein the molybdenum nitride film includes a portion of a gate stack disposed above a semiconductor channel region, wherein at an average thickness of the molybdenum nitride film between about 15 Å and 50 Å, the molybdenum nitride film The gate stack has an effective work function between about 4.6 eV and 4.75 eV. 如請求項2之方法,其中,該氮化鉬膜包含安置於一半導體通道區上方之一閘極堆疊之一部分,其中在約15 Å與50 Å之間的平均氮化鉬膜厚度下,該閘極堆疊具有約4.75 eV之實質上恆定的有效功函數。The method of claim 2, wherein the molybdenum nitride film includes a portion of a gate stack disposed above a semiconductor channel region, wherein at an average thickness of the molybdenum nitride film between about 15 Å and 50 Å, the molybdenum nitride film The gate stack has a substantially constant effective work function of about 4.75 eV. 一種半導體裝置結構,包含: 一半導體通道區;及 直接安置於該半導體通道區上之一閘極堆疊,其中該閘極堆疊包含: 一閘極介電質,安置於該半導體通道區上;及 一閘電極,包含安置於該閘極介電質上之一氮化鉬膜。A structure of a semiconductor device, including: A semiconductor channel area; and A gate stack directly arranged on the semiconductor channel region, wherein the gate stack includes: A gate dielectric is arranged on the semiconductor channel region; and A gate electrode includes a molybdenum nitride film arranged on the gate dielectric. 如請求項23之半導體裝置結構,其中,該閘極介電質直接安置於該半導體通道區上。The semiconductor device structure of claim 23, wherein the gate dielectric is directly disposed on the semiconductor channel region. 如請求項23之半導體裝置結構,其中,該氮化鉬膜直接安置於該閘極介電質上。The semiconductor device structure of claim 23, wherein the molybdenum nitride film is directly disposed on the gate dielectric. 如請求項23之半導體裝置結構,其中,該氮化鉬膜在小於100 Å之平均氮化鉬膜厚度下具有小於750 μΩ-cm之電阻率。The semiconductor device structure of claim 23, wherein the molybdenum nitride film has a resistivity of less than 750 μΩ-cm at an average molybdenum nitride film thickness of less than 100 Å. 如請求項23之半導體裝置結構,其中,該氮化鉬膜在小於100 Å之平均氮化鉬膜厚度下具有小於250 μΩ-cm之電阻率。The semiconductor device structure of claim 23, wherein the molybdenum nitride film has a resistivity of less than 250 μΩ-cm at an average molybdenum nitride film thickness of less than 100 Å. 如請求項23之半導體裝置結構,其中,該氮化鉬膜在小於25 Å之平均氮化鉬膜厚度下具有小於500 μΩ-cm之電阻率。The semiconductor device structure of claim 23, wherein the molybdenum nitride film has a resistivity of less than 500 μΩ-cm at an average molybdenum nitride film thickness of less than 25 Å. 如請求項23之半導體裝置結構,其中,該氮化鉬膜具有包含一MoN相及一Mo2 N相之組成。The semiconductor device structure of claim 23, wherein the molybdenum nitride film has a composition including a MoN phase and a Mo 2 N phase. 如請求項23之半導體裝置結構,其中,該氮化鉬膜為具有小於40 Å之平均膜厚度之物理上連續的氮化鉬膜。The semiconductor device structure of claim 23, wherein the molybdenum nitride film is a physically continuous molybdenum nitride film having an average film thickness of less than 40 Å. 如請求項23之半導體裝置結構,其中,該氮化鉬膜為非晶形的。The semiconductor device structure of claim 23, wherein the molybdenum nitride film is amorphous. 如請求項23之半導體裝置結構,其中,該氮化鉬膜為結晶的。The semiconductor device structure of claim 23, wherein the molybdenum nitride film is crystalline. 如請求項23之半導體裝置結構,其中,在小於50 Å之平均氮化鉬膜厚度下,該閘極堆疊具有大於4.6 eV之有效功函數。Such as the semiconductor device structure of claim 23, wherein the gate stack has an effective work function greater than 4.6 eV at an average molybdenum nitride film thickness of less than 50 Å. 如請求項23之半導體裝置結構,其中,在等於或小於50 Å之平均氮化鉬膜厚度下,該閘極堆疊具有大於4.75 eV之有效功函數。Such as the semiconductor device structure of claim 23, wherein the gate stack has an effective work function greater than 4.75 eV at an average molybdenum nitride film thickness equal to or less than 50 Å. 如請求項23之半導體裝置結構,其中,在15 Å與50 Å之間的平均氮化鉬膜厚度下,該閘極堆疊具有約4.75 eV之實質上恆定的有效功函數。Such as the semiconductor device structure of claim 23, wherein, at an average molybdenum nitride film thickness between 15 Å and 50 Å, the gate stack has a substantially constant effective work function of about 4.75 eV. 如請求項23之半導體裝置結構,其中,該半導體通道區包含一FinFET半導體裝置結構之一部分。The semiconductor device structure of claim 23, wherein the semiconductor channel region includes a part of a FinFET semiconductor device structure. 如請求項23之半導體裝置結構,其中,該半導體通道區包含一環繞式閘極半導體裝置結構之一部分。The semiconductor device structure of claim 23, wherein the semiconductor channel region includes a part of a wrap-around gate semiconductor device structure. 一種反應系統,經組態以執行請求項1之方法。A reaction system configured to perform the method of request 1. 一種半導體裝置結構,其包括藉由請求項1之方法沉積之一氮化鉬膜。A semiconductor device structure including a molybdenum nitride film deposited by the method of claim 1.
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