TW202107720A - Solar cell, and surface passivation structure and surface passivation method thereof - Google Patents

Abstract

A solar cell, and a surface passivation structure and a surface passivation method thereof are disclosed. The surface passivation structure of the solar cell is disposed on at least one of a front surface and a rear surface of a semiconductor substrate. The surface passivation structure includes a main passivation layer and an auxiliary passivation stacked layer, in which the main passivation layer is disposed between the semiconductor substrate and the auxiliary passivation stacked layer. The auxiliary passivation stacked layer includes a plurality of films. The surface passivation structure includes at least three heterointerfaces therein. In the surface passivation method of the solar cell, after the formations of the main passivation layer and the auxiliary passivation stacked layer, an annealing process is performed to passivate the surface and interior defects of the semiconductor substrate.

Description

Solar cell, its surface passivation structure and its surface passivation method

The invention relates to a solar cell, its surface passivation structure and its surface passivation method, in particular to a solar cell with good passivation effect, its surface passivation structure and its surface passivation method.

Solar cells are elements used to convert light energy into electrical energy. The photoelectric conversion efficiency of a solar cell is affected by several factors, including the proportion of incident light absorbed by the solar cell substrate and the recombination rate of carriers in the solar cell. Each electron-hole pair recombination will eliminate charge carriers and reduce the photoelectric conversion efficiency of the solar cell.

Carrier recombination is related to defects existing in or on the surface of the silicon substrate. The dangling bonds (unsuspended chemical bonds) on silicon atoms are one of the defects on the surface of the silicon substrate. In addition, if there is excessive charge (for example, positive charge) in the dielectric layer or passivation layer adjacent to the surface of the silicon substrate, it will accumulate excessive negative charge on the surface of the solar cell silicon substrate (for example, p-type silicon). The charge forms a shunt current, which reduces the lifetime of carriers and reduces the efficiency of solar cells.

In order to improve the photoelectric conversion efficiency of the solar cell, a passivation layer can be introduced to reduce the carrier recombination rate on the surface. One way to improve the passivation effect of the passivation layer is to have enough hydrogen (H) source in the passivation layer for passivation of the inner and surface of the silicon substrate. Another way to improve the function of the passivation layer is to make the passivation layer have a charge that is beneficial to passivate the silicon substrate or reduce the amount of undesired charges to avoid the formation of shunt current.

The passivation layer commonly used in the industry is usually a single-layer passivation film of silicon oxide or silicon nitride. In order to increase the light absorption of the silicon substrate at the same time, a structured film is often added to the single-layer passivation film to form a double-layer passivation structure such as silicon oxide/silicon nitride, silicon oxide/silicon oxynitride, silicon oxynitride/silicon nitride, etc. Membrane structure. However, the above-mentioned single-layer passivation film actually cannot provide a sufficient amount of hydrogen (H) source, nor can it introduce a sufficient amount of hydrogen (H) source into the silicon substrate to passivate defects in and on the silicon substrate. In addition, the existing passivation layer cannot provide favorable charges or reduce the amount of undesired charges in the passivation layer.

Take the Passivated Emitter and Rear Cell (PERC) solar cell as an example. In PERC solar cells, aluminum oxide/silicon nitride or silicon oxynitride/silicon nitride is usually used as the back passivation layer of the two-layer structure. After that, the back passivation layer is partially opened, and then aluminum paste is applied and sintered. Form a local back electric field. In addition to passivating the solar cell substrate (usually silicon), the back passivation layer also needs to be able to prevent the aluminum paste from entering and destroying the underlying passivation layer and/or reacting with the solar cell substrate during sintering.

However, when using the prior art to form the back passivation layer, pinholes are usually formed inside the back passivation layer, and the pinholes will continue to extend as the thickness of the back passivation layer increases. In the subsequent sintering process, the aluminum paste located on the back passivation layer may pass through the micropores and contact the back passivation layer to damage the back passivation layer and/or react with the solar cell substrate. In other words, even if the back passivation layer is thickened, it is difficult to prevent the aluminum paste from penetrating through the micropores, and it will also increase the process cost.

Therefore, there is a need to improve the structure and method of the passivation layer on the surface of the silicon substrate to provide a sufficient amount of hydrogen (H) source, or to drive a sufficient amount of hydrogen (H) source into and passivate the defects on the inner and surface of the silicon substrate, and Reduce the amount of unwanted charges in the passivation film. In addition, the passivation layer structure needs to reduce internal pinholes (pinholes) and/or avoid continuity of internal micropores to prevent burn-through of subsequent metal electrode sintering processes, such as aluminum paste sintering.

The technical problem to be solved by the present invention is to provide a solar cell, its surface passivation structure and a method for surface passivation in view of the deficiencies of the prior art, so as to further improve the passivation effect of the inside and surface of the solar cell substrate, and improve the photoelectric conversion efficiency of the solar cell .

In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a solar cell, which includes a semiconductor substrate, a surface passivation structure, a front electrode layer and a back electrode layer. The semiconductor substrate has a front surface and a back surface, and the semiconductor substrate has a front surface emitter layer connected to the front surface. The surface passivation structure is located on at least one of the front side and the back side of the semiconductor substrate. The front electrode layer is arranged on the front surface of the semiconductor substrate and is electrically connected to the front emitter layer. The back electrode layer is arranged on the back surface of the semiconductor substrate and is electrically connected to the semiconductor substrate. The surface passivation structure includes a main passivation layer and an auxiliary passivation stack, and the main passivation layer is connected between the semiconductor substrate and the auxiliary passivation stack. The auxiliary passivation stack includes a plurality of film layers, and there are at least three heterogeneous interfaces in the surface passivation structure.

In order to solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a surface passivation structure of a solar cell, which is used to be disposed on a front side or a back side of a semiconductor substrate. The surface passivation structure includes: a main passivation layer and an auxiliary passivation stack. The main passivation layer is connected between the semiconductor substrate and the auxiliary passivation stack, and the auxiliary passivation stack includes a plurality of film layers, and the surface passivation structure has at least three heterogeneous interfaces.

In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a surface passivation method for solar cells, which includes: providing a doped semiconductor substrate, and the semiconductor substrate has an initial front emitter layer; A surface passivation structure is formed on at least one of the front surface and the back surface of the semiconductor substrate. The surface passivation structure includes a main passivation layer and an auxiliary passivation stack, the main passivation layer is located between the semiconductor substrate and the auxiliary passivation stack, and the auxiliary passivation stack includes multiple film layers, and the surface passivation structure has at least three heterogeneous Interface; and after the step of forming a surface passivation structure, an annealing process is performed.

One of the beneficial effects of the present invention is that the solar cell, its surface passivation structure and its surface passivation method provided by the present invention can be connected by the "surface passivation structure including a main passivation layer and an auxiliary passivation layer. The main passivation layer" Between the semiconductor substrate and the auxiliary passivation stack, the auxiliary passivation stack includes a plurality of film layers, and the surface passivation structure has at least three heterogeneous interfaces" and "after the step of forming the surface passivation structure, perform an annealing treatment" The technical solution is to improve the passivation effect on the inside and the surface of the semiconductor substrate, and improve the conversion efficiency of the solar cell.

More specifically, the present invention enhances the passivation effect by providing an auxiliary passivation stack including multiple film layers on the front and/or back of the solar cell, and combined with the subsequent annealing treatment, it can promote a greater amount of hydrogen. Atoms diffuse into the semiconductor substrate and reduce the number of unwanted charges, which will further enhance the passivation effect. At the same time, the light absorption of the semiconductor substrate can be maximized by forming a surface passivation structure with multiple layers, thereby improving the photoelectric conversion of the solar cell. efficacy.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings about the present invention. However, the provided drawings are only for reference and description, and are not used to limit the present invention.

The following are specific examples to illustrate the implementation of the “solar cell, its surface passivation structure and its surface passivation method” disclosed in the present invention. Those skilled in the art can understand the advantages and advantages of the present invention from the content disclosed in this specification. effect. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to actual size, and are stated in advance. The following embodiments will further describe the related technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention.

It should be understood that although terms such as "first", "second", and "third" may be used herein to describe various material layers, these material layers should not be limited by these terms. These terms are mainly used to distinguish one material layer from another material layer. In addition, the term "or" used in this document may include any one or a combination of more of the associated listed items depending on the actual situation.

Please refer to FIG. 1, an embodiment of the present invention provides a surface passivation method for solar cells, which at least includes the following steps.

In detail, in step S100, a doped semiconductor substrate is provided, and the doped semiconductor substrate has an initial front emitter layer. In step S110, a surface passivation structure is formed on at least one of the front side and the back side of the semiconductor substrate. In one embodiment, a surface passivation structure is formed on the front surface or the back surface of the semiconductor substrate. In another embodiment, a surface passivation structure is formed on both the front side and the back side of the semiconductor substrate. At this time, two surface passivation structures can be formed on the front side and the back side of the semiconductor substrate in order or in the reverse order.

The surface passivation structure includes a main passivation layer and an auxiliary passivation stack, and the main passivation layer is connected between the semiconductor substrate and the auxiliary passivation stack. The auxiliary passivation stack includes a plurality of film layers. Overall, the surface passivation structure has at least three heterogeneous interfaces. After that, in step S120, an annealing process is performed.

The surface passivation method of the solar cell provided by the present invention can be integrated into the manufacturing process of the solar cell. Please refer to FIG. 2 to FIG. 7. The following takes the manufacturing of a passivated emitter and rear cell (PERC) as an example to further describe the process details of each step.

It should be noted that in this embodiment, the surface passivation structure is a back passivation structure and is formed on the back surface of the semiconductor substrate.

Please refer to step S100 in FIG. 1 and FIG. 2 in cooperation. As shown in Fig. 2, the doped semiconductor substrate 1'has a front side 1a and a back side 1b. In Fig. 2, the front side 1a of the semiconductor substrate 1'has been roughened (or textured), and has a rough structure.

In one embodiment, the semiconductor substrate 1'is a silicon substrate, which has been doped with the first conductivity type to form a first conductivity type substrate. For example, the semiconductor substrate 1'is originally a p-type silicon substrate. After that, gas diffusion or ion implantation can be used to form an initial front surface emitter layer 11' connected to the front surface 1a of the semiconductor substrate 1'in the semiconductor substrate 1'. The initial front-side emitter layer 11' contains dopants of the second conductivity type, for example, n-type doping, and has a conductivity type opposite to that of the semiconductor substrate 1'.

That is, the initial front emitter layer 11' is the second conductivity type initial front emitter layer 11'. It is worth noting that, in the semiconductor substrate 1', the other regions where the initial front emitter layer 11' is not formed are the initial base region 10' of the first conductivity type. A PN junction 12' is formed between the initial front emitter layer 11' and the initial base region 10'.

In addition, in FIG. 2, an initial front surface passivation structure layer 2'has been formed on the front surface 1a of the semiconductor substrate 1'. The initial front-side passivation structure layer 2'can be used to passivate the surface of the initial front-side emitter layer 11' (ie, the front side 1a of the semiconductor substrate 1') to reduce the probability of carrier recombination, and can be used as an anti-reflection layer. Furthermore, the initial front side passivation structure layer 2'may be a multilayer film (not shown in FIG. 2). The material of the initial front side passivation structure layer 2'can be silicon _{oxide (SiO x} ), silicon oxynitride (SiON), aluminum oxide (AlO _x ), aluminum nitride (AlN), silicon nitride (SiN _x ), or any of them combination.

It is worth noting that, in one embodiment, the step of forming the initial front side passivation structure layer 2'can also be performed after performing step S110 and step S120 in FIG. 1. In other words, first forming a surface passivation structure on the back surface 1b of the semiconductor substrate 1'and performing annealing treatment, and then forming an initial front surface passivation structure layer 2'on the front surface 1a of the semiconductor substrate 1'can also achieve the objective of the present invention.

Please refer to step S110 in FIG. 1, FIG. 3, and FIG. 3A. In this embodiment, a surface passivation structure 4'is formed on the back surface 1b of the semiconductor substrate 1'. The surface passivation structure 4'can be prepared by a plasma chemical vapor deposition (PECVD) process.

As shown in FIG. 3, in this embodiment, the surface passivation structure 4'includes a main passivation layer 41 and an auxiliary passivation stack 42. The main passivation layer 41 is located between the semiconductor substrate 1'and the auxiliary passivation stack 42. In other words, the main passivation layer 41 and the auxiliary passivation stack 42 are sequentially formed on the back surface 1b of the semiconductor substrate 1'.

In an embodiment, the main passivation layer 41 may include a first sub-layer 411 and a second sub-layer 412, wherein the first sub-layer 411 is directly connected to the back surface 1b. In an embodiment, the total thickness of the main passivation layer 41 is about 1 nm to 150 nm, and the thickness of the first sub-layer 411 is 1 nm to 15 nm.

In this embodiment, passivation is performed on the surface (ie, back side 1b) of the initial substrate region 10' of the first conductivity type (p-type). If the main passivation layer 41 carries too much positive charges, negative charges may be induced It is accumulated on the back surface 1b to form an n-type inversion layer. In other words, the number of electrons generated on the back side 1b exceeds the number of holes. The electrons in the reversal layer may form a shunt current on the back side, and may even move to the contact point on the back side 1b, and recombine with the holes, resulting in a reduction in the conversion efficiency of the solar cell.

It should be noted that in the prior art, for the p-type initial substrate region 10', materials with negative charges, such as aluminum oxide (AlO _x ), are usually selected to reduce the above-mentioned problems. However, materials with negative charges only have a passivation effect on the p-type substrate region, but have a poor passivation effect on the n-type substrate region. Accordingly, in the present invention, the material of the main passivation layer 41 is not deliberately selected as a material with a negative charge, but a material with a simple process and a lower cost, but less charged or less positively charged. Regardless of whether the initial substrate region 10' is p-type or n-type, the main passivation layer 41 in the present invention combined with the structure of the auxiliary passivation stack 42 and the subsequent annealing treatment can effectively passivate the back side 1b. This part of the effect will be It is explained in detail in the text.

In this embodiment, the first sub-layer 411 is a silicon oxide (SiO _x ) layer, and the second sub-layer 412 is a silicon oxynitride (SiO _x N _y ) layer or a silicon oxide (SiO _x ) layer. In detail, in the present invention, when the main passivation layer 41 is prepared by the plasma chemical vapor deposition (PECVD) process, nitrous oxide (N ₂ O) plasma is used in the initial stage to form the back surface of the semiconductor substrate 1' 1b forms a silicon oxide layer (first sub-layer 411). After that, the mixed gas plasma is used to form the second sub-layer 412 on the first sub-layer 411.

When the second sub-layer 412 is a silicon oxynitride layer, the aforementioned mixed gas plasma includes silane (SiH ₄ ), nitrous oxide (N ₂ O), and ammonia (NH ₃ ) plasma. When the second sub-layer 412 is a silicon oxide layer, the aforementioned mixed gas plasma includes silane (SiH ₄ ) and nitrous oxide (N ₂ O) plasma. In other words, in the same deposition process, providing different gas plasmas at different times can continuously form the first sub-layer 411 and the second sub-layer 412 of different materials.

The auxiliary passivation stack 42 includes a plurality of film layers and has at least one heterogeneous interface. In an embodiment, the materials of any two adjacent film layers in the plurality of film layers are different. In this embodiment, the multiple film layers include a first film layer 420 and a second film layer 421, wherein the first film layer 420 and the second film layer 421 are of different materials and are connected to each other to form at least one heterogeneous interface. In one embodiment, the thickness of each layer is between 1 nm and 150 nm.

Furthermore, in this embodiment, the plurality of film layers include a plurality of first film layers 420 (two are shown in FIG. 3A as an example) and a plurality of second film layers 421 (two are shown in FIG. 3A as an example) . The plurality of first film layers 420 and the plurality of second film layers 421 are alternately stacked to form the auxiliary passivation stack 42. In this embodiment, the main passivation layer 41 and the auxiliary passivation stack 42 can be prepared by a plasma chemical vapor deposition (PECVD) process, and different gas plasmas are supplied at different time points to sequentially The main passivation layer 41 and the auxiliary passivation stack 42 are formed.

In one embodiment, the hydrogen content of the first film layer 420 may be greater than the hydrogen content of the second film layer 421. In addition, it should be noted that in the process of forming the main passivation layer 41 and the auxiliary passivation stack 42, more heterogeneous interfaces are formed between any two adjacent first film layers 420 and second film layers 421. Dangling bonds (dangling bonds), and can be bonded with more hydrogen atoms. Therefore, the heterogeneous interface can be used as a hydrogen storage area to store more hydrogen atoms.

In other words, the hydrogen content in the heterogeneous interface is greater than the hydrogen content in the first film layer 420 or the second film layer 421 on both sides thereof. Accordingly, the heterogeneous interface between the first film layer 420 and the second film layer 421 is a hydrogen storage heterogeneous interface.

Accordingly, the auxiliary passivation stack 42 includes multiple hydrogen storage heterogeneous interfaces formed by multiple film layers, which can provide more hydrogen sources than traditional single-layer or double-layer passivation structures. In the subsequent manufacturing process, hydrogen atoms can diffuse into the semiconductor substrate 1'and enter the semiconductor substrate 1'to passivate the defects in the substrate and the surface of the semiconductor substrate 1'.

In addition, the auxiliary passivation stack 42 includes at least two alternately stacked film layers, which can avoid the formation of continuous pinholes inside. In detail, when a single film is prepared by a plasma chemical vapor deposition (PECVD) process, micropores are usually formed inside the film, and the micropores continue to extend as the thickness of the single film increases. However, if the heterogeneous film layers are alternately formed, the micropores can be prevented from continuing to extend. Therefore, the micropores in each layer may only extend to the heterogeneous interface between adjacent layers. In this way, in the subsequent sintering process, the auxiliary passivation stack 42 can more effectively prevent the metal paste from penetrating through the micropores and destroying the main passivation layer 41 and/or reacting with the semiconductor substrate 1'.

In addition, the thickness and refractive index of the multilayer first film layer 420 (or the multilayer second film layer 421) do not have to be the same, but can be adjusted according to actual requirements. For example, if the first film layer 420 is a silicon nitride layer (SiN _x : H) containing hydrogen, the refractive index of the silicon nitride layer can be changed by adjusting the ratio of silicon/nitrogen atoms in the silicon nitride layer And the hydrogen content to maximize the light absorption of the semiconductor substrate and provide more hydrogen sources, thereby improving the photoelectric conversion efficiency of the solar cell. When the ratio of silicon/nitrogen atoms in the silicon nitride layer is higher, the refractive index of the silicon nitride layer is higher, and the hydrogen content is also higher. In one embodiment, the refractive index and hydrogen content of the first film layer 420 closer to the main passivation layer 41 (or the semiconductor substrate 1') are higher than the refractive index of the first film layer 420 farther from the main passivation layer 41 And hydrogen content.

On the other hand, compared with a silicon nitride layer with a higher silicon/nitrogen ratio, a silicon nitride layer with a lower silicon/nitrogen ratio is less likely to react with metals (such as aluminum) in the subsequent sintering process. Therefore, arranging the silicon nitride layer with a low silicon/nitrogen ratio on the outside (the side away from the main passivation layer 41) can provide the auxiliary passivation stack 42 with a better protection effect during the subsequent sintering process.

The second film layer 421 may be a silicon oxynitride layer, an aluminum oxide layer or a silicon oxide layer, and the first film layer 420 may be a silicon nitride layer or a silicon carbide layer. In a preferred embodiment, the first film layer 420 is a silicon nitride layer (SiN _x : H) containing hydrogen, and the second film layer 421 is a silicon oxynitride layer. That is, the auxiliary passivation stack 42 has a stack structure of _{SiN x} /SiOxNy/SiN _{x /SiOxNy.}

However, in other embodiments, any of the silicon oxynitride layers can also be replaced with an aluminum oxide layer or a silicon oxide layer. For example, the auxiliary passivation stack 42 may also have _{a stack structure of SiN x} /SiO _x /SiN _x /SiOxNy, or a stack structure of SiN _x /AlO _x /SiN _x /SiOxNy.

Please refer to FIG. 3B, which shows a partial enlarged schematic view of a surface passivation structure according to another embodiment of the present invention. In this embodiment, the multiple film layers further include a third film layer 422, and the material of the third film layer 422 is different from the materials of the first film layer 420 and the second film layer 421. In one embodiment, the hydrogen content of the first film layer 420 is greater than the hydrogen content of the second film layer 421 and the third film layer 422. The third film layer 422 may be a silicon oxynitride layer, an aluminum oxide layer, or a silicon oxide layer. The third film layer 422 is adjacent to the first film layer 420 or the second film layer 421 to form a heterogeneous interface. Furthermore, a plurality of first film layers 420, a plurality of second film layers 421, and a plurality of third film layers 422 may be sequentially stacked on the back surface 1b of the semiconductor substrate 1'.

However, as long as the surface passivation structure 4 has multiple heterogeneous interfaces, the present invention does not limit the stacking order of the first film layer 420, the second film layer 421, or the third film layer 422 in the auxiliary passivation stack 42. In the auxiliary passivation stack 42 shown in FIG. 3A, any second film layer 421 can be replaced with a third film layer 422, which can also achieve the purpose of the present invention. In a preferred embodiment, the number of heterogeneous interfaces of the surface passivation structure 4 is 5-15.

In an embodiment, the material of the first film layer 420 may also be different from the material of the second sub-layer 412 to which it is connected, and may form one of the heterogeneous interfaces. Specifically, if the second sub-layer 412 is a silicon oxynitride layer, the first film layer 420 may be a silicon nitride layer containing hydrogen (SiNx: H). In addition, the second film layer 421 may be a silicon oxynitride layer, an aluminum oxide layer, or a silicon oxide layer. However, the present invention is not limited to the foregoing examples.

Please refer to step S120 in FIG. 1 and FIG. 4. In step S120, an annealing process is performed. It should be noted that the annealing treatment at this stage is different from the sintering process after coating the metal slurry in the prior art. Time sintering process is generally performed is usually not more than 2 minutes, while the embodiment of the present invention, when performing the annealing process, an annealing temperature greater than 500 ^o C, and the temperature held for at least 5 minutes.

By performing the annealing process, the hydrogen originally located in the auxiliary passivation stack 42 can be driven to diffuse into the semiconductor substrate 1 to passivate the surface or internal defects of the semiconductor substrate 1. It is worth noting that in the back passivation layer without multiple heterogeneous interfaces, hydrogen atoms may also diffuse in a direction away from the semiconductor substrate 1, resulting in a passivation effect that is not as expected.

However, in the embodiment of the present invention, since the auxiliary passivation stack 42 has multiple heterogeneous interfaces, and the hydrogen content of the first film layer 420 and the heterogeneous interfaces closer to the semiconductor substrate 1'is higher than that of the heterogeneous interfaces farther away from the semiconductor substrate 1' The hydrogen content of the first film layer 420 and the heterogeneous interface. The hydrogen atoms that originally existed in the heterogeneous interface and the film layer closest to the semiconductor substrate 1'tend to diffuse toward the semiconductor substrate 1', so that most of the hydrogen atoms can enter the semiconductor substrate 1', which can provide The semiconductor substrate 1'has a better passivation effect.

The aforementioned annealing treatment can be performed in an environment such as vacuum, nitrogen, oxygen, hydrogen, or forming gas. In a preferred embodiment, the annealing treatment can be performed in an environment of hydrogen gas or nitrogen-hydrogen synthesis gas.

In addition, the annealing treatment can also make the layers of the main passivation layer 41 and the auxiliary passivation layer 42 more dense, and can prevent the metal paste from sintering and destroying the main passivation layer 41 and the main passivation layer 41 and the auxiliary passivation layer 42 in the subsequent sintering process. /Or react with the semiconductor substrate 1.

On the other hand, after the annealing process is performed, the positive charges originally present in the surface passivation structure 4'can be further reduced, and the accumulation of negative charges on the back surface 1b of the semiconductor substrate 1'can be avoided. In this way, the probability of carriers being recombined can be reduced, and the photoelectric conversion efficiency of the solar cell can be improved.

That is to say, in the surface passivation structure 4'of the embodiment of the present invention, the main passivation layer 41 cooperates with the structure of the auxiliary passivation stack 42 and performs annealing treatment, in addition to providing a sufficient amount of hydrogen source and reducing the defects in the surface passivation structure 4' If the amount of charge is required to effectively passivate the semiconductor substrate 1, it can also effectively prevent the metal paste from sintering to destroy the main passivation layer 41 and/or react with the semiconductor substrate 1.

In addition, referring to FIGS. 3 and 4, in this embodiment, after the annealing process is performed, the doping profile of the second conductivity type doping in the initial front emitter layer 11' includes the doping concentration and depth, and It is adjusted again, and the position of the PN junction 12 in the semiconductor substrate 1 is changed. Specifically, after the annealing process is performed, the PN junction 12 in FIG. 4 will be farther away from the front surface 1a of the semiconductor substrate 1 than the PN junction 12' in FIG. As the depth of the PN junction 12 increases and is farther away from the front surface 1a, the metal-induced carrier recombination caused by subsequent electrode sintering can be reduced. In addition, in the front emitter layer 11, the doping concentration near the surface 1a can be reduced, thereby reducing the carrier surface recombination speed.

Please further refer to FIG. 5 and FIG. 6 to form the front electrode layer 3 and the back electrode layer 5. In detail, referring to FIG. 5, a part of the surface passivation structure 4'is removed to form the surface passivation structure 4 having the opening pattern H1. In other words, by performing a partial opening process on the surface passivation structure 4', the surface passivation structure 4 has an opening pattern H1. The hole-opening process, for example, uses a laser hole or an etching paste to form a patterned hole, but the present invention is not limited.

It is worth noting that, in one embodiment, the partial opening process is performed first, and then the aforementioned annealing treatment is performed on the surface passivation structure 4, which can also achieve the objective of the present invention. In other words, the annealing treatment can be performed after the partial opening process. In another embodiment, the annealing treatment can also be performed before the partial opening process. Therefore, the present invention does not limit the sequence of performing the annealing treatment and the partial opening process.

Referring to FIG. 6, an initial front electrode layer 3'is formed on the initial front passivation structure layer 2', and an initial back electrode layer 5'is formed on the surface passivation structure 4.

The structure of the initial front electrode layer 3'can be adjusted according to actual needs. For example, the initial front electrode layer 3'may be a grid electrode layer, which includes at least one bus bar and a plurality of finger electrodes connected to the bus bar.

In addition, the initial back electrode layer 5'is in contact with the back surface 1b of the semiconductor substrate 1 through the opening pattern H1 of the surface passivation structure 4. The initial front electrode layer 3'and the initial back electrode layer 5'may both be metal paste layers, and can be formed on the initial front passivation structure layer 2'and the surface passivation structure 4 by screen printing, respectively. In an embodiment, the initial front electrode layer 3'may be silver paste, and the initial back electrode layer 5'may be aluminum paste. In other embodiments, the initial front electrode layer 3'and the initial back electrode layer 5'can also be formed by evaporation, sputtering, or electroplating.

Afterwards, a sintering process is performed to form a front electrode layer 3 electrically connected to the emitter region 11 on the front side 1a of the semiconductor substrate 1, and a back electrode layer 3 electrically connected to the base region 10 on the back side 1b of the semiconductor substrate 1 Layer 5.

In detail, in the sintering process, the initial front electrode layer 3'passes through the front passivation structure layer 2 and is electrically connected to the front emitter layer 11. In addition, a part of the initial back electrode layer 5'located in the opening pattern H1 will react with the semiconductor substrate 1 and be electrically connected to the base region 10 of the semiconductor substrate 1. In addition, a part of the metal atoms (such as aluminum) in the initial back electrode layer 5'will diffuse into the semiconductor substrate 1 during the sintering process to form a local back electric field 13.

Please refer to FIG. 7, which shows a schematic cross-sectional view of the solar cell according to the first embodiment of the present invention. The solar cell S1 includes a semiconductor substrate 1, a front passivation structure layer 2, a front electrode layer 3, a surface passivation structure 4 and a back electrode layer 5.

The semiconductor substrate 1 has a front surface 1a and a back surface 1b opposite to the front surface 1a. In this embodiment, the front surface 1a of the semiconductor substrate 1 is a rough surface. The semiconductor substrate 1 includes a base region 10 of a first conductivity type and a front emitter layer 11 of a second conductivity type. The base region 10 and the front emitter layer 11 form a PN junction 12 in the semiconductor substrate 1.

In one embodiment, the base region 10 of the first conductivity type is a p-type base region, and the front emitter layer 11 of the second conductivity type is an n-type front emitter layer. In addition, the base region 10 and the front emitter layer 11 are respectively connected to the back surface 1b and the front surface 1a of the semiconductor substrate 1.

The front passivation structure layer 2 is located on the front side 1a of the semiconductor substrate 1, and may include a passivation film and an anti-reflection film. The material of the passivation film and the anti-reflection film can be silicon _{oxide (SiO x} ), silicon oxynitride (SiON), aluminum oxide (AlO _x ), aluminum nitride (AlN) or silicon nitride (SiN _x ) or any combination thereof, The invention is not limited. In an embodiment, the front passivation structure layer 2 may include a silicon oxide film and a silicon nitride film. In another embodiment, the front passivation structure layer 2 may include an aluminum oxide film and a silicon nitride film.

The front electrode layer 3 is disposed on the front side 1 a of the semiconductor substrate 1, and the front electrode layer 3 passes through the front passivation structure layer 2 to be electrically connected to the semiconductor substrate 1. As mentioned above, the front electrode layer 3 will be electrically connected to the emitter region 11.

The surface passivation structure 4 is disposed on the back surface 1b of the semiconductor substrate 1, and the surface passivation structure 4 has an opening pattern H1. 3A and 3B in conjunction, in this embodiment, the surface passivation structure 4 includes a main passivation layer 41 and an auxiliary passivation stack 42. The main passivation layer 41 is connected between the semiconductor substrate 1 and the auxiliary passivation stack 42.

In one embodiment, the total thickness of the main passivation layer 41 is about 1 nm to 150 nm. The main passivation layer 41 may be a single-layer film or a multilayer film. In one embodiment, the main passivation layer 41 is a single-layer film, such as a silicon oxide layer or a silicon oxynitride layer. When the main passivation layer 41 is a multilayer film, it may include a first sub-layer 411 and a second sub-layer 412, wherein the first sub-layer 411 is directly connected to the back surface 1b, and the thickness of the first sub-layer 411 is 1 nm to 15 nm. Specifically, the first sub-layer 411 is a silicon oxide layer, and the second sub-layer 412 is a silicon oxynitride layer.

The auxiliary passivation stack 42 includes a plurality of film layers to form a heterogeneous interface. Furthermore, in the embodiment of FIG. 3A, the plurality of film layers include a first film layer 420 and a second film layer 421, wherein the first film layer 420 and the second film layer 421 have different materials and are connected to each other to At least one heterogeneous interface is formed. In one embodiment, the thickness of each layer is between 1 nm and 150 nm.

Furthermore, the plurality of film layers may include a plurality of first film layers 420 (two are shown as an example in FIG. 3A) and a plurality of second film layers 421 (two are shown as an example in FIG. 3A), which are alternately stacked. The auxiliary passivation stack 42 is formed sequentially in the same deposition process by plasma chemical vapor deposition (PECVD) in an alternately stacked manner.

In a preferred embodiment, the first film layer 420 is a silicon nitride layer (SiN _x : H) containing hydrogen, and the second film layer 421 is a silicon oxynitride layer. When the second film layer 421 is a silicon oxynitride layer, in the subsequent sintering process, the barrier property to aluminum paste is better. In other embodiments, any one of the silicon oxynitride layers can also be replaced with an aluminum oxide layer or a silicon oxide layer.

In the embodiment of FIG. 3B, the plurality of film layers further include a third film layer 422, and the material of the third film layer 422 is different from the materials of the first film layer 420 and the second film layer 421. The third film layer 422 may be a silicon oxynitride layer, an aluminum oxide layer, or a silicon oxide layer.

The third film layer 422 is connected to the first film layer 420 or the second film layer 421 to form a heterogeneous interface. Furthermore, a plurality of first film layers 420, a plurality of second film layers 421, and a plurality of third film layers 422 may be sequentially stacked on the back surface 1b of the semiconductor substrate 1'.

However, as long as the surface passivation structure 4 includes at least three heterogeneous interfaces, the present invention does not limit the stacking order of the first film layer 420, the second film layer 421, or the third film layer 422 in the auxiliary passivation stack 42. For example, replacing any second film layer 421 with the third film layer 422 in the auxiliary passivation stack 42 shown in FIG. 3A can also achieve the purpose of the present invention. In a preferred embodiment, the number of heterogeneous interfaces of the surface passivation structure 4 is 5-15.

The back electrode layer 5 is disposed on the surface passivation structure 4, and the back electrode layer 5 is electrically connected to the base region 10 of the semiconductor substrate 1 through the opening pattern H1. In detail, multiple parts of the back electrode layer 5 enter the back surface layer of the semiconductor substrate 1. In addition, the backside surface layer of the semiconductor substrate 1 has local back electric fields 13 corresponding to these portions, respectively.

Please refer to FIG. 8, which shows a schematic cross-sectional view of a solar cell according to a second embodiment of the present invention. The components of the solar cell S2 in this embodiment that are the same or similar to those in the previous embodiment have the same reference numerals, and the same parts will not be repeated.

The solar cell S2 of this embodiment is a bifacial solar cell. In other words, the solar cell S2 of this embodiment can receive light on both the front side 1a and the back side 1b, so as to increase the power generation. Therefore, the front surface 1a and the back surface 1b of the solar cell S2 of this embodiment have been roughened, and thus have a roughened structure.

In addition to the base region 10 and the front emitter layer 11, the semiconductor substrate 1 of the solar cell S2 also includes a first conductivity type back surface electric field layer 14. The base region 10 is located between the front emitter layer 11 and the back electric field layer 14. In this embodiment, the base region 10 and the back electric field layer 14 have the same conductivity type, and the base region 10 and the front emitter layer 11 have the opposite conductivity type. Therefore, the front emitter layer 11 has the second conductivity type. For example, the base region 10 and the back electric field layer 14 may both include n-type doping, and the front emitter layer 11 may include p-type doping.

In other words, the base area 10 and the back electric field layer 14 are respectively an n-type base area and an n-type back electric field layer 14, and the front emitter layer 11 is a p-type front emitter layer. Accordingly, a PN junction 12 is also formed between the base region 10 and the front emitter layer 11. In addition, in this embodiment, the front electrode layer 3 is electrically connected to the front emitter layer 11 through the front passivation structure layer 2, and the back electrode layer 5 is electrically connected to the back electric field layer 14 through the surface passivation layer 4.

In this embodiment, the surface passivation structure 4 includes a main passivation layer 41 and an auxiliary passivation stack 42. In addition, the front passivation structure layer 2 of this embodiment may have the same structure as the surface passivation structure 4, that is, it may include a main passivation layer and an auxiliary passivation stack.

In other words, the surface passivation structure 4 of the embodiment of the present invention can be provided on the front side 1a and/or the back side 1b of the semiconductor substrate 1 to passivate the front side 1a and/or the back side 1b of the semiconductor substrate 1 to reduce the recombination speed of carriers, and Improve the photoelectric conversion efficiency of the solar cell S2.

That is to say, the surface passivation structure (including the main passivation layer and the auxiliary passivation stack) of the embodiment of the present invention is not limited to be applied to the solar cell exemplified in the present invention, but can be applied to any solar cell that requires surface passivation.

[Beneficial effects of the embodiment]

In the solar cell, the surface passivation structure and the surface passivation method provided by the present invention, the surface passivation structure 4 includes a main passivation layer 41 and an auxiliary passivation stack 42 to form at least three heterogeneous interfaces. Main passivation The layer 41 is connected between the semiconductor substrate 1 and the auxiliary passivation stack 42, and the auxiliary passivation stack 42 includes a plurality of film layers" and "after the step of forming the surface passivation structure 4', perform an annealing treatment" technical solution, In order to improve the passivation effect on the surface of the semiconductor substrate 1.

More specifically, the heterogeneous interface formed between any two adjacent first film layers 420 and the second film layer 421 of the auxiliary passivation stack 42 is a hydrogen storage heterogeneous interface. Secondly, the multiple heterogeneous interfaces of the auxiliary passivation stack 42 can slow the diffusion of hydrogen atoms outward (that is, in a direction away from the semiconductor substrate 1). Therefore, compared with the back passivation layer in the prior art, the combination of the surface passivation structure 4 of the embodiment of the present invention and the subsequent annealing treatment can promote more hydrogen atoms to diffuse into the semiconductor substrate 1, and reduce undesired in the surface passivation structure 4. The amount of charge has a better passivation effect, and improves the photoelectric conversion efficiency of solar cells S1 and S2.

In addition, the auxiliary passivation stack 42 includes at least two alternately stacked film layers, which can avoid the formation of continuous pinholes inside. In this way, in the subsequent sintering process, the back passivation structure 4 can more effectively prevent the metal paste from penetrating through the micropores and destroying the main passivation layer 41 and/or reacting with the semiconductor substrate 1.

The content disclosed above is only the preferred and feasible embodiments of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the description and schematic content of the present invention are included in the application of the present invention. Within the scope of the patent.

S1, S2: Solar cell 1, 1’: Semiconductor substrate 1a: front 1b: back 10’: Initial basal area 10: Basal area 11’: Initial frontal emitter layer 11: Frontal emitter layer 12, 12’: PN junction 13: Local back electric field 14: Backside electric field layer 2’: Initial front side passivation structure layer 2: Front passivation structure layer 3’: Initial front electrode layer 3: Front electrode layer 4’, 4: Surface passivation structure H1: Opening pattern 41: Main passivation layer 411: first sublayer 412: second sublayer 42: auxiliary passivation stack 420: first layer 421: second film layer 422: third layer 5’: Initial back electrode layer 5: Back electrode layer

FIG. 1 is a flowchart of a method for surface passivation of a solar cell according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a solar cell in a manufacturing process according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a solar cell in a manufacturing process according to an embodiment of the present invention.

FIG. 3A is an enlarged schematic diagram of part IIIA of FIG. 3.

3B is a partial enlarged schematic diagram of a surface passivation structure according to another embodiment of the invention.

Fig. 4 is a schematic diagram of a solar cell in a manufacturing process according to an embodiment of the present invention.

5 to 6 are schematic diagrams of a solar cell in a manufacturing process according to an embodiment of the invention.

FIG. 7 is a schematic cross-sectional view of the solar cell according to the first embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view of a double-sided solar cell according to a second embodiment of the invention.

S100~S120: process steps

Claims (19)

A surface passivation structure of a solar cell, which is used to be arranged on a front side or a back side of a semiconductor substrate. The surface passivation structure includes: a main passivation layer and an auxiliary passivation stack, and the main passivation layer is connected to the Between the semiconductor substrate and the auxiliary passivation stack, the auxiliary passivation stack includes a plurality of film layers, and the surface passivation structure has at least three heterogeneous interfaces. The surface passivation structure according to claim 1, wherein the plurality of film layers include at least a first film layer and a second film layer connected to the first film layer to form one of the heterogeneous interfaces And the hydrogen content of the first film layer is greater than the hydrogen content of the second film layer. The surface passivation structure according to the second item of the scope of patent application, wherein the plurality of film layers further include a third film layer, and the third film layer is adjacent to the first film layer or the second film layer, To form another said heterogeneous interface. The surface passivation structure according to claim 1, wherein the plurality of film layers include a plurality of first film layers and a plurality of second film layers stacked alternately, and one of the first film layers is connected The hydrogen content of the main passivation layer and the heterogeneous interface closer to the semiconductor substrate is greater than the hydrogen content of the other heterogeneous interface farther from the semiconductor substrate. According to the surface passivation structure described in the first item of the scope of patent application, the total thickness of the main passivation layer is about 1 nm to 150 nm, and the thickness of each of the film layers of the auxiliary passivation stack is about 1 nm to 150 nm. The surface passivation structure according to the first item of the patent application, wherein the main passivation layer is a single-layer film, and the main passivation layer is a silicon oxide layer or a silicon oxynitride layer. The surface passivation structure according to the first item of the patent application, wherein the main passivation layer includes at least a first sublayer and a second sublayer, and the first sublayer is located on the semiconductor substrate and the second sublayer. Between the two sub-layers, the first sub-layer is a silicon oxide layer, the second sub-layer is a silicon oxynitride layer, and the thickness of the first sub-layer is between 1 nm and 15 nm. A solar cell, comprising: the surface passivation structure according to any one of items 1 to 7 in the scope of the patent application. A method for surface passivation of solar cells, which includes: Providing a doped semiconductor substrate, and the semiconductor substrate has an initial front emitter layer; and A surface passivation structure is formed on at least one of a front surface and a back surface of the semiconductor substrate, wherein the surface passivation structure includes a main passivation layer and an auxiliary passivation stack, and the main passivation layer is located on the Between the semiconductor substrate and the auxiliary passivation stack, the auxiliary passivation stack includes a plurality of film layers, and the surface passivation structure has at least three heterogeneous interfaces. The surface passivation method according to claim 9, wherein the plurality of film layers include at least a first film layer and a second film layer connected to the first film layer to form one of the heterogeneous layers Interface, and the hydrogen content of the first film layer is greater than the hydrogen content of the second film layer. The surface passivation method according to item 10 of the scope of patent application, wherein the plurality of film layers further include a third film layer, and the third film layer is adjacent to the first film layer or the second film layer, To form another said heterogeneous interface. The surface passivation method according to claim 9, wherein the plurality of film layers include a plurality of first film layers and a plurality of second film layers stacked alternately, and one of the first film layers is connected The hydrogen content of the main passivation layer and the heterogeneous interface closer to the semiconductor substrate is greater than the hydrogen content of the other heterogeneous interface farther from the semiconductor substrate. According to the method for surface passivation described in item 9 of the scope of patent application, the total thickness of the main passivation layer is about 1 nm to 150 nm, and the thickness of each film layer of the auxiliary passivation layer is about 1 nm to 150 nm. According to the surface passivation method described in item 9 of the scope of patent application, the main passivation layer is a single-layer film, and the main passivation layer is a silicon oxide layer or a silicon oxynitride layer. The surface passivation method according to item 9 of the scope of patent application, wherein the surface passivation structure is formed by a plasma chemical vapor deposition process, and the step of forming the main passivation layer includes: using nitrous oxide ( N ₂ O) plasma to form a first sub-layer on the semiconductor substrate, the first sub-layer is a silicon oxide layer, and the thickness of the first sub-layer is between 1 nm and 15 nm; and The mixed gas plasma forms a second sublayer on the first sublayer, and the second sublayer is a silicon oxynitride layer or a silicon oxide layer. The surface passivation method according to claim 9 of the scope of patent application, wherein, in the step of forming the surface passivation structure, two surfaces are formed on the front surface and the back surface of the semiconductor substrate sequentially or in reverse order. The surface passivation structure. The surface passivation method as described in item 9 of the scope of patent application, wherein after the step of forming the surface passivation structure, an annealing treatment is performed. The surface passivation method according to item 17 of the scope of patent application, wherein the surface passivation structure is formed on the back surface of the semiconductor substrate, and the surface passivation method further includes: A partial opening process is performed to form a surface passivation structure with an opening pattern; wherein, the annealing treatment is performed before or after the partial opening process. The surface passivation method according to item 17 of the scope of patent application, wherein, when the annealing treatment is performed, the annealing temperature is greater than 500 ^o C and the temperature is maintained for more than 5 minutes.

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