TW202105228A - Methods, flash memory controller, and electronic device for secure digital memory card device - Google Patents

Abstract

A method for controlling data transmission mode of a secure digital (SD) memory card device, which at least operates under an SD mode, includes: sending a first power signal from an electronic device to the SD memory card device via a pin VDD1 to make the SD memory card device enter an initial state; and, sending a second power signal via one of a pin VDD2 and a pin VDD3 to the SD memory card device, to control the SD memory card device to enter an Linkup state of a PCIe mode wherein a voltage level of the second power signal is lower than a voltage level of the first power signal.

Description

Method for secure digital card, flash memory controller and electronic device

The present invention relates to a mechanism for controlling the data transmission mode of a memory card device, and more particularly to a method and an electronic device for controlling the data transmission mode of a secure digital card.

Generally speaking, the types of memory card devices designed, manufactured, or sold by different manufacturers on the market are different. Different types of memory card devices may have different numbers of signal pins and supported data transmission modes. The actual voltage value of the logic signal level and the voltage value of the power supply level specified by the input/output communication interface standard corresponding to different data transmission modes are also different. Therefore, when a memory card device is connected On the previous host side, if the data transmission modes supported by the host side and the memory card device are not the same, it may cause circuit damage.

Therefore, one of the objectives of the present invention is to provide a method for controlling the data transmission mode of a secure digital card, a corresponding electronic device, a method used in a secure digital card, and a flash memory controller of the secure digital card , In order to solve the problems of existing technology.

According to an embodiment of the present invention, a method for controlling a data transmission mode of a secure digital card is disclosed. As a host, an electronic device has a first external signal port, and the secure digital card can be operated at least An SD mode has a second external signal port, the secure digital card is used to couple to the electronic device through the first external signal port and the second external signal port, and the method includes: The electronic device sends a first power signal corresponding to the SD mode to the secure digital card through a pin VDD1 of the first external signal port and the second external signal port, and controls the secure digital card to enter an initialization Status; and from the electronic device, through one of a pin VDD2 and a pin VDD3 of the second external signal port, a second power signal is sent to the secure digital card to control the secure digital card to enter a PCIe mode A connection state, a voltage level of the second power signal is lower than a voltage level of the first power signal; wherein the SD mode of the secure digital card adopts a UHS-I input/output communication interface standard The plurality of pins used as data lines are shared by a PCIe channel adopted by the PCIe mode and another input/output communication interface standard of an NVMe protocol. The SD mode is used as the plurality of data lines Each pin includes multiple pins with pin numbers 1, 7, 8, 9.

According to an embodiment of the present invention, an electronic device is also disclosed. The electronic device is coupled to a secure digital card and can control a data transmission mode of the secure digital card. The electronic device is located on a host and has a first external device. A signal port, the secure digital card can operate in at least an SD mode and has a second external signal port, and the electronic device includes the first external signal port, a driving circuit and a processor, the first external signal port has The pins are used for coupling to the pins of the second external signal port of the secure digital card, and the driving circuit is coupled to the first external signal port. The processor is coupled to the driving circuit and used for: controlling the driving circuit to send a pin VDD1 corresponding to the SD mode from the electronic device through the first external signal port and the second external signal port The first power signal is sent to the secure digital card to control the secure digital card to enter an initialization state; and from the electronic device, through one of a pin VDD2 and a pin VDD3 of the second external signal port, a second external signal port is sent. Two power signals to the secure digital card to control the secure digital card to enter a connection state in a PCIe mode, a voltage level of the second power signal is lower than a voltage level of the first power signal; wherein the secure digital card The SD mode of the card adopts a UHS-I input/output communication interface standard. The multiple pins used as the data line are used by the PCIe mode. One PCIe channel and the other input/output of the NVMe protocol Common to the communication interface standard, the multiple pins used as data lines in the SD mode include multiple pins with pin numbers 1, 7, 8, 9.

According to an embodiment of the present invention, a method for controlling a data transmission mode of a secure digital card is also disclosed. As a host, an electronic device has a first external signal port, and the secure digital card can operate on at least one The SD mode has a second external signal port, the secure digital card is used to couple to the electronic device through the first external signal port and the second external signal port, and the method includes: from the host as the host The electronic device sends a first power signal corresponding to the SD mode to the secure digital card through a pin VDD1 of the first external signal port and the second external signal port, and controls the secure digital card to enter an initialization state ; Send a command CMD0 corresponding to the SD mode from the electronic device to the secure digital card through a pin CMD used in the SD mode or send the SD mode corresponding to a pin CLK used in the SD mode A specific clock SDCLK is sent to the secure digital card to control and make the secure digital card enter the SD mode from the initialization state and operate in the SD mode; send a command CMD8 to the secure digital card from the electronic device through the pin CMD The digital card asks whether the secure digital card supports a PCIe mode; if the secure digital card responds that it does not support the PCIe mode, the secure digital card is maintained in the SD mode; and if the secure digital card responds that it supports the PCIe mode, Then, the electronic device sends a second power signal to the secure digital card through one of a pin VDD2 and a pin VDD3 of the second external signal port, and controls the secure digital card to enter a PCIe mode connection State, a voltage level of the second power signal is lower than a voltage level of the first power signal; wherein the SD mode of the secure digital card adopts a UHS-I input/output communication interface standard for The multiple pins used as the data line are shared by a PCIe channel adopted by the PCIe mode and another input/output communication interface standard of an NVMe protocol. The SD mode is used as the multiple pins of the data line Contains multiple pins with pin numbers 1, 7, 8, 9.

According to an embodiment of the present invention, an electronic device is also disclosed. The electronic device is coupled to a secure digital card and can be used to control a data transmission mode of the secure digital card. The electronic device is located on a host and has a first An external signal port, the secure digital card can operate in at least an SD mode and has a second external signal port, and the electronic device includes the first external signal port, a driving circuit and a processor, the first external signal port There are a plurality of pins for coupling to the second external signal port of the secure digital card, and the driving circuit is coupled to the first external signal port. The processor is coupled to the driving circuit, and is used to: control the driving circuit to send a first signal corresponding to the SD mode from the electronic device through a pin VDD1 of the first external signal port and the second external signal port A power signal to the secure digital card controls the secure digital card to enter an initialization state; the processor controls the drive circuit to send a command CMD corresponding to the SD mode from the electronic device through the pin CMD used in the SD mode To the secure digital card or send a specific clock SDCLK corresponding to the SD mode to the secure digital card through a pin CLK used in the SD mode to control the secure digital card to enter the SD mode from the initialization state and Operate in the SD mode; the processor controls the drive circuit to send a command CMD8 from the electronic device to the secure digital card via the pin CMD to inquire whether the secure digital card supports a PCIe mode; if the secure digital card responds no If the PCIe mode is supported, the processor maintains the secure digital card in the SD mode; and if the secure digital card responds to support the PCIe mode, the processor controls the driving circuit to pass the second external signal from the electronic device One of a pin VDD2 and a pin VDD3 of the port sends a second power signal to the secure digital card to control the secure digital card to enter a connection state in a PCIe mode, and a voltage of the second power signal is standard Is lower than a voltage level of the first power signal; wherein the SD mode of the secure digital card adopts a UHS-I input/output communication interface standard that uses a plurality of pins used as data lines by the One PCIe channel used in PCIe mode is shared with another input/output communication interface standard of an NVMe protocol. The multiple pins used as data lines in the SD mode include pin numbers 1, 7, 8 , 9 multiple pins.

According to an embodiment of the present invention, a method for use in a secure digital card is also disclosed. As a host, an electronic device has a first external signal port, and the secure digital card can operate in at least an SD mode and has a first external signal port. Two external signal ports, the secure digital card is used to couple to the electronic device through the first external signal port and the second external signal port, and the method includes: receiving from the electronic device through the first external signal port and A pin VDD1 of the second external signal port sends a first power signal corresponding to the SD mode to enter an initialization state; and receives a pin VDD2 and a pin VDD2 from the electronic device through the second external signal port One of the pins VDD3 sends a second power signal to enter a connection state in a PCIe mode, and a voltage level of the second power signal is lower than a voltage level of the first power signal; The SD mode of the secure digital card adopts a UHS-I input/output communication interface standard. The plurality of pins used as data lines are the other of the PCIe channel and the NVMe protocol adopted by the PCIe mode. Common to the input/output communication interface standard, the multiple pins used as data lines in the SD mode include multiple pins with pin numbers 1, 7, 8, 9.

According to an embodiment of the present invention, a flash memory controller of a secure digital card is also disclosed, the secure digital card is used for coupling to an electronic device, the electronic device is located on a host side and has a first external signal port , The secure digital card can operate in at least an SD mode and has a second external signal port, the second external signal port having a plurality of pins for coupling to a plurality of the first external signal port of the electronic device Pin, the secure digital card further includes a flash memory, and the flash memory controller is used for coupling between the flash memory and the second external signal port and includes a register and a processor Circuit. The register is used to temporarily store the information of the flash memory. The processing circuit is coupled to the register for receiving a first power signal corresponding to the SD mode sent from the electronic device through a pin VDD1 of the first external signal port and the second external signal port , Make the secure digital card enter an initialization state; and the processing circuit is used to receive a second power signal sent from the electronic device through one of a pin VDD2 and a pin VDD3 of the second external signal port , Make the secure digital card enter a connection state in a PCIe mode, a voltage level of the second power signal is lower than a voltage level of the first power signal; wherein the SD mode of the secure digital card is adopted The multiple pins of a UHS-I input/output communication interface standard used as data lines are shared by a PCIe channel adopted by the PCIe mode and another input/output communication interface standard of the NVMe protocol. The SD The plurality of pins used as the data line of the mode includes a plurality of pins with pin numbers 1, 7, 8, 9.

According to an embodiment of the present invention, a method for use in a secure digital card is also disclosed. As a host, an electronic device has a first external signal port, and the secure digital card can operate in at least an SD mode and has a first external signal port. Two external signal ports, the secure digital card is used to couple to the electronic device through the first external signal port and the second external signal port, and the method includes: receiving from the electronic device through the first external signal port and A pin VDD1 of the second external signal port sends a first power signal corresponding to the SD mode to the secure digital card to enter an initialization state; receiving from the electronic device through an interface used in the SD mode A command CMD0 corresponding to the SD mode sent by pin CMD or a specific clock SDCLK corresponding to the SD mode is sent through a pin CLK used in the SD mode to enter the SD mode from the initialization state and Operate in the SD mode; receive a command CMD8 sent from the electronic device through the pin CMD, where the command CMD8 is used to inquire whether the secure digital card supports a PCIe mode; if the PCIe mode is not supported, respond The secure digital card of the electronic device does not support the PCIe mode and is maintained in the SD mode; and if the PCIe mode is supported, the secure digital card supports the PCIe mode in response to the electronic device, and then receives from the electronic device through the second One of a pin VDD2 and a pin VDD3 of the two external signal ports sends a second power signal to enter a connection state of a PCIe mode, and a voltage level of the second power signal is lower than the first power signal. A voltage level of a power signal; wherein the SD mode of the secure digital card adopts a UHS-I input/output communication interface standard, and the multiple pins used as data lines are adopted by the PCIe mode A PCIe channel is shared with another input/output communication interface standard of an NVMe protocol. The plurality of pins used as data lines in the SD mode include pin numbers 1, 7, 8, 9 Pin.

According to an embodiment of the present invention, a flash memory controller of a secure digital card is also disclosed, the secure digital card is used for coupling to an electronic device, the electronic device is located on a host side and has a first external signal port , The secure digital card can operate in at least an SD mode and has a second external signal port, the second external signal port has a plurality of pins for coupling to a plurality of the first external signal port of the electronic device Pin, the secure digital card further includes a flash memory, and the flash memory controller is used for coupling between the flash memory and the second external signal port and includes a register and a processor Circuit. The register is used to temporarily store the information of the flash memory. The processing circuit is coupled to the register, and the processing circuit is used to receive the first one corresponding to the SD mode sent from the electronic device through a pin VDD1 of the first external signal port and the second external signal port The power signal causes the secure digital card to enter an initialization state; the processing circuit is used to receive a command CMD0 corresponding to the SD mode sent from the electronic device through the pin CMD used in the SD mode or through the SD A pin CLK used in the mode sends a specific clock SDCLK corresponding to the SD mode, so that the secure digital card enters the SD mode from the initialization state and operates in the SD mode; the processing circuit is used to receive from the electronic The device sends a command CMD8 through the pin CMD, where the command CMD8 is used to inquire whether the secure digital card supports a PCIe mode; if the secure digital card does not support the PCIe mode, the processing circuit responds to the electronic device The secure digital card does not support the PCIe mode and the secure digital card is maintained in the SD mode; and if the secure digital card supports the PCIe mode, the processing circuit responds to the electronic device that the secure digital card supports the PCIe mode, and then Receiving a second power signal sent from the electronic device through one of a pin VDD2 and a pin VDD3 of the second external signal port, so that the secure digital card enters a connection state of a PCIe mode, the first One of the voltage levels of the second power signal is lower than the voltage level of the first power signal; wherein the SD mode of the secure digital card adopts a UHS-I input/output communication interface standard that is used as a data line A plurality of pins are shared by a PCIe channel adopted by the PCIe mode and another input/output communication interface standard of an NVMe protocol. The plurality of pins used as data lines in the SD mode include pins Multiple pins numbered 1, 7, 8, 9.

The present invention aims to provide a mechanism for a memory card device with one of different data transmission modes. The different data transmission mode is, for example, a secure digital memory card (Secure digital Memory Card). The data transmission mode supported is a secure digital mode (hereinafter referred to as SD Mode) and the PCIe mode that supports both PCIe (Peripheral Component Interconnect Express) channels and NVMe protocol (NVM Express protocol), that is, the PCIe mode is implemented by using the PCIe interface at the bottom layer and the NVMe protocol at the upper layer. It can also be called PCIe/ In NVMe mode, the different data transmission modes share at least one signal pin of an external communication signal port of the memory card device; in addition, the present invention protects and prevents the memory card device from switching between different data transmission modes due to the actual signal level. The circuit damage caused by the difference in voltage and/or the data transmission between the memory card device and the electronic device as the host can adopt a faster transmission mode to increase the transmission rate.

At present, the general security digital cards produced by manufacturers on the market have a small number of pins in the signal port, such as only one row of signal pins. The data transmission mode supported by the secure digital card is SD mode. The UHS-I input/output communication interface standard defined by the model is used for data transmission and communication with the electronic device as the host side.

This case provides a memory card device with different data transmission modes that has a larger number of pins, such as the first row of signal pins and the second row of signal pins, and the supported data transmission interface includes SD mode The defined UHS-I input/output communication interface standard and the PCIe mode that supports both the PCIe interface and the NVMe protocol can communicate with the electronic device as the host through different defined communication standards. In addition, the version information of the driver circuit and/or the driver program of the electronic device as the host side can be divided into, for example, the driver circuit and/or driver program that supports the above-mentioned fewer pins and SD mode and the driver program that supports the above-mentioned larger number Pin and PCIe mode driving circuit and/or driver.

It should be noted that the actual standard voltage values of the signal logic level of the input/output communication interface standards used in SD mode and PCIe mode are different during data transmission. As a result, the memory card device may be affected by the signal logic level. The actual standard voltage value is different and circuit damage occurs.

Therefore, in order to avoid circuit damage and achieve faster control of the memory card device to enter the higher data transmission speed mode that it can support, this case also proposes a novel control of the memory card device to switch between SD mode and PCIe mode. Methods.

The memory card device of the embodiment of the present invention is, for example, a digital security card device (but not limited to). The memory card disclosed in this case has two rows of more pins that support SD mode and PCIe mode, and can operate in either SD mode or PCIe mode. The memory card in this case operates in the SD mode and the PCIe mode. In PCIe mode, at least one pin of an external communication port is shared to communicate with an electronic device acting as a host. The first table below lists the pin numbers used in the SD mode and the corresponding names, types, and descriptions Description, and the second table lists the pin numbers used in the PCIe mode and the corresponding names, types, and descriptions: SD mode Pin number name Types of description 1 CD/DAT3 I/O/PP Card detection/data line 3[bit 3] 2 CMD I/O/PP Command/response 3 VSS1 S Power ground 4 VDD S power supply 5 CLK I Clock 6 VSS2 S Power ground 7 DAT0 I/O/PP Data line 0 [bit 0] 8 DAT1 I/O/PP Data line 1 [bit 1] 9 DAT2 I/O/PP Data line 2 [bit 2]

Among them, S stands for power supply, I stands for input, O stands for output driven by push-pull, and PP stands for input and output driven by push-pull. The above commands are transmitted through the CMD pin, and the data to be transmitted is transmitted through the pins DAT0, DAT1, DAT2, and CD/DAT3. PCIe mode Pin number name Types of description 1 PERST# Input signal (low voltage operation) The function of resetting the memory card defined by the PCIe Mini CEM specification PE-Reset 4 VDD1 Supply voltage 2.7V to 3.6V 7 REFCLK+ Differential signal: input Clock input 8 REFCLK- Differential signal: input Clock input 9 CLKREQ# I/O (low-voltage operation, open drain) Reference clock request signal, also used by L1 PM sub-state 10 VSS3 Grounded 11 PCIe TX+ Differential signal Memory card input 12 PCIe TX- Differential signal Memory card input 13 VSS4 Grounded 14 VDD2 Supply voltage 2 1.70V to 1.95V 15 PCIe RX- Differential signal Memory card output 16 PCIe RX+ Differential signal Memory card output 17 VSS5 Grounded 18* VDD3 Supply voltage 3 1.14V to 1.30V

Among them, "*" means reserved for future use when the pin of supply voltage 3 is used. When the memory card device is operated in the SD mode and the PCIe mode, the common pins used are the pins with pin numbers 1, 7, 8, 9 (not limited by this case); it should be noted that the above description is just an example It is not a limitation of this case. The method flow of this case is applied to the driving circuit of the electronic device as the host side, for controlling the memory card device to enter and operate in SD mode or PCIe mode, which can avoid circuit damage and improve data transmission efficiency at the same time.

Please refer to FIG. 1. FIG. 1 is a flowchart of a method for controlling a data transmission mode of a memory card device according to a first embodiment of the present invention. If substantially the same result can be achieved, it is not necessary to follow the sequence of steps in the process shown in Figure 1, and the steps shown in Figure 1 do not have to be continuous, that is, other steps can be inserted into it. ; The detailed process steps are described below:

Step 105: Start;

Step 110: As an electronic device on the host side, send a first power signal from a driving circuit of the electronic device to the memory card device through a pin VDD1 to control and make the memory card device enter an initialization state, wherein the initialization The state is a virtual initial state (Pseudo initial state);

Step 115: Send a specific command (such as command CMD0) corresponding to the SD mode from the drive circuit of the electronic device through a pin CMD to the memory card device and/or from the drive circuit of the electronic device through a pin CLK Sending a specific clock SDCLK corresponding to the SD mode to the memory card device to control and make the memory card device enter the SD mode from the initialization state and operate in the SD mode;

Step 120: Send a command CMD8 from the drive circuit of the electronic device to the memory card device through the pin CMD to inquire whether the memory card device supports PCIe mode and wait for the memory card device to respond, if the memory card device responds to support In PCIe mode, go to step 125, otherwise, if the memory card device responds that PCIe mode is not supported, go to step 150;

Step 125: Send or activate a second power signal corresponding to the PCIe mode to the memory card device from the drive circuit of the electronic device as the host through the pin VDD2 or VDD3 to control and make the memory card device slave The SD mode enters the Linkup state of the PCIe mode;

Step 130: In the connection state of the PCIe, the memory card device performs a communication connection protocol with the electronic device on the host side, and the electronic device determines whether the protocol is successful. If the communication connection is successful, proceed to step 135, otherwise, If the communication connection fails, proceed to step 140;

Step 135: The electronic device controls the memory card device to operate in the PCIe mode;

Step 140: The electronic device decides whether to retry, if it decides to retry, it proceeds to step 135, otherwise, if it does not retry, it proceeds to step 145;

Step 145: Send the command CMD0 corresponding to the SD mode from the drive circuit of the electronic device through the pin CMD to the memory card device and/or send the command CMD0 corresponding to the SD mode through the pin CLK from the drive circuit of the electronic device A specific clock SDCLK to the memory card device to control and make the memory card device enter the SD mode from the connection state of the PCIe mode and operate in the SD mode;

Step 150: Maintain in the SD mode; and

Step 155: End.

In addition, in one embodiment, the electronic device as the host may decide not to enter the SD mode first, but choose to send the second power signal to the memory card device on the pin VDD2 or the pin VDD3, and try to enter the PCIe mode first. Please refer to FIG. 2. FIG. 2 is a flowchart of a method for controlling a data transmission mode of a memory card device according to a second embodiment of the present invention. If generally the same result can be achieved, it is not necessary to follow the sequence of steps in the process shown in Figure 2, and the steps shown in Figure 2 do not have to be continuous, that is, other steps can be inserted into it. ; The detailed process steps are described below:

Step 205: start;

Step 210: The electronic device as the host sends a first power signal from the drive circuit of the electronic device to the memory card device through the pin VDD1, and controls and causes the memory card device to enter the virtual initialization state;

Step 215: Send or activate a second power signal corresponding to the PCIe mode to the memory card device from the drive circuit of the electronic device as the host through the pin VDD2 or VDD3 to control and make the memory card device slave The SD mode enters the connection state of the PCIe mode;

Step 220: In the connection state of the PCIe, the memory card device performs a communication connection protocol with the electronic device on the host side, and the electronic device determines whether the protocol is successful, if the communication connection is successful, go to step 225, otherwise, If the communication connection fails, go to step 230;

Step 225: The electronic device controls the memory card device to operate in the PCIe mode;

Step 230: The electronic device decides whether to retry, if it decides to retry, proceed to step 220, otherwise, if it does not retry, proceed to step 235;

Step 235: Send the command CMD0 corresponding to the SD mode from the drive circuit of the electronic device through the pin CMD to the memory card device and/or send the command CMD0 corresponding to the SD mode through the pin CLK from the drive circuit of the electronic device A specific clock SDCLK to the memory card device to control and make the memory card device enter the SD mode from the connection state of the PCIe mode and operate in the SD mode; and

Step 240: End.

Figure 3 shows memory card devices with different numbers of pins. For example, the memory card device on the left has only one row of pins (a total of 9 pins). For example, a secure digital card supports the first generation UHS (UHS-I) data transmission interface, and the memory card device provided in this case is, for example, the memory card device on the right, which has two rows of pins (a total of 18 pins), for a secure digital card, for example, it supports SD The UHS-I input/output communication interface standard defined by the mode and the PCIe mode that supports the PCIe interface and the NVMe protocol.

Please refer to FIG. 4, which is a schematic diagram of the state switching of the data transmission mode of the memory card device according to an embodiment of the present invention. In this example, the memory card device is a memory card device that supports both SD mode and PCIe mode. That is, the above-mentioned first mode refers to SD mode, and its data transfer rate may be lower than that of the second mode (PCIe mode). ), and the aforementioned first power signal VDD1, such as 3.3 volts, is different from the second power signal, such as 1.2 volts on pin VDD3 or 1.8 volts on pin VDD2; however, this is not a limitation of this case. For the secure digital card that supports both SD mode and PCIe mode, as shown in Figure 1 and Figure 2, the electronic device as the host can control the secure digital card to operate in SD mode before trying to enter In PCIe mode, you can also control the secure digital card to directly try to enter the PCIe mode first. If it does not work, control the secure digital card to enter the SD mode.

During initialization, the electronic device as the host sends a first power signal (for example, 3.3V) to the secure digital card through the pin VDD1 of the external signal port, so the secure digital card then enters the virtual initialization state.

In the virtual initialization state, as shown in the flow in Figure 1, the electronic device can send a specific command CMD0 corresponding to the SD mode or a specific clock SDCLK corresponding to the secure digital card to make the secure digital card Enter the SD mode from the initialization state, or as shown in the process in Figure 2, the electronic device can be changed to send or activate a second power signal (such as 1.8V or 1.2V) corresponding to the PCIe mode through the pin VDD2 or VDD3 ) To the secure digital card, so that the secure digital card enters the PCIe mode connection state directly from the initialization state.

When the secure digital card is operating in the SD mode, the electronic device can control the secure digital card to try to enter the PCIe mode, and send or activate a second power signal corresponding to the PCIe mode to the secure digital card through the pin VDD2 or VDD3. Control and make the secure digital card enter the connection state of PCIe mode from SD mode.

When the secure digital card is connected in PCIe mode, the electronic device can control the secure digital card to enter the SD mode by sending the specific command CMD0 corresponding to the SD mode or the corresponding specific clock SDCLK to the secure digital card , Control and make the secure digital card enter SD mode from the connection state of PCIe mode, where the connection state of PCIe mode refers to the state of waiting for the connection protocol result before entering PCIe mode, so even if a secure digital card does not support PCIe mode , It may also enter the state of waiting for connection. Therefore, if the result of the connection protocol is unsuccessful, the electronic device will send the specific command CMD0 corresponding to the SD mode or the specific clock SDCLK corresponding to the secure digital card. Control the secure digital card to enter SD mode from the state of waiting for connection. When the connection protocol between the electronic device and the secure digital card is successful, the secure digital card is controlled to enter the PCIe mode from the connection state of the PCIe mode.

When operating in PCIe mode, the secure digital card can exit the PCIe mode and return to the PCIe mode connection state, or the electronic device can turn off the second power signal corresponding to the PCIe mode on the pin VDD2 or VDD3, Control and make the secure digital card return from the PCIe mode to a virtual initialization state.

For example, when operating in PCIe mode, the bottom layer of the communication between the secure digital card and the electronic device as the host will record a register Linkup, which can be temporarily stored in the electronic device (For example, in the corresponding drive circuit; but not limited), when the secure digital card changes from operating in PCIe mode to connection failure, the temporarily stored connection parameter will become zero, and the secure digital card will exit PCIe mode and return to In the PCIe mode of the connection state, the electronic device will try to connect again at this time, and the number of reconnections depends on the design of the electronic device and is not limited. With the above operations, the electronic device can dynamically control and switch the mode of the secure digital card in response to the requirements of different system performance and so on, and is not limited to a mode that necessarily operates at a faster data transmission rate.

When the secure digital card is in the PCIe mode connection state, the electronic device can also control the secure digital card to enter a virtual initialization state by turning off the second power signal on the pin VDD2 or the pin VDD3.

Please refer to FIG. 5. FIG. 5 is a block diagram of a memory card device (such as a secure digital card) 400 and an electronic device 405 as a host terminal implemented by the method of the embodiment of the present invention. The memory card 400 includes an external signal port 4001, a flash memory 410, and a flash memory controller 420. The controller 420 is coupled between the external signal port 4001 and the flash memory 410 and passes through an internal bus. Connected to the flash memory 410, the flash memory controller 420 includes a register 415 and a processing circuit 416. The register 415 can be used to temporarily store the basic data of the flash memory 410, and the processing circuit 416 It is used to perform the corresponding operations of the flash memory controller 420 (for example, the above-mentioned input/output interface data or signal receiving, sending, and accessing calculations, etc.). The flash memory 410 includes one or more flashes Memory chip. The electronic device 405 includes an external signal port 4055, a memory card driving circuit 4051, and a processor 4053. The electronic device 405 is coupled to the memory card 400 through the signal ports 4055 and 4001 (the signal ports each include a plurality of corresponding pins). The memory card 400 can at least operate in the SD mode. The processor 4053 is used to control the driving circuit 4051 to send the first power signal corresponding to the SD mode to the memory card 400 through the external signal port 4055 and the pin VDD1 of the external signal port 4001 from the electronic device 405, and the controller 420 When the first power signal is detected on the pin VDD1, the memory card 400 is controlled to enter the initialization state accordingly. In addition, the memory card 400 can be additionally operated in PCIe mode. When the memory card 400 is operated in SD mode and PCIe mode, some pins of the external signal port 4001, for example, pins with pin numbers 1, 7, 8, 9 will be shared .

In addition, the processor 4053 controls the driving circuit 4051 to send the second power signal corresponding to the PCIe mode from the electronic device 405 to the memory card 400 through the pin VDD2 or to send the second power corresponding to the PCIe mode through the pin VDD3 Signal to the memory card 400, and when the controller 420 detects the second power signal on the pin VDD2 or VDD3, for example, if the second power signal is detected on the pin VDD3, it will control and make the memory accordingly The card 400 enters the PCIe mode connection state from the initialization state. In the PCIe mode connection state, the processor 4053 performs a communication connection protocol with the controller 420 of the memory card 400 through the drive circuit 4051, the external signal port 4055, and the external signal port 4001 If the communication connection protocol is successful, the memory card 400 will operate in the PCIe mode; if the communication connection protocol is unsuccessful, the drive circuit 4051 can retry, and if it decides not to retry, the memory card 400 will be in the connected state Enter SD mode.

In addition, the processor 4053 can also control the drive circuit 4051 in the PCIe mode connection state, through the drive circuit 4051, the external signal port 4055, and the external signal port 4001 to turn off the PCIe mode transmitted on pin VDD2 or pin VDD3. The second power signal is used to control and return the memory card 400 from the PCIe mode connection state to the initialization state.

In addition, the processor 4053 can also control the drive circuit 4051. Through the drive circuit 4051, the external signal port 4055 and the external signal port 4001, the electronic device 405 sends specific commands corresponding to the SD mode, such as CMD0 and a corresponding specific clock SDCLK. At least one of them is sent to the controller 420 of the memory card 400 to control and make the memory card 400 enter the SD mode from the initialization state accordingly.

FIG. 6 is a schematic diagram of a signal example of some pins of the electronic device 405 on the host side shown in FIG. 5 directly controlling the memory card 400 to enter the PCIe mode from the initialization state. As shown in Figure 6, the electronic device 405 as the host first pulls the pin CMD from a low voltage level (for example, zero volt) to a high voltage level (for example, 3.3 volts or 1.8 volts), and also connects the pin CLKREQ# pulls from zero volts to 3.3 volts or 1.8 volts, and pulls the pin VDD1 from a low voltage level (such as zero volt) to a high voltage level (such as 3.3 volts) to provide the first power signal to the memory The card 400 makes the memory card 400 enter the initialization state.

In this embodiment, the electronic device 405 chooses to directly control the memory card 400 to try to enter the PCIe mode, and therefore directly provides the second power signal in the initialization state to pull the pin VDD3 from a low voltage level (for example, zero volt) to a high level. Voltage level (for example, 1.2 volts); it should be noted that the electronic device 405 can also pull the pin VDD2 from a low voltage level (for example, zero volt) to a high voltage level (for example, 1.8 volts) to provide the second power signal Depends on the design of the electronic device 405 and whether the memory card 400 supports the pin VDD3. If the memory card 400 does not support the pin VDD3, the electronic device 405 can try to change the pin VDD2 from a low voltage level (such as zero volts) Pull up to a high voltage level (for example, 1.8V), or directly control the memory card 400 to enter the SD mode.

Therefore, as shown in the embodiment in FIG. 6, when the memory card 400 detects that the pin VDD3 is pulled up from, for example, zero volts to, for example, 1.2 volts, it will enter the PCIe mode connection state. In the PCIe mode connection state, the memory card 400 will pull down the pin CLKREQ# from 3.3 volts or 1.8 volts to zero volts, for example, to inform the electronic device 405 that it has received the PCIe mode connection request and is ready to receive the data from the electronic device 405. Provided the clock input signal, and the electronic device 405 as the host will wait, for example, at most 1 millisecond (ms) to detect whether the pin CLKREQ# is pulled down from the high voltage level to the low voltage level, and if it is pulled down to If the voltage level is low, the electronic device 405 will then start to transmit a differential clock input signal (for example, between 0.8V and 1.2V) to the memory card 400 through the pin REFCLK- and pin REFCLK+, and determine whether it can be stable Provide the differential clock input signal for at least 100 microseconds, for example, if the differential clock input signal can be stably provided, the electronic device 405 will then pull the pin PERST# from a low voltage level (for example, zero volts) As high as a high voltage level (for example, 3.3 volts or 1.8 volts), the electronic device 405 starts to perform link training in PCIe mode. After the link training is completed, the memory card 400 operates in PCIe mode. Initialization of PCIe mode.

And if the connection status of PCIe mode fails (for example, the pin CLKREQ# is always at a high voltage level and has not been pulled down by the memory card 400, or the link training in PCIe mode has been failed), the memory card 400 will enter SD mode , The electronic device 405 accesses the memory card 400 through the UHS-I data transmission interface in SD mode.

In addition, it should be noted that, in the embodiment shown in Figure 6, since the clock signal SDCLK corresponding to the SD mode is not received (the level of the signal SDCLK is maintained at a low voltage level (such as zero volts, for example). )), so the memory card 400 will not enter the SD mode from the initialization state. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should fall within the scope of the present invention.

105~155,205~240: steps 400: Memory card 405: electronic device 410: flash memory 415: register 416: processing circuit 420: flash memory controller 4001, 4055: External signal port 4051: Memory card drive circuit 4053: processor

FIG. 1 is a schematic flowchart of a method for controlling a data transmission mode of a memory card device according to the first embodiment of the present invention. FIG. 2 is a schematic flowchart of a method for controlling a data transmission mode of a memory card device according to a second embodiment of the present invention. Figure 3 is a schematic diagram of the back of different memory card devices with different numbers of pins. FIG. 4 is a schematic diagram of state switching of the data transmission mode of the memory card device according to the embodiment of the present invention. FIG. 5 is a block diagram of the memory card device and the electronic device implemented by the method of the embodiment of the present invention. FIG. 6 is a schematic diagram of a signal example of some pins of the electronic device on the host side that directly controls the memory card to enter the PCIe mode from the initialization state as shown in FIG. 5.

105~155: steps

Claims (8)

A method for controlling a data transmission mode of a secure digital card. As a host, an electronic device has a first external signal port, the secure digital card can at least operate in an SD mode and has a second external signal Port, the secure digital card is used to couple to the electronic device through the first external signal port and the second external signal port, and the method includes: From the electronic device as the host, send a first power signal corresponding to the SD mode to the secure digital card through a pin VDD1 of the first external signal port and the second external signal port to control the The secure digital card enters an initialization state; From the electronic device, send a second power signal to the secure digital card through one of a pin VDD2 and a pin VDD3 of the second external signal port, and control the secure digital card to enter a PCIe mode connection State, a voltage level of the second power signal is lower than a voltage level of the first power signal; In the connection state of the PCIe mode, using the electronic device to perform a communication connection protocol with the secure digital card; If the communication connection protocol is successful, the secure digital card operates in the PCIe mode; and If the communication connection protocol is unsuccessful, send a command CMD0 corresponding to the SD mode on a pin CMD used in the SD mode from the electronic device through the first external signal port and the second external signal port. Or, on a pin CLK used in the SD mode, a specific clock SDCLK corresponding to the SD mode is sent to the secure digital card to control the secure digital card to enter the SD mode from the connected state. The method described in item 1 of the scope of the patent application also includes: In the connection state of the PCIe mode, turn off the second power signal of the PCIe mode from the electronic device through the first external signal port and the second external signal port, and control the secure digital card to return from the connection state The initialization state. An electronic device for being coupled to a secure digital card and capable of controlling a data transmission mode of the secure digital card. The electronic device is located on a host and has a first external signal port. The secure digital card can be operated at least An SD mode and a second external signal port, and the electronic device includes: The first external signal port has a plurality of pins for coupling to a plurality of pins of the second external signal port of the secure digital card; A driving circuit for coupling to the first external signal port; and A processor for coupling to the driving circuit, and for: Control the driving circuit to send a first power signal corresponding to the SD mode to the secure digital card from the electronic device through a pin VDD1 of the first external signal port and the second external signal port, and control the secure digital card The card enters an initialization state; From the electronic device, send a second power signal to the secure digital card through one of a pin VDD2 and a pin VDD3 of the second external signal port, and control the secure digital card to enter a PCIe mode connection State, a voltage level of the second power signal is lower than a voltage level of the first power signal; In the connection state of the PCIe mode, perform a communication connection protocol with the secure digital card; If it is determined that the communication connection protocol is successful, make the secure digital card operate in the PCIe mode; and If the communication connection protocol is unsuccessful, the first external signal port and the second external signal port are used to send a command CMD0 corresponding to the SD mode on a pin CMD used in the SD mode or to the SD A specific clock SDCLK corresponding to the SD mode is sent to the secure digital card on a pin CLK used in the mode, and the secure digital card is controlled to enter the SD mode from the connected state. For example, the electronic device described in item 3 of the scope of patent application, wherein when the secure digital card is in the connection state of the PCIe mode, the processor is used to control the driving circuit through the first external signal port and the first external signal port. The two external signal ports turn off the second power signal of the PCIe mode, and control the secure digital card to return from the connection state to the initialization state. A method used in a secure digital card. As a host, an electronic device has a first external signal port. The secure digital card can operate in at least an SD mode and has a second external signal port. The secure digital card For coupling to the electronic device through the first external signal port and the second external signal port, and the method includes: Receiving a first power signal corresponding to the SD mode sent from the electronic device through a pin VDD1 of the first external signal port and the second external signal port to enter an initialization state; and Receiving a second power signal sent from the electronic device through one of a pin VDD2 and a pin VDD3 of the second external signal port to enter a connection state of a PCIe mode, the second power signal is A voltage level is lower than a voltage level of the first power signal; Performing a communication connection protocol with the electronic device in the connection state of the PCIe mode; If the communication connection protocol is successful, the secure digital card operates in the PCIe mode; and If the communication connection protocol is unsuccessful, then from the electronic device through the first external signal port and the second external signal port on a pin CMD used in the SD mode to receive a command CMD0 or corresponding to the SD mode A specific clock SDCLK corresponding to the SD mode is received on a pin CLK used in the SD mode to the secure digital card to enter the SD mode from the connected state. The method described in item 5 of the scope of patent application also includes: In the connection state of the PCIe mode, when the electronic device detects that the second power signal of the PCIe mode is turned off through the first external signal port and the second external signal port, it returns from the connection state The initialization state. A flash memory controller for a secure digital card, the secure digital card is used to couple to an electronic device, the electronic device is located on a host side and has a first external signal port, the secure digital card can be operated at least An SD mode has a second external signal port, the second external signal port has a plurality of pins for coupling to the plurality of pins of the first external signal port of the electronic device, and the secure digital card further includes A flash memory, and the flash memory controller is used for coupling between the flash memory and the second external signal port and includes: A register for temporarily storing the information of the flash memory; and A processing circuit, coupled to the register, for: Receiving a first power signal corresponding to the SD mode sent from the electronic device through a pin VDD1 of the first external signal port and the second external signal port, so that the secure digital card enters an initialization state; Receiving a second power signal sent from the electronic device through one of a pin VDD2 and a pin VDD3 of the second external signal port, so that the secure digital card enters a connection state of a PCIe mode, the first A voltage level of the second power signal is lower than a voltage level of the first power signal; Performing a communication connection protocol with the electronic device in the connection state of the PCIe mode; If the communication connection protocol is successful, the processing circuit will operate in the PCIe mode; and If the communication connection protocol is unsuccessful, the processing circuit will receive a command CMD0 or corresponding to the SD mode on a pin CMD used in the SD mode through the first external signal port and the second external signal port. A specific clock SDCLK corresponding to the SD mode is received on a pin CLK used in the SD mode, so that the secure digital card enters the SD mode from the connected state. The flash memory controller described in item 7 of the scope of patent application, wherein when the secure digital card is in the connection state of the PCIe mode, if the processing circuit detects the second power signal of the PCIe mode Is closed, the processing circuit will control the secure digital card to return from the connected state to the initialized state.

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