TW202105228A - Methods, flash memory controller, and electronic device for secure digital memory card device - Google Patents
Methods, flash memory controller, and electronic device for secure digital memory card device Download PDFInfo
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本發明係關於一種控制記憶卡裝置之資料傳輸模式的機制,特別涉及一種控制一安全數位卡之資料傳輸模式的方法及電子裝置。The present invention relates to a mechanism for controlling the data transmission mode of a memory card device, and more particularly to a method and an electronic device for controlling the data transmission mode of a secure digital card.
一般來說,市面上不同廠商所設計、生產製造或販售之記憶卡裝置的類型有所不同,類型不同的記憶卡裝置可能有不同個數的訊號接腳以及所支援的資料傳輸模式也可能不相同,而不同資料傳輸模式所對應採用之輸入/輸出通訊介面標準所規定之邏輯訊號準位的實際電壓值以及電源供應準位的電壓值也並不相同,因此,當一記憶卡裝置連接上一主機端時,如果主機端與記憶卡裝置所支援的資料傳輸模式不相同時,則可能會造成電路損傷。Generally speaking, the types of memory card devices designed, manufactured, or sold by different manufacturers on the market are different. Different types of memory card devices may have different numbers of signal pins and supported data transmission modes. The actual voltage value of the logic signal level and the voltage value of the power supply level specified by the input/output communication interface standard corresponding to different data transmission modes are also different. Therefore, when a memory card device is connected On the previous host side, if the data transmission modes supported by the host side and the memory card device are not the same, it may cause circuit damage.
因此,本發明之目的之一在於提出一種用以控制一安全數位卡之資料傳輸模式的方法、對應的電子裝置、使用於一安全數位卡的方法以及安全數位卡的一快閃記憶體控制器,以解決現有技術的難題。Therefore, one of the objectives of the present invention is to provide a method for controlling the data transmission mode of a secure digital card, a corresponding electronic device, a method used in a secure digital card, and a flash memory controller of the secure digital card , In order to solve the problems of existing technology.
根據本發明之實施例,其係揭露一種用以控制一安全數位卡之一資料傳輸模式的方法,作為一主機端之一電子裝置具有一第一外部訊號埠,該安全數位卡至少可操作於一SD模式並具有一第二外部訊號埠,該安全數位卡用以通過該第一外部訊號埠與該第二外部訊號埠耦接於該電子裝置,以及該方法包含:從作為該主機端之該電子裝置,通過該第一外部訊號埠與該第二外部訊號埠的一接腳VDD1,發送對應於該SD模式之一第一電源訊號至該安全數位卡,控制該安全數位卡進入一初始化狀態;以及從該電子裝置,通過該第二外部訊號埠的一接腳VDD2與一接腳VDD3的其中一個,發送一第二電源訊號至該安全數位卡,控制該安全數位卡進入一PCIe模式之一連接狀態,該第二電源訊號之一電壓準位低於該第一電源訊號之一電壓準位;其中該安全數位卡之該SD模式所採用之一UHS-I輸入/輸出通訊介面標準之用於作為資料線的複數個接腳係被該PCIe模式所採用之一PCIe通道與一NVMe協定的另一輸入/輸出通訊介面標準所共用,該SD模式之用於作為資料線的該複數個接腳包含有接腳編號為1、7、8、9的多個接腳。According to an embodiment of the present invention, a method for controlling a data transmission mode of a secure digital card is disclosed. As a host, an electronic device has a first external signal port, and the secure digital card can be operated at least An SD mode has a second external signal port, the secure digital card is used to couple to the electronic device through the first external signal port and the second external signal port, and the method includes: The electronic device sends a first power signal corresponding to the SD mode to the secure digital card through a pin VDD1 of the first external signal port and the second external signal port, and controls the secure digital card to enter an initialization Status; and from the electronic device, through one of a pin VDD2 and a pin VDD3 of the second external signal port, a second power signal is sent to the secure digital card to control the secure digital card to enter a PCIe mode A connection state, a voltage level of the second power signal is lower than a voltage level of the first power signal; wherein the SD mode of the secure digital card adopts a UHS-I input/output communication interface standard The plurality of pins used as data lines are shared by a PCIe channel adopted by the PCIe mode and another input/output communication interface standard of an NVMe protocol. The SD mode is used as the plurality of data lines Each pin includes multiple pins with pin numbers 1, 7, 8, 9.
根據本發明之實施例,另揭露一種電子裝置,電子裝置用以耦接至一安全數位卡並可控制該安全數位卡之一資料傳輸模式,該電子裝置位於一主機端並具有一第一外部訊號埠,該安全數位卡至少可操作於一SD模式並具有一第二外部訊號埠,以及該電子裝置包含該第一外部訊號埠、一驅動電路以及一處理器,該第一外部訊號埠具有多個接腳用以耦接至該安全數位卡的該第二外部訊號埠的多個接腳,驅動電路耦接至該第一外部訊號埠。該處理器,耦接至該驅動電路,並用以:控制該驅動電路從該電子裝置通過該第一外部訊號埠與該第二外部訊號埠的一接腳VDD1,發送對應於該SD模式之一第一電源訊號至該安全數位卡,控制該安全數位卡進入一初始化狀態;以及從該電子裝置,通過該第二外部訊號埠的一接腳VDD2與一接腳VDD3的其中一個,發送一第二電源訊號至該安全數位卡,控制該安全數位卡進入一PCIe模式之一連接狀態,該第二電源訊號之一電壓準位低於該第一電源訊號之一電壓準位;其中該安全數位卡之該SD模式所採用之一UHS-I輸入/輸出通訊介面標準之用於作為資料線的複數個接腳係被該PCIe模式所採用之一PCIe通道與一NVMe協定的另一輸入/輸出通訊介面標準所共用,該SD模式之用於作為資料線的該複數個接腳包含有接腳編號為1、7、8、9的多個接腳。According to an embodiment of the present invention, an electronic device is also disclosed. The electronic device is coupled to a secure digital card and can control a data transmission mode of the secure digital card. The electronic device is located on a host and has a first external device. A signal port, the secure digital card can operate in at least an SD mode and has a second external signal port, and the electronic device includes the first external signal port, a driving circuit and a processor, the first external signal port has The pins are used for coupling to the pins of the second external signal port of the secure digital card, and the driving circuit is coupled to the first external signal port. The processor is coupled to the driving circuit and used for: controlling the driving circuit to send a pin VDD1 corresponding to the SD mode from the electronic device through the first external signal port and the second external signal port The first power signal is sent to the secure digital card to control the secure digital card to enter an initialization state; and from the electronic device, through one of a pin VDD2 and a pin VDD3 of the second external signal port, a second external signal port is sent. Two power signals to the secure digital card to control the secure digital card to enter a connection state in a PCIe mode, a voltage level of the second power signal is lower than a voltage level of the first power signal; wherein the secure digital card The SD mode of the card adopts a UHS-I input/output communication interface standard. The multiple pins used as the data line are used by the PCIe mode. One PCIe channel and the other input/output of the NVMe protocol Common to the communication interface standard, the multiple pins used as data lines in the SD mode include multiple pins with pin numbers 1, 7, 8, 9.
根據本發明之實施例,另揭露一種用以控制一安全數位卡之一資料傳輸模式的方法,作為一主機端之一電子裝置具有一第一外部訊號埠,該安全數位卡至少可操作於一SD模式並具有一第二外部訊號埠,該安全數位卡用以通過該第一外部訊號埠與該第二外部訊號埠耦接於該電子裝置,以及該方法包含:從作為該主機端之該電子裝置,通過該第一外部訊號埠與該第二外部訊號埠的一接腳VDD1,發送對應於該SD模式之一第一電源訊號至該安全數位卡,控制該安全數位卡進入一初始化狀態;從該電子裝置通過該SD模式所採用之一接腳CMD發送該SD模式所對應之一命令CMD0至該安全數位卡或是通過該SD模式所採用之一接腳CLK發送該SD模式所對應之一特定時脈SDCLK至該安全數位卡,控制並令該安全數位卡從該初始化狀態進入該SD模式並操作於該SD模式;從該電子裝置通過該接腳CMD發送一命令CMD8至該安全數位卡以詢問該安全數位卡是否支援一PCIe模式;如果該安全數位卡回應不支援該PCIe模式,則令該安全數位卡維持於該SD模式;以及如果該安全數位卡回應支援該PCIe模式,則從該電子裝置通過該第二外部訊號埠的一接腳VDD2與一接腳VDD3的其中一個,發送一第二電源訊號至該安全數位卡,控制該安全數位卡進入一PCIe模式之一連接狀態,該第二電源訊號之一電壓準位低於該第一電源訊號之一電壓準位;其中該安全數位卡之該SD模式所採用之一UHS-I輸入/輸出通訊介面標準之用於作為資料線的複數個接腳係被該PCIe模式所採用之一PCIe通道與一NVMe協定的另一輸入/輸出通訊介面標準所共用,該SD模式之用於作為資料線的該複數個接腳包含有接腳編號為1、7、8、9的多個接腳。According to an embodiment of the present invention, a method for controlling a data transmission mode of a secure digital card is also disclosed. As a host, an electronic device has a first external signal port, and the secure digital card can operate on at least one The SD mode has a second external signal port, the secure digital card is used to couple to the electronic device through the first external signal port and the second external signal port, and the method includes: from the host as the host The electronic device sends a first power signal corresponding to the SD mode to the secure digital card through a pin VDD1 of the first external signal port and the second external signal port, and controls the secure digital card to enter an initialization state ; Send a command CMD0 corresponding to the SD mode from the electronic device to the secure digital card through a pin CMD used in the SD mode or send the SD mode corresponding to a pin CLK used in the SD mode A specific clock SDCLK is sent to the secure digital card to control and make the secure digital card enter the SD mode from the initialization state and operate in the SD mode; send a command CMD8 to the secure digital card from the electronic device through the pin CMD The digital card asks whether the secure digital card supports a PCIe mode; if the secure digital card responds that it does not support the PCIe mode, the secure digital card is maintained in the SD mode; and if the secure digital card responds that it supports the PCIe mode, Then, the electronic device sends a second power signal to the secure digital card through one of a pin VDD2 and a pin VDD3 of the second external signal port, and controls the secure digital card to enter a PCIe mode connection State, a voltage level of the second power signal is lower than a voltage level of the first power signal; wherein the SD mode of the secure digital card adopts a UHS-I input/output communication interface standard for The multiple pins used as the data line are shared by a PCIe channel adopted by the PCIe mode and another input/output communication interface standard of an NVMe protocol. The SD mode is used as the multiple pins of the data line Contains multiple pins with pin numbers 1, 7, 8, 9.
根據本發明之實施例,另揭露一種電子裝置,電子裝置用以耦接至一安全數位卡並可用以控制該安全數位卡之一資料傳輸模式,該電子裝置位於一主機端並具有一第一外部訊號埠,該安全數位卡至少可操作於一SD模式並具有一第二外部訊號埠,以及該電子裝置包含該第一外部訊號埠、一驅動電路以及一處理器,該第一外部訊號埠具有多個接腳用以耦接至該安全數位卡的該第二外部訊號埠的多個接腳,驅動電路耦接至該第一外部訊號埠。處理器耦接至該驅動電路,並用以:控制該驅動電路從該電子裝置通過該第一外部訊號埠與該第二外部訊號埠的一接腳VDD1,發送對應於該SD模式之一第一電源訊號至該安全數位卡,控制該安全數位卡進入一初始化狀態;該處理器控制該驅動電路從該電子裝置通過該SD模式所採用之該接腳CMD發送該SD模式所對應之一命令CMD0至該安全數位卡或是通過該SD模式所採用之一接腳CLK發送該SD模式所對應之一特定時脈SDCLK至該安全數位卡,控制該安全數位卡從該初始化狀態進入該SD模式並操作於該SD模式;該處理器控制該驅動電路從該電子裝置通過該接腳CMD發送一命令CMD8至該安全數位卡以詢問該安全數位卡是否支援一PCIe模式;如果該安全數位卡回應不支援該PCIe模式,則該處理器令該安全數位卡維持於該SD模式;以及如果該安全數位卡回應支援該PCIe模式,則該處理器控制該驅動電路從該電子裝置通過該第二外部訊號埠的一接腳VDD2與一接腳VDD3的其中一個,發送一第二電源訊號至該安全數位卡,控制該安全數位卡進入一PCIe模式之一連接狀態,該第二電源訊號之一電壓準位低於該第一電源訊號之一電壓準位;其中該安全數位卡之該SD模式所採用之一UHS-I輸入/輸出通訊介面標準之用於作為資料線的複數個接腳係被該PCIe模式所採用之一PCIe通道與一NVMe協定的另一輸入/輸出通訊介面標準所共用,該SD模式之用於作為資料線的該複數個接腳包含有接腳編號為1、7、8、9的多個接腳。According to an embodiment of the present invention, an electronic device is also disclosed. The electronic device is coupled to a secure digital card and can be used to control a data transmission mode of the secure digital card. The electronic device is located on a host and has a first An external signal port, the secure digital card can operate in at least an SD mode and has a second external signal port, and the electronic device includes the first external signal port, a driving circuit and a processor, the first external signal port There are a plurality of pins for coupling to the second external signal port of the secure digital card, and the driving circuit is coupled to the first external signal port. The processor is coupled to the driving circuit, and is used to: control the driving circuit to send a first signal corresponding to the SD mode from the electronic device through a pin VDD1 of the first external signal port and the second external signal port A power signal to the secure digital card controls the secure digital card to enter an initialization state; the processor controls the drive circuit to send a command CMD corresponding to the SD mode from the electronic device through the pin CMD used in the SD mode To the secure digital card or send a specific clock SDCLK corresponding to the SD mode to the secure digital card through a pin CLK used in the SD mode to control the secure digital card to enter the SD mode from the initialization state and Operate in the SD mode; the processor controls the drive circuit to send a command CMD8 from the electronic device to the secure digital card via the pin CMD to inquire whether the secure digital card supports a PCIe mode; if the secure digital card responds no If the PCIe mode is supported, the processor maintains the secure digital card in the SD mode; and if the secure digital card responds to support the PCIe mode, the processor controls the driving circuit to pass the second external signal from the electronic device One of a pin VDD2 and a pin VDD3 of the port sends a second power signal to the secure digital card to control the secure digital card to enter a connection state in a PCIe mode, and a voltage of the second power signal is standard Is lower than a voltage level of the first power signal; wherein the SD mode of the secure digital card adopts a UHS-I input/output communication interface standard that uses a plurality of pins used as data lines by the One PCIe channel used in PCIe mode is shared with another input/output communication interface standard of an NVMe protocol. The multiple pins used as data lines in the SD mode include pin numbers 1, 7, 8 , 9 multiple pins.
根據本發明之實施例,另揭露一種使用於一安全數位卡之方法,作為一主機端之一電子裝置具有一第一外部訊號埠,該安全數位卡至少可操作於一SD模式並具有一第二外部訊號埠,該安全數位卡用以通過該第一外部訊號埠與該第二外部訊號埠耦接於該電子裝置,以及該方法包含:接收從該電子裝置通過該第一外部訊號埠與該第二外部訊號埠的一接腳VDD1所發送對應於該SD模式之一第一電源訊號,以進入一初始化狀態;以及接收從該電子裝置通過該第二外部訊號埠的一接腳VDD2與一接腳VDD3的其中一個所發送之一第二電源訊號,以進入一PCIe模式之一連接狀態,該第二電源訊號之一電壓準位低於該第一電源訊號之一電壓準位;其中該安全數位卡之該SD模式所採用之一UHS-I輸入/輸出通訊介面標準之用於作為資料線的複數個接腳係被該PCIe模式所採用之一PCIe通道與一NVMe協定的另一輸入/輸出通訊介面標準所共用,該SD模式之用於作為資料線的該複數個接腳包含有接腳編號為1、7、8、9的多個接腳。According to an embodiment of the present invention, a method for use in a secure digital card is also disclosed. As a host, an electronic device has a first external signal port, and the secure digital card can operate in at least an SD mode and has a first external signal port. Two external signal ports, the secure digital card is used to couple to the electronic device through the first external signal port and the second external signal port, and the method includes: receiving from the electronic device through the first external signal port and A pin VDD1 of the second external signal port sends a first power signal corresponding to the SD mode to enter an initialization state; and receives a pin VDD2 and a pin VDD2 from the electronic device through the second external signal port One of the pins VDD3 sends a second power signal to enter a connection state in a PCIe mode, and a voltage level of the second power signal is lower than a voltage level of the first power signal; The SD mode of the secure digital card adopts a UHS-I input/output communication interface standard. The plurality of pins used as data lines are the other of the PCIe channel and the NVMe protocol adopted by the PCIe mode. Common to the input/output communication interface standard, the multiple pins used as data lines in the SD mode include multiple pins with pin numbers 1, 7, 8, 9.
根據本發明之實施例,另揭露一種安全數位卡的一快閃記憶體控制器,該安全數位卡用以耦接至一電子裝置,該電子裝置位於一主機端並具有一第一外部訊號埠,該安全數位卡至少可操作於一SD模式並具有一第二外部訊號埠,該第二外部訊號埠具有多個接腳用以耦接至該電子裝置的該第一外部訊號埠的多個接腳,該安全數位卡另包含一快閃記憶體,以及該快閃記憶體控制器用以耦接於該快閃記憶體與該第二外部訊號埠之間並包含有一暫存器與一處理電路。暫存器用以暫存該快閃記憶體的資訊。處理電路耦接於該暫存器,用以接收從該電子裝置通過該第一外部訊號埠與該第二外部訊號埠的一接腳VDD1所發送之對應於該SD模式之一第一電源訊號,令該安全數位卡進入一初始化狀態;以及該處理電路用以接收從該電子裝置通過該第二外部訊號埠的一接腳VDD2與一接腳VDD3的其中一個所發送之一第二電源訊號,令該安全數位卡進入一PCIe模式之一連接狀態,該第二電源訊號之一電壓準位低於該第一電源訊號之一電壓準位;其中該安全數位卡之該SD模式所採用之一UHS-I輸入/輸出通訊介面標準之用於作為資料線的複數個接腳係被該PCIe模式所採用之一PCIe通道與一NVMe協定的另一輸入/輸出通訊介面標準所共用,該SD模式之用於作為資料線的該複數個接腳包含有接腳編號為1、7、8、9的多個接腳。According to an embodiment of the present invention, a flash memory controller of a secure digital card is also disclosed, the secure digital card is used for coupling to an electronic device, the electronic device is located on a host side and has a first external signal port , The secure digital card can operate in at least an SD mode and has a second external signal port, the second external signal port having a plurality of pins for coupling to a plurality of the first external signal port of the electronic device Pin, the secure digital card further includes a flash memory, and the flash memory controller is used for coupling between the flash memory and the second external signal port and includes a register and a processor Circuit. The register is used to temporarily store the information of the flash memory. The processing circuit is coupled to the register for receiving a first power signal corresponding to the SD mode sent from the electronic device through a pin VDD1 of the first external signal port and the second external signal port , Make the secure digital card enter an initialization state; and the processing circuit is used to receive a second power signal sent from the electronic device through one of a pin VDD2 and a pin VDD3 of the second external signal port , Make the secure digital card enter a connection state in a PCIe mode, a voltage level of the second power signal is lower than a voltage level of the first power signal; wherein the SD mode of the secure digital card is adopted The multiple pins of a UHS-I input/output communication interface standard used as data lines are shared by a PCIe channel adopted by the PCIe mode and another input/output communication interface standard of the NVMe protocol. The SD The plurality of pins used as the data line of the mode includes a plurality of pins with pin numbers 1, 7, 8, 9.
根據本發明之實施例,另揭露一種使用於一安全數位卡之方法,作為一主機端之一電子裝置具有一第一外部訊號埠,該安全數位卡至少可操作於一SD模式並具有一第二外部訊號埠,該安全數位卡用以通過該第一外部訊號埠與該第二外部訊號埠耦接於該電子裝置,以及該方法包含:接收從該電子裝置通過該第一外部訊號埠與該第二外部訊號埠的一接腳VDD1所發送對應於該SD模式之一第一電源訊號至該安全數位卡,以進入一初始化狀態;接收從該電子裝置通過該SD模式所採用之一接腳CMD所發送之該SD模式所對應之一命令CMD0或是通過該SD模式所採用之一接腳CLK發送該SD模式所對應之一特定時脈SDCLK,以從該初始化狀態進入該SD模式並操作於該SD模式;接收從該電子裝置通過該接腳CMD所發送之一命令CMD8,其中該命令CMD8用以詢問該安全數位卡是否支援一PCIe模式;如果不支援該PCIe模式,則回應該電子裝置該安全數位卡不支援該PCIe模式並令維持於該SD模式;以及如果支援該PCIe模式,則回應該電子裝置該安全數位卡支援該PCIe模式,並接著接收從該電子裝置通過該第二外部訊號埠的一接腳VDD2與一接腳VDD3的其中一個所發送之一第二電源訊號,以進入一PCIe模式之一連接狀態,該第二電源訊號之一電壓準位低於該第一電源訊號之一電壓準位;其中該安全數位卡之該SD模式所採用之一UHS-I輸入/輸出通訊介面標準之用於作為資料線的複數個接腳係被該PCIe模式所採用之一PCIe通道與一NVMe協定的另一輸入/輸出通訊介面標準所共用,該SD模式之用於作為資料線的該複數個接腳包含有接腳編號為1、7、8、9的多個接腳。According to an embodiment of the present invention, a method for use in a secure digital card is also disclosed. As a host, an electronic device has a first external signal port, and the secure digital card can operate in at least an SD mode and has a first external signal port. Two external signal ports, the secure digital card is used to couple to the electronic device through the first external signal port and the second external signal port, and the method includes: receiving from the electronic device through the first external signal port and A pin VDD1 of the second external signal port sends a first power signal corresponding to the SD mode to the secure digital card to enter an initialization state; receiving from the electronic device through an interface used in the SD mode A command CMD0 corresponding to the SD mode sent by pin CMD or a specific clock SDCLK corresponding to the SD mode is sent through a pin CLK used in the SD mode to enter the SD mode from the initialization state and Operate in the SD mode; receive a command CMD8 sent from the electronic device through the pin CMD, where the command CMD8 is used to inquire whether the secure digital card supports a PCIe mode; if the PCIe mode is not supported, respond The secure digital card of the electronic device does not support the PCIe mode and is maintained in the SD mode; and if the PCIe mode is supported, the secure digital card supports the PCIe mode in response to the electronic device, and then receives from the electronic device through the second One of a pin VDD2 and a pin VDD3 of the two external signal ports sends a second power signal to enter a connection state of a PCIe mode, and a voltage level of the second power signal is lower than the first power signal. A voltage level of a power signal; wherein the SD mode of the secure digital card adopts a UHS-I input/output communication interface standard, and the multiple pins used as data lines are adopted by the PCIe mode A PCIe channel is shared with another input/output communication interface standard of an NVMe protocol. The plurality of pins used as data lines in the SD mode include pin numbers 1, 7, 8, 9 Pin.
根據本發明之實施例,另揭露一種安全數位卡的一快閃記憶體控制器,該安全數位卡用以耦接至一電子裝置,該電子裝置位於一主機端並具有一第一外部訊號埠,該安全數位卡至少可操作於一SD模式並具有一第二外部訊號埠,該第二外部訊號埠具有多個接腳用以耦接至該電子裝置的該第一外部訊號埠的多個接腳,該安全數位卡另包含一快閃記憶體,以及該快閃記憶體控制器用以耦接於該快閃記憶體與該第二外部訊號埠之間並包含有一暫存器與一處理電路。暫存器用以暫存該快閃記憶體的資訊。處理電路耦接於該暫存器,處理電路用以接收從該電子裝置通過該第一外部訊號埠與該第二外部訊號埠的一接腳VDD1所發送之對應於該SD模式之一第一電源訊號,令該安全數位卡進入一初始化狀態;處理電路用以接收從該電子裝置通過該SD模式所採用之該接腳CMD所發送之該SD模式所對應之一命令CMD0或是通過該SD模式所採用之一接腳CLK所發送該SD模式所對應之一特定時脈SDCLK,令該安全數位卡從該初始化狀態進入該SD模式並操作於該SD模式;處理電路用以接收從該電子裝置通過該接腳CMD所發送之一命令CMD8,其中該命令CMD8用以詢問該安全數位卡是否支援一PCIe模式;如果該安全數位卡不支援該PCIe模式,則該處理電路回應該電子裝置該安全數位卡不支援該PCIe模式並令該安全數位卡維持於該SD模式;以及如果該安全數位卡支援該PCIe模式,則該處理電路回應該電子裝置該安全數位卡支援該PCIe模式,並接著接收從該電子裝置通過該第二外部訊號埠的一接腳VDD2與一接腳VDD3的其中一個所發送之一第二電源訊號,令該安全數位卡進入一PCIe模式之一連接狀態,該第二電源訊號之一電壓準位低於該第一電源訊號之一電壓準位;其中該安全數位卡之該SD模式所採用之一UHS-I輸入/輸出通訊介面標準之用於作為資料線的複數個接腳係被該PCIe模式所採用之一PCIe通道與一NVMe協定的另一輸入/輸出通訊介面標準所共用,該SD模式之用於作為資料線的該複數個接腳包含有接腳編號為1、7、8、9的多個接腳。According to an embodiment of the present invention, a flash memory controller of a secure digital card is also disclosed, the secure digital card is used for coupling to an electronic device, the electronic device is located on a host side and has a first external signal port , The secure digital card can operate in at least an SD mode and has a second external signal port, the second external signal port has a plurality of pins for coupling to a plurality of the first external signal port of the electronic device Pin, the secure digital card further includes a flash memory, and the flash memory controller is used for coupling between the flash memory and the second external signal port and includes a register and a processor Circuit. The register is used to temporarily store the information of the flash memory. The processing circuit is coupled to the register, and the processing circuit is used to receive the first one corresponding to the SD mode sent from the electronic device through a pin VDD1 of the first external signal port and the second external signal port The power signal causes the secure digital card to enter an initialization state; the processing circuit is used to receive a command CMD0 corresponding to the SD mode sent from the electronic device through the pin CMD used in the SD mode or through the SD A pin CLK used in the mode sends a specific clock SDCLK corresponding to the SD mode, so that the secure digital card enters the SD mode from the initialization state and operates in the SD mode; the processing circuit is used to receive from the electronic The device sends a command CMD8 through the pin CMD, where the command CMD8 is used to inquire whether the secure digital card supports a PCIe mode; if the secure digital card does not support the PCIe mode, the processing circuit responds to the electronic device The secure digital card does not support the PCIe mode and the secure digital card is maintained in the SD mode; and if the secure digital card supports the PCIe mode, the processing circuit responds to the electronic device that the secure digital card supports the PCIe mode, and then Receiving a second power signal sent from the electronic device through one of a pin VDD2 and a pin VDD3 of the second external signal port, so that the secure digital card enters a connection state of a PCIe mode, the first One of the voltage levels of the second power signal is lower than the voltage level of the first power signal; wherein the SD mode of the secure digital card adopts a UHS-I input/output communication interface standard that is used as a data line A plurality of pins are shared by a PCIe channel adopted by the PCIe mode and another input/output communication interface standard of an NVMe protocol. The plurality of pins used as data lines in the SD mode include pins Multiple pins numbered 1, 7, 8, 9.
本發明旨在於提供一種具有不同資料傳輸模式之一記憶卡裝置的機制,該不同資料傳輸模式例如是一安全數位卡(Secure digital Memory Card)所支援的資料傳輸模式為安全數位模式(以下簡稱SD模式)以及同時支援PCIe(Peripheral Component Interconnect Express)通道與NVMe協定(NVM Express protocol)的PCIe模式,亦即該PCIe模式採用底層為PCIe介面而上層是NVMe協定來實現,亦可被稱為PCIe/NVMe模式,該不同資料傳輸模式會共用記憶卡裝置的一外部通訊訊號埠之至少一訊號接腳;此外,本發明會保護並避免該記憶卡裝置於不同資料傳輸模式切換時由於訊號準位實際電壓的不同所造成的電路損傷,及/或能夠令記憶卡裝置與作為主機端之電子裝置之間的資料傳輸採用傳輸速率較快的傳輸模式,以提升傳輸速率。The present invention aims to provide a mechanism for a memory card device with one of different data transmission modes. The different data transmission mode is, for example, a secure digital memory card (Secure digital Memory Card). The data transmission mode supported is a secure digital mode (hereinafter referred to as SD Mode) and the PCIe mode that supports both PCIe (Peripheral Component Interconnect Express) channels and NVMe protocol (NVM Express protocol), that is, the PCIe mode is implemented by using the PCIe interface at the bottom layer and the NVMe protocol at the upper layer. It can also be called PCIe/ In NVMe mode, the different data transmission modes share at least one signal pin of an external communication signal port of the memory card device; in addition, the present invention protects and prevents the memory card device from switching between different data transmission modes due to the actual signal level. The circuit damage caused by the difference in voltage and/or the data transmission between the memory card device and the electronic device as the host can adopt a faster transmission mode to increase the transmission rate.
目前市面上廠商所生產的一般安全數位卡,其訊號埠具有較少個數的接腳,例如僅具有一排的訊號接腳,該安全數位卡所支援的資料傳輸模式為SD模式,通過SD模式所定義之UHS-I輸入/輸出通訊介面標準來與作為主機端的電子裝置進行資料傳輸通訊。At present, the general security digital cards produced by manufacturers on the market have a small number of pins in the signal port, such as only one row of signal pins. The data transmission mode supported by the secure digital card is SD mode. The UHS-I input/output communication interface standard defined by the model is used for data transmission and communication with the electronic device as the host side.
本案所提供一種具有不同資料傳輸模式的記憶卡裝置具有較多個數的接腳,例如具有第一排訊號接腳及第二排訊號接腳,並且所支援的資料傳輸介面包含有SD模式所定義之UHS-I輸入/輸出通訊介面標準以及同時支援PCIe介面與NVMe協定的PCIe模式,可通過所定義的不同通訊標準來與作為主機端的電子裝置進行資料傳輸通訊。此外,作為主機端的電子裝置之驅動電路及/或其驅動程式的版本資訊亦可分為例如支援上述較少個數接腳及SD模式之驅動電路及/或驅動程式以及支援上述較多個數接腳以及PCIe模式的驅動電路及/或驅動程式。This case provides a memory card device with different data transmission modes that has a larger number of pins, such as the first row of signal pins and the second row of signal pins, and the supported data transmission interface includes SD mode The defined UHS-I input/output communication interface standard and the PCIe mode that supports both the PCIe interface and the NVMe protocol can communicate with the electronic device as the host through different defined communication standards. In addition, the version information of the driver circuit and/or the driver program of the electronic device as the host side can be divided into, for example, the driver circuit and/or driver program that supports the above-mentioned fewer pins and SD mode and the driver program that supports the above-mentioned larger number Pin and PCIe mode driving circuit and/or driver.
應注意的是,SD模式及PCIe模式在進行資料傳輸時其所分別採用之輸入/輸出通訊介面標準之訊號邏輯準位的實際規範電壓值是不同的,致使記憶卡裝置可能因為訊號邏輯準位的實際規範電壓值不同而發生電路損傷。It should be noted that the actual standard voltage values of the signal logic level of the input/output communication interface standards used in SD mode and PCIe mode are different during data transmission. As a result, the memory card device may be affected by the signal logic level. The actual standard voltage value is different and circuit damage occurs.
因此,為了避免發生電路損傷以及同時達到可以更快速地控制記憶卡裝置進入其所能夠支援的較高資料傳輸速度的模式,本案也提出了新穎的控制記憶卡裝置於SD模式及PCIe模式進行切換的方法。Therefore, in order to avoid circuit damage and achieve faster control of the memory card device to enter the higher data transmission speed mode that it can support, this case also proposes a novel control of the memory card device to switch between SD mode and PCIe mode. Methods.
本發明之實施例的記憶卡裝置例如是數位安全卡裝置(但不限定)。本案所公開的記憶卡具有兩排較多個數的接腳可支援SD模式以及PCIe模式,並可於SD模式或PCIe模式其中任一個模式下運作,本案的記憶卡操作於該SD模式及該PCIe模式時會共用一外部通訊埠的至少一接腳以和作為主機端的一電子裝置進行通訊,下面的第一個表格列舉了該SD模式所採用的接腳編號及對應的名稱、類型、描述說明,而第二個表格列舉了該PCIe模式所採用的接腳編號及對應的名稱、類型、描述說明:
其中S表示電源供給,I表示輸入,O表示採用推拉驅動的輸出,PP表示採用推拉驅動的輸入輸出。上述命令均是通過CMD接腳所傳輸,而所要傳輸的資料則通過接腳DAT0、DAT1、DAT2及CD/DAT3所傳輸。
其中「*」代表保留給將來使用到供應電壓3的接腳時使用。該記憶卡裝置分別操作於該SD模式及該PCIe模式時所共同使用到的接腳為接腳編號1、7、8、9的接腳(非本案的限制);應注意,上述說明只是舉例並非是本案的限制。本案之方法流程例如應用於作為主機端之電子裝置的驅動電路,用以控制記憶卡裝置進入並操作於SD模式或PCIe模式,能夠避免造成電路損傷以及同時提升資料傳輸效率。Among them, "*" means reserved for future use when the pin of supply voltage 3 is used. When the memory card device is operated in the SD mode and the PCIe mode, the common pins used are the pins with pin numbers 1, 7, 8, 9 (not limited by this case); it should be noted that the above description is just an example It is not a limitation of this case. The method flow of this case is applied to the driving circuit of the electronic device as the host side, for controlling the memory card device to enter and operate in SD mode or PCIe mode, which can avoid circuit damage and improve data transmission efficiency at the same time.
請參照第1圖,第1圖是本發明第一實施例之控制一記憶卡裝置之資料傳輸模式的方法流程示意圖。倘若大體上可達到相同的結果,並不需要一定照第1圖所示之流程中的步驟順序來進行,且第1圖所示之步驟不一定要連續進行,亦即其他步驟亦可插入其中;詳細的流程步驟係說明於下:Please refer to FIG. 1. FIG. 1 is a flowchart of a method for controlling a data transmission mode of a memory card device according to a first embodiment of the present invention. If substantially the same result can be achieved, it is not necessary to follow the sequence of steps in the process shown in Figure 1, and the steps shown in Figure 1 do not have to be continuous, that is, other steps can be inserted into it. ; The detailed process steps are described below:
步驟105:開始;Step 105: Start;
步驟110:作為主機端之一電子裝置通過一接腳VDD1從該電子裝置的一驅動電路發送一第一電源訊號至該記憶卡裝置,控制並令該記憶卡裝置進入一初始化狀態,其中該初始化狀態為虛擬的初始化狀態(Pseudo initial state);Step 110: As an electronic device on the host side, send a first power signal from a driving circuit of the electronic device to the memory card device through a pin VDD1 to control and make the memory card device enter an initialization state, wherein the initialization The state is a virtual initial state (Pseudo initial state);
步驟115:從該電子裝置的驅動電路通過一接腳CMD發送該SD模式所對應之一特定命令(例如命令CMD0)至該記憶卡裝置及/或從該電子裝置的驅動電路通過一接腳CLK發送SD模式所對應之一特定時脈SDCLK至該記憶卡裝置,控制並令該記憶卡裝置從該初始化狀態進入該SD模式並操作於該SD模式;Step 115: Send a specific command (such as command CMD0) corresponding to the SD mode from the drive circuit of the electronic device through a pin CMD to the memory card device and/or from the drive circuit of the electronic device through a pin CLK Sending a specific clock SDCLK corresponding to the SD mode to the memory card device to control and make the memory card device enter the SD mode from the initialization state and operate in the SD mode;
步驟120:從該電子裝置的驅動電路通過該接腳CMD發送一命令CMD8至該記憶卡裝置以詢問該記憶卡裝置是否支援PCIe模式並等待該記憶卡裝置的回應,如果該記憶卡裝置回應支援PCIe模式,則進行步驟125,反之,如果該記憶卡裝置回應不支援PCIe模式,則進行步驟150;Step 120: Send a command CMD8 from the drive circuit of the electronic device to the memory card device through the pin CMD to inquire whether the memory card device supports PCIe mode and wait for the memory card device to respond, if the memory card device responds to support In PCIe mode, go to step 125, otherwise, if the memory card device responds that PCIe mode is not supported, go to step 150;
步驟125:從作為該主機端之該電子裝置的驅動電路通過該接腳VDD2或VDD3發送或啟動對應於該PCIe模式之一第二電源訊號至該記憶卡裝置,控制並令該記憶卡裝置從該SD模式進入該PCIe模式的連接狀態(Linkup state);Step 125: Send or activate a second power signal corresponding to the PCIe mode to the memory card device from the drive circuit of the electronic device as the host through the pin VDD2 or VDD3 to control and make the memory card device slave The SD mode enters the Linkup state of the PCIe mode;
步驟130:於該PCIe之該連接狀態中,該記憶卡裝置與該主機端之電子裝置進行通訊連接協議並由該電子裝置來判斷協議是否成功,如果通訊連接成功,則進行步驟135,反之,如果通訊連接失敗,則進行步驟140;Step 130: In the connection state of the PCIe, the memory card device performs a communication connection protocol with the electronic device on the host side, and the electronic device determines whether the protocol is successful. If the communication connection is successful, proceed to step 135, otherwise, If the communication connection fails, proceed to step 140;
步驟135:該電子裝置控制該記憶卡裝置操作於該PCIe模式;Step 135: The electronic device controls the memory card device to operate in the PCIe mode;
步驟140:該電子裝置決定是否進行重試,如果決定重試,則進行步驟135,反之,如果不重試,則進行步驟145;Step 140: The electronic device decides whether to retry, if it decides to retry, it proceeds to step 135, otherwise, if it does not retry, it proceeds to step 145;
步驟145:從該電子裝置的驅動電路通過該接腳CMD發送該SD模式所對應之命令CMD0至該記憶卡裝置及/或從該電子裝置的驅動電路通過該接腳CLK發送SD模式所對應的特定時脈SDCLK至該記憶卡裝置,控制並令該記憶卡裝置從該PCIe模式的連接狀態進入該SD模式並操作於該SD模式;Step 145: Send the command CMD0 corresponding to the SD mode from the drive circuit of the electronic device through the pin CMD to the memory card device and/or send the command CMD0 corresponding to the SD mode through the pin CLK from the drive circuit of the electronic device A specific clock SDCLK to the memory card device to control and make the memory card device enter the SD mode from the connection state of the PCIe mode and operate in the SD mode;
步驟150:維持於該SD模式;以及Step 150: Maintain in the SD mode; and
步驟155:結束。Step 155: End.
另外,在一實施例,作為主機的電子裝置可以決定不要先進入SD模式而是選擇於接腳VDD2或接腳VDD3上發送第二電源訊號至該記憶卡裝置,嘗試先進入PCIe模式。請參照第2圖,第2圖是本發明第二實施例之控制一記憶卡裝置之資料傳輸模式的方法流程示意圖。倘若大體上可達到相同的結果,並不需要一定照第2圖所示之流程中的步驟順序來進行,且第2圖所示之步驟不一定要連續進行,亦即其他步驟亦可插入其中;詳細的流程步驟係說明於下:In addition, in one embodiment, the electronic device as the host may decide not to enter the SD mode first, but choose to send the second power signal to the memory card device on the pin VDD2 or the pin VDD3, and try to enter the PCIe mode first. Please refer to FIG. 2. FIG. 2 is a flowchart of a method for controlling a data transmission mode of a memory card device according to a second embodiment of the present invention. If generally the same result can be achieved, it is not necessary to follow the sequence of steps in the process shown in Figure 2, and the steps shown in Figure 2 do not have to be continuous, that is, other steps can be inserted into it. ; The detailed process steps are described below:
步驟205:開始;Step 205: start;
步驟210:作為主機端之電子裝置通過該接腳VDD1從該電子裝置的驅動電路發送第一電源訊號至該記憶卡裝置,控制並令該記憶卡裝置進入該虛擬的初始化狀態;Step 210: The electronic device as the host sends a first power signal from the drive circuit of the electronic device to the memory card device through the pin VDD1, and controls and causes the memory card device to enter the virtual initialization state;
步驟215:從作為該主機端之該電子裝置的驅動電路通過該接腳VDD2或VDD3發送或啟動對應於該PCIe模式之一第二電源訊號至該記憶卡裝置,控制並令該記憶卡裝置從該SD模式進入該PCIe模式的連接狀態;Step 215: Send or activate a second power signal corresponding to the PCIe mode to the memory card device from the drive circuit of the electronic device as the host through the pin VDD2 or VDD3 to control and make the memory card device slave The SD mode enters the connection state of the PCIe mode;
步驟220:於該PCIe之該連接狀態中,該記憶卡裝置與該主機端之電子裝置進行通訊連接協議並由該電子裝置來判斷協議是否成功,如果通訊連接成功,則進行步驟225,反之,如果通訊連接失敗,則進行步驟230;Step 220: In the connection state of the PCIe, the memory card device performs a communication connection protocol with the electronic device on the host side, and the electronic device determines whether the protocol is successful, if the communication connection is successful, go to step 225, otherwise, If the communication connection fails, go to step 230;
步驟225:該電子裝置控制該記憶卡裝置操作於該PCIe模式;Step 225: The electronic device controls the memory card device to operate in the PCIe mode;
步驟230:該電子裝置決定是否進行重試,如果決定重試,則進行步驟220,反之,如果不重試,則進行步驟235;Step 230: The electronic device decides whether to retry, if it decides to retry, proceed to step 220, otherwise, if it does not retry, proceed to step 235;
步驟235:從該電子裝置的驅動電路通過該接腳CMD發送該SD模式所對應之命令CMD0至該記憶卡裝置及/或從該電子裝置的驅動電路通過該接腳CLK發送SD模式所對應的特定時脈SDCLK至該記憶卡裝置,控制並令該記憶卡裝置從該PCIe模式的連接狀態進入該SD模式並操作於該SD模式;以及Step 235: Send the command CMD0 corresponding to the SD mode from the drive circuit of the electronic device through the pin CMD to the memory card device and/or send the command CMD0 corresponding to the SD mode through the pin CLK from the drive circuit of the electronic device A specific clock SDCLK to the memory card device to control and make the memory card device enter the SD mode from the connection state of the PCIe mode and operate in the SD mode; and
步驟240:結束。Step 240: End.
第3圖繪示了具有不同接腳數目的記憶卡裝置,舉例來說,左邊的記憶卡裝置僅具有一排接腳(共有9個接腳),以安全數位卡來說例如支援第一代UHS(UHS-I)的資料傳輸介面,而本案所提供的是例如右邊的記憶卡裝置,其具有上、下兩排接腳(共有18個接腳),以安全數位卡來說例如支援SD模式所定義之UHS-I輸入/輸出通訊介面標準以及支援PCIe介面與NVMe協定的PCIe模式。Figure 3 shows memory card devices with different numbers of pins. For example, the memory card device on the left has only one row of pins (a total of 9 pins). For example, a secure digital card supports the first generation UHS (UHS-I) data transmission interface, and the memory card device provided in this case is, for example, the memory card device on the right, which has two rows of pins (a total of 18 pins), for a secure digital card, for example, it supports SD The UHS-I input/output communication interface standard defined by the mode and the PCIe mode that supports the PCIe interface and the NVMe protocol.
請參照第4圖,第4圖為本發明之一實施例之記憶卡裝置的資料傳輸模式之狀態切換示意圖。在此例中,該記憶卡裝置為一同時支援SD模式與PCIe模式的記憶卡裝置,也就是,上述第一模式指的是SD模式,其資料傳輸速率可能會低於第二模式(PCIe模式)的最高資料傳輸速率,以及上述的第一電源訊號VDD1例如3.3伏,不同於第二電源訊號例如接腳VDD3上的1.2伏或接腳VDD2上的1.8伏;然此均並非本案的限制。對於同時支援SD模式與PCIe模式的該安全數位卡,如第1圖及第2圖所示的流程操作,作為主機端之該電子裝置可以控制該安全數位卡先操作於SD模式再嘗試是否進入PCIe模式,也可以控制該安全數位卡先直接嘗試是否進入PCIe模式,如果不行,則控制該安全數位卡進入到SD模式。Please refer to FIG. 4, which is a schematic diagram of the state switching of the data transmission mode of the memory card device according to an embodiment of the present invention. In this example, the memory card device is a memory card device that supports both SD mode and PCIe mode. That is, the above-mentioned first mode refers to SD mode, and its data transfer rate may be lower than that of the second mode (PCIe mode). ), and the aforementioned first power signal VDD1, such as 3.3 volts, is different from the second power signal, such as 1.2 volts on pin VDD3 or 1.8 volts on pin VDD2; however, this is not a limitation of this case. For the secure digital card that supports both SD mode and PCIe mode, as shown in Figure 1 and Figure 2, the electronic device as the host can control the secure digital card to operate in SD mode before trying to enter In PCIe mode, you can also control the secure digital card to directly try to enter the PCIe mode first. If it does not work, control the secure digital card to enter the SD mode.
於初始化時,作為主機端之該電子裝置通過該外部訊號埠的接腳VDD1發送第一電源訊號(例如3.3伏)至該安全數位卡,因此該安全數位卡接著進入該虛擬初始化狀態。During initialization, the electronic device as the host sends a first power signal (for example, 3.3V) to the secure digital card through the pin VDD1 of the external signal port, so the secure digital card then enters the virtual initialization state.
在該虛擬初始化狀態中,如第1圖的流程所示,該電子裝置可以發送SD模式所對應之一特定命令CMD0或所對應之一特定時脈SDCLK至該安全數位卡,令該安全數位卡從該初始化狀態進入SD模式,或者如第2圖的流程所示,該電子裝置可以改成通過接腳VDD2或VDD3發送或啟動PCIe模式所對應之一第二電源訊號(例如1.8伏或1.2伏)至該安全數位卡,令該安全數位卡從該初始化狀態直接進入PCIe模式的連接狀態。In the virtual initialization state, as shown in the flow in Figure 1, the electronic device can send a specific command CMD0 corresponding to the SD mode or a specific clock SDCLK corresponding to the secure digital card to make the secure digital card Enter the SD mode from the initialization state, or as shown in the process in Figure 2, the electronic device can be changed to send or activate a second power signal (such as 1.8V or 1.2V) corresponding to the PCIe mode through the pin VDD2 or VDD3 ) To the secure digital card, so that the secure digital card enters the PCIe mode connection state directly from the initialization state.
在該安全數位卡操作於SD模式中,該電子裝置可以控制該安全數位卡嘗試進入PCIe模式,通過接腳VDD2或VDD3發送或啟動PCIe模式所對應之一第二電源訊號至該安全數位卡,控制並令該安全數位卡從SD模式進入PCIe模式的連接狀態。When the secure digital card is operating in the SD mode, the electronic device can control the secure digital card to try to enter the PCIe mode, and send or activate a second power signal corresponding to the PCIe mode to the secure digital card through the pin VDD2 or VDD3. Control and make the secure digital card enter the connection state of PCIe mode from SD mode.
當該安全數位卡於PCIe模式的連接狀態時,該電子裝置可以控制該安全數位卡進入SD模式,通過發送該SD模式所對應之特定命令CMD0或所對應之特定時脈SDCLK至該安全數位卡,控制並令該安全數位卡從該PCIe模式的連接狀態進入SD模式,其中PCIe模式的連接狀態係指在進入PCIe模式之前的等待連接協議結果的狀態,因此即使一安全數位卡不支援PCIe模式,也有可能會進入該等待連接的狀態,因此之後如果連接協議的結果是不成功,則該電子裝置會發送SD模式所對應之特定命令CMD0或所對應之特定時脈SDCLK至該安全數位卡,控制該安全數位卡從等待連接的狀態進入SD模式。當該電子裝置與該安全數位卡連接協議成功時,會控制該安全數位卡從該PCIe模式的連接狀態進入PCIe模式。When the secure digital card is connected in PCIe mode, the electronic device can control the secure digital card to enter the SD mode by sending the specific command CMD0 corresponding to the SD mode or the corresponding specific clock SDCLK to the secure digital card , Control and make the secure digital card enter SD mode from the connection state of PCIe mode, where the connection state of PCIe mode refers to the state of waiting for the connection protocol result before entering PCIe mode, so even if a secure digital card does not support PCIe mode , It may also enter the state of waiting for connection. Therefore, if the result of the connection protocol is unsuccessful, the electronic device will send the specific command CMD0 corresponding to the SD mode or the specific clock SDCLK corresponding to the secure digital card. Control the secure digital card to enter SD mode from the state of waiting for connection. When the connection protocol between the electronic device and the secure digital card is successful, the secure digital card is controlled to enter the PCIe mode from the connection state of the PCIe mode.
當操作於PCIe模式時,該安全數位卡可以退出該PCIe模式回到PCIe模式的連接狀態,或者是該電子裝置可以通過關閉在接腳VDD2或VDD3上的PCIe模式所對應之第二電源訊號,控制並令該安全數位卡從該PCIe模式回到虛擬初始化狀態。When operating in PCIe mode, the secure digital card can exit the PCIe mode and return to the PCIe mode connection state, or the electronic device can turn off the second power signal corresponding to the PCIe mode on the pin VDD2 or VDD3, Control and make the secure digital card return from the PCIe mode to a virtual initialization state.
例如,當操作於PCIe模式時,該安全數位卡與該作為主機的電子裝置之間的通訊底層會記錄一個暫存連接參數(register Linkup),該暫存連接參數可暫存於該電子裝置內(例如相應的驅動電路中;但不限定),當安全數位卡從操作於PCIe模式中變成連線失敗時,該暫存連接參數會變成零,該安全數位卡就會退出PCIe模式而回到PCIe模式的連接狀態,此時該電子裝置會重新再嘗試連接一次,而其重新連接的次數端視電子裝置的設計而定,並未限定。以上的操作,該電子裝置均可以因應於不同系統效能等等的需求,動態地對該安全數位卡進行控制及模式切換,不限定於必然操作於較快資料傳輸速率的模式。For example, when operating in PCIe mode, the bottom layer of the communication between the secure digital card and the electronic device as the host will record a register Linkup, which can be temporarily stored in the electronic device (For example, in the corresponding drive circuit; but not limited), when the secure digital card changes from operating in PCIe mode to connection failure, the temporarily stored connection parameter will become zero, and the secure digital card will exit PCIe mode and return to In the PCIe mode of the connection state, the electronic device will try to connect again at this time, and the number of reconnections depends on the design of the electronic device and is not limited. With the above operations, the electronic device can dynamically control and switch the mode of the secure digital card in response to the requirements of different system performance and so on, and is not limited to a mode that necessarily operates at a faster data transmission rate.
當該安全數位卡位於PCIe模式的連接狀態時,該電子裝置也可以通過關閉接腳VDD2或接腳VDD3上的第二電源訊號,以控制該安全數位卡進入到虛擬的初始化狀態。When the secure digital card is in the PCIe mode connection state, the electronic device can also control the secure digital card to enter a virtual initialization state by turning off the second power signal on the pin VDD2 or the pin VDD3.
請參照第5圖,第5圖為本發明實施例方法所實現之記憶卡裝置(例如安全數位卡)400及作為主機端之電子裝置405的方塊示意圖。記憶卡400包含外部的訊號埠4001、快閃記憶體410以及快閃記憶體控制器420,控制器420耦接於外部的訊號埠4001與快閃記憶體410之間,並通過一內部匯流排連接至快閃記憶體410,快閃記憶體控制器420內包含一暫存器415與一處理電路416,其中暫存器415可用來暫存快閃記憶體410的基本資料,而處理電路416則用來執行快閃記憶體控制器420的相對應操作(例如上述輸入/輸出介面之資料或訊號接收、發送及存取計算等等),快閃記憶體410則包含一或多個快閃記憶體晶片。電子裝置405包含外部的訊號埠4055、記憶卡驅動電路4051及處理器4053。電子裝置405通過訊號埠4055、4001(訊號埠均分別包含對應的多個接腳)耦接至記憶卡400。記憶卡400至少可操作於SD模式。處理器4053係用以控制驅動電路4051從電子裝置405並通過外部訊號埠4055、外部訊號埠4001的接腳VDD1發送對應於該SD模式之第一電源訊號至記憶卡400,而控制器420於接腳VDD1上偵測到該第一電源訊號時,便會據此控制記憶卡400進入初始化狀態。另外,記憶卡400可另外操作於PCIe模式,記憶卡400操作於SD模式及PCIe模式下其外部訊號埠4001的部分接腳,例如接腳編號1、7、8、9的接腳會被共用。Please refer to FIG. 5. FIG. 5 is a block diagram of a memory card device (such as a secure digital card) 400 and an
此外,處理器4053係控制驅動電路4051以用以從電子裝置405通過接腳VDD2發送對應於PCIe模式之第二電源訊號至記憶卡400或是通過接腳VDD3來發送對應於PCIe之第二電源訊號至記憶卡400,而控制器420於接腳VDD2或VDD3上偵測到該第二電源訊號時,例如如果在接腳VDD3上偵測到第二電源訊號,則會據此控制並令記憶卡400從初始化狀態進入PCIe模式的連接狀態,於PCIe模式的連接狀態中處理器4053通過驅動電路4051、外部訊號埠4055及外部訊號埠4001來與記憶卡400的控制器420進行一通訊連接協議,如果通訊連接協議成功,則記憶卡400會操作於該PCIe模式;如果通訊連接協議不成功,則驅動電路4051可以進行重試,而如果決定不再重試,則記憶卡400會從連接狀態進入到SD模式。In addition, the
此外,處理器4053也可以控制驅動電路4051於PCIe模式的連接狀態中,通過驅動電路4051、外部訊號埠4055及外部訊號埠4001來關閉接腳VDD2或接腳VDD3上所發送的PCIe模式之第二電源訊號,據此控制並令記憶卡400從PCIe模式的連接狀態回到初始化狀態。In addition, the
此外,處理器4053也可以控制驅動電路4051,通過驅動電路4051、外部訊號埠4055及外部訊號埠4001,從電子裝置405發送SD模式所對應之特定命令例如CMD0及所對應之一特定時脈SDCLK的至少其中之一至記憶卡400的控制器420,據此控制並令記憶卡400從初始化狀態進入SD模式。In addition, the
第6圖是第5圖所示的主機端之電子裝置405直接控制記憶卡400從初始化狀態進入到PCIe模式的部分接腳的訊號範例示意圖。如第6圖所示,作為主機端的電子裝置405先將接腳CMD從一低電壓準位(例如零伏)拉至一高電壓準位(例如3.3伏或1.8伏),以及也將接腳CLKREQ#從零伏拉至3.3伏或1.8伏,並且將接腳VDD1從一低電壓準位(例如零伏)拉高至一高電壓準位(例如3.3伏)以提供第一電源訊號至記憶卡400,令記憶卡400進入初始化狀態。FIG. 6 is a schematic diagram of a signal example of some pins of the
在此實施例,電子裝置405選擇直接控制記憶卡400嘗試進入PCIe模式,因此於初始化狀態中直接提供第二電源訊號將接腳VDD3從一低電壓準位(例如零伏)拉高至一高電壓準位(例如1.2伏);應注意的是,電子裝置405也可以將接腳VDD2從低電壓準位(例如零伏)拉高至高電壓準位(例如1.8伏)來提供第二電源訊號,視電子裝置405的設計以及記憶卡400是否有支援接腳VDD3而定,如果記憶卡400不支援接腳VDD3,則電子裝置405可以嘗試將接腳VDD2從低電壓準位(例如零伏)拉高至高電壓準位(例如1.8伏),或是直接控制記憶卡400進入SD模式。In this embodiment, the
因此,如第6圖的實施例所示,當記憶卡400偵測到接腳VDD3從例如零伏被拉高至例如1.2伏時便會進入PCIe模式的連接狀態。於PCIe模式的連接狀態中,記憶卡400會將接腳CLKREQ#從3.3伏或1.8伏拉低至例如零伏,以告知電子裝置405已接收到PCIe模式連接的請求並且準備接收電子裝置405所提供的時脈輸入訊號,而作為主機的電子裝置405會等候例如至多1毫秒(ms)以偵測接腳CLKREQ#是否從高電壓準位被拉低至低電壓準位,如果被拉低至低電壓準位,則電子裝置405接著會開始通過接腳REFCLK-及接腳REFCLK+傳入差動時脈輸入訊號(例如0.8伏至1.2伏之間)至記憶卡400,並判斷是否能夠穩定地提供該差動時脈輸入訊號例如至少100微秒,如果能夠穩定地提供該差動時脈輸入訊號,則電子裝置405接著會將接腳PERST#從一低電壓準位(例如零伏)拉高至一高電壓準位(例如3.3伏或1.8伏),之後電子裝置405便開始進行PCIe模式的鏈路訓練(Link training),待該鏈路訓練完成後,記憶卡400便操作PCIe模式進行PCIe模式的初始化。Therefore, as shown in the embodiment in FIG. 6, when the
而如果PCIe模式的連接狀態失敗(例如接腳CLKREQ#一直位於高電壓準位而並未被記憶卡400拉低,或是PCIe模式的鏈路訓練一直失敗),則記憶卡400會進入SD模式,電子裝置405會通過SD模式的UHS-I資料傳輸介面來存取記憶卡400。And if the connection status of PCIe mode fails (for example, the pin CLKREQ# is always at a high voltage level and has not been pulled down by the
此外,應注意的是,在第6圖所示的實施例中,由於並沒有接收到對應於SD模式的時脈訊號SDCLK(訊號SDCLK的準位例如維持於一低電壓準位(例如零伏)),因此記憶卡400不會從初始化狀態進入到SD模式。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。In addition, it should be noted that, in the embodiment shown in Figure 6, since the clock signal SDCLK corresponding to the SD mode is not received (the level of the signal SDCLK is maintained at a low voltage level (such as zero volts, for example). )), so the
105~155,205~240:步驟
400:記憶卡
405:電子裝置
410:快閃記憶體
415:暫存器
416:處理電路
420:快閃記憶體控制器
4001,4055:外部訊號埠
4051:記憶卡驅動電路
4053:處理器
105~155,205~240: steps
400: Memory card
405: electronic device
410: flash memory
415: register
416: processing circuit
420:
第1圖是本發明第一實施例之控制一記憶卡裝置之資料傳輸模式的方法流程示意圖。 第2圖是本發明第二實施例之控制一記憶卡裝置之資料傳輸模式的方法流程示意圖。 第3圖是具有不同接腳數目之不同記憶卡裝置的背面示意圖。 第4圖是本發明之實施例之記憶卡裝置的資料傳輸模式之狀態切換示意圖。 第5圖是本發明實施例方法所實現之記憶卡裝置及電子裝置的方塊示意圖。 第6圖是第5圖所示的主機端之電子裝置直接控制記憶卡從初始化狀態進入到PCIe模式的部分接腳的訊號範例示意圖。FIG. 1 is a schematic flowchart of a method for controlling a data transmission mode of a memory card device according to the first embodiment of the present invention. FIG. 2 is a schematic flowchart of a method for controlling a data transmission mode of a memory card device according to a second embodiment of the present invention. Figure 3 is a schematic diagram of the back of different memory card devices with different numbers of pins. FIG. 4 is a schematic diagram of state switching of the data transmission mode of the memory card device according to the embodiment of the present invention. FIG. 5 is a block diagram of the memory card device and the electronic device implemented by the method of the embodiment of the present invention. FIG. 6 is a schematic diagram of a signal example of some pins of the electronic device on the host side that directly controls the memory card to enter the PCIe mode from the initialization state as shown in FIG. 5.
105~155:步驟 105~155: steps
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