TW202102719A - Catalytic laminate with conductive traces formed during lamination - Google Patents

Abstract

A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. Trace channels and apertures are formed into the catalytic laminate, electroless plated with a metal such as copper, filled with a conductive paste containing metallic particles, which are then melted to form traces. In a variation, multiple circuit board layers have channels formed into the surface below the exclusion depth, apertures formed, are electroless plated, and the channels and apertures filled with metal particles. Several such catalytic laminate layers are placed together and pressed together under elevated temperature until the catalytic laminate layers laminate together and metal particles form into traces for a multi-layer circuit board.

Description

Catalytic laminate with conductive traces formed during lamination

The invention relates to a catalytic laminate and its use for forming traces. In particular, the build-up board has the property of providing fine-pitch circuit interconnection, and the circuit interconnection can be formed in a channel with flash copper and solder paste to form a circuit board layer with a flat surface, and the circuit board layer is embedded There are conductors or surface conductors.

In the prior art, a printed circuit board (PCB) is formed by using conductive metal interconnections (called "tracks"). The conductive metal interconnections are formed on a dielectric substrate, and each of them carries a conductor on the surface The department is called "layer". Each dielectric core (dielectric core) has traces formed on one surface or on both surfaces, and by stacking a number of such dielectric cores with exposed dielectric layers (the traces are formed between them), and Laminating them together under application of temperature and pressure can form a multilayer printed circuit. The dielectric substrate contains epoxy resin embedded in a fibrous matrix, such as glass fibers woven into cloth. In a conventional manufacturing method, copper is laminated on the outer surface of the dielectric layer, and the surface of the copper is patterned using a photoresist or photosensitive film to produce a masked area and a non-masked area, and then etching is performed To form a conductive trace layer on one or both sides of the dielectric core. The stack of dielectric cores with conductive traces can then be laminated to form a multilayer board, and any layers made of through holes (drills plated with copper) are interconnected to form an annular ring, providing Layer-to-layer connection.

A printed circuit board (PCB) is generally used to provide conductive traces between various electronic components mounted on it. One type of electronic component is a through-hole device, which is mounted on the PCB by passing a wire through one or more holes of the PCB, wherein the hole of the PCB includes a conductive ring on each trace connection layer, and the wire component is Hole ring soldered to PCB hole. Through-hole components have wires, which makes it difficult to align with the relevant PCB mounting holes; however, surface mount technology (SMT) provides a better mounting system, in which the wire components are simply placed on the surface of the PCB pad and soldered. This is better in PCB assembly because of its higher density and easy mechanized assembly. Surface mount components only need surface mount pads on the outside of the finished PCB layer. In a double-layer or multilayer PCB, through holes are used to complete the interconnection of conductive traces between layers, and the conductive traces on one of the trace layers lead to the through holes, which generally pass through One or more dielectric layers of the PCB are plated with copper or other conductive metals to complete the connection of the trace layer. Holes that pass through all dielectric layers are called thru-vias, and holes that only pass through the outer layer (usually part of a single-layer manufacturing) are called micro-vias and pass through Holes with one or more inner layers are called blind holes. For any of these through-hole types, the through-hole is patterned to include the perforated conductor area of the trace layer opposite to the PCB, where the drilled hole is lined with a conductive material that connects to either the build-up board or the PCB Test the hole ring conductor.

The use of electroplating can increase the thickness of pre-patterned or post-patterned copper on the printed circuit board laminate, where the PCB or dielectric layer with traces is placed in the electrolyte bath, and the DC voltage source is connected to the sacrificial anode conductor (such as Copper rod) and the existing conductive layer of the PCB. When there is no pre-existing conductive copper layer on the PCB to facilitate electroplating, for example, there is no exposed dielectric material or drilling through holes, a copper seed layer must be deposited first. It is accomplished with the aid of a "seed" catalytic material (which promotes the deposition of specific conductive materials) and is accomplished using an electroless plating method, where the catalytic material is deposited on the surface of the dielectric, and then the circuit board layer is placed on the electroless plating In the bath. For catalysts such as palladium and copper electroless plating baths, the copper ions in the solution are deposited on the palladium until the surface of the palladium is sufficiently covered to provide uniform conductivity, and then the electroless copper deposited copper is used to provide a conductive support. It can be used to add materials in the subsequent electroplating process. For the completion of the electroplating operation, electroplating is preferred because the deposition rate is faster than that of the electroless copper plating process.

With the increasing complexity of electronic assembly, we intend to increase the component density of PCB assembly, such as the use of smaller trace widths (called fine-pitch traces) and increasingly dense integrated circuit (IC) wire patterns. One of the problems of the conventional surface mount PCB manufacturing and assembly methods is the following: because the traces are formed on the surface of the dielectric, for the narrow conductor line width (called fine-pitch traces), copper traces The adhesive force between the wire and the underlying build-up board is reduced, which leads to separation (lifting) of fine-pitch traces and component pads during component replacement operations, which destroys the entire circuit board assembly and expensive components. Another problem with fine-pitch surface traces is the following: When manufacturing multilayer circuit boards, pressure is applied in a high-temperature environment to laminate the various trace layers together. During high temperature lamination, when the resin is in a semi-liquid state, the fine-pitch traces tend to move laterally across the surface of the dielectric. In high-speed circuit design, it is intended to maintain a fixed impedance between traces, especially for differential pair (edge-coupled) transmission lines. During lamination, the lateral displacement of the trace will cause the impedance of the finished PCB transmission line to vary with the length of the trace, which results in reflection and loss compared to a transmission line with a constant pitch (characterized by a fixed impedance). In addition, the step of forming the traces is separated from the laminating step, which results in the need for many steps to manufacture the multilayer circuit board. Another consideration for manufacturing circuit boards with copper conductors is that before the circuit board is assembled (the components are soldered to the finished printed circuit board), the copper oxide traces will be coated with non-oxidized nickel or other materials, which are combined with the subsequently added materials. Solder paste compatible, used to solder surface-mounted components placed on the solder paste, and then bake the circuit board at a temperature sufficient to melt the solder paste, and complete the electrical connection.

For the above reasons, we intend to provide a circuit board with good impedance control and trace geometry. We also intend to provide a multilayer circuit board, in which laminating layers and forming traces can be performed in a single step. In addition, we intend to form a trace in the channel to avoid displacement of the trace during the lamination process.

Purpose of the invention

The first object of the present invention is one or more layers of catalytic prepreg formed by a mixture of catalytic particles, resin and fiber matrix, which has a distribution of catalytic particles below the removal depth of the surface layer, wherein the exposed under the removal depth There is sufficient catalytic particle density in the area to provide electroless copper deposition, and the trace channels below the exclusion depth are formed in the surface of the catalytic laminate, and the electroless copper deposition in the channels is sufficient to allow By filling the channels with conductive materials to form conductive traces in the channels, and then exposing the metal particles and the trace channels to a baking temperature higher than the melting temperature of the metal particles so that the conductive particles form the traces, And selectively implement other layers in the lamination step, and interconnect the layers at the positions of through holes or channels adjacent to each other.

The second object of the present invention is a multilayer circuit board formed by a plurality of catalytic laminates, each catalytic laminate has a resin-rich surface, which does not have sufficient catalytic particle density to support electroless copper deposition, and Each catalytic laminate has catalytic particles below the rejection depth and has sufficient density to allow chemical deposition. The surface of the catalytic laminate has channels and holes that extend below the rejection depth. The channels are made of conductive metal. Traces formed by particles, which can be melted in channels and holes to form traces.

The third object of the present invention is a method for forming a circuit board layer from a catalytic laminate. The catalytic laminate is made of a resin mixed with catalytic particles and a selective fiber net. The catalytic particles are only in the catalytic particles of the catalytic laminate. Excluding the support of electroless copper deposition in the channels formed below the depth, the circuit board layer selectively has holes for electrical interconnection between the opposite surfaces of the circuit board layer, and the channels and selective holes are filled with conductive metal particles, and the conductive metal particles and The catalytic laminate is heated to a temperature sufficient to melt the conductive metal particles to form conductors in the channels and holes.

The fourth object of the present invention is a method of forming a multilayer circuit board from separate circuit board layers, each circuit board layer is formed by a catalytic laminate, the catalytic laminate containing a mixture of catalytic particles and selective fiber mesh The resin is cured (as shown in Figure 1A and Figure 1B), and the catalytic particles of at least one circuit board layer only support the electroless copper deposition in the channel (below the removal depth of the catalytic particles formed on the catalytic laminate), at least One circuit board layer selectively has holes for electrically interconnecting opposite surfaces of the circuit board layers, and conductive metal particles fill the channels and selective holes of each circuit board layer, stack at least two circuit board layers, and The conductive metal particles and the catalytic laminate are heated to a temperature sufficient to melt the conductive metal particles to form conductive traces in the channel and the at least two circuit board layers to bond to each other.

In the first specific example of the present invention, the catalytic prepreg system is formed by mixing resin, volatile solvent, and catalytic particles to form a catalytic resin mixture; injecting catalytic resin into fiber fabrics such as woven glass or other fibers. Form the "A-stage" catalytic prepreg; bake the fiber and resin at a high temperature to remove most of the volatile solvents and form a partially cured "B-stage" catalytic prepreg (for example, in the form of a sheet); then pre-preg the B-stage The immersion body is placed in a laminator, and the B-stage prepreg is heated at the gel point to make the prepreg a liquid/solid equilibrium state; then high temperature and pressure are applied to enable the catalytic particles to migrate out of the outer surface of the prepreg The residence time of the prepreg is used to cure the prepreg to form a finished "C-stage" prepreg with a resin-rich surface, and the surface does not contain exposed surface catalytic particles. Mechanical removal of the resin-rich surface will therefore expose the underlying catalytic particles and form a surface suitable for electroless plating of copper ions in the solution, or form a surface suitable for electroless plating of metal ions in any solution.

In the second embodiment of the present invention, a single-layer PCB or a multi-layer PCB is formed by patterning the exposed surface onto a resin-rich prepreg. The surface of the prepreg excludes catalysis from the surface. Particles, in which the catalytic particles are distributed at the depth of exclusion below the resin-rich surface and are not exposed. In the first step, selective through holes (holes) are formed through the catalytic laminate, catalytic particles are exposed on the surface of the drilled hole and channels are formed on the surface of the catalytic laminate, which causes the underlying catalytic particles to be exposed. The holes and channels can be formed by using any removal means to remove the surface of the catalytic material. The removal means include laser cutting, plasma etching, chemical etching, mechanical grinding or mechanical cutting. A patterned mask may or may not be used. In the second step, the catalytic laminate is placed in an electroless plating bath, in which electroless metal (for example, copper) is attracted and bonded to the exposed catalytic particles (for example, platinum) in the patterned area, where the The resin-rich surface in the zone has been removed. The second step is performed until the sides and bottom of the patterned trench channel are covered by electroless plating, and the selective holes plated with metal are covered, but the thickness is only enough to fill the trench channel, for example, the thickness of electroless copper plating is between 0.05 density Ear to 0.20 mils (approximately 1 µm to approximately 5 µm). In the third step, conductive paste is applied to fill the channels and vias, for example by coating an unpatterned (blanket coverage) surface, and then a surface squeegee is used to remove the channels and vias. Area excess conductive paste, the above-mentioned conductive paste contains metal suspended particles with a relatively low melting temperature (for example, 180 °C), which are mixed with a suitable wetting agent and used in the subsequent particle consolidation step. The thickness of the electroless plating in the second step is generally the minimum required to maintain the adhesion of the conductive metal particles, so after the baking step, the inner surfaces of the channels and the through holes are lined with chemical copper.

In a specific example of the present invention, the respective catalytic laminate layer has channels formed to the depth of removal and selective holes, and the catalytic laminate is subjected to electroless plating, so that when the channels and holes are filled with metal particles and sintered in the metal particles Or, when baking at melting temperature, it is sufficient to form traces, but the final step involves positioning one or more catalytic layers prepared by channels filled with conductive paste together and placing them in a laminator, so that the layers are processed in one step Laminating and sintering and melting metal particles to form traces.

Optional additional steps provide for the manufacture of multilayer boards. In this variant embodiment, the additional two layers are the outer layer prepared as described above, in which selective through holes and channels, flash copper (chemical copper) are formed, and the channels and through holes are filled with relatively low melting temperature metal particles , And put it into the laminator. The melting temperature of the metal particles in the conductive paste is selected to be lower than the lamination temperature to ensure that the metal particles can be consolidated when the layers are laminated. When the lamination temperature is higher than the melting temperature of the metal particles in the trace channel, lamination and trace formation occur in one step. Then, additional outer layers can be applied in a series of additional operations to form multiple layers as needed. In a specific example, a layer is applied to each outer surface and laminated to an inner core layer that has been previously laminated. In another specific example, before any lamination step, all layers are positioned together in a lamination press, and all layers are laminated and the metal particles are melted or sintered to form conductive traces in one step. In an optional subsequent step, a solder mask is applied to cover the area of the catalytic build-up board and the area of the patterned traces.

In the third specific example of the present invention, the catalytic prepreg of the first specific example has holes, which are formed by drilling or cutting or other methods of removing material to produce a gap from one surface of the prepreg to the opposite surface. Hole, the hole is adjacent to the pad area, in which the surface of the prepreg near the hole is removed, thus exposing the catalytic particles under the prepreg on the inner surface of the hole and the outer surface of the prepreg. The channel and the through-hole are then exposed to flash electroless copper plating for a period of time so as to be sufficient to coat the inner surface of the channel and the through-hole to form a deposited layer for adhering to the subsequently applied conductive paste containing metal particles, wherein the metal particles are melted to On the surface of the deposited layer. In an example of the present invention, the thickness of electroless copper is in the range of 0.05 mil to 0.15 mil (about 1 µm to about 4 µm), or the thickness of electroless copper is about 2 µm. In the subsequent lamination step, the metal particles in the electroless plating channel are melted or sintered together to the deposited layer to form conductive traces. The lamination step can be performed on a single layer with through holes or channels, or it can be performed on the outer layer of the inner laminated core, or it can be performed on all the inner and outer layers at once. The flash electroless deposition layer has a resistivity that is at least 10 times greater than that of subsequently formed conductive traces. Compared with alternative trace formation methods, this saves electroless copper deposition time and provides component adhesion advantages when assembling components onto the board.

Figure 1A illustrates an example of the operation of manufacturing a prepreg (pre-impregnated fiber matrix bonded in resin). The fiber of the prepreg can use many different materials, including woven glass fiber cloth, carbon fiber or other fibers, and the resin can use a variety of different materials, including epoxy resin, polyimide resin, cyanate ester resin, PTFE ( Teflon) mixed resin or other resins. One aspect of the present invention is the printed circuit board base layer, which can support fine-pitch conductive traces with a trace width of 1 mil (25 µm) and edge separation from other traces. Although it is described that a catalyst used to form electroless copper plating is used to form copper traces, it should be understood that the scope of the present invention can be extended to other metals suitable for electroless plating and electroplating. For electroless copper deposition channels, it is preferable to use elemental palladium (Pd) as a catalyst, although transition metal elements of the periodic table can also be selected, such as platinum (Pt), rhodium (Rh), and iridium (Ir) from groups 9 to 11 , Nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu) or other compounds of the above elements, including iron (Fe), manganese (Mn), chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tin (Sn) and other metals or mixtures or salts of the above metals, any of the above can be used as catalytic particles. This candidate list is intended to be exemplary rather than comprehensive, because it is known in the art that other catalysts that attract copper ions between electroless plating can also be used. In an example of the present invention, the catalytic particles are homogeneous catalytic particles. In another example of the present invention, the catalytic particles are inorganic particles or plastic particles that can withstand high temperatures, which are coated with catalytic metal with a thickness of several angstroms (Å) to form heterogeneous catalytic particles with a thin catalytic outer surface. It coats non-catalytic inner particles. For larger catalytic particles, such as those with a longest dimension of 25 µm, such a composition may be desirable. The heterogeneous catalytic particles of this composition can contain inorganic fillers, organic fillers or inert fillers, such as silica (SiO ₂ ), inorganic clay (such as kaolin) or high-temperature plastic fillers, and the surface of which is coated with adsorbed on A catalyst such as palladium on it (for example, palladium adsorbed on the surface of the packing material by vapor deposition or chemical deposition). Catalytic particles only need a few atomic layers of catalyst to have ideal performance in favor of electroless plating.

In an example of the formation of heterogeneous catalytic particles, fillers (organic fillers or inorganic fillers) are classified by size to contain particles with a size of less than 25 µm, and these classified inorganic particles are mixed in the water bath of the tank, Stir, then palladium salt such as PdCl (or any other catalyst, such as silver salt of other catalysts), acid such as hydrochloric acid, and reducing agent such as hydrazine hydrate are introduced together, thereby reducing the coated inorganic The mixture of particulate metal palladium provides a few angstroms of palladium coating on the filler, thereby producing heterogeneous catalytic particles with the catalytic performance of uniform palladium particles, and compared with the use of homogeneous palladium metal particles, heterogeneous The volume requirements of the catalytic particles for palladium are greatly reduced. However, for very small catalytic particles of several nanometers, it is preferable to use homogeneous catalytic particles (such as pure palladium).

Examples of inorganic fillers include clay minerals such as hydrous aluminum phyllosilicates, which may contain variable amounts of iron, magnesium, alkali metals, alkaline earth metals, and other cations. The inorganic fillers of this family include silica, aluminum silicate, kaolin (Al ₂ Si ₂ O ₅ (OH) ₄ ), polysilicate or other clay minerals belonging to the kaolin or porcelain clay family. Examples of organic fillers include PTFE (Teflon), and other polymers with high temperature resistance.

Examples of palladium salts are as follows: BrPd, CL ₂ Pd, Pd(CN) ₂ , I ₂ Pd, Pd(NO ₃ ) ₂ *2H ₂ O, Pd(NO ₃ ) ₂ , PdSO ₄ , Pd(NH ₃ ) ₄ Br _2. Pd(NH ₃ ) ₄ Cl ₂ H ₂ O. The catalytic powder of the present invention may also include a mixture of heterogeneous catalytic particles (for example, catalytic materials coated on inorganic filler particles), homogeneous catalytic particles (for example, elemental palladium), and non-catalytic particles (selected from inorganic fillers). family).

Among the catalysts, the preferred catalyst is palladium because of its economical benefits, its availability, and its mechanical properties. However, other catalysts can also be used.

Figure 1A shows a roll of fabric cloth 102 such as woven glass fiber, which is fed by a set of rollers that guide the fabric into a groove 108, which is filled with epoxy resin mixed with catalytic particles , And mixed with volatile liquids to reduce viscosity to form a stage A (liquid) prepreg.

This resin can be a mixture of polyimide resin, epoxy resin and cyanide ester (which provides curing at high temperatures) or any other suitable resin composition that enables it to have optional Viscosity and thermosetting properties after cooling. Flame retardants can be added, for example, to meet flammability standards, or to be compatible with one of the standard FR series prepregs such as FR-4 or FR-10. Another requirement for high-speed circuits is the dielectric constant ε (permittivity), which is usually about 4 and controls the characteristic impedance of the transmission line formed on the dielectric value and is used to measure the frequency within a certain distance The loss tangent d of related energy absorption, where the loss tangent is calculated in dB per centimeter of the transmission line length to measure how the dielectric interacts with the high-frequency electric field to undesirably reduce the signal amplitude. The resin system is mixed with the size-sorted catalytic particles. In an example of composition, the catalytic particles include at least one of the following: homogeneous catalytic particles (metal palladium), or heterogeneous catalytic particles (palladium coated on inorganic particles or palladium coated on high-temperature plastic), and for Catalytic particles of any composition preferably have a maximum size of less than 25 µm, and 50% of the particles have a size between 12 µm and 25 µm, or between 1 µm and 25 µm, or less. These specific examples of catalytic particle sizes are not intended to limit the scope of the invention. In a specific example, the size of the catalytic particles (homogeneous catalytic particles or heterogeneous catalytic particles) is between 1 µm and 25 µm. In another example of the present invention, the homogeneous catalytic particles are formed by grinding metallic palladium into particles, and passing the resulting particles through a sieve with a 25 µm rectangular opening grid. In another example, the catalytic resin mixture 106 is formed by mixing homogeneous catalytic particles or heterogeneous catalytic particles into the prepreg resin in a weight ratio, for example, the catalytic particles having a weight ratio of substantially 12% to the resin. . Or, the weight ratio of the catalytic particles in the resin mixture may be in the range of 8% to 16% of the total weight of the resin. It should be understood that other mixing ratios can also be used, and preferably smaller particles can be used. In an example of the present invention, the density of the catalytic particles is selected to provide an average distance between the catalytic particles of 3 µm to 5 µm.

After the fabric is immersed in the catalytic resin bath 106 with roller 104, the cloth impregnated with catalytic particles is guided to the roller 110, which establishes the thickness of the prepreg 105 in the uncured liquid A stage, and also establishes the glass plus resin in resin proportion. Then, the A-stage prepreg 105 passes through the oven 103. The oven 103 drives out the organic compounds and other volatile compounds in the A-stage prepreg, and greatly reduces the liquid content, thereby forming a tack-free transported by the roller 111.的B-stage prepreg 107. In a specific example, the oven 103 drives out the volatile compounds of the A-stage prepreg containing 80% solvent to about the B-stage prepreg containing less than 0.1% solvent. The obtained B-stage prepreg 107 is provided to material handling 111, and can be cut into sheets for easy handling and storage, and then placed in the laminator 126 of FIG. 1B, which is vacuum-treated Pressure is applied to the surface of the sheet and the temperature distribution is changed when the prepreg core is in the laminator (which follows the temperature profile 202 in Figure 2). In an example of the present invention, in order to produce a resin-rich surface, the prepreg material located near the outer surface (the surface is later removed to expose the underlying catalytic particles) is selected to have more than 65% resin, such as Glass 106 (71% resin), Glass 1067 or Glass 1035 (65% resin), and select the internal prepreg (which has not been subjected to surface removal) to have less than 65% resin. In addition, in order to reduce the possibility of glass fibers present near the surface of the catalytic prepreg, woven glass fibers can be used for the inner prepreg layer, and flat nonwoven glass fibers can be used for the outer resin-rich prepreg layer. The combination of resin-rich prepreg and flat nonwoven glass fibers creates an exclusion zone of 0.7 mils (17 µm) to 0.9 mils (23 µm) on the outer surface layer, which is between the outer surface and the coated Between glass fibers. It is better to use glass styles 106, 1035 and 1067 on the outer surface rich in resin, because the thickness of these glass fibers is smaller than that of general prepregs (1.3 mils to 1.4 mils, converted to 33 µm to 35 µm), the central area of the base layer of the general prepreg material uses more than 65% resin, such as glass style 2116, which has 3.7 mils (94 µm) fibers. These values are given as examples only, and the smallest commercially available glass fiber diameter is expected to continue to decrease. In the present invention, a temperature-time line is made so that the catalytic particles and glass fibers can migrate from the outer surface of the base layer, which are repelled by the surface tension of the epoxy resin during the liquid state of the gel point temperature. After the curve 202 cooling cycle, the solidified C-stage prepreg is unloaded 114. The process of forming a cured C-stage prepreg can use a single fiber fabric or multiple fiber fabrics to change the thickness of the finished product, which can vary from 2 mils (51 µm) to 60 mils (1.5 mm).

Fig. 3 shows a flow chart of the manufacturing process of the base layer of the prepreg, in which the catalytic particles are injected into the prepreg but excluded from the outer surface thereof. Step 302 is a step of mixing catalytic particles into the resin, and organic volatiles are usually added to reduce the viscosity of the mixture, which forms the catalytic resin 106 placed in the storage tank 108. Step 304 is a step of injecting the catalytic resin into the fabric. For example, the roller 104 of FIG. 1 can provide a stage A prepreg; step 306 is the preliminary rolling of the fabric in which the catalyst resin is injected, for example, a stage B is formed by the roller 110 The step of prepreg; step 307 is a baking step to remove the organic solvent to form a B-stage prepreg; and step 308 is to press the fabric 130 into which the catalyst resin is injected into a catalyst C-stage prepreg in the laminator 126 The step of sheeting, which follows the temperature cycle of curve 202, the vacuum pump 128 evacuates the chamber 124 throughout the lamination process to remove bubbles in the epoxy resin and reduce any air gaps that may be formed in the epoxy resin . The cooled finished product catalyzed C-stage prepreg is cut and stored for subsequent use.

The temperature vs. time curve 202 in FIG. 2 shows the temperature distribution of the prepreg in the laminator 112, which is critical for the formation of the catalytic prepreg. The catalytic prepreg has the surface properties of catalytic particles, and the catalytic prepreg has the surface properties of catalytic particles. The particles are excluded from the resin-rich outer surface, but exist just below the resin-rich outer surface. The resin is in a liquid state in the storage tank 108, and after the resin is impregnated in the glass fiber and passed through the roller 110, the prepreg system is in the A stage. After baking 103, the prepreg system is in stage B, in which the volatile organic compounds are baked and accompanied by the initial hardening of the resin. At the end of the lamination cycle, such as the cooling stage in Fig. 2, the stage B prepreg is transformed into C Stage prepreg. The B-stage prepreg was placed in a laminator and evacuated to avoid the formation of trapped air between the laminated layer and the laminated layer. During the temperature rise 204, heat is applied to reach the prepreg gel point 205 (the gel point is defined as the state where the liquid and solid are close to each other), which is determined by the temperature and pressure and lasts for 10 to 15 seconds. The process of migrating out of the surface is critical, after which the temperature of the prepreg is maintained at the residence temperature and residence time 206 (which can be between 60 minutes and 90 minutes), followed by a cooling cycle 208. The residence temperature and the gel point temperature depend on the pressure and the resin, for example between 120°C (for resin) to 350°C (for Teflon/polyimide resin). If the prepreg remains at the gel point 205 too short, it will cause the fiber glass catalytic particles to unfavorably exist on the surface of the finished prepreg.

4 shows the resulting catalytic prepreg 402 formed by the processes of FIGS. 1, 2 and 3, in which the catalytic particles 414 are evenly distributed in the central area of the prepreg 402, but not on the first surface 404 Below the boundary region 408 below, or does not exist below the boundary region 410 below the second surface 406. For example, for the particle distribution of particles smaller than 25 µm, the catalytic particle boundary is generally 10 µm to 12 µm below the surface (about half the particle size), so this depth (or deeper depth) of the surface material must be shifted. Divide, so that the embedded catalytic particles can be used for electroless plating.

The conventional catalytic laminate has an activated surface and must be shielded to avoid undesirable electroless plating on the activated surface of the catalytic laminate. On the contrary, the catalytic laminate of the present invention excludes catalytic particles in the thickness range from the first surface 404 to the first boundary 408 and from the second surface 406 to the second boundary 410, which provides the advantages of: Like the conventional technology, electroless plating does not require a separate masking layer to avoid contact with the catalytic particles. Therefore, removing the surface material from the first surface 404 to the depth (or deeper) of the first boundary 408, or removing the surface material from the second surface 406 to the depth of the second boundary 410, will result in the The electroplated catalytic material is exposed. It is also hoped that the method of providing a resin-rich surface not only eliminates the catalyst, but also eliminates the fiber fabric, because removing the surface layer in the subsequent steps that will cause the fiber exposure will require an additional cleaning step, so it is better to remove only the surface Resin to expose the catalytic particles below. This is accomplished by using a combination of a resin-rich outer prepreg layer and flat nonwoven glass fibers with smaller diameter fibers on the outer layer. The additional benefit of using electroless plating to form traces in the channels is that the traces are mechanically supported on three sides, which provides greatly improved trace adhesion to the dielectric substrate.

Figure 5 illustrates the process of using a catalytic laminate to form a single-layer circuit board. The catalytic laminate can be formed into 502, or provided in the form of a catalytic particle distribution as shown in Figure 4, which has an exclusion depth of 418 and is Electroless deposition is provided in the channel deeper than the exclusion depth 418, and does not support electroless plating on the surface or areas where the surface material is not removed. This is formed by the process of FIG. 1A, FIG. 2 and FIG. 3 and shown in FIG. 5 Step 502 presents the basic characteristics of the catalytic laminate. The catalytic laminate 502 may have selective holes formed in step 504 and then formed in step 506 to extend to below the drainage depth. Any method can be used to form the vias and channels, including the use of laser drilling, mechanical drilling, chemical etching, plasma etching using a mask, or by direct application to a local area. In a preferred method, laser cutting is used to form the channels and through holes, wherein the laser scans along the pattern of the channels and through holes and adjusts the amplitude to a rectangular channel shape. Or, although it is preferable to form a rectangular channel, other channel shapes (trapezoid, negative edge slope, positive edge slope) can also be formed.

In step 508, the board is placed in an electroless copper bath, which results in the deposition of electroless copper in the channels and selective holes. This electroless deposition system is performed to provide the thinnest metal layer (such as a copper layer), which is preferably between 1 µm and 4 µm in thickness, or 2 µm in thickness, to ensure that the metal particles are melted in the channels and holes Into a trace.

Step 508 is drawn with a dashed line. As another specific example of the present invention relative to FIG. 5, step 502 uses a non-catalytic laminate, and in step 508 no electroless copper plating is deposited. The through hole is drilled 504 and the channel 506 is formed, and then step 510 is performed, and metal powder is provided in the channel and the hole, and there is no previously deposited metal in the previously formed channel and the hole. In this other specific example where there is no electroless copper deposition, any conductive metal powder can be used in combination with the baking/sintering process. However, generally lead-containing solder paste formulations or lead-free solder paste formulations that do not use conductive pastes are used because of their A copper substrate is required to successfully perform surface wetting and bonding with conductive paste. Commercial lead-free conductive pastes can contain traces of tin, copper, silver, bismuth, indium, zinc, antimony, and other metals. The conventional lead-containing conductive paste formulations (tin/lead) are 60/40 and 63/37, which provide eutectic properties.

In order to be used with a catalytic layer or a non-catalytic layer having channels or holes, in step 510, metal particles are introduced into the channels and holes. In an example of the present invention, the metal particles as a metal suspension are provided together with a wetting agent, and are coated with a doctor blade to ensure that the metal particles are only present in the channels and selective holes, and that the metal particles are not distributed in the On the surface of the circuit board. Scraper metal particle injection can be performed on one side at a time, or on both sides together, or on one side of a single-sided plate with channels on only one side, or on both sides of both sides of the plate. For the veneer, the baking step 516 is performed at a temperature sufficient to cause the metal particles to sinter together in the channels or any holes to form unconsolidated porous traces, or preferably melt together and form uniform without gaps Or the trace of the gap.

The conductive paste can be any conductive paste known in the prior art, such as an emulsion of conductive particles with an average size of 10 µm, wherein the conductive particles contain at least one of copper, silver, gold, palladium, nickel, indium, bismuth, tin, or lead. One, optionally combined in proportion to form a eutectic system with a better single melting temperature, or the particles may be formed of copper coated with gold, silver or nickel, any type of particles and a binder (such as phenolic plastic, Phenolic epoxy resin (a pre-polymerized resin that cures when heated), or any of the following resins mixed with a solvent: diethylene glycol dibutyl ether, poly(formaldehyde/phenol) 2,3 epoxy propylene Ethyl ether or ethyl sorbitol acetate, either of the above provides fast drying time. Alternatively, the conductive particles may be mixed with a binder such as fatty acid or stearic acid and a solvent such as alcohol or acetone. Examples of commercially available conductive powders are silver-plated copper powders manufactured by Hitachi Chemical Co., Ltd.: GB05K (average particle size of 5.5 µm) or GB10K (average particle size of 10 µm), with an aspect ratio of approximately 1.0. Although these are available examples, the conductive paste preferably contains metal particles of 1 µm or smaller, although this requirement will vary with the width and depth of the relevant channel. In a preferred embodiment, the metal particles have a maximum length of one-hundredth or less of the characteristic width of the channel or hole, or the particle size can be one-fourth or less of the depth of the channel. A particle size significantly smaller than a quarter of the channel depth is used to better fill the channel, for example, 5 µm is preferable.

In one embodiment of the present invention, the commercially available conductive paste is MP500 manufactured by Tutsuta Corporation (please refer to the following website: www.tatsuta.com), which has an exemplary property of a maximum metal particle size of 25 µm, and is 4 µm Metal particles with half the volume of any given volume within the size range of 6 µm. In another embodiment of the present invention, the conductive paste has at least one composition by weight or by volume: tin (40%-50%), copper (20%-30%), silver (1%-10%) , Nickel (1%-10%), zinc (1%-10%), bismuth (10%-20%) and resin (4%-7%). In another embodiment of the present invention, the commercially available conductive paste is Ormet 701 manufactured by Ormet Circuits (please refer to the following website: www.ormetcircuits.com).

In a preferred embodiment of the present invention, step 514 can be performed separately to form a number of separate plates, and the plates can be aligned or stacked in a laminator, as shown in Figure 1C 134, and then heated and extruded Press until the individual boards are laminated together, and form a trace that is consolidated and melted in the channel and in the hole, including from one circuit board to another through the laminated surface and through the through hole Any interconnection. In this way, a laminated circuit board and conductive paste can be formed into conductive traces in a single process.

6A to 6G show cross-sectional views of a circuit board formed using several steps of the manufacturing process. Fig. 6A shows a catalytic laminate with outer surfaces 602A and 602B, which does not contain catalytic particles, but has catalytic particles at the depth of removal below the surface. 6B shows selective laser drilling holes 604 and 606, which expose the catalytic particles in the inner surface of the drilling holes or through holes 604 and 606. FIG. 6C illustrates the formation of channels 608A on the top surface and the formation of channels 608B on the bottom surface. An optional ring channel may be formed around each through hole 604. Figure 6D illustrates the electroless copper flash plating step, where the channels and via holes receive a thin electroless copper mold that supports the adhesion of traces formed later in the channel. Figure 6E shows a paste emulsion coated with metal particles, such as a wetting agent, and metal particles such as copper, silver, gold, palladium, nickel, indium, bismuth, tin, or lead, which are selectively combined in proportions To form a eutectic system with a better low single melting temperature, or to use particles formed of copper coated with any one of gold, silver, or nickel. The metal particles are preferably less than one third of the smallest dimension of the channel. For example, a channel of 0.001 inches (about 25 µm) with a depth of 3 µm will use metal particles of about 1 µm or smaller. The electroless plating layer with conductive paste can be heated until the metal particles and optional wetting agent form circuit board traces. The circuit layer of FIG. 6E can be coated on one or more other layers to be laminated and combined in a single step The metal particles are melted into traces. 6F shows an example in which the layer 622 is pre-baked until the metal particles are sintered or melted into conductive traces, and the layer 624 and the layer 620 with the metal particles are aligned and positioned adjacent to each other, and then they are heated And extruded together to form a laminated multilayer circuit board. An additional layer with metal particles in the channel can then be applied to the outer layer laminated and assembled in the previous step to form a multilayer circuit board. The metal particles can be laminated and fused into traces using all layers of the circuit board in a single high-temperature lamination step, or it can be performed on successive layers of the outer layer, until all layers are laminated and traces are formed by molten metal particles. line. Figure 6G shows the final multilayer board with vias 626 and 630, which provide connections from one trace layer to another trace layer and layers 624 and 620 laminated to layer 622, by in one step or as The sequential operation melts the conductive paste to form laminates and traces.

Fig. 7A illustrates the outer layer treatment according to another specific example of the present invention. The outer layers 702A and 702B are laser drilled holes 704 and 706, and as described above, channels 708A and 708B are formed, and electroless plating is performed as shown in FIG. 7D. As shown by the dashed line 701 (compressed and not drawn to scale), these layers are laminated to the inner layer, such as the inner layer formed using the process shown in FIGS. 5 and 6A to 6G. The laminate is subjected to solder dipping 7E, in which the board is immersed in the solder, and a hot air knife providing a continuous hot air line is pulled through the board (for example, the board is transported by an air knife), which drives out excess solder on the surface and enters the channels and through-hole holes, And solder instead of metal particles to form traces in the land. This is advantageous because the electronic components are adhered to the outer layer, and because the traces are formed by the mixed material, no additional processing steps (solder paste and solder paste) are required after the final processing step of FIG. 7F.

FIG. 7G illustrates the top view 724 of FIG. 7F, which has traces 710A, through holes 724, and transitions to the traces of solder pads 728 and is ready to be applied to an example 8-pin surface mount integrated circuit . Since the pads (and traces) are composed of solder, the solder is compatible with the adhesive components on the board using conventional technology, thus simplifying the subsequent assembly steps of placing the components on the circuit board. In the prior art, separate solder paste tools are applied, which have holes corresponding to the pad elements, and solder/wetting agents are applied. In this structure, it is only necessary to apply a wetting agent, place the component on the top of the pad, and perform solder reflow in a high-temperature furnace, thereby saving steps and tools compared with the prior art manufacturing process.

In another variant embodiment of the present invention, for the outer layer of the board, an additional step 7G can be added, in which the solder resist is applied to all areas except the area 730 around the pad 728, as used in the prior art Solder mask tool to prevent the application of solder mask to the pad components. In an example of the present invention without a mold, the solder resist is applied to the entire surface of the outer circuit layer, and laser cutting is used to remove the solder resist in the area 730 of the pad component 728, thereby exposing the underlying pad Element 728.

In a specific example of the present invention, for a through-hole component (a component with a wire located in a conductive hole in a conductive laminate assembly), after the lamination/melting step at the hole where the through-hole is adhered, the second is implemented in the through-hole The secondary operation of the secondary drilling component sticking to the hole. The diameter of the drilled hole is smaller than the diameter of the filled through-hole hole to form a conductive material hole ring surrounding the hole of the drilled element.

The foregoing description is only used to provide examples of the present invention for understanding the fundamental mechanism and structure used, and is not intended to limit the scope of the present invention to the specific method or structure illustrated. For example, for example, the sequence of FIG. 6 can be used with a single-sided or double-sided structure. The through-hole holes of FIGS. 6F and 6G can be offset across layers, or aligned to provide continuous plugging holes for drilling to form through-hole component adhesion ring (as described above), and without loss of generality In some cases, the process shown in FIGS. 7A to 7F can be used to form the outer layer of a double-sided (single-layer base) board or a multilayer board.

In this specification, "approximately" should be understood as less than or less than 4 times, and "substantially" should be understood as less than or less than 2 times. Values of "order of magnitude" or "on the order of" include values ranging from 0.1 times to 10 times.

For printed circuit board manufacturing, several common post-process operations are not shown because these operations are universal and can be performed on boards manufactured according to the new method using conventional methods. Such operations include tin plating to improve solder flow, gold flash to improve conductivity and reduce corrosion, solder resist operations, and screen printing information on the board (part number, part name, etc.) 、Score the finished board or provide separators, etc. When several of these operations are performed on several facing flat panels of the present invention, improved results can be provided. For example, due to the thickness of the traces and through holes on the surface of the board, it will generally cause cracks when the symbols are screen printed on the traces or through holes. However, the above operation will provide excellent results on a flat surface. .

Figure 1A shows a schematic diagram of a method of forming an unprocessed catalytic prepreg.

Figure 1B illustrates a vacuum laminator that forms a finished catalytic prepreg from an unprocessed catalytic prepreg.

Figure 1C illustrates the vacuum lamination stage used to form a multilayer catalytic prepreg during lamination.

FIG. 2 illustrates the process time of the vacuum lamination stage of FIG. 1.

Figure 3 illustrates the process steps for forming a catalytic prepreg.

Fig. 4 is a diagram showing the distribution of catalytic particles in the prepreg material relative to a cross-sectional view of the prepreg material.

FIG. 5 illustrates the process steps of forming a single circuit board layer according to an example of the present invention.

6A to 6G illustrate the process steps according to the present invention.

7A to 7F illustrate the process steps of the outer layer according to the present invention.

Fig. 7G shows a top view of the outer layer prepared according to the steps of Figs. 7A to 7F.

502: Step

504: Step

506: step

508: step

510: Step

514: step

516: step

Claims (24)

A circuit board layer formed by a catalytic prepreg layer, which has a distribution of catalytic particles at a depth below the surface layer, which is sufficient to provide electroless copper deposition; The circuit board layer has trace channels, the depth of the trace channels is lower than the exclusion depth, and the circuit board layer also optionally has holes; The trace channels have electroless plating in the areas exposed by the catalytic particles; The trace channels and the selective holes have conductive traces, and the conductive traces are formed by melting conductive paste in the trace channels and the selective holes. For the circuit board layer described in item 1 of the scope of patent application, the catalytic particles are homogeneous. For the circuit board layer described in item 2 of the scope of patent application, the homogeneous catalytic particles are at least one of the following: palladium (Pd), platinum (Pt), rhodium (Rh) of transition metal elements of groups 9 to 11 , Iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu). For the circuit board layer described in item 1 of the scope of the patent application, the catalytic particles include filled particles coated with a catalyst. For example, the circuit board layer described in item 4 of the scope of patent application, wherein the filler particles are at least one of the following: clay minerals, hydrous aluminum phyllosilicate, silica, kaolin, polysilicate, The kaolin or porcelain clay family member or high temperature plastic. For the circuit board layer described in item 1 of the scope of patent application, the catalytic particles are silica or kaolin coated with catalytic materials. The circuit board layer described in item 1 of the scope of patent application, wherein the electroless electroplating is copper. The circuit board layer described in item 7 of the scope of patent application, wherein the electroless electroplating has a thickness ranging from 0.2 μm to 20 μm. The circuit board layer according to the first item of the scope of patent application, wherein the conductive paste contains at least among the copper, silver, gold, palladium, nickel, indium, bismuth, tin, lead or copper coated with gold, silver or nickel A kind of metal particles. The circuit board layer described in item 1 of the scope of patent application, wherein the conductive paste has at least one composition by weight or by volume: tin (40%-50%), copper (20%-30%), Silver (1%-10%), nickel (1%-10%), zinc (1%-10%), bismuth (10%-20%). The circuit board layer according to the 10th item of the scope of patent application, wherein the conductive paste contains 4% to 7% resin by weight or by volume. As for the circuit board layer described in item 1 of the scope of patent application, the trace channels are formed only on one side of the catalytic laminated board or are formed on both sides of the catalytic laminated board. A method for forming a circuit board layer from an autocatalytic laminate plate, the catalytic laminate plate having catalytic particles below the removal depth of at least one surface, the method comprising: Forming channels in the at least one surface of the catalytic laminated plate, the channels being formed below the exclusion depth; Selectively forming holes from one surface of the catalytic laminate to the opposite surface of the catalytic laminate; Electroplating and electroless plating on the channels and holes of the catalytic laminated board so as to be sufficient to bond the conductive paste after melting or sintering; Apply the conductive paste to the channels and the selective holes; and The circuit board layer is heated until the conductive paste is sintered or melted or sintered onto the electroless plating deposition of the channels. The method described in item 13 of the scope of patent application, wherein the catalytic laminate is a resin mixed with homogeneous particles, and the particles are at least one of the following: palladium (Pd) of transition metal elements of groups 9 to 11, platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu). The method described in item 13 of the scope of the patent application, wherein the catalytic laminate is a resin mixed with catalytic particles containing filled particles coated with a catalyst. The circuit board layer according to item 15 of the scope of patent application, wherein the filler particles are at least one of the following: clay minerals, hydrated aluminum phyllosilicate, silica, kaolin, polysilicate, the kaolin or porcelain clay family Member or high temperature plastic. For example, the method described in claim 13, wherein the channels are formed by using at least one of the following: laser cutting, mechanical grinding, mechanical cutting, chemical etching or plasma etching, thereby exposing the catalytic particles below Below the exclusion depth. The method described in item 13 of the scope of the patent application, wherein the electroless electroplating is copper and has a thickness ranging from 0.2 μm to 20 μm. The method described in item 13 of the scope of patent application, wherein the conductive paste has at least one composition by weight or by volume: tin (40%-50%), copper (20%-30%), silver ( 1%-10%), nickel (1%-10%), zinc (1%-10%), bismuth (10%-20%). The method according to item 13 of the scope of patent application, wherein the conductive paste contains metal particles, and the metal particles are at least one of copper, silver, gold, palladium, nickel, indium, bismuth, tin, and lead. A method of forming a plurality of circuit board layers, the plurality of circuit board layers are formed of a plurality of catalytic laminate layers, each of the catalytic laminate layers is formed of resin and catalytic particles, and each of the catalytic laminate layers The layer has a resin-rich surface, each surface has catalytic particles that are insufficient to support electroless copper deposition, and each of the catalytic laminate layers has catalytic particles that are lower than the exclusion depth and have sufficient density to allow electroless deposition; Each of the catalytic laminate layers has channels and selective holes, the channels extend below the exclusion depth, and the channels and the selective holes have electroless copper deposited therein; The channels and the selective holes of each of the catalytic laminates are filled with conductive paste, and each of the catalytic laminates is placed adjacent to each other and bears high pressure and high temperature, The high pressure and the high temperature are sufficient to laminate the catalytic laminate layers, and the conductive paste in the channels and the selective holes is melted or sintered into conductive continuous traces. In the method described in claim 21, at least one of the conductive continuous traces in the selective through holes is drilled to accommodate through-hole components. A method of forming a circuit board layer from a catalytic laminated board formed of a resin mixed with catalytic particles and a selective fiber net, the catalytic laminated board having catalytic particles below the removal depth of the outer surface, The method includes: Forming channels and pores in the catalytic laminate, the depth of the channels exceeding the exclusion depth; Depositing copper in the channels and holes by using electroless deposition methods; Filling the channels and the selective holes with conductive paste containing metal particles; The conductive metal particles and the catalytic laminate are heated to a temperature sufficient to sinter or melt the conductive metal particles to form conductive traces. A method for forming a multi-layer circuit board, the multi-layer circuit board is formed by a plurality of catalytic laminated board layers, each of the catalytic laminated board layers is formed by a resin mixed with catalytic particles and a selective fiber net, at least one circuit The catalytic particles of the plate layer only support electroless copper deposition in the channels, and the channels are formed below the catalytic particle removal depth of the catalytic laminated plate. The method includes: Forming channels and selective holes in each of the catalytic laminate layers; Electroless copper plating in the channels and holes in each of the catalytic laminate layers; Filling the channels and the holes with conductive paste containing metal particles; A plurality of circuit board layers are stacked and placed in a laminator, and the conductive particles and the catalytic laminate are heated to a temperature sufficient to melt or sinter the conductive particles, so that the passages and the at least two Conductive traces are formed in the circuit board layers to bond with each other.

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