TW202101969A - Solid-state imaging element - Google Patents

Abstract

The purpose of the present invention is to reduce electricity consumption. This solid-state imaging element comprises: a photoelectric conversion element that photoelectrically converts incident light to generate an electric current; an electric current/voltage conversion unit that converts the electric current input from the photoelectric conversion element to voltage; and an individual subtractor and a shared subtractor that are connected to the electric current/voltage conversion unit and subtract the other voltage from one voltage of voltages input from the electric current/voltage conversion unit at different timings.

Description

Solid-state image sensor

The present disclosure relates to a non-synchronous solid-state imaging device.

Conventionally, in imaging devices and the like, a synchronous solid-state imaging element that captures image data (frame) in synchronization with a synchronization signal such as a vertical synchronization signal has been used. In this general synchronous solid-state imaging device, since the image data can only be obtained in each cycle (for example, 1/60 second) of the synchronization signal, it is difficult to respond to the requirements for higher-speed processing in transportation or robotics related fields. situation. Therefore, it has been proposed that a detection circuit for real-time detection is provided in an asynchronous solid-state imaging element for each pixel by setting the purpose of the light amount of the pixel exceeding the threshold value as an address event according to each pixel address (for example, refer to Patent Document 1). In this way, the solid-state image sensor that detects address events per pixel is called DVS (Dynamic Vision Sensor). [Prior Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Publication No. 2017-535999

[The problem to be solved by the invention]

Among the above-mentioned non-synchronous solid-state imaging devices (ie, DVS), data can be generated and output far ahead of synchronous solid-state imaging devices. Therefore, in the field of transportation, for example, the image recognition process of people or obstacles can be executed at a high speed to improve safety. However, the detection circuit for address events has a larger number of components than the image circuit and transistor in the synchronous type, and there is a problem of increased power consumption.

The purpose of the present disclosure is to provide a solid-state imaging device capable of achieving low power consumption. [Technical means to solve the problem]

The solid-state imaging element of the present disclosure includes: a photoelectric conversion element that photoelectrically converts incident light to generate a current; a current-to-voltage conversion unit that converts the current input from the photoelectric conversion element into a voltage; and a plurality of subtraction units, which Etc. are connected to the current-voltage conversion unit, and one voltage input from the current-voltage conversion unit is subtracted from another voltage at a different timing.

The solid-state imaging element of the present disclosure includes: a plurality of photoelectric conversion elements, each of which photoelectrically converts incident light to generate current; a plurality of current-voltage conversion parts, each of which is connected to each of the plurality of photoelectric conversion elements, And convert the current input from the photoelectric conversion element into a voltage; and a common subtraction unit, which is connected to the plurality of current-voltage conversion units, and is based on a voltage input from each of the current-voltage conversion units at different timings The first voltage is subtracted from the second voltage based on another voltage.

Hereinafter, a mode for implementing the technique of the present disclosure (hereinafter referred to as an "embodiment") will be described in detail using drawings. The technology of this disclosure is not limited to the embodiment. In the following description, the same symbols are used for the same elements or elements with the same function, and repeated descriptions are omitted. In addition, the description is given in the following order. 1. General description of the imaging device and solid-state imaging element of the present disclosure 2. The first embodiment of this disclosure (flicker suppression) 3. The second embodiment of this disclosure (multi-resolution sensor) 4. The third embodiment of this disclosure (weighted addition and convolution calculation)

1 to 4, the structure common to the solid-state imaging device of each embodiment of the present disclosure and the structure of the imaging device using the solid-state imaging device will be described. First, using FIG. 1, a schematic configuration of an imaging device using the solid-state imaging element of each embodiment will be described.

FIG. 1 is a block diagram showing a configuration example of the imaging device 100 of each embodiment of the present disclosure. As shown in FIG. 1, the imaging device 100 includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and a control unit 130. As the imaging device 100, a camera mounted on an industrial robot, an in-vehicle camera, or the like is assumed.

The imaging lens 110 condenses incident light and guides the light to the solid-state imaging element 200. The solid-state imaging device 200 photoelectrically converts incident light to capture image data. The solid-state imaging device 200 performs specific signal processing such as image recognition processing on the captured image data, and outputs the data representing the processing result and the detection signal of the address event to the recording unit 120 via the signal line 209 .

The recording unit 120 records data from the solid-state imaging device 200. The control unit 130 controls the solid-state imaging device 200 to capture image data.

Next, the solid-state imaging device 200 of each embodiment of the present disclosure will be described using FIGS. 2 to 4. FIG. 2 is a diagram showing an example of the layered structure of the solid-state imaging device 200. As shown in FIG. 2, the solid-state imaging device 200 includes a detection wafer 202 and a light-receiving wafer 201 laminated on the detection wafer 202. The detection chip 202 and the light-receiving chip 201 are electrically connected via connecting parts such as via holes. In addition, in addition to vias, Cu-Cu bonding or bumps can also be used for connection.

FIG. 3 is a block diagram showing a configuration example of the solid-state imaging device 200 of each embodiment of the present disclosure. As shown in FIG. 3, the solid-state imaging element 200 includes a drive circuit 211, a signal processing unit 212, an arbiter 213, a row ADC 220, and a pixel array unit 300.

In the pixel array part 300, a plurality of pixels are arranged in a two-dimensional grid. In addition, the pixel array portion 300 is divided into a plurality of pixel blocks each containing a specific number of pixels. Hereinafter, the set of pixels or pixel blocks arranged in the horizontal direction is referred to as "row", and the set of pixels or pixel blocks arranged in the vertical direction of the column is referred to as "row".

Each of the pixels generates an analog signal corresponding to the voltage of the photocurrent as the pixel signal. In addition, each of the pixels detects the presence or absence of an address event by whether the variation of the photocurrent exceeds a certain threshold. Moreover, when an address event occurs, the pixel block outputs the request to the arbiter. The pixel blocks are constructed in a way that performs different functions according to each implementation. The function of the pixel block is described below.

The driving circuit 211 drives each of the pixels to output the pixel signal to the row ADC 220.

The arbiter 213 mediates the request from each pixel, and sends a response to the pixel based on the mediation result. The pixel that has received the response supplies a detection signal indicating the detection result to the drive circuit 211 and the signal processing unit 212.

The row ADC 220 converts the analog pixel signal from the row into a digital signal according to the row of each pixel block. The row ADC 220 supplies the digital signal to the signal processing unit 212.

The signal processing unit 212 performs specific signal processing such as CDS (Correlated Double Sampling) processing or image recognition processing on the digital signal from the ADC 220. The signal processing unit 212 supplies the data representing the processing result and the detection signal to the recording unit 120 via the signal line 209.

4 is a circuit diagram showing a configuration example of the pixel P in each embodiment of the present disclosure. The pixel array unit 300 has a plurality of pixels P arranged in m columns×n rows (m and n are natural numbers). The plurality of pixels P are arranged in a matrix, for example, in the pixel array section 300.

As shown in FIG. 4, the pixel P includes a pixel signal generating unit 320, a light receiving unit 330, and an address event detecting unit 4. The vertical signal line VSL is wired for each pixel P row. If the number of rows of the pixels P is n (n is a natural number), n vertical signal lines VSL are arranged.

The light receiving unit 330 photoelectrically converts incident light to generate photocurrent. The light receiving unit 330 supplies photocurrent to any one of the pixel signal generating unit 320 and the address event detecting unit 4 according to the control of the driving unit 211.

The pixel signal generating unit 320 generates a voltage signal corresponding to the photocurrent as the pixel signal SIG. The pixel signal generating part 320 supplies the generated pixel signal SIG to the row ADC 220 via the vertical signal line VSL.

The address event detection unit 4 detects the presence or absence of an address event based on whether the change amount of the photocurrent from the light receiving unit 330 exceeds a specific threshold. The address event is composed of, for example, an on event indicating that the amount of change in photocurrent exceeds (above) the upper limit threshold, and an off event indicating that the amount of change in photocurrent exceeds (below) the lower limit threshold. In addition, the detection signal of the address event is composed of, for example, 1 bit indicating the detection result of the on event and 1 bit indicating the detection result of the off event. In addition, the address event detection unit 4 may only detect the ON event.

When an address event occurs, the address event detection unit 4 supplies a request for sending a detection signal to the arbiter 213. In addition, when a response to the request is received from the arbiter 213, the address event detection unit 4 supplies the detection signal to the drive circuit 211 and the signal processing unit 212.

As shown in FIG. 4, the pixel signal generating unit 320 includes a reset transistor 321, an amplification transistor 322, a selection transistor 323, and a floating diffusion layer 324. The light receiving unit 330 is connected to the address event detection unit 4.

In addition, the light receiving unit 330 includes a transmission transistor 331, an OFG (Over Flow Gate) transistor 332, and a photoelectric conversion element 333. A transmission transistor 331, an OFG transistor 332, and a photoelectric conversion element 333 are arranged for each pixel P. The transmission signal TRG is supplied to the transmission transistor 331 by the driving circuit 211 (refer to FIG. 3). The drive circuit 211 supplies the control signal OFG to the OFG transistor 332.

In addition, as the reset transistor 321, the amplifying transistor 322, and the selection transistor 323, for example, an N-type MOS (Metal-Oxide-Semiconductor) transistor is used. For the transmission transistor 331 and OFG transistor 332, N-type MOS transistors are also used.

In addition, each of the photoelectric conversion elements 333 is arranged on the light-receiving wafer 201 (refer to FIG. 2). All elements other than the photoelectric conversion element 333 are arranged on the detection wafer 202 (refer to FIG. 2).

The photoelectric conversion element 333 photoelectrically converts incident light to generate electric charge. The transfer transistor 331 transfers charges from the corresponding photoelectric conversion element 333 to the floating diffusion layer 324 according to the transfer signal TRG. The OFG transistor 332 supplies the electrical signal generated by the corresponding photoelectric conversion element 333 to the address event detection unit 4 according to the control signal OFG. Here, the supplied electrical signal is a photocurrent containing charge.

The floating diffusion layer 324 accumulates electric charge and generates a voltage corresponding to the amount of accumulated electric charge. The reset transistor 321 initializes the charge amount of the floating diffusion layer 324 according to the reset signal from the driving circuit 211. The amplifier transistor 322 amplifies the voltage of the floating diffusion layer 324. The selection transistor 323 uses the signal of the amplified voltage as the pixel signal SIG according to the selection signal SEL from the driving circuit 211 and outputs it to the row ADC 220 (see FIG. 3) through the vertical signal line VSL.

The driving circuit 211 drives the OFG transistors 332 of all the pixels P by the control signal OFG when the control unit 130 instructs the start of detection of the address event to supply photocurrent. Thereby, the photocurrent of the light receiving part 330 of the pixel P is supplied to the address event detecting part 4.

Moreover, if an address event is detected in a certain pixel P, the driving circuit 211 turns the OFG transistor 332 of the pixel P into an off state, and stops the photocurrent supply to the address event detection unit 4. Then, the driving circuit 211 sequentially drives the respective transfer transistors 331 by the transfer signal TRG, so that the charges are transferred to the floating diffusion layer 324. Thereby, the pixel signals of each of the plurality of pixels in the pixel block 310 are sequentially output.

In this way, the solid-state imaging device 200 only outputs the pixel signal of the pixel P whose address event is detected to the row ADC 220. In this way, regardless of the presence or absence of address events, compared with the case where the pixel signals of all pixels are output, the power consumption of the solid-state imaging device 200 or the processing amount of image processing can be reduced.

[First Embodiment] Next, the solid-state imaging device according to the first embodiment of the present disclosure will be described using FIGS. 5 to 17. The first embodiment is divided into Embodiment 1-1 to Embodiment 1-7, and 7 types of flicker suppression techniques will be described.

However, when lighting devices such as lighting devices or display devices installed in the house are driven by dynamic lighting (pulse lighting or load lighting) at a constant frequency and high-speed blinking, these devices may flicker (subtle brightness). Dark (flicker)) phenomenon. When a solid-state image sensor is used in a house, the brightness caused by the flicker phenomenon may be misdetected as an address event. As a result, the detection accuracy of the address event of the solid-state image sensor may be reduced. The solid-state imaging device of the present embodiment is characterized in that it can suppress the deterioration of detection accuracy of address events caused by the flicker phenomenon.

[Embodiment 1-1] FIG. 5 is a circuit block diagram showing an example of the configuration of the address detection unit 4 and the flicker detection circuit 5 of the solid-state imaging device 200 of the first embodiment 1-1. In addition, in FIG. 5, the illustration of the pixel signal generating portion 320, the transmission transistor 331 and the OFG transistor 332 provided in the pixel P is omitted.

As shown in FIG. 5, the solid-state imaging device 200 includes a plurality of address detection units 4, an addition unit 6 connected to the plurality of address event detection units 4, and a flicker detection circuit 5 connected to the addition unit 6. The number k of the address event detection parts 4 connected to the addition part 6 and the flicker detection circuit 5 is a natural number less than the total number (m×n) of the pixels P arranged in the pixel array part 300. The address event detection part 4 is formed in every pixel P. Therefore, the solid-state imaging element 200 of the present embodiment includes (m×n)/k addition units 6 and flicker detection circuits 5.

As shown in FIG. 5, the address event detection unit 4 provided in each of the pixels P provided in the solid-state imaging element 200 has the same configuration. The address event detection unit 4 has a current-voltage conversion unit 41, a subtractor (an example of an individual subtracting unit) 430, a quantizer (an example of a determination unit) 43, and a transmission unit (not shown). The current-voltage conversion unit 41 has a logarithmic conversion circuit 41a and a buffer circuit 41b.

As shown in FIG. 5, the solid-state imaging element 200 includes a plurality of (two shown in FIG. 5) photoelectric conversion elements 333 that respectively perform photoelectric conversion of incident light to generate current. In addition, the solid-state imaging element 200 includes a plurality of current-voltage conversion sections 41 that are connected to each of the plurality of photoelectric conversion elements 333 one by one, and convert the current input from the photoelectric conversion element 333 into voltage (two are shown in FIG. 5). . The current-voltage conversion unit 41 has a logarithmic conversion circuit 41a and a buffer circuit 41b. The current-voltage conversion unit 41 is configured to convert the current (photocurrent) input from the photoelectric conversion element 333 into a logarithmic output voltage value in the logarithmic conversion circuit 41a. The buffer circuit 41b has a source follow-up configuration and is configured to perform impedance conversion.

As shown in FIG. 5, the solid-state imaging element 200 includes an individual subtractor (an example of an individual subtractor) 42 which is connected to each of the plurality of current-voltage conversion units 41 one by one, and the connected current-voltage conversion unit 41 is free to differ In the sequence, one voltage input from the current-voltage conversion unit 41 subtracts the other voltage. The individual subtractor 42 is configured to output a difference voltage from the voltage at the timing when the column drive signal from the drive circuit 211 (see FIG. 3) is switched from the on state to the off state.

The quantizer 43 is configured to use two thresholds to quantize the voltage signal input from the individual subtractor 42 into a digital signal, and output to the transmission unit as a detection signal (+) and a detection signal (-).

The transmission unit is configured to transmit the detection signal (+) and the detection signal (-) input from the quantizer 43 to the signal processing unit 212 and the like. When the transmission unit detects an address event, it supplies a request for sending a detection signal to the arbiter 213. Next, when the transmission unit 450 receives a response to the request from the arbiter 213, it supplies the detection signal (+) and the detection signal (-) to the drive circuit 211 and the signal processing unit 212.

Next, the specific configuration of each component of the address event detection unit 4 will be described. As shown in FIG. 5, the logarithmic conversion circuit 41a constituting the current-voltage conversion unit 41 includes an N-type transistor 411, an N-type transistor 413, a P-type transistor 412, and a capacitor C41. As these transistors, for example, MOS transistors can be used.

The source of the N-type transistor 411 is connected to the cathode of the photoelectric conversion element 333. The drain of the N-type transistor 411 is connected to a power terminal (not shown). The P-type transistor 412 and the N-type transistor 413 are connected in series between the power terminal and the ground terminal. In addition, the connection point of the P-type transistor 412 and the N-type transistor 413 is connected to the gate of the N-type transistor 411 and the input terminal of the buffer circuit 41b. In addition, a specific bias voltage Vblog is applied to the gate of the P-type transistor 412.

The gate of the N-type transistor 413 is connected to the cathode of the photoelectric conversion element 333 and the source of the N-type transistor 411. One electrode of the capacitor C41 is connected to the gate of the N-type transistor 413 and the connection point of the P-type transistor 412 and the N-type transistor 413. The other electrode of the capacitor C41 is connected to the cathode of the photoelectric conversion element 333 and the gate of the N-type transistor 413.

The drains of the N-type transistors 411 and 413 are connected to the power supply side. This type of circuit is called a source follower. The two source followers connected in a ring shape convert the photocurrent input from the light receiving unit 330 into its logarithmic voltage signal. In addition, the P-type transistor 412 supplies a constant current to the N-type transistor 413. The capacitor C41 is provided to stabilize the gate voltage of each of the N-type transistor 411 and the N-type transistor 413. The logarithmic conversion circuit 41a may not have the capacitor C41.

As shown in FIG. 5, the buffer circuit 41b has a P-type transistor 414 and a P-type transistor 415. As these transistors, for example, MOS transistors can be used. The P-type transistor 414 and the P-type transistor 415 are connected in series between the power terminal and the ground terminal. The gate of the P-type transistor 415 is connected to the output terminal of the logarithmic conversion circuit 41a (the connection point of the P-type transistor 412 and the N-type transistor 413). The connection point of the P-type transistor 414 and the P-type transistor 415 is connected to the input terminal of the individual subtractor 42. In addition, a specific bias voltage Vbsf is applied to the gate of the P-type transistor 414.

As shown in FIG. 5, the individual subtractor 42 has a P-type transistor 421, a P-type transistor 422, an N-type transistor 423, and a capacitor C422. As these transistors, for example, MOS transistors can be used. In addition, the individual subtractor 42 has an individual capacitor C421 having one electrode connected to the current-voltage conversion section 41 to which the individual subtractor 42 is connected, and the other electrode arranged opposite to the one electrode.

The P-type transistor 422 and the N-type transistor 423 are connected in series between the power terminal and the ground terminal. The connection part of the P-type transistor 422 and the N-type transistor 423 is connected to the input terminal of the quantizer 43. A specific bias voltage Vbdiff is applied to the gate of the N-type transistor 423.

The source of the P-type transistor 421 is connected to the gate of the P-type transistor 422. The drain of the P-type transistor 421 is connected to the connecting portion of the P-type transistor 422 and the N-type transistor 423. The gate of the P-type transistor 421 is connected to the output terminal of the reset circuit 44 in the pixel provided in the pixel P. The details of the reset circuit 44 in the pixel are described below.

One electrode of the individual capacitor C421 is connected to the output terminal of the buffer circuit 41b (the connecting portion of the P-type transistor 414 and the P-type capacitor 415). The other electrode of the individual capacitor C421 is connected to the source of the P-type transistor 421 and the gate of the P-type transistor 422.

One electrode of the capacitor C422 is connected to the other electrode of the individual capacitor C421, the source of the P-type transistor 421, and the gate of the P-type transistor 422. The other electrode of the capacitor C422 is connected to the connecting portion of the P-type transistor 422 and the N-type transistor 423 and the drain of the P-type transistor 421.

The P-type transistor 421 is switched from the off state to the on state, and the N-type transistor 423 is switched from the off state to the on state. Thereby, a voltage (an example of a voltage) input from the current-voltage conversion unit 41 is applied to one electrode of the individual capacitor C421 at the time (timing) when the states of the P-type transistor 421 and the N-type transistor 423 are switched. In contrast, the voltage of the ground terminal is applied to the other electrode of the individual capacitor C421. At this time, assuming that the capacitance of the individual capacitor C421 is C1, the charge Qinit accumulated in the individual capacitor C421 is expressed by the following formula (1). On the other hand, since both ends of the capacitor C422 are short-circuited, its accumulated charge is zero. Qinit=C1×Vinit・・・(1)

After a certain period of time after the P-type transistor 421 is switched from the off state to the on state, the P-type transistor 421 is switched from the on state to the off state, and the N-type transistor 423 is switched from the on state It is disconnected. Thereby, a voltage corresponding to the voltage input from the current-voltage conversion unit 41 (an example of another voltage) is applied to the individual capacitor C421. If the voltage input from the current-voltage conversion unit 41 is Vafter, the charge Qafrer accumulated in the individual capacitor C421 is expressed by the following formula (2). Qafter=C1×Vafter・・・(2)

On the other hand, if the output voltage is set to Vdiff_after, the charge Q2 accumulated in the capacitor C422 is expressed by the following equation (3). Q2=-C2×Vdiff_after・・・(3)

At this time, since the total amount of charge of the individual capacitors C421 and C422 does not change (the charge preservation law), the following equation (4) holds. Qinit=Qafter+Q2・・・(4)

If formula (1) to formula (3) are substituted into formula (4) and deformed, the following formula can be obtained. Vdiff_after=-(C1/C2)×(Vdiff_after-Vinit)・・・(5)

Equation (5) represents the subtraction operation of the voltage signal, and the profit of the subtraction result becomes C1/C2. Generally, it is desired to maximize the profit, so it is better to increase the capacitance C1 of the individual capacitor C421 and reduce the capacitance C2 of the capacitor C422. On the other hand, if the capacitance C2 of the capacitor C422 is too small, the kTC noise may increase and the noise characteristics may deteriorate. Therefore, the capacitance reduction of the capacitor C2 of the capacitor C422 is limited to the allowable noise range. In addition, the address detection unit 4 including the individual subtractor 42 is installed for each pixel P. Therefore, the capacitance C1 of the individual capacitor C421 or the capacitance C2 of the capacitor C422 has area constraints. Considering these, determine the values of the capacitance C1 of the individual capacitor C421 and the capacitance C2 of the capacitor C422.

As shown in FIG. 5, the quantizer 43 has a P-type transistor 431, an N-type transistor 432, a P-type transistor 433, and an N-type transistor 434. As these transistors, for example, MOS transistors can be used.

The P-type transistor 431 and the N-type transistor 432 are connected in series between the power terminal and the ground terminal. The P-type transistor 433 and the N-type transistor 434 are connected in series between the power terminal and the ground terminal. The gate of the P-type transistor 431 and the gate of the P-type transistor 433 are connected to the output terminal of the individual subtractor 42 (the connecting portion of the P-type transistor 422 and the N-type transistor 423). The voltage level applied to the gate of the N-type transistor 432 is the upper threshold Vhigh of the high-level voltage. The voltage level applied to the gate of the N-type transistor 434 is the lower voltage threshold Vlow of the low level. The connection part of the P-type transistor 431 and the N-type transistor 432 is the output terminal of the detection signal (+) and is connected to the input terminal of the transmission part. The connection part of the P-type transistor 433 and the N-type transistor 434 is the output terminal of the detection signal (-), which is connected to other input terminals of the transmission part.

The quantizer 43 outputs the voltage level and the power supply voltage when the voltage value of the voltage input from the individual subtractor 42 is between the upper threshold Vhigh and the lower threshold Vlow (the upper threshold Vhigh and the lower threshold Vlow are not exceeded) The detection signal (+) of approximately the same level, and the detection signal (-) of the voltage level and the voltage of the ground terminal approximately the same level. In this case, the output of the quantizer 43 is "0", and the address event detection unit 4 detects that an event corresponding to the amount of light received by the photoelectric conversion element 333 has not occurred.

When the voltage value of the voltage input from the individual subtractor 42 exceeds the upper threshold Vhigh (when the voltage value is higher than the upper threshold Vhigh), the quantizer 43 outputs a detection signal of the same level as the ground terminal (+) , And the detection signal (-) whose voltage level is approximately the same as that of the ground terminal. In this case, the output of the quantizer 43 is "+1", and the address event detection unit 4 detects that an ON event corresponding to the amount of light received by the photoelectric conversion element 333 has occurred.

When the voltage value of the voltage input from the individual subtractor 42 exceeds the lower threshold value Vlow (below the lower threshold value Vlow), the quantizer 43 outputs a detection signal whose voltage level is approximately the same as the power supply voltage (+) , And the detection signal (-) whose voltage level is approximately the same as the power supply voltage. In this case, the output of the quantizer 43 is "-1", and the address event detection unit 4 detects that an off event corresponding to the amount of light received by the photoelectric conversion element 333 has occurred.

The reset circuit 44 in the pixel is constituted by, for example, an OR gate. The in-pixel reset circuit 44 is configured to output the control signal of the voltage level obtained by logically adding the output reset signal Vsum_rst and the column driving signal of the area reset generating circuit 53 (details are described below) provided in the flicker detection circuit 5 To the gate of P-type transistor 421. When the address event detection unit 4 performs a normal operation, the in-pixel reset circuit 44 outputs a control signal dependent on the column driving signal to the gate of the P-type transistor 421. On the other hand, the in-pixel reset circuit 44 outputs the control signal dependent on the output reset signal Vsum_rst to the gate of the P-type transistor 421 when the flicker detection circuit 5 detects the flicker. Thereby, the reset circuit 44 in the pixel can output an appropriate control signal according to whether the flicker detection circuit 5 detects flicker.

As shown in FIG. 5, the flicker detection circuit 5 equipped with the solid-state imaging element 200 has a common subtractor 51, which is connected to a plurality of (k in this example) current-to-voltage conversion units 41, and is based on self-current at different timings. Each of the voltage conversion unit 41 inputs a first voltage of one voltage, and subtracts a second voltage based on another voltage. The flicker detection circuit 5 has a common determination unit 52 that determines whether the difference between the first voltage and the second voltage based on the subtraction result of the common subtractor (an example of the common subtraction unit) 51 exceeds the upper threshold Vhigh and the lower threshold Vlow (either Those are examples of specific thresholds). The flicker detection circuit 5 has a region reset generation circuit (an example of a reset unit) 53 which is determined by the shared determination unit 52 that the difference based on the subtraction result of the shared subtractor 51 exceeds the upper threshold Vhigh (or the lower threshold Vlow) In this case, the operation of at least one of the plurality of photoelectric conversion elements 333, the plurality of current-voltage conversion units 41, and the plurality of individual subtractors 42 is reset.

Next, the specific configuration of each component of the flicker detection circuit 5 will be described. As shown in FIG. 5, the common subtractor 51 has a P-type transistor 511, a P-type transistor 512, an N-type transistor 513, and a capacitor C511. As these transistors, for example, MOS transistors can be used.

The P-type transistor 512 and the N-type transistor 513 are connected in series between the power terminal and the ground terminal. The connection part of the P-type transistor 512 and the N-type transistor 513 is connected to the input terminal of the common determination part 52. A specific bias voltage Vbdiff is applied to the gate of the N-type transistor 513.

The source of the P-type transistor 511 is connected to the gate of the P-type transistor 512. The drain of the P-type transistor 511 is connected to the connection part of the P-type transistor 512 and the N-type transistor 513. It is configured to reset the output signal of the generating circuit 53 or the column driving signal, etc. to the gate application area of the P-type transistor 512.

One electrode of the capacitor C511 is connected to the source of the P-type transistor 511 and the gate of the P-type transistor 512. The other electrode of the capacitor C511 is connected to the connecting portion of the P-type transistor 512 and the N-type transistor 513 and the drain of the P-type transistor 511. Since the operation of the common subtractor 51 is the same as that of the individual subtractor 42, the description is omitted.

As shown in FIG. 5, the common determination unit 52 is constituted by a quantizer. The common determination unit 52 has a P-type transistor 521, an N-type transistor 522, a P-type transistor 523, and an N-type transistor 524. As these transistors, for example, MOS transistors can be used.

The P-type transistor 521 and the N-type transistor 522 are connected in series between the power terminal and the ground terminal. The P-type transistor 523 and the N-type transistor 524 are connected in series between the power terminal and the ground terminal. The gate of the P-type transistor 521 and the gate of the P-type transistor 523 are connected to the output terminal of the common subtractor 51 (the connecting portion of the P-type transistor 512 and the N-type transistor 513). The voltage level applied to the gate of the N-type transistor 522 is the upper threshold Vhigh of the high-level voltage. The voltage level applied to the gate of the N-type transistor 524 is the lower voltage threshold Vlow of the low level. The connection part of the P-type transistor 521 and the N-type transistor 522 is the output terminal of the detection signal (+), and is connected to the input terminal of the area reset generating circuit 53. The connection part of the P-type transistor 523 and the N-type transistor 524 is the output terminal of the detection signal (-), and is connected to other input terminals of the area reset generating circuit 53.

When the voltage value of the voltage input from the shared subtractor 51 is between the upper threshold Vhigh and the lower threshold Vlow (the upper threshold Vhigh and the lower threshold Vlow are not exceeded), the sharing determination unit 52 outputs the power supply level and the power supply voltage The detection signal (+) of approximately the same level, and the detection signal (-) of the voltage level and the voltage of the ground terminal approximately the same level. The details are described below, but the voltage input from the common subtractor 51 (ie, the voltage output by the common subtractor 51) is the total voltage of the output voltages of the k individual subtractors 42 added by the addition unit 6. Therefore, when the output voltage of the shared subtractor 51 does not exceed the upper limit threshold Vhigh and the lower limit threshold Vlow, the output of the shared determination section 52 is "0", and the flicker detection circuit 5 detects that the photoelectric conversion element 333 receives no light. Flicker phenomenon.

When the voltage value of the voltage input from the shared subtractor 51 exceeds the upper threshold value Vhigh (when the voltage value is higher than the upper threshold value Vhigh), the common determination unit 52 outputs a detection signal of the same level as the ground terminal (+) , And the detection signal (-) whose voltage level is approximately the same as that of the ground terminal. In this case, the output of the common determination unit 52 is "+1", and the flicker detection circuit 5 detects that the light received by the photoelectric conversion element 333 has a flicker that changes from the dark state to the bright state.

When the voltage value of the voltage input from the shared subtractor 51 exceeds the lower threshold value Vlow (below the lower threshold value Vlow), the shared determination unit 52 outputs a detection signal with the voltage level approximately the same as the power supply voltage (+) , And the detection signal (-) whose voltage level is approximately the same as the power supply voltage. In this case, the output of the common determination unit 52 is "-1", and the flicker detection circuit 5 detects that the light received by the photoelectric conversion element 333 changes from the bright state to the dark state.

As shown in FIG. 5, the area reset generation circuit 53 is configured to receive the detection signal (+) and the detection signal (-) output by the common determination unit 52. The area reset generating circuit 53 is configured to output an output reset signal Vsum_rst of a specific voltage level according to the voltages of the detection signal (+) and the detection signal (-). The area reset generating circuit 53 receives a detection signal (+) whose voltage level is approximately the same level as the power supply voltage, and a detection signal (-) whose voltage level is approximately the same level as the voltage of the ground terminal, for example, The output voltage level is the high-level output reset signal Vsum_rst. Thereby, the output signal output by the reset circuit 44 in the pixel is a control signal dependent on the column driving signal. As a result, the P-type transistor 421 provided in the individual subtractor 42 is controlled by the output reset signal Vsum_rst and is not turned on.

On the other hand, the area reset generating circuit 53 receives a detection signal (+) whose voltage level is approximately the same level as the ground terminal, and a detection signal (-) whose voltage level is approximately the same level as the ground terminal voltage. In this case, the output voltage level is the low level output reset signal Vsum_rst. Similarly, when the region reset generating circuit 53 receives a detection signal (+) whose voltage level is approximately the same level as the power supply voltage, and a detection signal (-) whose voltage level is approximately the same level as the power supply voltage, for example, , It also outputs the output reset signal Vsum_rst whose voltage level is low. Thus, the output signal output by the reset circuit 44 in the pixel is a control signal dependent on the output reset signal Vsum_rst. As a result, the P-type transistor 421 provided in the individual subtractor 42 is controlled by the output reset signal Vsum_rst to be turned on. When the P-type transistor 421 continues to be turned on, the output voltage of the individual subtractor 42 is a constant value, and the upper threshold Vhigh and the lower threshold Vlow are not exceeded in the quantizer 43. As a result, it is possible to prevent the address event detecting unit 4 from detecting erroneous detection of the address event based on the flicker phenomenon.

As shown in FIG. 5, the solid-state imaging element 200 includes an addition unit 6 that adds the voltages output from each of a plurality of (k in this example) current-voltage conversion units 41. The adding unit 6 has adding capacitors C61 to C6k (k is the number of pixels P), which have: one electrode connected to one of the electrodes of the individual capacitor C421 provided in the current-voltage conversion unit 41 and opposite to the one electrode It is configured and connected to the other electrode of the common subtractor 51. The other electrodes of each of the addition capacitors C61 to C6k are connected to each other.

The addition capacitors C61 to C6k are configured to have a smaller capacitance than the individual capacitor C421 connected to each of the addition capacitors C61 to C6k. Therefore, the output voltage Vout of the current-voltage converter 41 is applied to one electrode of the addition capacitors C61 to C6k and the individual capacitor C421, and accordingly, the voltage variation of the other electrode is smaller than the individual capacitor C421. In this way, by making the voltage variation based on the output voltage Vout of the current-voltage conversion unit 41 in each of the addition capacitors C61 to C6k smaller than the individual capacitor C421, the solid-state imaging device 200 can prevent the normal detection in the address event detection unit 4 Misdetection of an address event is an address event caused by flickering.

The other electrodes of the addition capacitors C61 to C6K are connected to each other to form a common electrode. Therefore, due to the change in the output voltage of the current-voltage converter 41 applied to one electrode of each of the addition capacitors C61 to C6k, the charges injected into the common electrode of the addition capacitors C61 to C6k (that is, the other electrode of each) are mutually Mix to produce an additive effect. As a result, the adding unit 6 can output to the common subtractor 51 an added voltage obtained by adding the voltages applied to each of the adding capacitors C61 to C6k. Therefore, the common subtractor 51 can subtract the voltage based on the voltage (an example of the other voltage) based on the voltage (an example of the first voltage) input from each of the current-voltage conversion sections at different timings. ) Is the added voltage (an example of the second voltage). In this way, the shared subtractor 51 can prevent missed detection of address events caused by the flicker phenomenon.

In this embodiment, the addition capacitors C61 to C6k have, for example, the same capacitances. Thereby, the solid-state imaging device 200 can make the detection accuracy of the flicker phenomenon in the plurality of address event detection units 4 connected to one flicker detection circuit 5 approximately the same.

＜Operation example of flicker detection circuit＞ Next, referring to FIG. 5 and using FIG. 6 and FIG. 7, the operation of the flicker detection circuit 5 of this embodiment will be described. FIG. 6 is a diagram showing an example of a timing chart when the flicker detection circuit 5 detects flicker. FIG. 7 is a diagram showing an example of a timing chart when the flicker detection circuit 5 does not detect flicker. The left side in FIG. 6 and FIG. 7 shows the timing diagram, and the right side in FIG. 6 and FIG. 7 schematically shows the pixel block PB of this example.

As shown in FIG. 6 and the right side in FIG. 7, in this example, the pixel block PB is composed of 16 pixels P1 to P16 arranged in 4 columns and 4 rows. In FIGS. 6 and 7, for 16 pixels P, subscripts are marked from left to right and top to bottom in FIGS. 6 and 7. In addition, in FIGS. 6 and 7, for easy understanding, the pixels P arranged at the corners of the pixel block PB are marked with symbols "P1", "P4", "P13", and "P16". Furthermore, in this example, a flicker detection circuit 5 is provided in the pixel P6 constituting the pixel block PB. Therefore, the pixel P6 is a pixel that is not useful for imaging. In FIGS. 6 and 7, for the convenience of description, the pixel P1 is set as the pixel P shown in the upper row in FIG. 5, and the pixel P16 is set as the pixel P shown in the lower row in FIG. 5.

"Vsf1" shown in FIG. 6 and FIG. 7 represents the voltage of the connection node sf1 (refer to FIG. 5) between one electrode of the individual capacitor C421 of the pixel P1 and one electrode of the addition capacitor C61 of the adding section 6. The "Vsf16" shown in FIG. 6 and FIG. 7 represents the voltage of the connection node sf16 (refer to FIG. 5) between one electrode of the individual capacitor C421 of the pixel P16 and one electrode of the addition capacitor C616 (k=16) of the adding section 6 . The "Vsum" shown in FIG. 6 and FIG. 7 represents the voltage of the connection node of the other electrodes of the addition capacitors C61 to C65 and C67 to C616 of the addition unit 6.

"Vint1" shown in FIGS. 6 and 7 represents the output voltage of the individual subtractor 42 of the pixel P1. "Vint16" shown in FIGS. 6 and 7 represents the output voltage of the individual subtractor 42 of the pixel P16. "Vint_sum" shown in FIG. 6 and FIG. 7 represents the output voltage of the common subtractor 51 of the flicker detection circuit 5 provided in the pixel P6.

The "Vsum_p" shown in FIG. 6 and FIG. 7 represents the voltage at the connection node sum_p (refer to FIG. 5), which is the connection part of the P-type transistor 521 and the N-type transistor 522 constituting the common determination section 52 of the flicker detection circuit 5 . That is, "Vsum_p" represents the voltage of the detection signal (+) output by the common determination unit 52. The "Vsum_n" shown in FIG. 6 and FIG. 7 represents the voltage of the connection node sum_n (refer to FIG. 5), which is the connection part of the P-type transistor 523 and the N-type transistor 524 constituting the common determination part 52 of the flicker detection circuit 5 . That is, "Vsum_n" represents the voltage of the detection signal (-) output by the common determination unit 52. The "Vsum_rst" shown in FIG. 6 and FIG. 7 represents the voltage of the output reset signal output by the area reset generation circuit 53 provided in the flicker detection circuit 5. "XAZ1-5, 7-16" shown in FIG. 6 and FIG. 7 indicate the voltage applied to the gate of the P-type transistor 421 provided in each of the pixels P1 to P5 and P7 to P16. The "XAZ_sum" shown in FIG. 6 and FIG. 7 represents the voltage applied to the gate of the P-type transistor 511 provided in the address event detection unit 4.

The horizontal axis in FIG. 6 and FIG. 7 represents time, and the vertical axis in FIG. 6 and FIG. 7 represents voltage. In Figs. 6 and 7, the passage of time is shown from left to right.

(When flicker is detected) As shown in FIG. 6, at time t1, the photoelectric conversion elements 333 provided in the pixels P1 to P5 and P7 to P16 respectively detect light changes based on the flicker phenomenon. As a result, the output voltage of the current-voltage conversion unit 41 starts to rise, so the voltages Vsf1 and Vsf16 connecting the nodes sf1 and sf16 start to rise. Although the drawing is omitted, the voltages Vsf2 to Vsf5 and Vsf7 to Vsf15 connecting the nodes sf2 to sf5 and sf7 to sf15 also start to rise. Furthermore, the voltage Vsum of the connection node sum in the adding unit 6 also starts to rise. The voltage Vsum connected to the node sum is a voltage obtained by adding the voltages Vsf1 to Vsf5 and Vsf7 to Vsf16 of the connection nodes sf1 to sf5 and sf7 to sf16. Therefore, the rate of increase of the voltage Vsum is higher than the voltages Vsf1 to Vsf5 and Vsf7 to Vsf16.

On the other hand, the output voltage Vint1 of the individual subtractor 42 provided in the pixel P1 decreases as the voltage Vsf1 increases. In addition, the output voltage Vint16 of the individual subtractor 42 provided in the pixel P16 decreases as the voltage Vsf16 increases. The output voltage Vint1 of the individual subtractor 42 provided in the pixel P16 decreases as the voltage Vsf1 increases. Although the drawing is omitted, the output voltages Vint2 to Vint5 and Vint7 to Vint15 of the individual subtractors 42 provided in the pixels P2 to P5 and P7 to P15 also decrease as the voltages Vsf2 to Vsf5 and Vsf7 to Vsf15 increase. Furthermore, as the voltage Vsum of the connection node sum in the adding unit 6 increases, the output voltage Vint_sum of the common subtractor 51 also begins to decrease. The reduction rate of the voltage Vint_sum is higher than the voltages Vint1～Vint5 and Vint7～Vint16.

At time t2 after a certain time has passed from time t1, the output voltage Vint_sum of the common subtractor 51 exceeds (below) the lower threshold Vlow. Thereby, at time t2, the voltage Vsum_p of the detection signal (+) of the common determination unit 52 is switched from a low level to a high level.

The area reset generating circuit 53 switches the voltage level of the voltage Vsum_n of the detection signal (-) to a high level, and switches the voltage level of the output reset signal Vsum_rst from the high level to the low level. Thereby, for the control signals XAZ1-5, 7-16 that the gate input voltage level of each P-type transistor 421 provided in the pixels P1～P5, P7-P16 is low, the P-type transistor 421 is turned on status. In addition, in synchronization with the switching of the voltage level of the output reset signal Vsum_rst, the voltage level applied to the gate of each N-type transistor 423 arranged in the pixels P1～P5, P7-P16 is a high-level voltage Vbdiff, N-type Transistor 423 is turned on. As a result, the individual capacitors C421 provided in the pixels P1 to P5 and P7 to P16 are applied based on the output voltages Vsf1 to Vsf5, Vsf7 to Vsf16 of the current-voltage conversion unit 41 at time t2 and the potential of the ground terminal (for example, 0 V) The voltage of the potential difference. The output voltage Vint of the individual subtractor 42 rises based on the voltage applied to the individual capacitor C421.

In this manner, if the flicker detection circuit 5 detects flicker, the output voltage of the individual subtractor 42 is fixed to a constant value. Thereby, the detection signal (+) of the quantizer 43 is fixed at a high level, and the detection signal (-) of the quantizer 43 is fixed at a low level. As a result, even if the photoelectric conversion element 333 detects the change of light based on the flicker phenomenon, the solid-state imaging element 200 can prevent the address event detection unit 4 from detecting the address event caused by the flicker phenomenon.

At time t3 when a specific time has elapsed since time t2, the control signal XAZ_sum whose gate voltage level of the P-type transistor 511 provided in the common subtractor 51 is input to the low-level control signal XAZ_sum, the P-type transistor 511 is turned on. In addition, in synchronization with the switching of the voltage level of the control signal XAZ_sum, a high-level voltage Vbdiff is applied to the gate of the N-type transistor 513 provided in the common subtractor 51, and the N-type transistor 513 is turned on. . As a result, the capacitor C511 provided in the common subtractor 51 is applied with a voltage based on the potential difference between the potential of the voltage Vsum of the connection node sum of the adding section 6 at time t3 and the potential (for example, 0 V) of the ground terminal. The output voltage Vint_sum of the common subtractor 51 rises based on the voltage applied to the capacitor C511.

At time t4 when a specific time has passed since time t3, the voltage level of the output reset signal Vsum_rst is switched from low level to high level, and the voltage level of the voltage Vbdiff applied to the gate of N-type transistor 423 is switched from high level For the low level. As a result, the address event detection unit 4 becomes a state capable of detecting events. Furthermore, at time t4, the voltage level of the control signal XAZ_sum is switched from a low level to a high level, and the voltage level of the voltage Vbdiff applied to the gate of the N-type transistor 513 is switched from a low level to a high level. Thereby, the flicker detection circuit 5 becomes a state capable of detecting flicker.

(When flicker is not detected) As shown in FIG. 7, at time t1, the photoelectric conversion element 333 provided in the pixel P1 detects the change of light based on the movement of a specific object, etc., and the other pixels P2 to P5 and P7 to P16 do not detect the change of light. As a result, the output voltage of the current-voltage conversion section 41 provided in the pixel P1 starts to rise, and therefore the voltage Vsf1 of the connection node sf1 starts to rise. On the other hand, the voltages Vsf2 to Vsf5 and Vsf7-Vsf16 of the connection nodes sf2 to sf5 and sf7 to sf16 in the other pixels P2 to P5 and P7 to P16 (voltages Vsf2 to Vsf5, Vsf7 to Vsf15 are not shown) hardly rise. Since the voltage Vsf1 of the connection node sf1 rises, the voltage Vsum of the connection node sum of the adding unit 6 starts to rise. However, the voltage value of the voltage applied to the addition capacitor C61 of the addition section 6 connected to the individual capacitor C421 of the pixel P is smaller than the voltage Vsf1 of the connection node sf1. Therefore, the rate of increase of the voltage Vsum of the connection node sum of the adding unit 6 is lower than the rate of increase of the voltage Vsf1 of the connection node sf1.

At time t2 after a specific time has elapsed from time t1, the output voltage of the current-to-voltage conversion section 41 provided in the pixel P1 (ie, the voltage Vsf1 connected to the node sf1) exceeds (below) the N type applied to the quantizer 43 The lower threshold Vlow of the gate of the transistor 434. Thereby, at time t2, the control signal XAZ1 whose voltage level is low is applied to the gate of the P-type transistor 421 of the individual subtractor 42 provided in the pixel P1. Furthermore, at time t2, the voltage level of the voltage Vbdiff applied to the gate of the N-type transistor 423 of the individual subtractor 42 provided in the pixel P1 is switched from a low level to a high level.

On the other hand, at time t2, the output voltage Vint_sum of the shared subtractor 51 does not exceed the lower gate threshold Vlow applied to the N-type transistor 524 provided in the shared determination section 52. Thereby, the area reset generating circuit 53 maintains the output reset signal Vsum_rst with the output voltage level at a high level.

Therefore, both the P-type transistor 421 and the N-type transistor 423 are in the on state. As a result, the individual capacitor C421 provided in the pixel P1 is applied with a voltage based on the potential difference between the potential of the output voltage Vsf1 of the current-voltage conversion unit 41 and the potential (for example, 0 V) of the ground terminal at time t2. The output voltage Vint of the individual subtractor 42 rises based on the voltage applied to the individual capacitor C421. On the other hand, the flicker detection circuit 5 continues the standby operation of flicker detection.

In this way, even if the photoelectric conversion element 333 provided in the pixels P1 to P5, P7 to P16 detects a change in light based on the movement of an object, etc., the flicker detection circuit 5 does not determine the change in light as a flicker phenomenon, but continues to detect the flicker Standby action. Thereby, when the photoelectric conversion element 333 detects the change of light due to the movement of an object, the solid-state imaging device 200 can also prevent the flicker detection circuit 5 from detecting the change of light as an address event caused by the flicker phenomenon.

At time t3 when a specific time has passed since time t2, the voltage level of the control signal XAZ1 is switched from low level to high level, and the voltage level of the voltage Vbdiff applied to the gate of the N-type transistor 423 is switched from low level to high level quasi. Thereby, the address event detection unit 4 provided in the pixel P1 can be converted from the output voltage of the current-voltage conversion unit 41 at time t2 (an example of a voltage), minus the current-voltage conversion unit input at a timing different from time t2 The state of 41 output voltage (an example of another voltage).

＜Other configuration examples of flicker detection circuit＞ The solid-state imaging device 200 of this embodiment is configured to set the P-type transistor 421 of the individual subtractor 42 provided in the address event detection section 4 to the ON state when the flicker detection circuit 5 detects the flicker. The detection signal (+) and the detection signal (-) of the quantizer 43 are fixed to a constant voltage. The solid-state imaging element 200 is not limited to this configuration, and it may have other configurations as long as the detection signal (+) and the detection signal (-) of the quantizer 43 can be fixed to a constant voltage.

(Other configuration example 1) The solid-state imaging element 200 of the other configuration example 1 is configured to separate the pixel P where the flicker phenomenon is detected from the other pixels P. For example, the solid-state imaging device 200 may also have a switch between the cathode of the photoelectric conversion element 333 and the gate of the N-type transistor 413 of the logarithmic conversion circuit 41a. The solid-state imaging element 200 can disconnect the photoelectric conversion element 333 from the current-voltage conversion section 41 by setting the switch to the off state. Therefore, the address event detection unit 4 cannot detect the address event based on the flicker phenomenon. As a result, the solid-state imaging device 200 can minimize the influence of the flicker phenomenon.

(Other configuration example 2) The solid-state imaging device 200 of other configuration example 2 may also be used between at least one of the drain of the N-type transistor 411 of the logarithmic conversion circuit 41a and the power terminal, and between the source of the N-type transistor 411 and the cathode of the photoelectric conversion element 333 , Has a switch. Thereby, the power supply to the photoelectric conversion element 333 can be blocked. As a result, the solid-state imaging device 200 can reduce the influence of the pixels P that have detected the flicker phenomenon on the normal pixels P that have not detected the flicker phenomenon. In the case of other configuration example 2, there is no need to provide a switch between the cathode of the photoelectric conversion element 333 and the gate of the N-type transistor 413 as in the other configuration example 1.

(Other configuration example 3) The solid-state imaging element 200 of the other configuration example 3 has a configuration that blocks the output of the current-voltage conversion unit 41. The solid-state imaging device 200 of other configuration example 3 may have a switch between, for example, the connection portion of the P-type transistor 414 and the N-type transistor 413 (the output portion of the current-voltage conversion portion 41) and one electrode of the individual capacitor C421. In addition, the solid-state imaging device 200 of other configuration example 3 may also have a switch between the drain of the P-type transistor 414 and the drain of the N-type transistor 413. In addition, the solid-state imaging device 200 of other configuration example 3 may have both of these switches. In another configuration example 3, these switches may be formed on the detection wafer 202 (see FIG. 2) instead of the light-receiving wafer 201. Therefore, the solid-state imaging element 200 of another configuration example 3 can improve the degree of design freedom.

(Other configuration example 4) The solid-state imaging element 200 of the other configuration example 4 has a configuration that blocks the individual subtractor 42. The solid-state imaging device 200 of other configuration example 4 may also have a switch between the other electrode of the individual capacitor C421 and the source of the P-type transistor 421, for example. In the other configuration example 4, similar to the other configuration example 3, the switch may be formed on the detection wafer 202 instead of the light receiving wafer 201. Therefore, the solid-state imaging element 200 of the other configuration example 4 can improve the degree of design freedom.

(Other configuration example 5) The solid-state imaging element 200 of other configuration example 5 can also be used between the connection part and the transmission part of the P-type transistor 431 and the N-type transistor 432 of the quantizer 43, and the P-type transistor 433 and N-type of the quantizer 43 Each of the connection part and the transmission part of the transistor 434 has a switch. Thereby, the detection signal (+) and the detection signal (-) output by the quantizer 43 are not transmitted to the transmission unit. Thereby, the address event detection unit 4 of the other configuration example 5 can only block the digital notification function. As a result, the solid-state imaging element 200 of the other configuration example 5 can minimize the influence on the operation of the normal pixel P.

(Other configuration example 6) The solid-state imaging device 200 of the other configuration example 6 has a configuration in which the pixels P are short-circuited. The solid-state imaging device 200 of other configuration example 6 may have a switch between the cathode of the photoelectric conversion element 333 and the ground terminal, for example. Thereby, the cathode and anode of the photoelectric conversion element 333 are at the same potential, and even if the photoelectric conversion element 333 receives light, no current is output to the current-voltage conversion unit 41. As a result, the solid-state imaging device 200 of the other configuration example 6 can eliminate the influence of the pixel P whose flicker phenomenon has been detected on the normal pixel P to the maximum.

(Other configuration example 7) The solid-state imaging device 200 of other configuration example 7 has a configuration in which the voltage value of the output voltage of the current-voltage conversion unit 41 is set to a constant value. The solid-state imaging element 200 of other configuration example 7 may have a switch between the output terminal and the ground terminal of the logarithmic conversion circuit 41a, for example. By setting the output terminal of the logarithmic conversion circuit 41a to the potential of the ground terminal (for example, 0 V), the logarithmic value of the output voltage of the logarithmic conversion circuit 41a becomes zero. As a result, the solid-state imaging element 200 of the other configuration example 7 can minimize the influence on the operation of the normal pixel P. In the case of other configuration example 7, there is no need to provide a switch between the cathode of the photoelectric conversion element 333 and the gate of the N-type transistor 413 as in the other configuration example 1.

(Other configuration example 8) The solid-state imaging element 200 of other configuration example 8 may have a switch between the output terminal of the current-voltage conversion section 41 (the output terminal of the buffer circuit 41b) and the ground terminal. Thereby, since the voltage input to the individual subtractor 42 is fixed at 0 V, for example, the detection signal (+) and the detection signal (-) of the quantizer 43 are constant values. Therefore, even if the photoelectric conversion element 333 detects light based on the flicker phenomenon, the solid-state imaging element 200 can prevent the address event detecting unit 4 from detecting an address event. In the other configuration example 8, similar to the other configuration example 3, the switch may be formed on the detection wafer 202 instead of the light receiving wafer 201. Therefore, the solid-state imaging element 200 of another configuration example 8 can improve the degree of design freedom.

(Other configuration example 9) The solid-state imaging device 200 of the other configuration example 9 is configured such that the P-type transistor 421 provided in the individual subtractor 42 can be continuously turned off. The solid-state imaging device 200 of the other configuration example 9 is controlled by the digital control that can switch the on and off of the P-type transistor 421, so that the influence on the operation of the normal pixel P can be suppressed to a minimum. In addition, the current fluctuation of the individual subtractor 42 can be suppressed. Therefore, the solid-state imaging element 200 of the other configuration example 9 can suppress the power noise of the pixel P caused by the detection of the flicker phenomenon.

(Other configuration example 10) The solid-state imaging element 200 of other configuration example 10 can also be used between the connection portion of the P-type transistor 431 and the N-type transistor 432 of the quantizer 43 and the power terminal, and the P-type transistor 433 and N-type of the quantizer 43 Each of the connecting portion of the transistor 434 and the ground terminal has a switch. Thereby, the solid-state imaging device 200 of other configuration example 10 can short-circuit the connection part of the P-type transistor 431 and the N-type transistor 432 of the quantizer 43 and the power terminal, thereby connecting the P-type transistor 433 and the P-type transistor 433 of the quantizer 43. The connection part of the N-type transistor 434 is short-circuited with the ground terminal. Therefore, the detection signal (+) output by the quantizer 43 is a signal whose voltage level is high, and the detection signal (-) output by the quantizer 43 becomes a signal whose voltage level is low. As a result, the solid-state imaging element 200 of the other configuration example 10 is that even if the photoelectric conversion element 333 detects light based on the flicker phenomenon, the detection signal (+) and detection signal (-) output by the address event detection unit 4 are also undetected A signal with the same voltage level as the situation of the address event. Thereby, the address event detection unit 4 of the other configuration example 10 can only block the digital notification function. As a result, the solid-state imaging device 200 of the other configuration example 10 can minimize the influence on the operation of the normal pixel P.

[Embodiment 1-2] Next, the solid-state imaging device according to Embodiment 1-2 of the present disclosure will be described using FIGS. 8 and 9. The solid-state imaging device 200 of this embodiment is characterized in that the quantizer 43 is stopped when the flicker detection circuit 5 detects flicker. FIG. 8 is a circuit diagram showing an example of the configuration of the address event detection unit 4 and the flicker detection circuit 5 provided in the solid-state imaging device 200 of this embodiment. In FIG. 8, the illustration of the pixel signal generating portion 320, the transmission transistor 331 and the OFG transistor 332 provided in the pixel P is omitted. 9 is a circuit diagram showing a configuration example of one of the stop circuits 45a and 45b for stopping the quantizer 43 when the flicker detection circuit 5 detects the flicker.

As shown in FIG. 8, the address event detection unit 4 provided in the solid-state imaging device 200 of this embodiment has stop circuits 45a and 45b connected to the common determination unit 52 provided in the flicker detection circuit 5. The stop circuit 45a is connected to the connection part of the P-type transistor 521 and the N-type transistor 522 of the common determination part 52. The stop circuit 45b is connected to the connection part of the P-type transistor 523 and the N-type transistor 524 of the common determination part 52. The stop circuit 45a is configured to operate based on the detection signal (+) input from the common determination unit 52. The stop circuit 45b is configured to operate based on the detection signal (-) input from the common determination unit 52.

Next, the specific configuration of the stop circuits 45a and 45b will be described using FIG. 9. As shown in FIG. 9, the stop circuit 45 a is provided between the P-type transistor 431 and the N-type transistor 432 provided in the quantizer 43. The stop circuit 45a has a P-type transistor 451a and an N-type transistor 452a. The gate of the P-type transistor 451a and the gate of the N-type transistor 452a are connected. The gate of the P-type transistor 451a and the gate of the N-type transistor 452a are connected to the connecting portion of the P-type transistor 521 and the N-type transistor 522 of the common determination portion 52. Thereby, the detection signal (+) input from the common determination unit 52 is applied to the gate of the P-type transistor 451a and the gate of the N-type transistor 452a.

The source of the P-type transistor 451a is connected to the power terminal. The drain of the P-type transistor 451a is connected to the drain of the N-type transistor 432 provided in the quantizer 43. The N-type transistor 452a is disposed between the P-type transistor 431 and the N-type transistor 432. The P-type transistor 431, the N-type transistor 452a, and the N-type transistor 432 are connected in series between the power terminal and the ground terminal.

As shown in FIG. 9, the stop circuit 45 b is provided between the P-type transistor 433 and the N-type transistor 434 provided in the quantizer 43. The stop circuit 45b has an N-type transistor 451b and a P-type transistor 452b. The gate of the N-type transistor 451b and the gate of the P-type transistor 452b are connected. The gate of the N-type transistor 451b and the gate of the P-type transistor 452b are connected to the connecting portion of the P-type transistor 523 and the N-type transistor 524 of the common determination portion 52. Thereby, the detection signal (-) input from the common determination unit 52 is applied to the gate of the N-type transistor 451b and the gate of the P-type transistor 452b.

The source of the N-type transistor 451b is connected to the ground terminal. The drain of the N-type transistor 451 b is connected to the drain of the N-type transistor 432 provided in the quantizer 43. The P-type transistor 452b is disposed between the P-type transistor 433 and the N-type transistor 434. The P-type transistor 433, the P-type transistor 452b, and the N-type transistor 434 are connected in series between the power terminal and the ground terminal.

Next, the operation of the stop circuits 45a and 45b will be described. When the flicker detection circuit 5 does not detect the flicker, the voltage level of the detection signal (+) output from the quantizer 43 is a high level. Therefore, the P-type transistor 451a provided in the stop circuit 45a is in an off state. On the other hand, the N-type transistor 452a provided in the stop circuit 45a is in the ON state. Therefore, the P-type transistor 431 and the N-type transistor 432 provided in the quantizer 43 are connected via the N-type transistor 452a.

In addition, when the flicker detection circuit 5 does not detect the flicker, the potential level of the detection signal (-) output from the quantizer 43 is a low level. Therefore, the N-type transistor 451b provided in the stop circuit 45a is turned off. On the other hand, the P-type transistor 452b provided in the stop circuit 45b is in the ON state. Therefore, the P-type transistor 433 and the N-type transistor 434 provided in the quantizer 43 are connected via the P-type transistor 452b.

When the flicker detection circuit 5 does not detect flicker, since the quantizer 43 has a circuit configuration equivalent to that without the stop circuits 45a and 45b, it can output a detection signal based on the voltage input from the individual subtractor 42 (+) And the detection signal (-).

On the other hand, when the flicker detection circuit 5 detects the flicker and the output voltage of the common determination unit 52 is higher than the upper threshold Vhigh, the voltage level of the detection signal (+) output from the quantizer 43 is a low level. Therefore, the P-type transistor 451a provided in the stop circuit 45a is turned on. On the other hand, the N-type transistor 452a provided in the stop circuit 45a is in an off state. Therefore, the P-type transistor 431 and the N-type transistor 432 provided in the quantizer 43 are cut off (disconnected) by the N-type transistor 452a. In addition, the drain of the N-type transistor 432 corresponding to the output terminal of the quantizer 43 is connected to the power terminal via the P-type transistor 451a. Thereby, the voltage of the detection signal (+) output by the quantizer 43 is fixed at a high level.

When the flicker detection circuit 5 detects the flicker and the output voltage of the common determination unit 52 is lower than the lower threshold value Vlow, the voltage level of the detection signal (-) output from the quantizer 43 is a high level. Therefore, the N-type transistor 451b provided in the stop circuit 45b is turned on. On the other hand, the P-type transistor 452b provided in the stop circuit 45b is in an off state. Therefore, the P-type transistor 433 and the N-type transistor 434 provided in the quantizer 43 are cut off (disconnected) by the P-type transistor 452b. In addition, the drain of the N-type transistor 434 corresponding to the output terminal of the quantizer 43 is connected to the ground terminal via the N-type transistor 451b. Thereby, the detection signal (-) output by the quantizer 43 is fixed at a low level.

When the flicker detection circuit 5 detects the flicker, the quantizer 43 cuts off (disconnects) the P-type transistors 431 and 433 and the N-type transistors 432 and 433 to be in a stopped state.

[Embodiment 1-3] Next, the solid-state imaging device according to Embodiments 1-3 of the present disclosure will be described using FIG. 10. The solid-state imaging device 200 of the present embodiment is characterized in that when the flicker detection circuit 5 detects flicker, the output terminal of the quantizer 43 is cut off from the transmission section. FIG. 10 is a circuit diagram showing a configuration example of the address event detection unit 4 and the flicker detection circuit 5 provided in the solid-state imaging device 200 of this embodiment. In FIG. 10, the illustration of the pixel signal generating portion 320, the transmission transistor 331 and the OFG transistor 332 provided in the pixel P is omitted.

As shown in FIG. 10, the solid-state imaging device 200 of this embodiment has switch circuits 54a and 54b connected between the output terminal of the quantizer 43 provided in the address event detection unit 4 and a transmission unit (not shown). The switch circuit 54a is arranged between the output terminal that outputs the detection signal (+) of the quantizer 43 and the transmission part. The switch circuit 54b is disposed between the output terminal that outputs the detection signal (-) of the quantizer 43 and the transmission part.

The control signal input terminals of the switch circuits 54a and 54b are connected to the output terminal of the common determination unit 52 provided in the flicker detection circuit 5. More specifically, the control signal input terminal of the switch circuit 54 a is connected to the connection part of the P-type transistor 521 and the N-type transistor 522 provided in the common determination part 52. The control signal input terminal of the switch circuit 54b is connected to the connection part of the P-type transistor 523 and the N-type transistor 524 provided in the common determination part 52.

The switch circuit 54a becomes a closed state (on state) when a control signal with a high voltage level is input to the control signal input terminal, and when a control signal with a low voltage level is input to the control signal input terminal, Be in the open state (disconnected state). The switch circuit 54b becomes a closed state (on state) when a control signal with a low voltage level is input to the control signal input terminal, and when a control signal with a high voltage level is input to the control signal input terminal, Be in the open state (disconnected state).

When the flicker detection circuit 5 does not detect the flicker, the voltage level of the detection signal (+) output from the quantizer 43 is high, and the voltage level of the detection signal (-) output from the quantizer 43 is low quasi. Therefore, the switch circuits 54a and 54b are in the closed state (on state). Thereby, when the flicker is not detected by the flicker detection circuit 5, the detection signal (+) and the detection signal (-) output from the quantizer 43 are input to the transmission unit.

On the other hand, when the flicker detection circuit 5 detects the flicker and the output voltage of the common determination unit 52 is higher than the upper threshold Vhigh, the voltage level of the detection signal (+) output from the quantizer 43 is a low level. Therefore, the switch circuit 54a is in the open state (off state). Thereby, when the flicker detection circuit 5 detects the flicker and the output voltage of the common determination unit 52 is higher than the upper threshold Vhigh, the detection signal (+) output from the quantizer 43 is not input to the transmission unit.

When the flicker detection circuit 5 detects the flicker and the output voltage of the common determination unit 52 is lower than the upper threshold value Vlow, the voltage level of the detection signal (-) output from the quantizer 43 is a high level. Therefore, the switch circuit 54a becomes the open state (off state). Thereby, when the flicker detection circuit 5 detects flicker, and the output voltage of the common determination unit 52 is lower than the upper threshold value Vlow, the detection signal (-) output from the quantizer 43 is not input to the transmission unit.

In this way, when the solid-state imaging device 200 of the present embodiment detects flicker from the flicker detector circuit 5, it can be prevented so as not to input the output voltage of the address detection unit 4 to the transmission unit. In this way, the solid-state imaging device 200 can prevent the detection of address events based on the flicker phenomenon.

[Embodiment 1-4] Next, the solid-state imaging device according to Embodiments 1-4 of the present disclosure will be described using FIGS. 11 and 12. The solid-state imaging device 200 of this embodiment is characterized by having a configuration in which capacitors corresponding to the addition capacitors of the addition section are dispersed in each pixel. FIG. 11 is a diagram schematically showing the pixel block PB provided in the solid-state imaging device 200 of this embodiment. FIG. 12 is a circuit diagram showing a configuration example of the address event detection section 4 and the flicker detection circuit 5 provided in the solid-state imaging device 200 of this embodiment. In FIG. 12, the illustration of the pixel signal generating part 320, the transmission transistor 331, and the OFG transistor 332 provided in the pixel P is omitted.

As shown in FIG. 11, in this embodiment, the pixel block PB is composed of, for example, 64 pixels P1 to P64 arranged in 8 columns and 8 rows. In FIG. 11, for 64 pixels P, subscripts are marked from left to right and from top to bottom in FIG. 11. In addition, in FIG. 11, for easy understanding, the pixels P arranged at the corners of the pixel block PB are denoted with symbols "P1", "P4", "P57", and "P64". In addition, the details are described below, but in this embodiment, the flicker detection circuit 5 is provided in the pixel P37 constituting the pixel block PB. Therefore, the pixel P37 becomes a pixel that is not useful for the detection of camera and address events.

As shown in FIG. 12, the pixel (hereinafter referred to as "normal pixel") P without the flicker detection circuit 5 is different from the pixel P of the above-mentioned first embodiment 1-1 in that it has a small capacitor C45 and Reset circuit 46 in the pixel.

As shown in FIG. 12, the address event detection unit 4 provided in the pixel P64 corresponding to a normal pixel has a current-voltage conversion unit 41 having the same configuration as the current-voltage conversion unit 41 of the above-mentioned first embodiment. In addition, the address event detection unit 4 provided in the pixel P64 has an individual subtractor 42 having the same configuration as the individual subtractor 42 of the 1-1 embodiment described above. In addition, the address event detection unit 4 provided in the pixel P64 has a quantizer 43 having the same configuration as the quantizer 43 of the above-mentioned Embodiment 1-1.

The address event detection unit 4 provided in the pixel P64 has a small capacitor C45, which has an electrode connected to one electrode of the individual capacitor C421 and the other electrode arranged opposite to the one electrode, and has a smaller capacitance than the individual capacitor C421. The small capacitor C45 performs the same function as the addition capacitor provided in the addition section 6 in the above-mentioned first embodiment.

As shown in FIG. 12, the solid-state imaging device 200 includes an in-pixel reset circuit 46 provided in the pixel P64. The reset circuit 46 in the pixel is formed of, for example, an OR gate. The in-pixel reset circuit 46 is configured to control the voltage level obtained by logically adding the output reset signal RST_FL and the arbiter reset signal RST_AR of the area reset generating circuit 53 (details are described below) provided in the flicker detection circuit 5 The signal is output to the gate of the P-type transistor 421. The arbiter reset signal RST_AR is the reset signal output by the arbiter 213 (refer to FIG. 3).

When the address event detection unit 4 performs a normal operation, the in-pixel reset circuit 46 outputs the control signal dependent on the arbiter reset signal RST_AR to the gate of the P-type transistor 421. On the other hand, when the flicker detection circuit 5 detects the flicker, the pixel reset circuit 46 outputs the control signal dependent on the output reset signal RST_FL output from the area reset generation circuit 55 to the P-type transistor 421 Gate. Thereby, the P-type transistor 421 is controlled by the arbiter 213 when the flicker is not detected by the flicker detection circuit 5, and is controlled by the flicker detection circuit 5 when the flicker detection circuit 5 detects the flicker.

Although the drawing is omitted in FIG. 12, the pixels P1 to P36 and P38 to P65 constituting the pixel block PB have the same configuration as the pixel P64 and perform the same function. Therefore, the pixels P1 to P36 and P38 to P64 correspond to an example of a plurality of individual pixels each having a photoelectric conversion element 333, a current-voltage conversion unit 41, and an individual subtractor 42.

As shown in FIG. 12, the pixel (hereinafter referred to as "flicker monitoring pixel") P37 provided with the flicker detection circuit 5 has substantially the same structure as the pixels P1 to P36 and P38 to P65 of normal pixels. That is, the pixel P37 corresponds to an example of a common pixel having a common subtractor (an example of a common subtractor) 51 provided in the flicker detection circuit 5. In addition, the pixel block PB is equivalent to an example of a pixel block having a common pixel and a plurality of individual pixels.

The pixel P37, which is the flicker monitoring pixel, is provided with a photoelectric conversion element 333 that performs photoelectric conversion on incident light to generate current. In addition, the pixel P37 is provided with a current-to-voltage conversion unit 56 connected to the photoelectric conversion element 333 and converts the current input from the photoelectric conversion element 333 into a voltage. The current-voltage conversion unit 56 has a logarithmic conversion circuit 56a and a buffer circuit 56b. The current-voltage conversion unit 56 is configured to convert the current (photocurrent) input from the photoelectric conversion element 333 into a logarithmic output voltage value in the logarithmic conversion circuit 56a. The buffer circuit 56b has a source follow-up configuration, and is configured to perform impedance conversion.

As shown in FIG. 12, the logarithmic conversion circuit 56a constituting the current-voltage conversion unit 56 has an N-type transistor 561, an N-type transistor 563, a P-type transistor 562, and a capacitor C56. As these transistors, for example, MOS transistors can be used.

The source of the N-type transistor 561 is connected to the cathode of the photoelectric conversion element 333. The drain of the N-type transistor 561 is connected to a power terminal (not shown). The P-type transistor 562 and the N-type transistor 563 are connected in series between the power terminal and the ground terminal. In addition, the connection point of the P-type transistor 562 and the N-type transistor 563 is connected to the gate of the N-type transistor 561 and the input terminal of the buffer circuit 56b. In addition, a specific bias voltage Vblog is applied to the gate of the P-type transistor 562.

The gate of the N-type transistor 563 is connected to the cathode of the photoelectric conversion element 333 and the source of the N-type transistor 561. One electrode of the capacitor C56 is connected to the gate of the N-type transistor 563 and the connection point of the P-type transistor 562 and the N-type transistor 563. The other electrode of the capacitor C56 is connected to the cathode of the photoelectric conversion element 333 and the gate of the N-type transistor 563.

The drains of the N-type transistors 561 and 563 are connected to the power supply side. This type of circuit is called a source follower. The two source followers connected in a ring shape convert the photocurrent input from the light receiving unit 330 into its logarithmic voltage signal. In addition, the P-type transistor 562 supplies a constant current to the N-type transistor 563. The capacitor C56 is provided to stabilize the gate voltage of each of the N-type transistor 561 and the N-type transistor 563. The logarithmic conversion circuit 56a may not have the capacitor C56.

As shown in FIG. 13, the buffer circuit 56b has a P-type transistor 564 and a P-type transistor 565. As these transistors, for example, MOS transistors can be used. The P-type transistor 564 and the P-type transistor 565 are connected in series between the power terminal and the ground terminal. The gate of the P-type transistor 565 is connected to the output terminal of the logarithmic conversion circuit 56a (the connection point of the P-type transistor 562 and the N-type transistor 563). The connection point of the P-type transistor 564 and the P-type transistor 565 is connected to the input terminal of the common subtractor 51. In addition, a specific bias voltage Vbsf is applied to the gate of the P-type transistor 564.

As shown in FIG. 12, a common subtractor (an example of a common subtractor) 51 is provided in the pixel P37, which is connected to the current-voltage conversion section 56, and the free current-voltage conversion section 56 receives input from the current-voltage conversion section 56 at different timings. One voltage, minus the other voltage. The shared subtractor 51 of the present embodiment has the same structure as the shared subtractor 51 of the above-mentioned 1-1 embodiment except for the point of having a dedicated capacitor C512.

The common subtractor 51 has a dedicated capacitor C512, which has one electrode and another electrode arranged opposite to the one electrode and connected to the other electrode of the small capacitor C45, and has a smaller capacitance than the individual capacitor C421. The dedicated capacitor C512 is provided in a flicker monitoring pixel (pixel P37) that is different from the individual pixels (pixels P1 and P45 in FIG. 14). The dedicated capacitor C512 is a dedicated capacitor for flicker monitoring of the flicker monitoring pixel (pixel P37). The dedicated capacitor C512 has, for example, the same capacitance as the small capacitor C45. The dedicated capacitor C512 is connected to the small capacitor C45 by wiring FLcom. Although the small capacitor C45 is provided in a pixel different from the common subtractor 51, it functionally constitutes a part of the common subtractor 51.

The sharing determination unit 52 provided in the pixel P37 has the same configuration as the sharing determination unit 52 of the above-mentioned Embodiment 1-1, and performs the same function. In this way, the pixel P37 is provided with the photoelectric conversion element 333, the current-voltage conversion unit 56, the common subtractor 51, and the common determination unit 52. However, since the capacitance of the dedicated capacitor C512 is small, the pixel P37 cannot detect address events based on the movement of an object.

The flicker detection circuit 5 provided in the pixel P37 has a common determination section 52 that determines whether the difference between the first voltage and the second voltage based on the subtraction result of the common subtractor 51 exceeds the upper threshold Vhigh or the lower threshold Vlow (both are specific thresholds) One example). The flicker detection circuit 5 provided in the pixel P37 has an area reset generation circuit (an example of the reset section) 55, which is determined by the common determination section 52 that the difference in voltage based on the subtraction result of the common subtractor 51 exceeds the upper limit threshold Vhigh( Or in the case of the lower threshold value Vlow), the operation of at least any one of the plurality of photoelectric conversion elements 333, the plurality of current-voltage conversion units 41, and the plurality of individual subtractors 42 is reset.

As shown in FIG. 12, the area reset generating circuit 55 is constituted by, for example, an OR gate. The input terminal of the area reset generating circuit 55 is connected to the connection part of the P-type transistor 521 and the N-type transistor 522 of the common determination part 52. The negative input terminal of the area reset generating circuit 55 is connected to the connection part of the P-type transistor 523 and the N-type transistor 524 of the common determination part 52. Thereby, the detection signal (+) output by the common determination unit 52 is input to the input terminal of the area reset generation circuit 55. On the other hand, a detection signal (-) is input to the negative input terminal of the area reset generating circuit 55.

When the voltage level of the detection signal (+) is at a high level or the voltage level of the detection signal (-) is at a low level, the area reset generating circuit 55 outputs a reset signal RST_FL with the output voltage level at a high level . When the voltage level of the detection signal (+) is at a low level and the voltage level of the detection signal (-) is at a high level, the area reset generating circuit 55 outputs a reset signal RST_FL with the output voltage level at a low level . When the flicker detection circuit 5 does not detect the flicker, the common determination unit 52 outputs the voltage level of the detection signal (+) to a high level, and the voltage level of the detection signal (-) to a low level signal.

Therefore, when the region reset generating circuit 55 does not detect the flicker by the flicker detection circuit 5, the output voltage level is a high level output reset signal RST_FL. Thereby, when the flicker detection circuit 5 does not detect the flicker, the output reset signal RST_FL whose voltage level is high is input to one of the input terminals of the reset circuit 46 in the pixel. As a result, the P-type transistors 421 provided in the pixels P1 to P36 and P38 to P64 are controlled by the arbiter 213. On the other hand, when the area reset generating circuit 55 detects a flicker by the flicker detection circuit 5, the output voltage level is a low level output reset signal RST_FL. Therefore, when the flicker detection circuit 5 detects the flicker, it outputs a reset signal RST_FL whose input voltage level is a low level to one of the input terminals of the reset circuit 46 in the pixel. As a result, the P-type transistors 421 provided in the pixels P1 to P36 and P38 to P64 are controlled by the flicker detection circuit 5.

The normal pixels constituting the pixel block PB of the solid-state imaging device 200 of the present embodiment have a small capacitor C45 corresponding to the addition capacitor of the addition section 6 of the above-mentioned 1-1 embodiment. In addition, the other electrode of the small capacitor C45 provided in each of the normal pixels constituting the pixel block PB is connected to each other and connected to the gate of the P-type transistor 512 of the common subtractor 51 of the flicker detection circuit 5. Thereby, the solid-state imaging device 200 of this embodiment can obtain the same effects as the solid-state imaging device 200 of the above-mentioned Embodiment 1-1.

[Embodiment 1-5] Next, the solid-state imaging device according to Embodiments 1 to 5 of the present disclosure will be described using FIGS. 13 and 14. The solid-state imaging element 200 of this embodiment is characterized in that the photoelectric conversion element 333 provided in the flicker monitoring pixel and the photoelectric conversion element 333 provided in the normal pixel are connected. FIG. 13 is a diagram schematically showing the pixel block PB provided in the solid-state imaging device 200 of this embodiment. FIG. 14 is a circuit diagram showing a configuration example of the address event detection section 4 and the flicker detection circuit 5 provided in the solid-state imaging device 200 of this embodiment. In FIG. 14, the illustration of the pixel signal generating portion 320, the transmission transistor 331 and the OFG transistor 332 provided in the pixel P is omitted.

As shown in FIG. 13, in this embodiment, the pixel block PB is composed of, for example, 64 pixels P1 to P64 arranged in 8 columns and 8 rows. In FIG. 13, for 64 pixels P, subscripts are marked from left to right and from top to bottom in FIG. In addition, in FIG. 13, for easy understanding, the pixels P arranged at the corners of the pixel block PB are denoted with symbols "P1", "P4", "P57", and "P64". In addition, in this embodiment, similar to the above-mentioned 1-4 embodiments, a flicker detection circuit 5 is provided in the pixel P37 constituting the pixel block PB. Therefore, the pixel P37 becomes a pixel that is not useful for the detection of camera and address events. In this way, the pixel P37 corresponds to an example of a common pixel having a common subtractor (a part of the common subtractor) 51 provided in the flicker detection circuit 5. In addition, the pixel block PB is equivalent to an example of a pixel block having a common pixel and a plurality of individual pixels. Furthermore, the details are described below, but the photoelectric conversion element 333 provided in the pixel P45 constituting the pixel block PB is connected to the photoelectric conversion element 333 provided in the pixel P37.

As shown in FIG. 14, the pixel P37 (an example of a shared pixel) has: a photoelectric conversion element 333 (an example of a shared photoelectric conversion element) that photoelectrically converts incident light to generate current; and a current-voltage conversion section 56 (a common current-voltage conversion An example of part), which converts the current input from the photoelectric conversion element 333 into a voltage, and outputs the voltage to one electrode of the dedicated capacitor C512. The photoelectric conversion element 333 is connected to the photoelectric conversion element 333 of the pixel P45 (an example of one individual pixel) provided in the pixels P1 to P36 and P38 to P64 (an example of a plurality of individual pixels). More specifically, the cathode of the photoelectric conversion element 333 provided in the pixel P37 is connected to the cathode of the photoelectric conversion element 333 provided in the pixel P45.

In this way, by connecting the photoelectric conversion element 333 provided in the flicker monitoring pixel with the photoelectric conversion element 333 provided in the normal pixel, the detection results of all the pixels P constituting the pixel block PB can be obtained. However, the photoelectric conversion element 333 of the pixel P45, which is a normal pixel for PD combining formed by combining the photoelectric conversion elements 333, is affected by the photoelectric conversion element 333 provided in the pixel P37, so it is impossible to output a current based solely on its own action to the current Voltage conversion unit 41.

[Embodiment 1-6] Next, the solid-state imaging device according to Embodiments 1-6 of the present disclosure will be described using FIGS. 15 and 16. The solid-state imaging device 200 of this embodiment is characterized in that the flicker detection circuit 5 is provided in an area different from the area where the pixels are arranged. FIG. 15 is a diagram schematically showing the arrangement relationship between the pixel block PB and the flicker detection circuit 5 provided in the solid-state imaging device 200 of this embodiment. FIG. 16 is a circuit diagram showing a configuration example of the address event detection section 4 and the flicker detection circuit 5 provided in the solid-state imaging device 200 of this embodiment. In FIG. 16, the illustration of the pixel signal generating part 320, the transmission transistor 331 and the OFG transistor 332 provided in the pixel P is omitted.

As shown in FIG. 15, in this embodiment, the pixel block PB is composed of, for example, 256 pixels P1 to P256 arranged in 16 columns and 16 rows. In FIG. 15, for 256 pixels P, subscripts are marked from left to right or top to bottom in FIG. 15. In addition, in FIG. 15, for ease of understanding, the pixels P arranged at the corners of the pixel block PB are denoted with symbols "P1", "P16", "P241", and "P256". In this embodiment, the flicker detection circuit 5 is not provided for the pixels P1 to P256 constituting the pixel block PB. Therefore, all the pixels P1 to P256 constituting the pixel block PB become pixels that contribute to the detection of imaging and address events.

As shown in FIG. 15, the flicker detection circuit 5 is arranged in an area different from the pixel area in which a plurality of pixels P1 to P256 (an example of individual pixels) are arranged. That is, the common subtractor 51 (refer to FIG. 16) provided in the flicker detection circuit 5 is arranged in an area different from the pixel area in which the plurality of pixels P1 to P256 are arranged.

As shown in FIG. 16, the pixels P1 to P256 of this embodiment have the same structure as the pixels P1 to P36 and P38 to P64 of the above-mentioned first to fourth embodiments. In addition, the flicker detection circuit 5 has the same configuration as the flicker detection circuit 5 of the above-mentioned Embodiment 1-1 except for the difference in the area reset generation circuit. The flicker detection circuit 5 of this embodiment has the same configuration as the area reset generation circuit 55 provided in the flicker detection circuit 5 of the first to fourth embodiments.

In this way, even if the flicker detection circuit 5 is arranged in a region different from the pixel region, it can be connected to the small capacitor C45 provided in the pixels P1 to P256 through the wiring FLcom. Thereby, the solid-state imaging device 200 of this embodiment can obtain the same effects as the solid-state imaging device 200 of the aforementioned first to fourth embodiments.

[Embodiment 1-7] Next, the solid-state imaging device of Embodiments 1-7 of the present disclosure will be described using FIG. 17. The solid-state imaging device 200 of the present embodiment is characterized by having pixels that are also used for flicker monitoring. FIG. 17 is a circuit diagram showing a configuration example of the address event detection unit 4 and the flicker detection circuit 5 provided in the solid-state imaging device 200 of this embodiment. In FIG. 17, the illustration of the pixel signal generating part 320, the transmission transistor 331 and the OFG transistor 332 provided in the pixel P is omitted.

As shown in FIG. 17, the solid-state imaging device 200 of this embodiment is provided with a first common switch 57a, in addition to the circuit configuration of the pixel (flicker monitoring circuit) of the flicker detection circuit 5 of the above-mentioned first to fourth embodiments. The second common switch 57b and the large capacitor C57. More specifically, the solid-state imaging device 200 includes a first common switch 57a that is provided to cut off the other electrode of the plurality of small capacitors C45 and the other electrode of the dedicated capacitor C512. In addition, the solid-state imaging element 200 includes a large capacitor C57 connected in parallel with the dedicated capacitor C512 and having a larger capacitance than the dedicated capacitor C512; and a second common switch 57b connected in series to the large capacitor C57 and parallel connected to the dedicated capacitor C512.

The first common switch 57a and the second common switch 57b are configured to be opened and closed by the control signal Mode_ctl. The control signal input terminal of the first common switch 57a is configured as a positive logic terminal, while the control signal input terminal of the second common switch 57b is configured as a negative input terminal. Therefore, the first common switch 57a and the second common switch 57b are in a state where opening and closing are always reversed. That is, if the first common switch 57a is in the open state (off state), the second common switch 57b is in the closed state (on state). On the other hand, if the first common switch 57a is in the closed state (on state), the second common switch 57b is in the on state (off state).

Therefore, to the flicker detection circuit 5, either the small capacitor C45 and the large capacitor C57 are connected. Therefore, in this embodiment, in the flicker detection mode, by setting the first common switch 57a to the on state and the second common switch 57b to the off state, the small capacitors C45 of a plurality of normal pixels Connect to flicker detection circuit 5 to perform flicker detection. After the flicker detection ends, the first common switch 57a is set to the off state, and the second common switch 57b is set to the on state. As a result, since the large capacitor C57 is connected to the common subtractor 51, the profit of the common subtractor 51 is improved. Therefore, the pixel P provided with the flicker detection circuit 5 can also detect the same address event as a normal pixel.

In this way, the solid-state imaging device 200 of the present embodiment can function as a pixel having the flicker detection circuit 5 as a flicker monitoring dual-purpose pixel.

As described above, the solid-state imaging device 200 of Embodiment 1-1 to Embodiment 1-7 includes one flicker detection circuit for every plural pixels. Thereby, the solid-state imaging element 200 of each embodiment can achieve lower power consumption compared with a case where a flicker detection circuit is provided for each pixel.

In addition, the solid-state imaging device 200 of the 1-1 embodiment to the 1-7 embodiment resets the address event detection unit 4 (for example, the individual subtractor 42) before the address event caused by the flicker phenomenon occurs, It can suppress the occurrence of address events caused by flicker.

[Second Embodiment] Next, the solid-state imaging device according to the second embodiment of the present disclosure will be described using FIGS. 18 and 19. The second embodiment is divided into a 2-1 embodiment and a 2-2 embodiment, and two kinds of resolution changing techniques will be described.

[Second Embodiment 2-1] FIG. 18 is a circuit diagram showing a configuration example of a low-resolution address event detection unit provided in the solid-state imaging device 200 of Embodiment 2-1. In addition, in FIG. 18, the illustration of the pixel signal generating portion 320, the transmission transistor 331 and the OFG transistor 332 provided in the pixel P is omitted.

As shown in FIG. 18, the solid-state imaging device 200 of this embodiment has the same features as the solid-state imaging device 200 of the above-mentioned Embodiment 1-1 except that it does not have the area reset generation circuit 53 and the in-pixel reset circuit 44. The composition. In addition, the solid-state imaging device 200 of this embodiment includes a low-resolution system circuit 9, which has the same features as the flicker detection circuit 5 except for the point that the region reset generation circuit 53 of the above-mentioned first embodiment is not connected. constitute.

The solid-state imaging element 200 of this embodiment includes: a plurality of photoelectric conversion elements 333, which respectively perform photoelectric conversion on incident light to generate current; and a plurality of current-voltage conversion sections 41, which are connected to the plurality of photoelectric conversion sections 333 one by one Each of them converts the current input from the photoelectric conversion element 333 into a voltage. In addition, the solid-state imaging element 200 includes a common subtractor (an example of a common subtractor) 91, which is connected to a plurality of current-voltage conversion sections 41, and is based on a voltage input from each of the current-voltage conversion sections 41 at different timings. The first voltage is subtracted from the second voltage based on another voltage.

In addition, the solid-state imaging element 200 includes a common determination unit 92 that determines whether the difference between the first voltage and the second voltage based on the subtraction result of the common subtractor 91 exceeds the upper limit threshold Vhigh or the lower limit threshold Vlow (both are examples of specific thresholds) . Furthermore, the solid-state imaging device 200 includes an addition unit 6 that adds the voltages output from each of the plurality of current-voltage conversion units 41. The common subtractor 91 is configured to add one of the added voltages, that is, the first voltage, from the addition unit 6 and input at different timings, and subtract the other added voltage, that is, the second voltage.

As shown in FIG. 18, the common subtractor 91 has a P-type transistor 911, a P-type transistor 912, an N-type transistor 913, and a capacitor C911. As these transistors, for example, MOS transistors can be used.

The P-type transistor 912 and the N-type transistor 913 are connected in series between the power terminal and the ground terminal. The connection part of the P-type transistor 912 and the N-type transistor 913 is connected to the input terminal of the common determination part 92. A specific bias voltage Vbdiff is applied to the gate of the N-type transistor 913.

The source of the P-type transistor 911 is connected to the gate of the P-type transistor 912. The drain of the P-type transistor 911 is connected to the connection part of the P-type transistor 912 and the N-type transistor 913.

One electrode of the capacitor C911 is connected to the source of the P-type transistor 911 and the gate of the P-type transistor 912. The other electrode of the capacitor C911 is connected to the connecting portion of the P-type transistor 912 and the N-type transistor 913 and the drain of the P-type transistor 911. Since the operation of the common subtractor 91 is the same as that of the individual subtractor 42, the description is omitted.

As shown in FIG. 18, the common determination unit 92 is constituted by a quantizer. The common determination unit 92 has a P-type transistor 921, an N-type transistor 922, a P-type transistor 923, and an N-type transistor 924. As these transistors, for example, MOS transistors can be used.

The P-type transistor 921 and the N-type transistor 922 are connected in series between the power terminal and the ground terminal. The P-type transistor 923 and the N-type transistor 924 are connected in series between the power terminal and the ground terminal. The gate of the P-type transistor 921 and the gate of the P-type transistor 923 are connected to the output terminal of the common subtractor 91 (the connecting portion of the P-type transistor 912 and the N-type transistor 913). The voltage level applied to the gate of the N-type transistor 922 is the upper threshold Vhigh of the high-level voltage. The voltage level applied to the gate of the N-type transistor 924 is the lower voltage threshold Vlow of the low level. The connection part of the P-type transistor 921 and the N-type transistor 922 is the output terminal of the detection signal (+). The connection part of the P-type transistor 923 and the N-type transistor 924 is the output terminal of the detection signal (-).

When the voltage value of the voltage input from the shared subtractor 91 is between the upper threshold Vhigh and the lower threshold Vlow (neither exceeds the upper threshold Vhigh and the lower threshold Vlow), the sharing determination unit 92 outputs the power supply level and the power supply voltage The detection signal (+) of approximately the same level, and the detection signal (-) of the voltage level and the voltage of the ground terminal approximately the same level. The voltage input from the common subtractor 91 (ie, the voltage output by the common subtractor 91) is the total voltage of the output voltages of the k individual subtractors 42 added by the adding unit 6. Therefore, when the output voltage of the common subtractor 91 does not exceed the upper limit threshold Vhigh and the lower limit threshold Vlow, the output of the common determination unit 92 is "0", and the low-resolution system circuit 9 detects the complex number connected to the addition unit 6 No address event has occurred in all pixels of (in this example, k) pixels.

When the voltage value of the voltage input from the shared subtractor 91 exceeds the upper threshold value Vhigh (when the voltage value is higher than the upper threshold value Vhigh), the common determination unit 92 outputs a detection signal of the same level as the ground terminal (+) , And the detection signal (-) whose voltage level is approximately the same as that of the ground terminal. In this case, the output of the common determination unit 92 is "+1", and the low-resolution system circuit 9 detects a certain number of pixels among the plural (k in this example) pixels connected to the adding unit 6, and An address event that changed from the dark state to the bright state occurred. In addition, the specific number differs according to the capacitance of the addition capacitors C61 to C6k provided in the addition unit 6 and the capacitance of the individual capacitor C421.

When the voltage value of the voltage input from the shared subtractor 91 exceeds the lower threshold value Vlow (below the lower threshold value Vlow), the shared determination unit 92 outputs a detection signal whose voltage level is approximately the same as the power supply voltage (+) , And the detection signal (-) whose voltage level is approximately the same as the power supply voltage. In this case, the output of the common determination unit 92 is "-1", and the low-resolution system circuit 9 detects a certain number of pixels among the plurality of (k in this example) pixels connected to the adding unit 6, and An address event that changed from the bright state to the dark state occurred.

The solid-state imaging element 200 is configured to use the voltage based on the photocurrent of the photoelectric conversion element 333 in the multi-pixel, and the added voltage added by the adding section 6, and a common subtractor 51 and a common determining section 52 determine whether to detect Out address event. In addition, the solid-state imaging device 200 is configured to be disposed in the pixel P, and can stop the operations of the individual subtractor 42 and the quantizer 43 that are not useful for the detection of address events.

As a result, the solid-state imaging device 200 can switch to the detection of low-resolution address events when the detection of multi-resolution address events is not required, and stop the individual subtractors 42 and that are not helpful for the detection of address events The action of the quantizer 43. As a result, the solid-state imaging element 200 can achieve low power consumption.

[Second Embodiment 2-2] FIG. 19 is a circuit diagram showing a configuration example of the low-resolution address event detection unit provided in the solid-state imaging device 200 of the 2-2 embodiment. In addition, in FIG. 19, the illustration of the pixel signal generating portion 320, the transmission transistor 331 and the OFG transistor 332 provided in the pixel P is omitted.

As shown in FIG. 19, the solid-state imaging device 200 of this embodiment includes a switch circuit 47 in addition to the structure of the solid-state imaging device 200 of the 2-1 embodiment described above. More specifically, the solid-state imaging device 200 includes individual subtractors (an example of individual subtractors) 42 which are respectively connected to a plurality of current-voltage conversion units 41, and are free to be input at different timings by the connected current-voltage conversion units 41 One voltage minus another voltage. Each of the plurality of individual subtractors 42 includes an individual capacitor C421, which has one electrode connected to the current-voltage conversion section 41 to which the individual subtractor 42 is connected, and the other electrode arranged opposite to the one electrode. Furthermore, the plurality of individual subtractors 42 have a switch circuit (an example of a switch) 47, which is connected to the other electrode of the individual capacitor C421, and the individual capacitor C421 can be disconnected from the individual subtractor 42. The adding unit 7 is connected to the connection part with the individual capacitor C421 and the switch circuit 47. The adding unit 7 is different from the adding unit 6 of the above-mentioned 2-1 embodiment in that it does not have an adding capacitor.

When the solid-state imaging device 200 is operating at a low resolution, the switch circuit 47 is switched to the on state (off state). Thereby, the constituent elements of the subsequent stage of the individual capacitor C421 can be separated from the current-voltage conversion unit 41. The input terminal of the common subtractor 91 is respectively connected to the other electrode of the individual capacitor C421 provided in the plurality of pixels P. In this way, the shared subtractor 91 obtains a specific profit through the individual capacitor C421 and the capacitor C911. As a result, the solid-state imaging device 200 can detect whether an address event has occurred by the common subtractor 91 and the common determination section 92 based on the voltage input from the plurality of current-voltage conversion sections 41.

In this way, when the solid-state imaging device 200 does not require multi-resolution address event detection, the switch circuit 47 can be set to the on state to switch to low-resolution address event detection, and stop is not beneficial to the address event The operation of the individual subtractor 42 and quantizer 43 of the detection. As a result, the solid-state imaging element 200 can achieve low power consumption.

As described above, the solid-state imaging device 200 of the 2-1 embodiment and the 2-2 embodiment can achieve low consumption by stopping the operations of the individual subtractor 42 and quantizer 43 that are not useful for detecting address events. Electrification.

[Third Embodiment] Next, the solid-state imaging device according to the third embodiment of the present disclosure will be described using FIGS. 20 to 25. The third embodiment is divided into the 3-1 embodiment to the 3-3 embodiment, and three kinds of weighting addition techniques will be described.

[Embodiment 3-1] FIG. 20 is a circuit diagram showing a configuration example of a low-resolution address event detection unit provided in the solid-state imaging device 200 of Embodiment 3-1. In addition, in FIG. 20, the illustration of the pixel signal generating portion 320, the transmission transistor 331 and the OFG transistor 332 provided in the pixel P is omitted.

As shown in FIG. 20, the solid-state imaging device 200 of this embodiment has the same features as the solid-state imaging device 200 of the above-mentioned Embodiment 1-1 except that it does not have the area reset generation circuit 53 and the in-pixel reset circuit 44. The composition. In addition, the solid-state imaging device 200 of this embodiment includes a threshold value processing circuit 10, which has the same configuration as the flicker detection circuit 5 except for the point that the region reset generation circuit 53 of the above-mentioned first embodiment is not connected.

The solid-state imaging element 200 of the present embodiment includes: a plurality of (four in this example) photoelectric conversion elements 333, which respectively perform photoelectric conversion on incident light to generate electric current; and a plurality of current-voltage conversion units 41, one by one It is connected to each of the plurality of photoelectric conversion elements 333, and converts the current input from the photoelectric conversion element 333 into voltage. In addition, the solid-state imaging element 200 includes a common subtractor (an example of a common subtractor) 101, which is connected to a plurality of (four in this example) current-voltage conversion sections 41, and is based on the current-voltage conversion section 41 at different timings. Each of them inputs a first voltage of one voltage, and subtracts a second voltage based on another voltage.

In addition, the solid-state imaging element 200 includes a common determination unit 102 that determines whether the difference between the first voltage and the second voltage based on the subtraction result of the common subtractor 101 exceeds the upper limit threshold Vhigh or the lower limit threshold Vlow (both are examples of specific thresholds) . Furthermore, the solid-state imaging element 200 includes an addition unit 6 that adds the voltages output from each of the plurality of current-voltage conversion units 41. The common subtractor 101 is configured to subtract one of the added voltages, which is the first voltage, from the addition section 6 and input at different timings, and subtract the other added voltage, which is the second voltage.

As shown in FIG. 20, the common subtractor 101 has a P-type transistor 1011, a P-type transistor 1012, an N-type transistor 1013, and a capacitor C1011. As these transistors, for example, MOS transistors can be used.

The P-type transistor 1012 and the N-type transistor 1013 are connected in series between the power terminal and the ground terminal. The connection part of the P-type transistor 1012 and the N-type transistor 1013 is connected to the input terminal of the common determination part 102. A specific bias voltage Vbdiff is applied to the gate of the N-type transistor 1013.

The source of the P-type transistor 1011 is connected to the gate of the P-type transistor 1012. The drain of the P-type transistor 1011 is connected to the connection part of the P-type transistor 1012 and the N-type transistor 1013.

One electrode of the capacitor C1011 is connected to the source of the P-type transistor 1011 and the gate of the P-type transistor 1012. The other electrode of the capacitor C1011 is connected to the connecting portion of the P-type transistor 1012 and the N-type transistor 1013 and the drain of the P-type transistor 1011. Since the operation of the common subtractor 101 is the same as that of the individual subtractor 42, the description is omitted.

As shown in FIG. 20, the common determination unit 102 is constituted by a quantizer. The common determination unit 102 has a P-type transistor 1021, an N-type transistor 1022, a P-type transistor 1023, and an N-type transistor 1024. As these transistors, for example, MOS transistors can be used.

The P-type transistor 1021 and the N-type transistor 1022 are connected in series between the power terminal and the ground terminal. The P-type transistor 1023 and the N-type transistor 1024 are connected in series between the power terminal and the ground terminal. The gate of the P-type transistor 1021 and the gate of the P-type transistor 1023 are connected to the output terminal of the common subtractor 101 (the connecting portion of the P-type transistor 1012 and the N-type transistor 1013). The voltage level applied to the gate of the N-type transistor 1022 is the upper threshold Vhigh of the high level. The voltage level applied to the gate of the N-type transistor 1024 is the lower voltage threshold Vlow of the low level. The connection part of the P-type transistor 1021 and the N-type transistor 1022 is the output terminal of the detection signal (+). The connection part of the P-type transistor 1023 and the N-type transistor 1024 is the output terminal of the detection signal (-).

When the voltage value of the voltage input from the shared subtractor 101 is between the upper threshold value Vhigh and the lower threshold value Vlow (neither exceeds the upper threshold value Vhigh and the lower threshold value Vlow), the sharing determination unit 102 outputs the voltage level and the power supply voltage The detection signal (+) of approximately the same level, and the detection signal (-) of the voltage level and the voltage of the ground terminal approximately the same level. The voltage input from the common subtractor 101 (ie, the voltage output by the common subtractor 101) is the total voltage of the output voltages of the k individual subtractors 42 added by the adding unit 6. Therefore, when the output voltage of the common subtractor 101 does not exceed the upper limit threshold Vhigh and the lower limit threshold Vlow, the output of the common determination unit 102 is "0", and the threshold processing circuit 10 detects that there are multiple ( In this example, there are no address events in all pixels of 4) pixels.

When the voltage value of the voltage input from the shared subtractor 101 exceeds the upper threshold value Vhigh (when the voltage value is higher than the upper threshold value Vhigh), the common determination unit 102 outputs a detection signal of approximately the same level as the ground terminal (+) , And the detection signal (-) whose voltage level is approximately the same as that of the ground terminal. In this case, the output of the common determination unit 102 becomes "+1", and the threshold processing circuit 10 detects that a specific number of pixels among the plural (4 in this example) pixels connected to the addition unit 6 have occurred. An address event that changes from the dark state to the bright state. In addition, the specific number differs according to the capacitance of the addition capacitors C61 to C64 provided in the addition unit 6 and the capacitance of the individual capacitor C421.

When the voltage value of the voltage input from the shared subtractor 91 exceeds the lower threshold value Vlow (below the lower threshold value Vlow), the shared determination unit 92 outputs a detection signal whose voltage level is approximately the same as the power supply voltage (+) , And the detection signal (-) whose voltage level is approximately the same as the power supply voltage. In this case, the output of the common determination unit 92 becomes "-1", and the threshold processing circuit 10 detects that a certain number of pixels among the plural (4 in this example) pixels connected to the adding unit 6 are received The light that changes from the bright state to the dark state.

The plural (four in this example) addition capacitors C61, C62, C63, and C64 provided in the addition unit 6 have mutually different capacitances. For example, with respect to the capacitance Ca of the added capacitor C61, the capacitance Cb of the added capacitor C62 is 4 times the capacitance Ca, the capacitance Cc of the added capacitor C63 is 8 times the capacitance Ca, and the capacitance Cd of the added capacitor C64 is 16 times the capacitance Cc.

The greater the capacitance of the added capacitor, the greater the weight. Therefore, even if each of the photoelectric conversion elements 333 provided in the four pixels P shown in FIG. 20 receives the same amount of light, it is the easiest to detect the address event of the shared subtractor 51 and the shared determination section 52 Detect the address event of the pixel P connected to the addition capacitor C64, then easily detect the address event of the pixel P connected to the addition capacitor C63, and then easily detect the address event of the pixel P connected to the addition capacitor C62, and It is most difficult to detect the address event of the pixel P connected to the addition capacitor C61. That is, by changing the capacitance of the capacitor, the same effect and effect as changing the values of the upper threshold Vhigh and the lower threshold Vlow for detecting the occurrence of address events can be obtained.

FIG. 21 is a diagram schematically showing an example of a weighted pattern of the pixel block PB provided in the solid-state imaging device 200 of this embodiment. As shown in FIG. 21, the solid-state imaging device 200 includes a pixel block PB, which is composed of a plurality of pixels P each having a photoelectric conversion element 333 and a current-voltage conversion unit 41 (see FIG. 20). The pixel block PB of this embodiment is composed of 64 pixels P arranged in 8 columns and 8 rows. In the pixel block PB, the pixels P connected to the addition capacitors C61 to C64 with the same capacitance are arranged in a specific pattern. In this embodiment, for example, the pixels P arranged on the outermost periphery are respectively connected to the addition capacitors C61. Furthermore, for example, to the pixels P arranged in the second row from the outer side of the pixel block PB, an addition capacitor C62 is connected. In addition, for example, an addition capacitor C63 is connected to the pixels P arranged in the third row from the outer side of the pixel block PB. Furthermore, for example, an addition capacitor C64 is connected to the pixels P arranged in the innermost circumference of the pixel block PB.

In this way, the solid-state imaging device 200 can change the difficulty of detecting address events in the pixel block PB. Thereby, the solid-state imaging device 200 can make the pixel block PB have the correction pattern implemented in the image processing. As a result, the processing load of the imaging device including the solid-state imaging element 200 can be reduced, and the power consumption of the imaging device including the solid-state imaging element 200 can be reduced.

[Embodiment 3-2] Next, the solid-state imaging device according to Embodiment 3-2 of the present disclosure will be described using FIGS. 22 and 23. The solid-state imaging device 200 of this embodiment is characterized in that in addition to weighting operations, convolution operations can also be performed. FIG. 22 is a diagram showing a configuration example of a circuit that performs weighting addition and threshold processing provided in the solid-state imaging device 200 of this embodiment. In addition, in FIG. 22, the illustration of the pixel signal generating portion 320, the transmission transistor 331 and the OFG transistor 332 provided in the pixel P is omitted. FIG. 23 is a diagram schematically showing the weighting pattern of the pixel block PB provided in the solid-state imaging device 200 of this embodiment.

As shown in FIG. 22, the solid-state imaging device 200 of this embodiment has the same configuration as the solid-state imaging device 200 of the above-mentioned Embodiment 3-1, except for the configuration of the addition unit 8. The addition unit 8 equipped in the solid-state imaging device 200 has a switch unit 81 that can individually cut off a plurality of current-voltage conversion units 41 from the common subtractor 51 and is provided. The switch part 81 has switches 811a, 811b, 811ka, and 811kb provided between one electrode of the individual capacitor C421 and one electrode of the plurality of addition capacitors C81a, C81b, C81ka, and C81kb. In addition, the switch section 81 has switches 812a, 812b, 812ka, and 812kb provided between the other electrodes of the addition capacitors C81a, C81b, C81ka, and C81kb and the common subtractor 51. The switches 811a to 811kb and 811a to 811kb are composed of, for example, MOS transistors. The capacitances of the addition capacitors C81a, C81b, C81ka, and C81kb are different from each other.

The solid-state imaging device 200 can perform convolution operation in addition to the weighted addition by switching the on and off states of the switches 811a to 811kb and 811a to 811kb. For example, the capacitance Ca of the adding capacitor C81a is 1/4 of the capacitance Cb of the adding capacitor C81b. The switch section 81 can set the output of the current-voltage conversion section 41 provided in the pixel P and the input terminal of the common subtractor 51 into the following four states. (A) Cut-off state (switch 811a: open, switch 812a: open; Switch 811b: open, switch 812b: open) (B) Connect with capacitor Ca (Switch 811a: on, switch 812a: on; Switch 811b: open, switch 812b: open) (C) Connect with capacitor Cb (Switch 811a: open, switch 812a: open; Switch 811b: on, switch 812b: on) (D) Connect with capacitor Ca+Cb (Switch 811a: open, switch 812a: open; Switch 811b: on, switch 812b: on)

In the state (B), the combined capacitor of the adding unit 8 is the capacitance Ca. In the state (C), the combined capacitor of the adding unit 8 is the capacitance Cb=(=4×Ca). In the state (D), the combined capacitor of the adding unit 8 is the capacitance Ca+Cb (=8×Ca). In this way, the adding unit 8 can change the weighted state of each pixel P constituting the pixel block PB by controlling the switch unit 81.

As shown in FIG. 23, the weighted pattern is the largest in the center, the second row surrounding the center is the second largest, and the third row surrounding the second row is the smallest pattern. By appropriately switching the switch part 81, as shown from left to right in the upper part of FIG. 23, the weighting pattern can be moved row by row in a pixel block PB composed of pixels P in 8 columns and 8 rows. Furthermore, by appropriately switching the switch portion 81, as shown from left to right in the lower part of FIG. 23, the weighting pattern can be moved column by column in the pixel block PB composed of 8 columns and 8 rows of pixels P.

In this way, the solid-state imaging device 200 can perform a convolution operation by moving the weighting pattern column by column or row by row.

[Embodiment 3-3] Next, the solid-state imaging device according to Embodiment 3-3 of the present disclosure will be described using FIG. 24. The solid-state imaging device 200 of this embodiment is characterized in that in addition to weighting operations, convolution operations can also be performed. FIG. 24 is a diagram showing a configuration example of a circuit that performs weighting addition and threshold processing provided in the solid-state imaging device 200 of this embodiment. In addition, in FIG. 24, the illustration of the pixel signal generating portion 320, the transmission transistor 331 and the OFG transistor 332 provided in the pixel P is omitted.

As shown in FIG. 24, the solid-state imaging device 200 of the present embodiment has the same configuration as the solid-state imaging device 200 of the above-mentioned 3-2 embodiment except for the configuration of the addition unit 8. The addition unit 8 equipped in the solid-state imaging device 200 has a switch unit 81 that can individually cut off a plurality of current-voltage conversion units 41 from the common subtractor 51 and is provided. The switch section 81 has switches 812a, 812b, 812ka, and 812kb provided between the other electrodes of the addition capacitors C81a, C81b, C81ka, and C81kb and the common subtractor 51. The switches 811a to 811kb are composed of, for example, MOS transistors. The capacitances of the addition capacitors C81a, C81b, C81ka, and C81kb are different from each other.

The solid-state imaging device 200 can perform convolution operation in addition to the weighted addition by switching the on and off states of the switches 811a to 811kb. For example, the capacitance Ca of the adding capacitor C81a is 1/4 of the capacitance Cb of the adding capacitor C81b. The switch section 81 can set the output of the current-voltage conversion section 41 provided in the pixel P and the input terminal of the common subtractor 51 into the following four states. (A) Cut-off state (switch 812a: open, switch 812b: open) (B) Connect with capacitor Ca (Switch 812a: on, switch 812b: off) (C) Connect with capacitor Cb (Switch 812a: off, switch 812b: on) (D) Connect with capacitor Ca+Cb (Switch 812a: off, switch 812b: on)

In the state (B), the combined capacitor of the adding unit 8 is the capacitance Ca. In the state (C), the combined capacitor of the adding unit 8 is the capacitance Cb (=4×Ca). In the state (D), the combined capacitor of the adding unit 8 is the capacitance Ca+Cb (=8×Ca). In this way, the adding unit 8 can change the weighted state of each pixel P constituting the pixel block PB by controlling the switch unit 81.

The addition unit 8 provided in the solid-state imaging device 200 of this embodiment may not have a switch between the addition capacitors C81a to C81kb and the individual capacitor C421. As a result, the solid-state imaging element 200 of this embodiment can reduce the circuit scale compared to the solid-state imaging element 200 of the above-mentioned 3-1 embodiment.

[Embodiment 3-4] Next, the solid-state imaging device according to Embodiment 3-4 of the present disclosure will be described using FIG. 25. The solid-state imaging device 200 of this embodiment is characterized in that in addition to weighting operations, convolution operations can also be performed. FIG. 25 is a diagram showing a configuration example of a circuit that performs weighting addition and threshold processing provided in the solid-state imaging device 200 of this embodiment. In addition, in FIG. 25, the illustration of the pixel signal generating portion 320, the transmission transistor 331, and the OFG transistor 332 provided in the pixel P is omitted.

As shown in FIG. 25, the solid-state imaging device 200 of this embodiment has the same configuration as the solid-state imaging device 200 of the above-mentioned 3-2 embodiment and the above-mentioned 3-3 embodiment except for the configuration of the addition unit 8. The addition unit 8 to which the solid-state imaging element 200 is mounted has a switch unit 81 that can individually cut off the plurality of current-voltage conversion units 41 from the common subtractor 51. The switch part 81 has switches 811a, 811b, 811ka, and 811kb provided between one electrode of the individual capacitor C421 and one electrode of the plurality of addition capacitors C81a, C81b, C81ka, and C81kb. The switches 811a to 811kb are composed of, for example, MOS transistors. The capacitances of the addition capacitors C81a, C81b, C81ka, and C81kb are different from each other.

The solid-state imaging device 200 can perform convolution operation in addition to the weighted addition by switching the on and off states of the switches 811a to 811kb. For example, the capacitance Ca of the adding capacitor C81a is 1/4 of the capacitance Cb of the adding capacitor C81b. The switch section 81 can set the output of the current-voltage conversion section 41 provided in the pixel P and the input terminal of the common subtractor 51 into the following four states. (A) Cut-off state (switch 811a: open, switch 811b: open) (B) Connect with capacitor Ca (Switch 811a: on, switch 811b: off) (C) Connect with capacitor Cb (Switch 811a: off, switch 811b: on) (D) Connect with capacitor Ca+Cb (Switch 811a: off, switch 811b: on)

In the state (B), the combined capacitor of the adding unit 8 is the capacitance Ca. In the state (C), the combined capacitor of the adding unit 8 is the capacitance Cb (=4×Ca). In the state (D), the combined capacitor of the adding unit 8 is the capacitance Ca+Cb (=8×Ca). In this way, the adding unit 8 can change the weighting state of each of the pixels P constituting the pixel block PB by controlling the switch unit 81.

The adding unit 8 to which the solid-state imaging element 200 of this embodiment is mounted does not have a switch between the adding capacitors C81a to C81kb and the common subtractor 51. As a result, the solid-state imaging element 200 of this embodiment can reduce the circuit scale compared to the solid-state imaging element 200 of the above-mentioned 3-1 embodiment.

As described above, the solid-state imaging device 200 according to Embodiment 3-1 to Embodiment 3-4 can make the pixel block PB have the correction pattern implemented in the image processing. As a result, the processing load of the imaging device including the solid-state imaging element 200 can be reduced, and the power consumption of the imaging device including the solid-state imaging element 200 can be reduced.

In the above-mentioned first embodiment to the above-mentioned third embodiment, focusing on one pixel P among the plural pixels P each having the address event detection unit 4, as shown in Fig. 5, Fig. 8, Fig. 10, Fig. 12, As shown in FIG. 14, FIG. 16, FIG. 17 to FIG. 20, FIG. 22, FIG. 24, and FIG. 25, the solid-state imaging element 200 includes: a photoelectric conversion element 333 that photoelectrically converts incident light to generate current; and a current-voltage conversion unit 41, which converts the current input from the photoelectric conversion element 333 into a voltage. The solid-state imaging element 200 includes an individual subtractor 42 and a common subtractor 51, 91, 101 (an example of a plurality of subtractors), which are connected to the current-voltage conversion section 41, and input from the current-voltage conversion section 41 at different timings One voltage minus another voltage.

However, the DVS sensor is a sensor that detects and outputs brightness change information. The previous DVS detects brightness change information per pixel and outputs it per pixel. In the structure that detects brightness change information per pixel, it is impossible to perform brightness change detection and processing for each pixel area in the pixel array. On the other hand, if processing capabilities such as flicker suppression or multi-resolution can be installed for each pixel array area, the effects of reducing the amount of data, reducing power, and reducing noise can be obtained. This technology can realize the function of the previous subtraction unit of DVS by having one subtraction unit of the plurality of DVS subtraction units, and utilize the remaining subtraction units as the information processing function of each pixel array area. Thereby, the solid-state imaging device 200 of the embodiment of the present technology can perform the signal processing function of each area that cannot be realized in the previous DVS.

The individual subtractor 42 and the individual subtractor 42 of the common subtractors 51, 91, and 101 (an example of a specific subtractor that is one of the multiple subtractors) has an individual capacitor C421 connected to the current-voltage conversion unit One electrode of 41 and the other electrode arranged opposite to the one electrode. As shown in Figure 5, Figure 8, Figure 10, Figure 12, Figure 14, Figure 16, Figure 17 to Figure 18, Figure 20, Figure 22, Figure 24 and Figure 25, the individual subtractor 42 and the common subtractor 51, 91 The common subtractors 51, 91, and 101 in, 101 (an example of at least a part of the remaining subtractors in the plural subtractors) are connected to one electrode of the individual capacitor C421.

As shown in FIG. 19, the individual subtractor 42 (an example of a specific subtractor that is one of the subtractors among the plurality of subtractors) has an individual capacitor C421 having an electrode connected to the current-voltage conversion unit 41 and The other electrode is arranged opposite to the electrode. The common subtractor 91 (an example of at least a part of the remaining subtracting units among the plurality of subtracting units) is connected to the other electrode of the individual capacitor C421.

The solid-state imaging element 200 includes at least one of an address event detection unit 4 (an example of the first detection unit) or a flicker detection circuit 5, a low-resolution system circuit 9 and a threshold processing circuit 10 (all are examples of the second detection unit) By. The address event detection unit 4 has: a current-voltage conversion unit 41; an individual subtractor 42 (an example of a specific subtractor); and a quantizer 43 (an example of a first determination unit) whose determination is based on the subtracted result of the individual subtractor 42 Whether the difference between one voltage and the other voltage exceeds the upper threshold Vhigh or the lower threshold Vlow (both are examples of specific thresholds), and is configured to detect an address event corresponding to the amount of light received by the photoelectric conversion element 333. The flicker detection circuit 5, the low-resolution system circuit 9, and the threshold value processing circuit 10 have: common subtractors 51, 91, 101 (an example of one of the remaining subtractors in a plurality of subtractors); and a common determination unit 52, 92, 102 (an example of the second determination unit), which determines whether the difference between one voltage and the other voltage of the subtraction results of the common subtractors 51, 91, 101 exceeds the upper threshold Vhigh or the lower threshold Vlow (both are An example of a specific threshold). In this embodiment, the solid-state imaging element 200 includes an address event detection unit 4 and a flicker detection circuit 5, an address event detection unit 4, and a low-resolution system circuit 9 or an address event detection unit 4 and a threshold processing circuit 10. By. The solid-state imaging element 200 includes a pixel P, which has an address event detection unit 4 and a photoelectric conversion element 333.

In addition, the effects described in this specification are only examples and are not limiting, and other effects may be possible.

In addition, the present disclosure may adopt the following configurations. (1) A solid-state imaging element including: Photoelectric conversion element, which performs photoelectric conversion of incident light to generate current; A current-to-voltage conversion unit that converts the current input from the photoelectric conversion element into a voltage; and A plurality of subtraction units are connected to the above-mentioned current-voltage conversion unit, and one voltage is inputted from the above-mentioned current-voltage conversion unit at different timings to subtract another voltage. (2) The solid-state imaging device as described in (1) above, wherein One of the plurality of subtraction units, that is, the specific subtraction unit has a capacitor having: one electrode connected to the current-voltage conversion unit and the other electrode arranged opposite to the one electrode; and At least a part of the remaining subtraction units among the plurality of subtraction units is connected to the one electrode. (3) The solid-state imaging device as described in (1) above, wherein One of the plurality of subtraction units, that is, the specific subtraction unit has a capacitor having: one electrode connected to the current-voltage conversion unit and the other electrode arranged opposite to the one electrode; and At least a part of the remaining subtraction units among the plurality of subtraction units is connected to the other electrode. (4) The solid-state imaging element as described in (2) or (3) above, which includes at least one of a first detection section or a second detection section, The first detection unit has: the current-voltage conversion unit; the specific subtraction unit; and a first determination unit that determines whether the difference between the one voltage and the other voltage based on the subtraction result of the specific subtraction unit exceeds a specific value Threshold, and detect the event corresponding to the amount of light received by the photoelectric conversion element; The second detection unit has: one of the subtraction units among the remaining subtraction units among the plurality of subtraction units; and a second determination unit that determines the difference between the one voltage and the other voltage based on the subtraction result of the one subtraction unit Whether the amount exceeds a certain threshold. (5) A solid-state imaging element including: A plurality of photoelectric conversion elements, each of which performs photoelectric conversion on incident light to generate electric current; A plurality of current-to-voltage conversion units are connected to each of the plurality of photoelectric conversion elements one by one, and convert the current input from the photoelectric conversion element into voltage; and A common subtraction unit is connected to the plurality of current-voltage conversion units, and subtracts a second voltage based on another voltage from a first voltage based on a voltage input from each of the current-voltage conversion units at different timings. (6) The solid-state imaging device described in (5) above, which includes: A common determination unit that determines whether the difference between the first voltage and the second voltage based on the subtraction result of the common subtraction unit exceeds a specific threshold. (7) The solid-state imaging device described in (6) above, which includes: An addition unit that adds the above-mentioned voltages output from each of the above-mentioned plurality of current-voltage conversion units; and The common subtraction unit subtracts the second voltage, which is one of the added voltages that are added by the adder and is input at a different time sequence, from another added voltage. (8) The solid-state imaging device described in (7) above, which includes: The individual subtraction unit is connected to each of the plurality of current-voltage conversion units one by one, and the connected current-voltage conversion unit is free to input one voltage at different timings and subtract another voltage; and The individual subtracting unit has: an individual capacitor having one electrode connected to the current-voltage conversion unit connected to the individual subtracting unit, and the other electrode arranged opposite to the one electrode, The adding unit includes an adding capacitor having one electrode connected to one of the electrodes of the individual capacitors provided in the current-voltage conversion unit, and another electrode arranged opposite to the one electrode and connected to the common subtracting unit. (9) The solid-state imaging device described in any one of (6) to (8) above, which includes: Individual subtraction units, which are respectively connected to the plurality of current-voltage conversion units, and are free to input one voltage minus another voltage at different timings by the connected current-voltage conversion units; and A resetting unit for resetting at least one of the plurality of photoelectric conversion elements, the plurality of current-voltage conversion units, and the plurality of individual subtracting units when the common determination unit determines that the difference exceeds the threshold value The action. (10) The solid-state imaging device described in (5) or (6) above, which has: Individual subtraction units connected to each of the above-mentioned plurality of current-voltage conversion units one by one, and freely connected to the above-mentioned current-voltage conversion unit to input one voltage minus another voltage at different timings; A plurality of individual pixels, each of which has the aforementioned photoelectric conversion element, the aforementioned current-voltage conversion unit, and the aforementioned individual subtraction unit; and A dedicated capacitor, which is arranged in a pixel different from the above-mentioned individual pixels; and Each of the plurality of individual subtracting units has: an individual capacitor having one electrode connected to the current-voltage conversion unit connected to the individual subtracting unit, and the other electrode arranged opposite to the one electrode, Each of the plurality of individual pixels has: a small capacitor having one electrode connected to one of the electrodes of the individual capacitor, and the other electrode disposed opposite to the one electrode, and the capacitance is smaller than the individual capacitor, The dedicated capacitor has one electrode and another electrode arranged opposite to the one electrode and connected to the other electrode of the small capacitor, and has a smaller capacitance than the individual capacitor. (11) The solid-state image sensor as described in (10) above, which includes: A common determination unit that determines whether the difference between the first electrode and the second voltage based on the subtraction result of the common subtraction unit exceeds a specific threshold; and A resetting unit that resets at least any one of the plurality of photoelectric conversion elements, the plurality of current-voltage conversion units, and the plurality of individual subtracting units when the common determination unit determines that the difference exceeds the threshold value The action of the person. (12) The solid-state imaging device described in (10) or (11) above, which has: A shared pixel, which has the above-mentioned dedicated capacitor and the above-mentioned shared subtraction unit; and The pixel block has the above-mentioned common pixel and the above-mentioned plurality of individual pixels. (13) The solid-state imaging element as described in (12) above, wherein The common pixel has: a common photoelectric conversion element that photoelectrically converts incident light to generate a current; and a common current-voltage conversion section that converts the current input from the common photoelectric conversion element into a voltage, and outputs the voltage to One of the electrodes of the above dedicated capacitor; and The common photoelectric conversion element is connected to the photoelectric conversion element provided in one individual pixel of the plurality of individual pixels. (14) The solid-state imaging device described in (10) above, wherein The common subtraction unit is arranged in an area different from the pixel area in which the plurality of individual pixels are arranged. (15) The solid-state imaging device described in (10) or (12) above, which includes: The first common switch is set to cut off the other electrode of the plurality of small capacitors and the other electrode of the dedicated capacitor; A large capacitor, which is connected in parallel to the above-mentioned common capacitor and has a capacitance greater than the above-mentioned common capacitor; and The second common switch is connected in series to the large capacitor and connected in parallel to the common capacitor. (16) The solid-state imaging device described in (7) above, which includes: The individual subtraction units are respectively connected to the plurality of current-voltage conversion units, and the connected current-voltage conversion units can input one voltage minus another voltage at different timings. (17) The solid-state imaging device as in (8) above, wherein A plurality of the above-mentioned adding capacitors have mutually different capacitances. (18) The solid-state imaging device described in (17) above, wherein The addition unit has a switch unit configured to individually cut off the plurality of current-voltage conversion units from the common subtraction unit; and The switch section has at least one of: a switch provided between one electrode of the individual capacitor and one electrode of the plurality of adding capacitors, and a switch provided between the other electrode of the adding capacitor and the common subtracting section. (19) The solid-state imaging device described in (17) or (18) above, which has: A pixel block, which is composed of a plurality of pixels each having the photoelectric conversion element and the current-voltage conversion unit; and In the pixel block, the pixels connected to the adding capacitors with the same capacitance are arranged in a specific pattern.

4: Address event detection department 5: Flicker detection circuit 6: Addition Department 7: Addition Department 8: Addition Department 9: System circuit for low resolution 10: Threshold processing circuit 41: Current-to-voltage conversion section 41a: Logarithmic conversion circuit 41b: Buffer circuit 42: Individual subtractor 43: Quantizer 44: Reset circuit in pixel 45a: Stop circuit 45b: Stop circuit 46: Reset circuit in pixel 47: switch circuit 51: Shared subtractor 52: Shared Judgment Department 53: Region reset generation circuit 54a: Switch circuit 54b: Switch circuit 55: Region reset generation circuit 56: Current-to-voltage conversion section 56a: Logarithmic conversion circuit 56b: Buffer circuit 57a: The first common switch 57b: second common switch 81: Switch part 91: Shared subtractor 92: Shared Judgment Department 100: camera device 101: Shared subtractor 102: Shared Judgment Department 110: Camera lens 120: Recording Department 130: Control Department 200: solid-state image sensor 201: Light receiving chip 202: Inspection wafer 209: signal line 211: drive circuit 212: Signal Processing Department 213: Arbiter 220: Row ADC 230: ADC 300: Pixel array section 310: pixel block 320: Pixel signal generator 321: reset transistor 322: Amplified Transistor 323: Select Transistor 324: Floating diffusion layer 330: Light Receiving Department 331: Transmission Transistor 332: OFG Transistor 333: photoelectric conversion element 411: N-type transistor 412: P-type transistor 413: N-type transistor 414: P-type transistor 415: P-type transistor 421: P-type transistor 422: P-type transistor 423: N-type transistor 431: P-type transistor 432: N-type transistor 433: P-type transistor 434: N-type transistor 450: Transmission Department 451a: P-type transistor 451b: N-type transistor 452a: N-type transistor 452b: P-type transistor 511: P-type transistor 512: P-type transistor 513: N-type transistor 521: P-type transistor 522: N-type transistor 523: P-type transistor 524: N-type transistor 561: N-type transistor 562: P-type transistor 563: N-type transistor 564: P-type transistor 565: N-type transistor 811a: switch 811b: switch 811ka: switch 811kb: switch 812a: switch 812b: switch 812ka: switch 812kb: switch 911: P-type transistor 912: P-type transistor 913: N-type transistor 921: P-type transistor 922: N-type transistor 923: P-type transistor 924: N-type transistor 1011: P-type transistor 1012: P-type transistor 1013: N-type transistor 1021: P-type transistor 1022: N-type transistor 1023: P-type transistor 1024: N-type transistor Ca: Capacitance Cb: Capacitance Cc: Capacitance Cd: Capacitance C41: Capacitor C45: Small capacitor C56: Capacitor C57: Large capacitor C61: add capacitor C62: add capacitor C63: add capacitor C64: add capacitor C65: add capacitor C67: add capacitor C68: add capacitor C69: add capacitor C6k: add capacitor C81: add capacitor C81a: add capacitor C81ka: add capacitor C81kb: add capacitor C421: Individual capacitor C422: Capacitor C511: Capacitor C512: dedicated capacitor C610: add capacitor C611: Add capacitor C612: add capacitor C613: add capacitor C614: add capacitor C615: add capacitor C616: add capacitor C81a: add capacitor C81b: add capacitor C81ka: add capacitor C81kb: add capacitor C911: Capacitor C1011: Capacitor FLcom: Wiring Mode_ctl: control signal OFG: control signal P: pixel P1: pixel P37: pixel P57: pixel P64: pixel P241: pixel P256: pixel PB: pixel block RST: reset signal RST_AR: Arbiter reset signal RST_FL: reset signal SEL: select signal sf1: connect node sf16: connect node SIG: pixel signal sum: connect node sum_n: connect node sum_p: connect node t1: moment t1~t4: time TRG: transmit signal V: voltage Vbdiff: Bias voltage Vblog: Bias voltage Vbsf: Bias voltage Vhigh: upper threshold Vlow: lower threshold Vint_sum: output voltage Vint1~Vint16: output voltage Vsf1~Vsf16: Voltage VSL: vertical signal line Vsum: Voltage Vsum_n: voltage Vsum_p: voltage Vsum_rst: output reset signal XAZ: Control signal XAZ_sum: control signal XAZ1-5, 7-16: control signal XAZk: control signal

FIG. 1 is a block diagram showing an example of the configuration of an imaging device including the solid-state imaging element of each embodiment of the present disclosure. FIG. 2 is a diagram showing an example of the multilayer structure of the solid-state imaging device in each embodiment of the present disclosure. FIG. 3 is a block diagram showing a configuration example of the solid-state imaging device of each embodiment of the present disclosure. 4 is a circuit diagram showing a configuration example of a pixel provided in the solid-state imaging device of each embodiment of the present disclosure. FIG. 5 is a circuit diagram showing a configuration example of the address event detection unit and the flicker detection circuit of the solid-state imaging device according to the 1-1 embodiment of the present disclosure. 6 is a diagram showing an example of a timing chart of the flicker detection processing of the solid-state imaging device according to the 1-1 embodiment of the present disclosure. FIG. 7 is a diagram showing an example of a timing chart of the event detection processing of the solid-state imaging device in the 1-1 embodiment of the present disclosure. FIG. 8 is a circuit diagram showing a configuration example of the address event detection unit and the flicker detection circuit of the solid-state imaging device according to the 1-2 embodiment of the present disclosure. FIG. 9 is a diagram illustrating the solid-state imaging device of the first and second embodiments of the present disclosure, and is a circuit diagram showing a configuration example of a stop circuit that stops the quantizer during flicker detection. FIG. 10 is a circuit diagram showing a configuration example of the address event detection unit and the flicker detection circuit of the solid-state imaging device of the first to third embodiments of the present disclosure. FIG. 11 is a diagram schematically showing the pixel blocks provided in the solid-state imaging device of Embodiments 1-4 of the present disclosure. FIG. 12 is a circuit diagram showing a configuration example of the address event detection unit and the flicker detection circuit of the solid-state imaging device of the first to fourth embodiments of the present disclosure. FIG. 13 is a diagram schematically showing the pixel blocks provided in the solid-state imaging device of Embodiments 1-5 of the present disclosure. FIG. 14 is a circuit diagram showing an example of the configuration of the address event detection section and the flicker detection circuit of the solid-state imaging device of the first to fifth embodiments of the present disclosure. FIG. 15 is a diagram schematically showing the pixel block and the flicker detection circuit of the solid-state imaging device according to Embodiments 1-6 of the present disclosure. 16 is a circuit diagram showing an example of the configuration of the address event detection unit and the flicker detection circuit of the solid-state imaging device in the first 1-6 embodiments of the present disclosure. FIG. 17 is a circuit diagram showing a configuration example of the address event detection unit and the flicker detection circuit of the solid-state imaging device provided in the first to seventh embodiments of the present disclosure. FIG. 18 is a circuit diagram showing a configuration example of a low-resolution address event detection unit provided in the solid-state imaging device of the 2-1 embodiment of the present disclosure. FIG. 19 is a circuit diagram showing a configuration example of a low-resolution address event detection unit provided in the solid-state imaging device of the 2-2 embodiment of the present disclosure. FIG. 20 is a diagram showing a configuration example of a circuit for performing weighting addition and threshold processing of the solid-state imaging device provided in the 3-1 embodiment of the present disclosure. FIG. 21 is a diagram schematically showing the weighted pattern of the pixel block provided in the solid-state imaging device of Embodiment 3-1 of the present disclosure. FIG. 22 is a diagram showing a configuration example of a circuit that performs weighting addition and threshold processing of the solid-state imaging element provided in the 3-2 embodiment of the present disclosure. FIG. 23 is a diagram schematically showing the weighted pattern of the pixel block provided in the solid-state imaging device of Embodiment 3-2 of the present disclosure. FIG. 24 is a diagram showing a configuration example of a circuit for performing weighting addition and convolution operation of the solid-state imaging device provided in the third embodiment of the present disclosure. FIG. 25 is a diagram showing a configuration example of a circuit for performing weighting addition and convolution operation of the solid-state imaging element provided in the 3-4th embodiment of the present disclosure.

4: Address event detection department

5: Flicker detection circuit

6: Addition Department

41: Current-to-voltage conversion section

41a: Logarithmic conversion circuit

41b: Buffer circuit

42: Individual subtractor

43: Quantizer

44: Reset circuit in pixel

51: Shared subtractor

52: Shared Judgment Department

53: Region reset generation circuit

333: photoelectric conversion element

411: N-type transistor

412: P-type transistor

413: N-type transistor

414: P-type transistor

415: P-type transistor

421: P-type transistor

422: P-type transistor

423: N-type transistor

431: P-type transistor

432: N-type transistor

433: P-type transistor

434: N-type transistor

511: P-type transistor

512: P-type transistor

513: N-type transistor

521: P-type transistor

522: N-type transistor

523: P-type transistor

524: N-type transistor

C41: Capacitor

C61~C6k: add capacitor

C421: Individual capacitor

C422: Capacitor

C511: Capacitor

P: pixel

sf1: connect node

sf16: connect node

sum: connect node

sum_n: connect node

sum_p: connect node

Vbdiff: Bias voltage

Vblog: Bias voltage

Vbsf: Bias voltage

Vhigh: upper threshold

Vint1: output voltage

Vint16: output voltage

Vlow: lower threshold

Vsum_rst: output reset signal

XAZ_sum: control signal

XAZ1: Control signal

XAZ16: Control signal

Claims (19)

A solid-state imaging element including: Photoelectric conversion element, which performs photoelectric conversion of incident light to generate current; A current-to-voltage conversion unit that converts the current input from the photoelectric conversion element into a voltage; and A plurality of subtraction units are connected to the above-mentioned current-voltage conversion unit, and one voltage is inputted from the above-mentioned current-voltage conversion unit at different timings to subtract another voltage. Such as the solid-state imaging device of claim 1, where One of the plurality of subtraction units, that is, the specific subtraction unit has a capacitor having an electrode connected to the current-voltage conversion unit and the other electrode arranged opposite to the one electrode, and At least a part of the remaining subtraction units among the plurality of subtraction units is connected to the one electrode. Such as the solid-state imaging device of claim 1, where One of the plurality of subtraction units, that is, the specific subtraction unit has a capacitor having one electrode connected to the current-voltage conversion unit and the other electrode arranged opposite to the one electrode, and At least a part of the remaining subtraction units among the plurality of subtraction units is connected to the other electrode. Such as the solid-state imaging device of claim 2, which has at least one of a first detection unit or a second detection unit, The first detection unit includes: the current-voltage conversion unit; the specific subtraction unit; and a first determination unit that determines whether the difference between the one voltage and the other voltage based on the subtraction result of the specific subtraction unit exceeds a specific threshold ; And detect the event corresponding to the amount of light received by the photoelectric conversion element, The second detection unit has: a subtraction unit among the remaining subtraction units of the plurality of subtraction units; and a second determination unit that determines the difference between the one voltage and the other voltage based on the subtraction result of the one subtraction unit Whether it exceeds a certain threshold. A solid-state imaging element including: A plurality of photoelectric conversion elements, each of which performs photoelectric conversion on incident light to generate electric current; A plurality of current-to-voltage conversion units are connected to each of the plurality of photoelectric conversion elements one by one, and convert the current input from the photoelectric conversion element into voltage; and A common subtraction unit is connected to the plurality of current-voltage conversion units, and subtracts a second voltage based on another voltage from a first voltage based on a voltage input from each of the current-voltage conversion units at different timings. Such as the solid-state imaging device of claim 5, which has: A common determination unit that determines whether the difference between the first voltage and the second voltage based on the subtraction result of the common subtraction unit exceeds a specific threshold. Such as the solid-state imaging device of claim 6, which has: An addition unit that adds the above-mentioned voltages output from each of the above-mentioned plurality of current-voltage conversion units; and The common subtraction unit subtracts the second voltage, which is one of the added voltages that are added by the adder and is input at a different time sequence, from another added voltage. Such as the solid-state imaging device of claim 7, which has: The individual subtraction unit is connected to each of the plurality of current-voltage conversion units one by one, and the connected current-voltage conversion unit is free to input one voltage at different timings and subtract another voltage; and The individual subtracting unit has: an individual capacitor having one electrode connected to the current-voltage conversion unit connected to the individual subtracting unit, and the other electrode arranged opposite to the one electrode, The adding unit includes an adding capacitor having one electrode connected to one of the electrodes of the individual capacitors provided in the current-voltage conversion unit, and another electrode arranged opposite to the one electrode and connected to the common subtracting unit. Such as the solid-state imaging device of claim 6, which has: Individual subtraction units, which are respectively connected to the plurality of current-voltage conversion units, and are free to input one voltage minus another voltage at different timings by the connected current-voltage conversion units; and A resetting unit for resetting at least one of the plurality of photoelectric conversion elements, the plurality of current-voltage conversion units, and the plurality of individual subtracting units when the common determination unit determines that the difference exceeds the threshold value The action. Such as the solid-state imaging device of claim 5, which has: Individual subtraction units connected to each of the above-mentioned plurality of current-voltage conversion units one by one, and freely connected to the above-mentioned current-voltage conversion unit to input one voltage minus another voltage at different timings; A plurality of individual pixels, each of which has the aforementioned photoelectric conversion element, the aforementioned current-voltage conversion unit, and the aforementioned individual subtraction unit; and A dedicated capacitor, which is arranged in a pixel different from the above-mentioned individual pixels; and Each of the plurality of individual subtracting units has: an individual capacitor having one electrode connected to the current-voltage conversion unit connected to the individual subtracting unit, and the other electrode arranged opposite to the one electrode, Each of the plurality of individual pixels has: a small capacitor having one electrode connected to one of the electrodes of the individual capacitor, and the other electrode disposed opposite to the one electrode, and the capacitance is smaller than the individual capacitor, The dedicated capacitor has one electrode and another electrode arranged opposite to the one electrode and connected to the other electrode of the small capacitor, and has a smaller capacitance than the individual capacitor. Such as the solid-state imaging device of claim 10, which has: A common determination unit that determines whether the difference between the first electrode and the second voltage based on the subtraction result of the common subtraction unit exceeds a specific threshold; and A resetting unit that resets at least any one of the plurality of photoelectric conversion elements, the plurality of current-voltage conversion units, and the plurality of individual subtracting units when the common determination unit determines that the difference exceeds the threshold value The action of the person. Such as the solid-state imaging device of claim 10, which has: A shared pixel, which has the above-mentioned dedicated capacitor and the above-mentioned shared subtraction unit; and The pixel block has the above-mentioned common pixel and the above-mentioned plurality of individual pixels. Such as the solid-state imaging device of claim 12, where The common pixel has: a common photoelectric conversion element that photoelectrically converts incident light to generate a current; and a common current-voltage conversion section that converts the current input from the common photoelectric conversion element into a voltage, and outputs the voltage to One of the electrodes of the above dedicated capacitor; and The common photoelectric conversion element is connected to the photoelectric conversion element provided in one individual pixel of the plurality of individual pixels. Such as the solid-state imaging device of claim 10, wherein The common subtraction unit is arranged in an area different from the pixel area in which the plurality of individual pixels are arranged. Such as the solid-state imaging device of claim 10, which has: The first common switch is set to cut off the other electrode of the plurality of small capacitors and the other electrode of the dedicated capacitor; A large capacitor, which is connected in parallel to the above-mentioned common capacitor and has a capacitance greater than the above-mentioned common capacitor; and The second common switch is connected in series to the large capacitor and connected in parallel to the common capacitor. Such as the solid-state imaging device of claim 7, which has: The individual subtraction units are respectively connected to the plurality of current-voltage conversion units, and the connected current-voltage conversion units can input one voltage minus another voltage at different timings. Such as the solid-state imaging device of claim 8, wherein A plurality of the above-mentioned adding capacitors have mutually different capacitances. Such as the solid-state imaging device of claim 17, wherein The addition unit has: a switch unit configured to individually cut off the plurality of current-voltage conversion units from the common subtraction unit; and The switch section has at least one of: a switch provided between one electrode of the individual capacitor and one electrode of the plurality of adding capacitors, and a switch provided between the other electrode of the adding capacitor and the common subtracting section. Such as the solid-state imaging device of claim 17, which has: A pixel block, which is composed of a plurality of pixels each having the photoelectric conversion element and the current-voltage conversion unit; and In the above-mentioned pixel block, the above-mentioned pixels connected to the above-mentioned adding capacitor with the same capacitance are arranged in a specific pattern.

Images