TW202101799A - Memory cell - Google Patents

Abstract

Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.

Description

Memory unit

The embodiment of the present invention relates to a memory unit.

Flash memory is a widely used type of non-volatile memory. However, it is expected that flash memory will experience scaling difficulties. Therefore, alternative types of non-volatile memory are being studied. One of the alternative types of these non-volatile memories is phase change memory (PCM). PCM is a type of non-volatile memory that uses the phase of PCM to represent the data unit. PCM has fast read and write time, non-destructive read and high scalability.

A memory cell according to an embodiment of the present invention includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etch stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etch stop layer and is in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer.

A method of forming a memory cell according to an embodiment of the present invention includes: forming a bottom electrode in a dielectric layer; forming an etch stop layer on the dielectric layer to cover the bottom electrode; and forming a stacked structure on the etch stop layer , Wherein the stacked structure includes a plurality of first layers and a plurality of second layers stacked alternately; a first opening is formed in the stacked structure to expose the etch stop layer; and the plurality of first layers are removed from The inner side walls of the plurality of first layers are recessed laterally; by using the stacked structure as a mask, removing a part of the etch stop layer to form a second opening exposing the bottom electrode; removing the stacked structure; A first variable resistance layer is formed in the second opening; and a top electrode is formed on the first variable resistance layer.

A semiconductor device with a memory cell according to an embodiment of the present invention includes a substrate, a first interconnection structure, a memory cell, and a second interconnection structure. The first interconnection structure is arranged on the substrate. The memory unit is arranged on the first interconnection structure. The memory cell includes a bottom electrode, an etch stop layer, a variable resistance layer, and a top electrode. The bottom electrode is electrically connected to the first interconnection structure. The etch stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etch stop layer and is in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. The second interconnection structure is disposed on the memory cell and electrically connected to the top electrode.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of the first feature on or on the second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include An embodiment in which an additional feature is formed with the second feature so that the first feature and the second feature may not directly contact. In addition, the present disclosure may repeat reference numerals and/or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself prescribe the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, examples such as “beneath”, “below”, “lower”, “above”, and “below The spatial relative terms of "upper" and the like describe the relationship between one element or feature and another element or feature as shown in each figure. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatial relative descriptors used in this article can also be interpreted accordingly.

The embodiments discussed herein can be discussed in a specific context, that is, a method of forming a memory cell, the method including filling the opening of the etch stop layer with a variable resistance layer. In this case, the sidewall of the variable resistance layer is protected by the etch stop layer from damage induced by the plasma caused by the dry etching process. Therefore, the native properties and characteristics of the deposited variable resistance layer can be maintained to enhance the performance and yield of the memory cell.

1A to 1G are cross-sectional views of a method of forming a semiconductor device with a memory cell according to an embodiment. The memory cell shown in the following embodiments can be applied to (but not limited to) a phase change random access memory (PCRAM) cell, which is hereinafter referred to as a PCM cell.

1A, a method of forming a semiconductor device 10 (as shown in FIG. 1G) with a memory cell 200 includes the following steps. First, the initial structure shown in FIG. 1A is set. The initial structure includes a first interconnect structure 110, a first dielectric layer 202, a second dielectric layer 204, and a bottom electrode 206.

In detail, the first interconnect structure 110 may include an insulating layer 115 and a conductive layer 116 disposed in the insulating layer 115. In some embodiments, the insulating layer 115 is called an inter-metal dielectric (IMD) layer, which can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, spin-on dielectric Materials or low-k dielectric materials. It should be noted that low-k dielectric materials are generally dielectric materials having a dielectric constant lower than 3.9. The conductive layer 116 may be a conductive wire, and the conductive layer 116 may include commonly used conductive materials, such as metals or metal alloys containing one or more of Al, AlCu, Cu, Ti, TiN, W, and the like. The conductive layer 116 forms a part of a current driving circuit (not shown) for supplying current to the PCM cell described later.

As shown in FIG. 1A, the first dielectric layer 202 and the second dielectric layer 204 are sequentially stacked on the first interconnect structure 110 to cover the conductive layer 116. The bottom electrode 206 is disposed in the first dielectric layer 202 and the second dielectric layer 204 to contact the conductive layer 116. In some embodiments, the top surface of the bottom electrode 206 is exposed through the second dielectric layer 204. In some embodiments, the first dielectric layer 202 and the second dielectric layer 204 have different materials. For example, the first dielectric layer 202 includes a silicon carbide (SiC) layer and the second dielectric layer 204 includes a silicon-rich oxide layer. In some alternative embodiments, the first dielectric layer 202 and the second dielectric layer 204 have different etch selectivities. In this case, the first dielectric layer 202 may be referred to as an etch stop layer to prevent the underlying conductive layer 116 from being damaged by over-etching.

In some embodiments, the bottom electrode 206 is formed by a single damascene process including the following steps. First, openings are formed in the first dielectric layer 202 and the second dielectric layer 204 to expose a part of the conductive layer 116. Next, the opening is filled with a conductive material. After that, a planarization process (for example, a CMP process) is performed to remove excess conductive material, thereby forming the bottom electrode 206. In some embodiments, the bottom electrode 206 includes a conductive material, such as Ti, Co, Cu, AlCu, W, TiN, TiW, TiAl, TiAlN, Ru, RuO _x, or a combination thereof. In some alternative embodiments, the bottom electrode 206 is referred to as a heater that is electrically coupled to or in contact with the conductive layer 116. The heater is configured to generate heat proportional to the current applied to the heater. In this case, the heater may be made of titanium nitride (TiN), titanium carbide (TiC), tungsten nitride (WN), some other high resistance material, Ru, RuO _x, or a combination thereof. In addition, the heater may have a circular, square or rectangular profile in the top view.

1B, an etch stop layer 208 is formed on the second dielectric layer 204 to cover the bottom electrode 206. In some embodiments, the etch stop layer 208 covers and contacts the top surface of the bottom electrode 206. In some embodiments, the etch stop layer 208 includes SiC, SiN, SiON, HfO _x , ZrO _x , LaO _x or a combination thereof. The etch stop layer 208 may be formed by any suitable method, such as chemical vapor deposition (CVD).

Next, the stacked structure 220 is formed on the etch stop layer 208 by any suitable method, such as CVD. As shown in FIG. 1B, the stacked structure 220 may include a plurality of first layers 222a, a first layer 222b, a first layer 222c (collectively referred to as a "first layer 222"), and a plurality of second layers 224a that are alternately stacked. , The second layer 224b, the second layer 224c (collectively referred to as the "second layer 224"). Although only three first layers 222 and three second layers 224 are shown in FIG. 1B, embodiments of the present disclosure are not limited thereto. In other embodiments, the number of the first layer 222 and the second layer 224 is adjusted as needed, for example, one first layer, two first layers, four first layers, or more first layers. The number of second layers corresponds to the number of first layers.

In some embodiments, the first layer 222a, the first layer 222b, and the first layer 222c have different thicknesses. For example, the first layer 222a has a first thickness T1, the first thickness T1 is greater than the second thickness T2 of the first layer 222b, and the first layer 222c has a second thickness T2, and the second thickness T2 is less than or substantially equal to the first thickness T2. The second thickness T2 of the layer 222b is the third thickness T3. That is, T1>T2≧T3. The first thickness T1 may be 300 nm to 500 nm, the second thickness T2 may be 200 nm to 300 nm, and the third thickness T3 may be 100 nm to 200 nm. In some alternative embodiments, the second layer 224a, the second layer 224b, and the second layer 224c may have substantially the same thickness. However, the embodiments of the present disclosure are not limited thereto, and in other embodiments, the second layer 224a, the second layer 224b, and the second layer 224c may have different thicknesses. In some embodiments, the first layer 222 and the second layer 224 have different thicknesses. For example, the thickness of one of the first layers 222 may be greater than the thickness of one of the second layers 224. On the other hand, the thickness of one of the first layers 222 may be less than the thickness of one of the second layers 224.

The first layer 222 and the second layer 224 may have different materials. For example, the first layer 222 is a silicon oxide (SiO) layer and the second layer 224 is a silicon nitride (SiN) layer. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the first layer 222 and the second layer 224 have materials with different etching selectivities. In some embodiments, the first layer 222 includes SiO _x , TEOS oxide, thermal oxide, or a combination thereof. The second layer 224 may include SiN _x or Si ₃ N ₄ .

Referring to FIGS. 1B and 1C, the first opening 225 is formed in the stack structure 220. In some embodiments, a photoresist pattern is formed on the stack structure 220, and then a first etching process is performed by using the photoresist pattern as an etching mask to remove a part of the stack structure 220, so as to form the first opening 225. In some embodiments, the first etching process includes a dry first etching process, such as a reactive ion etching (RIE) process. In this case, as shown in FIG. 1C, the first opening 225 penetrates the stack structure 220 and exposes the top surface 208t of the etch stop layer 208. In some alternative embodiments, the etch stop layer 208 and the stacked structure 220 (including the first layer 222 and the second layer 224) have different etch selectivities. That is, during the first etching process, the stacked structure 220 has an etching rate greater than the etching rate of the etching stop layer 208. Therefore, the etch stop layer 208 is not removed or a small amount of the etch stop layer 208 is removed, and most of the stack structure 220 is removed. In addition, in some embodiments, after the first opening 225 is formed, the inner sidewall 222s of the first layer 222 and the inner sidewall 224s of the second layer 224 are substantially aligned.

1C and 1D, the first layer 222 is recessed laterally through the first opening 225 by using a second etching process. In some embodiments, the portion of the first layer 222 exposed through the first opening 225 is removed, and therefore, as shown in FIG. 1D, a plurality of gaps G1, G2, and G3 are formed in the etch stop layer 208 and Between two adjacent ones of the second layer 224. In some embodiments, the second etching process includes a wet etching process by using a suitable etchant, such as a dilute HF solution. The dilute HF solution may include a dilution ratio of about 100:1 to about 500:1, such as 100:1, 200:1, 300:1, 400:1, or 500:1. Other chemical etchants may also be used depending on the material of the first layer 222. The second etching process can be performed at room temperature for 30 seconds to 3000 seconds. In this case, the uppermost first layer 222c is in contact with the etchant for a longer time than the lower first layer 222b, and therefore the removal amount of the uppermost first layer 222c is greater than the removal of the lower first layer 222b the amount. Similarly, the removal amount of the first layer 222b is greater than the removal amount of the underlying first layer 222a. Therefore, as shown in FIG. 1D, the gap G3 has a depth D3 greater than the depth D2 of the gap G2, and the gap G1 has a depth D1 less than the depth D2 of the gap G2. In other words, the depth D1, the depth D2, and the depth D3 gradually increase from bottom to top, that is, D1>D2>D3. Here, the depth D1, the depth D2, and the depth D3 are respectively measured from the inner sidewall 224s of one second layer 224 to the inner sidewall 222s' of the corresponding first layer 222. In other words, the distance (for example, the depth D1, the depth D2, and the depth D3) are respectively formed between the inner sidewall 224s of one second layer 224 and the inner sidewall 222s' of the corresponding first layer 222, and therefore the distance of the first layer 222 The inner sidewall 222s' is not aligned with the inner sidewall 224s of the second layer 224. In addition, in some alternative embodiments, the etch stop layer 208 and the first layer 222 have different etch selectivities. That is, during the second etching process, the first layer 222 has an etching rate greater than the etching rate of the etching stop layer 208. Therefore, the etch stop layer 208 is not removed or a small amount of the etch stop layer 208 is removed, and most of the first layer 222 is removed.

1D and 1E, the second opening 227 is formed by removing a part of the etch stop layer 208. In some embodiments, the third etching process is performed on the etch stop layer 208 to form the second opening 227 by using the stack structure 220 as a mask. As shown in FIG. 1E, the second opening 227 communicates with the first opening 225 and is disposed under the first opening 225. The second opening 227 exposes the top surface 206 t of the bottom electrode 206 and a part of the second dielectric layer 204. In some embodiments, the third etching process includes a dry etching process, such as a reactive ion etching (RIE) process. The second opening 227 has a sidewall 227s substantially aligned with the sidewall S1 of the gap G1. In other embodiments, the second opening 227 is referred to as a containment space for disposing the memory element 210 (as shown in FIG. 1F) to be formed.

Referring to FIG. 1F, a filling material 213 is formed on the portion of the structure shown in FIG. 1E. In some embodiments, the filling material 213 includes a two-layer structure having a first filling layer 213a and a second filling layer 213b on the first filling layer 213a. The first filling layer 213a may include a variable resistance layer. The second filling layer 213b may include a conductive layer. In some embodiments, the filling material 213 is formed by a deposition method, such as physical vapor deposition (PVD), atomic layer deposition (ALD) or the like. During the deposition process, a part of the filling material 213 is filled in the second opening 227 to form the first pattern 210, and the other part of the filling material 213 is formed on the sidewall of the stacked structure 220 to form a plurality of second patterns 211. In some embodiments, the first pattern 210 may have a top surface 210t that is substantially coplanar or lower than the top surface 208t of the etch stop layer 208. In some embodiments, since the gap G1, the gap G2, and the gap G3 are small enough and are respectively sandwiched by the adjacent second layer 224, the filling material 213 is not easy to fill the gap G1, the gap G2, and the gap G3. Therefore, as shown in FIG. 1F, the second patterns 211 are respectively formed on the inner sidewalls 224s of the second layer 224 and the top surface of the stack structure 220 (ie, the top surface 224t of the uppermost second layer 224c), and It is not filled in the gap G1, the gap G2, and the gap G3. In some embodiments, the thickness 211t1 of the second pattern 211 on the inner sidewall 224s of the second layer 224c is smaller than the thickness 211t2 of the second pattern 211 on the top surface 224t of the second layer 224c. In some embodiments, the second pattern 211 has the same thickness respectively disposed on the inner sidewalls 224s of the second layer 224a, the second layer 224b, and the second layer 224c. In some embodiments, since the second pattern 211 and the first pattern 210 are separated from each other, the second pattern 211 and the first pattern 210 are collectively referred to as an automatic separation pattern or a self-aligned pattern. In addition, the pattern can be formed without the lithography step and the etching step, thereby saving process cost. In some alternative embodiments where the second patterns 211 are separated from each other, parts of the second patterns 211 may also extend into the gaps G1, G2, and G3 to cover parts of the top and bottom surfaces of the second layer 224.

1F and 1G, a lift-off process is performed to remove the second pattern 211 on the second layer 224 of the stacked structure 220 and the stacked structure 220. In this case, the etch stop layer 208 is exposed. In some embodiments, the lift-off process includes a wet etching process by using a suitable etchant, such as a dilute HF solution. In detail, the dilute HF solution may include a dilution ratio of about 100:1 to about 500:1, such as 100:1, 200:1, 300:1, 400:1, or 500:1. Other chemical etchants may also be used depending on the material of the first layer 222. The peeling process can be performed at room temperature for 30 seconds to 3000 seconds. In some embodiments, since the filling material 213 does not cover the inner sidewall 222s′ of the first layer 222a, the first layer 222a is easily removed during the peeling process, thereby removing the entire stack structure 220.

As shown in FIG. 1G, the semiconductor device 10 with the memory cell 200 is completed after the peeling process is performed. Specifically, the memory cell 200 may include a bottom electrode 206, an etch stop layer 208 on the bottom electrode 206, and a first pattern 210 embedded in the etch stop layer 208. In some embodiments, the first pattern 210 is referred to as a memory element (hereinafter referred to as “memory element 210”), and the memory element includes at least a variable resistance layer 212 and a top electrode 214. Although the memory device 210 shown in FIG. 1G has a two-layer structure, the memory device 210 may have a single-layer structure (for example, a variable resistance layer) or a multilayer structure, such as a three-layer structure. For example, the memory device 210 is one of the memory device 210a to the memory device 210g of FIGS. 2A to 2G, and the details thereof will be described below.

In some embodiments, as shown in FIG. 1G, the memory device 210 includes a variable resistance layer 212 and a top electrode 214 on the variable resistance layer 212. The variable resistance layer 212 may have a top surface 212t lower than the top surface 208t of the etch stop layer 208. The top electrode 214 has a top surface 214t that is substantially flush with or lower than the top surface 208t of the etch stop layer 208.

In one embodiment, when the memory cell 200 is a PCM cell, the variable resistance layer 212 includes a phase change material. The phase change material may include chalcogenide materials, such as indium (In)-antimony (Sb)-tellurium (Te) (indium-antimony-tellurium; IST) material or germanium (Ge)-antimony (Sb)-tellurium (Te) (Germanium-antimony-tellurium; GST) material. The ISG material may include In ₂ Sb ₂ Te ₅ , In ₁ Sb ₂ Te ₄ , In ₁ Sb ₄ Te ₇ or the like. The GST material may include Ge ₈ Sb ₅ Te ₈ , Ge ₂ Sb ₂ Te ₅ , Ge ₁ Sb ₂ Te ₄ , Ge ₁ Sb ₄ Te ₇ , Ge ₄ Sb ₄ Te ₇ , Ge ₄ SbTe ₂ , Ge ₆ SbTe ₂ or the like Things. The hyphenated chemical composition symbol as used herein indicates an element contained in a particular mixture or compound, and is intended to represent all stoichiometric quantities related to the indicated element. For example, other phase change materials may include Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb- Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd and Ge-Te- Sn-Pt. Other resistance variable materials include transition metal oxide materials or alloys including two or more metals such as transition metals, alkaline earth metals, and/or rare earth metals. The embodiments are not limited to one or more specific variable resistance materials associated with the memory elements of the PCM cell. In some alternative embodiments, variable resistance materials are used to form resistive random access memory (RRAM) cells, magnetoresistive random access memory (MRAM) cells, and ferroelectric random access memory (RRAM) cells. Access memory (ferroelectric random access memory; FeRAM) unit or a combination of memory elements. That is, the variable resistance material may include binary metal oxide materials, colossal magnetoresistance materials, and/or various polymer resistance variable materials, or the like.

In some embodiments, the top electrode 214 includes a conductive material, such as Ti, Co, Cu, AlCu, W, TiN, TiW, TiAl, TiAlN, or a combination thereof. The top electrode 214 and the bottom electrode 206 may have the same material or different materials. For example, both the top electrode 214 and the bottom electrode 206 are made of TiN.

When the variable resistance layer 212 is a phase change material layer (hereinafter referred to as the PCM layer 212), the PCM layer 212 has a variable phase representing a data bit. For example, the PCM layer 212 has an interchangeable crystalline phase and an amorphous phase. The crystalline phase and the amorphous phase may respectively represent binary "1" and binary "0", or vice versa. Therefore, the PCM layer 212 has a variable resistance that changes with the variable phase of the PCM layer 212. For example, the PCM layer 212 has high resistance in the amorphous phase and low resistance in the crystalline phase.

In the operation of the PCM cell 200, the data state of the PCM cell 200 is read by measuring the resistance of the PCM cell 200 (ie, the resistance from the bottom electrode 106 to the top electrode 214). The phase of the PCM layer 212 represents the data state of the PCM cell 200, the resistance of the PCM layer 212, or the resistance of the PCM cell 200. In addition, the data state of the PCM cell 200 can be set and reset by changing the phase of the PCM layer 212.

In some embodiments, the phase of the PCM layer 212 is changed by heating. For example, the bottom electrode (or heater) 106 heats the PCM layer 212 to a first temperature that induces the crystallization of the PCM layer 212, so as to change the PCM layer 212 to a crystalline phase (for example, to set the PCM cell 200). Similarly, the bottom electrode (or heater) 106 heats the PCM layer 212 to a second temperature that melts the PCM layer 212 so as to change the PCM layer 212 to an amorphous phase (for example, to reset the PCM cell 200). The first temperature is lower than the second temperature. In some embodiments, the first temperature is 100°C to 200°C and the second temperature is 500°C to 800°C.

The amount of heat generated by the bottom electrode 106 changes in proportion to the current applied to the bottom electrode 106. That is, the PCM layer 212 is heated to a temperature higher than the melting temperature when the current passes through the PCM layer 212 (ie, the second temperature). Then the temperature quickly drops below the crystallization temperature. In this case, a part of the contact bottom electrode 106 of the PCM layer 212 changes to an amorphous state having a high resistivity, and thus the state of the PCM cell 200 changes to a high resistance state. Then, the part of the PCM layer 212 may be reset back to the crystalline state by heating the PCM layer 212 to a temperature higher than the crystallization temperature and lower than the melting temperature (ie, the first temperature) for a certain period of time.

Based on the above, it is well known that the PCM layer 212 is a key layer for operating the PCM unit 200. In this embodiment, the PCM layer 212 is formed by filling the second opening 227 with a phase change material. Therefore, the sidewall 212s of the PCM layer 212 is protected by the etch stop layer 208 and the top surface 212t of the PCM layer 212 is protected by the top electrode 214. For example, during the sequential etching process, the sidewalls 212s and the top surface 212t of the PCM layer 212 are protected from damage induced by the plasma. In particular, the sidewall 212s of the PCM layer 212 may be in contact with the etch stop layer 208 (directly or physically), and therefore, there is no etching residue sandwiched between the PCM layer 212 and the etch stop layer 208.

Conventionally, when the PCM layer is patterned through an etching process, the properties of the PCM layer are undesirably changed due to process deviations. For example, the etched PCM layer has different atomic ratios at the central part and the peripheral part, and some undesirable etching residues remain on the sidewalls of the etched PCM layer, or the sidewalls of the etched PCM layer are uneven And damaged. In other words, it is not easy to maintain the properties of the PCM layer in the original design. On the contrary, in some embodiments, since the PCM layer 212 is formed by filling the opening (for example, the second opening 227) without going through other processes such as an etching process, the PCM layer 212 can maintain the native film properties to conform to the initial design. In some embodiments, the PCM layer 212 is divided into a central part CP and a peripheral part PP surrounding the central part CP, and the central part CP and the peripheral part PP may have the same atomic ratio. Herein, the term "atomic ratio" refers to a measurement of the ratio of one kind of atoms to another kind of atoms. For example, when the PCM layer 212 is made of Ge ₂ Sb ₂ Te ₅ , the atomic ratios of Ge, Sb, and Te in the central part CP and the peripheral part PP are all 2:2:5 as originally designed. In other words, by being formed in the opening, the properties of the PCM layer 212 are not affected by process variations and can be maintained, thereby enhancing the performance and yield of the memory cell.

FIG. 2A shows a memory cell 200a having a memory element 210a. The memory element 210a is similar to the memory element 210 of FIG. 1G, that is, the structure, material, and function of the memory element 210a are similar to the structure, material, and function of the memory element 210, and therefore the details are omitted herein. The main difference between the memory device 210a and the memory device 210 is that the top surface 212t of the variable resistance layer 212a and the top surface 208t of the etch stop layer 208 are substantially coplanar. Therefore, the top surface 214t of the top electrode 214 is higher than the top surface 208t of the etch stop layer 208.

FIG. 2B shows a memory cell 200b with a memory element 210b. The arrangement and material of the memory unit 200b are similar to the arrangement and material of the memory unit 200, and therefore its details are omitted herein. The main difference between the memory cell 200 b and the memory cell 200 is that the memory cell 200 b has a selector 216 on the top electrode 214. In some embodiments, the selector 216 includes an ovonic threshold switch (OTS) material. The OTS material may include a chalcogenide material that responds to the voltage applied on the selector 216. For an applied voltage that is less than the threshold voltage, the selector 216 is maintained in an "off" state (for example, a non-conductive state). Or, in response to the applied voltage on the selector 216 that is greater than the threshold voltage, the selector 216 enters an "on" state, such as a conductive state. That is, the selector 216 is called a switch for determining whether to turn on or turn off the memory unit 200b. In some alternative embodiments, the chalcogenide material of the OTS material is different from the chalcogenide material of the variable resistance layer 212.

FIG. 2C shows a memory cell 200c having a memory element 210c. The arrangement and material of the memory unit 200c are similar to the arrangement and material of the memory unit 200a, and therefore the details thereof are omitted herein. The main difference between the memory cell 200c and the memory cell 200a is that the memory cell 200c has a selector 216 on the top electrode 214. In some embodiments, the selector 216 is similar to the selector 216 of FIG. 2B, and therefore its details are omitted herein.

FIG. 2D shows a memory cell 200d having a memory element 210d. The arrangement and material of the memory unit 200d are similar to the arrangement and material of the memory unit 200, and therefore the details thereof are omitted herein. The main difference between the memory cell 200 d and the memory cell 200 is that the variable resistance layer 212 b of the memory cell 200 d further extends into the second dielectric layer 204. In this case, as shown in FIG. 2D, a part of the variable resistance layer 212b is embedded in the second dielectric layer 204 and protected by the second dielectric layer 204. That is because the second opening 227a extends down into the second dielectric layer 204 during the third etching process shown in FIG. 1E. In other words, during the third etching process, the etching stop layer 208 and the second dielectric layer 204 are all removed. Therefore, the second opening 227a has a bottom surface 227bt lower than the bottom surface 208bt of the etch stop layer 208, as shown in FIG. 2D. Therefore, the memory device 210d also has a bottom surface 210bt lower than the bottom surface 208bt of the etch stop layer 208.

FIG. 2E shows a memory cell 200e having a memory element 210e. The arrangement and material of the memory unit 200e are similar to the arrangement and material of the memory unit 200a, and therefore the details thereof are omitted herein. The main difference between the memory cell 200e and the memory cell 200a is that the variable resistance layer 212c of the memory cell 200e further extends into the second dielectric layer 204. Therefore, the memory element 210e has a bottom surface 210bt lower than the bottom surface 208bt of the etch stop layer 208.

FIG. 2F shows a memory cell 200f having a memory element 210f. The arrangement and material of the memory cell 200f are similar to the arrangement and material of the memory cell 200d, and thus the details thereof are omitted herein. The main difference between the memory cell 200f and the memory cell 200d is that the memory cell 200f has a selector 216 on the top electrode 214. In some embodiments, the selector 216 is similar to the selector 216 of FIG. 2B, and therefore its details are omitted herein.

FIG. 2G shows a memory cell 200g with a memory element 210g. The arrangement and material of the memory unit 200g are similar to the arrangement and material of the memory unit 200e, and therefore the details thereof are omitted herein. The main difference between the memory cell 200 g and the memory cell 200 e is that the memory cell 200 g has a selector 216 on the top electrode 214. In some embodiments, the selector 216 is similar to the selector 216 of FIG. 2B, and therefore its details are omitted herein.

FIG. 3 is a cross-sectional view of a semiconductor device having a memory cell according to another embodiment. The memory unit shown in the following embodiments is applied to (but not limited to) the PCM unit. The structure, materials, and manufacturing process may be similar to those depicted in FIG. 1G and discussed with reference to FIG. 1G. Therefore, the details are not repeated in this article.

3, the semiconductor device 20 may include a substrate 100, a device region 102, a first interconnect structure 110, a memory cell 200, and a second interconnect structure 120. In some embodiments, the substrate 100 is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 100 may be doped (for example, with a p-type dopant or an n-type dopant) or undoped. The substrate 100 may be a wafer, such as a silicon wafer. Generally speaking, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer is, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate (usually a silicon or glass substrate). Other substrates can also be used, such as multilayer or gradient substrates. In some embodiments, the substrate 100 includes: device semiconductors, such as silicon or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors, such as SiGe , GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and GaInAsP, or combinations thereof.

In some embodiments, the device area 102 is disposed on the substrate 100 in a front-end-of-line (FEOL) process. The device area 102 may include a wide variety of devices. In some alternative embodiments, the device includes active elements, passive elements, or combinations thereof. In some other embodiments, the device includes an integrated circuit device. The device is, for example, a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse device, or other similar devices. In an embodiment, the device region 102 includes a gate structure, source and drain regions, and an isolation structure (not shown) such as a shallow trench isolation (STI) structure. In the device area 102, various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices (such as electrical Crystals or memory and the like) can be formed and interconnected to perform one or more functions. Other devices (such as capacitors, resistors, diodes, photodiodes, fuses, and the like) can also be formed on the substrate 100. The function of the device may include memory, processor, sensor, amplifier, power distribution, input/output circuit, or the like.

As shown in FIG. 3, the first interconnection structure 110 is disposed on the device area 102, and the device area 102 is disposed between the substrate 100 and the first interconnection structure 110. In addition to the insulating layer 115 and the conductive layer 116 shown in FIG. 1G, the first interconnect structure 110 further includes an insulating layer 111, an insulating layer 113, a via 112, and a conductive layer 114. The via 112 is disposed on the device area 102 and is electrically connected to the device area 102. The conductive layer 114 is disposed on the via hole 112 and electrically connected to the via hole 112. The insulating layer 111 and the insulating layer 113 are collectively referred to as an IMD layer, and the IMD layer wraps the via 112 and the conductive layer 114 laterally.

The memory cell 200 and the second interconnection structure 120 are sequentially stacked on the first interconnection structure 110. The memory unit 200 is disposed between the first interconnect structure 110 and the second interconnect structure 120 and is electrically connected to the first interconnect structure 110 and the second interconnect structure 120. Specifically, the bottom electrode 206 is in contact with the conductive layer 116 and is electrically connected to the conductive layer 116, and the top electrode 214 is in contact with the via hole 122 and is electrically connected to the via hole 122. The conductive layer 116 and the via 122 can provide current to make the memory element 210 conductive. In one embodiment, the width 210w of the memory element 210 is greater than the width 206w of the bottom electrode 206. The ratio of the width 210w to the width 206w may be 100 to 20. It should be noted that although the memory unit 200 is shown in FIG. 3, embodiments of the present disclosure are not limited thereto. In other embodiments, one of the memory unit 200a to the memory unit 200g is used instead of the memory unit 200.

The second interconnect structure 120 may include a first insulating layer 121, a second insulating layer 123, a via 122 and a conductive layer 124. The first insulating layer 121 is disposed on the memory cell 200 to cover the memory element 210. The via 122 is disposed in the first insulating layer 121 to be electrically connected to the memory element 210. The second insulating layer 123 is disposed on the first insulating layer 121. The conductive layer 124 is disposed in the second insulating layer 123. The conductive layer 124 is in contact with the via hole 122 and is electrically connected to the via hole 122. In some embodiments, the insulating layer 121 and the insulating layer 123 are collectively referred to as an intermetal dielectric (IMD) layer, and the intermetal dielectric layer is made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, Spin-on dielectric materials or low-k dielectric materials. The IMD layer is in contact (directly or physically) with the top surface 210t of the memory device 210. The conductive layer 124 may be a conductive wire, and the conductive layer 124 may include a metal or a metal alloy including one or more of Al, AlCu, Cu, Ti, TiN, W, or the like. The conductive layer 124 is a part of a current driving circuit (not shown) used to provide current to the memory cell 200. In some embodiments, the via 122 and the conductive layer 124 are formed by a dual damascene process. That is, the via hole 122 and the conductive layer 124 may be formed at the same time.

In some embodiments, the conductive layer 114 is called metal 1 (M1), the conductive layer 114 is called metal n-1 (Mn-1), and the conductive layer 124 is called metal n (Mn). The memory cell 200 may be placed between Mn and Mn-1. That is, the memory cell 200 can be disposed between any two adjacent conductive layers in a back-end-of-line (BEOL) structure. For example, the memory unit 200 is placed between M2 and M3, between M3 and M4, and so on. Therefore, the manufacturing process of the memory cell is compatible with the BEOL process of the semiconductor device, thereby simplifying the process steps and efficiently increasing the integration density. In some alternative embodiments, the memory cell 200 and Mn-1 are at the same height. In addition, one or more conductive layers may be further disposed between M1 and Mn-1.

According to some embodiments, the memory cell includes a bottom electrode, an etch stop layer, a variable resistance layer, and a top electrode. The etch stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etch stop layer and is in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer.

In some embodiments, the top electrode is embedded in the etch stop layer.

In some embodiments, the sidewall of the top electrode is aligned with the sidewall of the variable resistance layer.

In some embodiments, the top surface of the variable resistance layer is lower than or substantially flush with the top surface of the etch stop layer.

In some embodiments, the memory cell further includes a dielectric layer laterally wrapping the bottom electrode, wherein a part of the variable resistance layer extends into the dielectric layer.

In some embodiments, the variable resistance layer includes a central part and a peripheral part, and the central part and the peripheral part have the same atomic ratio.

In some embodiments, the variable resistance layer includes germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) material or indium (In)-antimony (Sb)-tellurium (Te) (IST) material .

In some embodiments, the memory unit further includes a selector disposed on the top electrode.

In some embodiments, the selector includes a bidirectional threshold switch (OTS) material.

In some embodiments, the memory cell includes a phase change random access memory (PCRAM) cell, a resistive random access memory (RRAM) cell, a magnetoresistive random access memory (MRAM) cell, a ferroelectric random access Memory (FeRAM) unit or its combination.

According to some embodiments, a method of forming a memory cell includes: forming a bottom electrode in a dielectric layer; forming an etch stop layer on the dielectric layer to cover the bottom electrode; and forming a stack structure on the etch stop layer , Wherein the stacked structure includes a plurality of first layers and a plurality of second layers alternately stacked; a first opening is formed in the stacked structure to expose the etch stop layer; and the plurality of first layers The inner side walls of the plurality of first layers are recessed laterally; by using the stacked structure as a mask, removing a part of the etch stop layer to form a second opening exposing the bottom electrode; removing the stacked structure; A first variable resistance layer is formed in the second opening; and a top electrode is formed on the first variable resistance layer.

In some embodiments, the forming the filling material includes forming a variable resistance material and a top electrode material on the variable resistance material.

In some embodiments, the plurality of first layers and the plurality of second layers have different thicknesses.

In some embodiments, the thickness of the plurality of first layers gradually decreases in a direction from the bottom electrode to the first pattern.

In some embodiments, after the plurality of first layers are recessed, a plurality of gaps are respectively formed between the plurality of second layers, and the depth of the plurality of gaps extends from the bottom electrode to The direction of the first pattern gradually increases.

In some embodiments, the plurality of first layers and the plurality of second layers have different etching selectivities for the etchant used in the step of recessing the plurality of first layers.

In some embodiments, the etch stop layer and the plurality of first layers have different etch selectivities for the etchant used in the step of removing the portion of the etch stop layer.

In some embodiments, the removing the stacked structure includes performing a lift-off process on the stacked structure to expose the etch stop layer.

According to some embodiments, a semiconductor device with a memory cell includes a substrate, a first interconnection structure, a memory cell, and a second interconnection structure. The first interconnection structure is arranged on the substrate. The memory unit is arranged on the first interconnection structure. The memory cell includes a bottom electrode, an etch stop layer, a variable resistance layer, and a top electrode. The bottom electrode is electrically connected to the first interconnection structure. The etch stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etch stop layer and is in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. The second interconnection structure is disposed on the memory cell and electrically connected to the top electrode.

In some embodiments, the semiconductor device with a memory cell further includes a selector disposed between the top electrode and the second interconnection structure.

The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purpose and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes herein without departing from the spirit and scope of the present disclosure. , Replacement and change.

10: Semiconductor device 100: base 102: Device area 106, 206: bottom electrode 110: The first internal connection structure 111, 113, 115: insulating layer 112, 122: Via hole 114, 116, 124: conductive layer 120: The second internal connection structure 121: first insulating layer 123: second insulating layer 200, 200a, 200b, 200c, 200d, 200e, 200f, 200g: memory unit 202: first dielectric layer 204: second dielectric layer 206t, 208t, 210t, 212t, 214t, 224t: top surface 206w, 210w: width 208: Etch stop layer 208bt, 210bt, 227bt: bottom surface 210, 210a, 210b, 210c, 210d, 210e, 210f, 210g: memory components 211: The second pattern 211t1, 211t2: thickness 212, 212a, 212b, 212c: variable resistance layer 212s, 227s, S1: sidewall 213: filling material 213a: the first filling layer 213b: second filling layer 214: Top electrode 216: selector 220: Stacked structure 222, 222a, 222b, 222c: first layer 222s, 222s', 224s: inner wall 224, 224a, 224b, 224c: second layer 225: The first opening 227, 227a: second opening CP: Central part D1, D2, D3: depth G1, G2, G3: gap M1: Metal 1 Mn: metal n Mn-1: Metal n-1 PP: Peripheral part T1: first thickness T2: second thickness T3: third thickness

Various aspects of the present disclosure can be best understood by reading the following specific embodiments in conjunction with the accompanying drawings. It should be noted that according to standard practices in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of each feature can be increased or decreased arbitrarily. 1A to 1G are cross-sectional views of a method of forming a semiconductor device with a memory cell according to an embodiment. 2A to 2G are cross-sectional views showing memory cells according to various embodiments. FIG. 3 is a cross-sectional view of a semiconductor device having a memory cell according to another embodiment.

10: Semiconductor device

110: The first internal connection structure

115: insulating layer

116: conductive layer

200: memory unit

202: first dielectric layer

204: second dielectric layer

206: bottom electrode

208: Etch stop layer

208t, 212t, 214t: top surface

210: memory component

212: Variable resistance layer

212s: sidewall

214: Top electrode

227: second opening

CP: Central part

PP: Peripheral part

Claims (1)

A memory unit, including: Bottom electrode An etch stop layer, arranged on the bottom electrode; A variable resistance layer embedded in the etch stop layer and in contact with the bottom electrode; and The top electrode is arranged on the variable resistance layer.

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