TW202101763A - Semiconductor device - Google Patents

Abstract

Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.

Description

Semiconductor device

The technology described in this disclosure relates generally to electronic systems, and more specifically to the use of partially buried insulator (BI) nano-sheet devices to increase the reading margin of electronic devices.

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a semiconductor device commonly used in both digital and analog circuits, including static random access memory (SRMA) devices. Metal oxide semiconductor field-effect transistors are commonly used to switch and amplify electronic signals in electronic devices. A typical metal oxide semiconductor field effect transistor includes source, drain, and gate electrodes. The energization of the gate electrode allows current to flow from the source to the drain through a channel area. The gate electrode is characterized by channel length and width. As electronic devices become smaller and smaller, the size of the channel length of the metal oxide semiconductor field effect transistor is reduced. However, because it is more difficult to control the channel area, such a reduction in channel length reduces the efficiency of the transistor.

Fin field effect transistors (FinFETs) are three-dimensional (3D) multi-gate metal oxide semiconductor field effect transistors that provide more control over the channel area. Using the fin-type field effect transistor design, a thin silicon fin is used as a channel, and the thin silicon fin is wrapped by a gate electrode. It is this 3-dimensional structure that promotes more control over the channel area. However, the reduction of the gate length can cause short channel effects, such as current leakage, surface scattering, velocity saturation, impact ionization, threshold voltage variations, and/or hot carrier effects.

Some embodiments of the present disclosure provide a semiconductor device including: a source region and a drain region, a buried insulator (BI) layer, and a first nanochip. The source region and the drain region are formed higher than the substrate. The buried insulator layer is formed under either the source region or the drain region and higher than the substrate. The first nanosheet is formed (i) between the source region and the drain region in the horizontal direction, and (ii) is higher than the buried insulator layer in the vertical direction.

The subsequent disclosure provides many different implementations or examples to achieve different features of the provided subject matter. Specific embodiments of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming the first feature on or on the second feature may include an embodiment in which the first and second features are formed by direct contact, and may also include additional features that may be formed on the first feature. And the second feature, so the first and second features may not be in direct contact. In addition, the present disclosure may repeat numbers and/or letters in each embodiment. Such repetition is for the sake of simplification and clarity, and does not mean the relationship between the various embodiments and/or configurations discussed.

In the fin-type field-effect transistor device, the reduction of the gate length will make the metal oxide semiconductor field-effect transistor vulnerable to many short-channel effects, such as current leakage, surface scattering, velocity saturation, impact ionization, critical voltage variation, And/or hot carrier effect. Nanochip devices can provide an alternative, which in some embodiments can have stronger gate controllability than fin-type field effect transistors. Generally, both fin-type field-effect transistors and nano-chip field-effect transistors use read/write auxiliary circuits, such as sense amplifiers, negative voltage bias circuits, and/or selective precharge circuits, to improve read performance. The devices and methods described herein include the use of partially buried insulator nanochip devices to eliminate the need for read auxiliary circuits.

Static random access memory devices are computer memory devices that are made of transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), and/or nanochip field effect Transistors (nano-sheet FETs). A plurality of static random access memory bit cells in an array can be combined with various control circuits to form a static random access memory macro. In the static random access memory macros, due to the use of fin-type field-effect transistors and/or nano-chip field-effect transistors, these devices are sensitive to current and may require additional read and/or write auxiliary circuits. The read margin is an index used to evaluate the read performance of static random access memory bit cells. The read margin can be characterized by a β-ratio, which is the ratio between multiple currents flowing through some transistors of the static random access memory bit cell. The higher the β ratio, the better the read operation performed by the static random access memory bit cell. When the β ratio is a low value, additional circuits can be used together with the static random access memory bit unit to improve the read performance of the static random access memory bit unit. More specifically, the read assist circuit can increase the read performance. The additional circuitry in turn means more space within the device that may or may not be feasible. In some embodiments, the device described herein includes a static random access memory bit cell with a part of multiple nano-chips, and a part of the multiple nano-chips enables the static random access memory bit cell to be readless Auxiliary static random access memory (read assist-free SRAM). Such a device includes a buried insulator layer and a nanochip. The buried insulator layer is below the source region or the drain region of the static random access memory bit cell. The nanochip connects the source region and the drain region to each other. Separated. In other words, the static random access memory bit cell described in some embodiments uses a buried insulator layer to increase the β ratio, eliminates the need for read auxiliary circuits and saves space within the device.

(1) 其中，I_PG 是通過與靜態隨機存取記憶體位元單元的位元線耦合的電晶體的電流，並且I_PD 是通過靜態隨機存取記憶體位元單元的反相器的另一個電晶體的電流，這兩者都在第2圖中詳細說明。因為埋入的絕緣體層120使I_PG 降低，所以I_PG 的數值小於I_PD 。較大的數目除以較小的數目導致了靜態隨機存取記憶體位元單元110的β比率為較大的數目。具有大的β比率，靜態隨機存取記憶體位元單元110的讀取效能為良好，並且不需附加的電路來輔助讀取效能。FIG. 1 is a top view of an exemplary part of a static random access memory device 100 according to various embodiments of the present disclosure. As shown in the figure, this part of the static random access memory device 100 includes a static random access memory bit cell 110. When the current I _PG flows across the gate 130, the current I _PG will decrease, so that the current I _{PG is} smaller than the current I _PD flowing through the gate 140. This reduction occurs in part because the buried insulator layer 120 is made of a dielectric material. Because of the lack of complete doped source/drain regions, this makeup reduces the number of ions within the device. Dielectric materials are insulating materials that inhibit the flow of current. In other words, the flow of current through the dielectric material is minimal. The β ratio of static random access memory bit cells can be expressed by the following equation:

(1) Among them, I _PG is the current through the transistor coupled with the bit line of the static random access memory bit cell, and I _PD is another electrical current through the inverter of the static random access memory bit cell. The crystal current, both of which are explained in detail in Figure 2. Since the buried insulator layer 120 so that I _PG decreased, so the value is less than I _PG I _PD. Dividing the larger number by the smaller number results in the β ratio of the static random access memory bit cell 110 being a larger number. With a large β ratio, the read performance of the static random access memory bit cell 110 is good, and no additional circuits are needed to assist the read performance.

FIG. 2 is a schematic illustration of the exemplary static random access memory bit cell 110 of FIG. 1 according to various embodiments of the present disclosure. The static random access memory bit cell 110 is six transistors with N-type metal oxide semiconductor (NMOS) transistors 210, 220, 230, 240, and P-type metal oxide semiconductor (PMOS) transistors 250, 260 (6T) Static random access memory. When power is supplied, the static random access memory bit unit 110 stores a single bit of information. Transistors 210 and 240 couple a pair of data lines (for example, bit lines BL/BLB) to storage nodes 215 and 235, respectively. The supply voltage VDD provides a positive voltage (for example, 0.6 to 3.0V) to the P-type metal oxide semiconductor transistors 250 and 260. The second supply voltage VSS can be set to ground or a negative voltage. According to the state of the static random access memory bit cell 110, the N-type metal oxide semiconductor transistors 220, 230 are coupled to the second supply voltage and to each other via the storage nodes 215, 235. The static random access memory bit cell 110 is a latch. As long as the power provided is sufficient to operate the components in the static random access memory bit cell 110, the static random access memory bit cell 110 will last indefinitely To maintain its data state. The P-type metal oxide semiconductor transistor 250 and the N-type metal oxide semiconductor transistor 220 together form a complementary metal oxide semiconductor (CMOS) inverter. The P-type metal oxide semiconductor transistor 260 and the N-type metal oxide semiconductor transistor 230 together form another complementary metal oxide semiconductor inverter. Two complementary metal oxide semiconductor inverters are cross-coupled and operated to continuously enhance the charge stored on the storage nodes 215, 235. The two storage nodes 215, 235 are inverted from each other. When the storage node 215 is a logic "1" (usually a high voltage), the storage node 235 is a logic "0" (usually a low voltage) at the same time, and vice versa. When the static random access memory bit cell 110 is written, the complementary write data signal is placed on the bit line BL/BLB. The positive control signal on the word line WL is coupled to the gates of both N-type metal oxide semiconductor transistors 210 and 240. The size of the N-type metal oxide semiconductor transistors 220, 230 and the P-type metal oxide semiconductor transistors 250, 260 should be set so that the data on the bit line BL/BLB can overwrite the stored data, and therefore write Static random access memory bit cell 110.

When a voltage is applied to the bit line BL/BLB, the static random access memory bit cell 110 is read. Once the voltage is applied to the bit line BL/BLB, the voltage is applied to the word line WL. One of the bit lines BL/BLB will be pulled down by the bit cell operation. This pull-down is facilitated by the electrical coupling of the bit line BL/BLB to the buried insulator layer 120, as described in more detail in FIG. 7. I _{PG is} defined as the current flowing through the N-type metal oxide semiconductor transistor 210. I _{PD is} defined as the current flowing through the N-type metal oxide semiconductor transistor 220. Because the current I _PG flows through the transistor 210, the current I _PG is electrically impacted by the buried insulator layer 120 and reduces the amperage. The current I _{PD is} greater than the current I _PG . Because of this, the β ratio of equation (1) is large, which means that no additional reading auxiliary circuit is required.

Figure 3 is a cross-sectional view of an exemplary nanochip transistor 300 that may be used in an exemplary static random access memory bit cell according to various embodiments of the present disclosure. The nanochip transistor 300 includes a substrate 310, a buried insulator layer 320, a source region 330, a drain region 340, a gate 350, a contact 360, a dielectric material 370, a nanosheet 380, and a gate electrode 390 . In the embodiment shown in FIG. 3, the buried insulator layer 320 may be formed under the source region 330. When the nanochip transistor 300 is operating, the driving current flows between the source region 330 and the drain region 340. The presence of the buried insulator layer 320 such that the drive current is reduced, resulting in a low current value I _PG, the low current value I _PG in turn increases the ratio β, as previously described in FIG. 1 through FIG. 2 as described in content. As a result, the nanochip transistor 300 does not need to be used in conjunction with any read auxiliary circuit.

The substrate 310 may be made of any number of suitable semiconductor materials, such as Si, P, Ge, Ga, SiGe, and/or InAs, or any combination thereof. The buried insulator layer 320 may be made of any number of suitable dielectric materials, such as Si ₃ N ₄ , SiO ₂ , Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , and/or TiO ₂ , or any of them combination. The source region 330 and the drain region 340 are doped regions for epitaxial growth. As is known in the art, such regions are interchangeable. Nanosheets 380 and gate electrodes 390 can be alternately stacked on top of each other, located (1) between the top surface of the buried insulator layer 320 and the bottom surface of the dielectric material 370 in the vertical direction, and ( ii) It is located between the source region 330 and the drain region 340 in the horizontal direction. The nanosheet serves as a channel between the source region 330 and the drain region 340. The driving current of the nanochip transistor 300 flows through the nanochip 380 along the current path 385. The nanosheet 380 may be made of any number of suitable semiconductor materials, such as Si, P, Ge, Ga, SiGe, and/or InAs, or any combination thereof. The gate electrode 390 is a conductive component that can surround a gate dielectric (not shown in Figure 3). Although not shown, the gate dielectric surrounds the nanosheet 380 and is located between the nanosheet 380 and the gate electrode 390. The gate dielectric can be made of any number of suitable dielectric materials, such as Si ₃ N ₄ , SiO ₂ , Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , and/or TiO ₂ , or any combination thereof . The gate electrode 390 may be made of any number of suitable conductive materials, such as Cu, W, CO, Ru, or any combination thereof. The gate 350 can be made of any number of suitable conductive materials, such as Cu, W, CO, Ru, or any combination thereof. Similarly, the contact 360 may be made of any number of suitable conductive materials, such as Cu, W, CO, Ru, or any combination thereof.

FIG. 4 is a cross-sectional view of another exemplary nanochip transistor 400 that may be used in an exemplary static random access memory bit cell according to various embodiments of the present disclosure. In the embodiment shown in FIG. 4, the buried insulator layer 420 is formed under the drain region 340 instead of under the source region 430.

(2) 多晶矽或閘極550具有一深度Dp(未示出)其小於多晶矽長度Lp的一量值(例如，~50倍Lp)，但大於多晶矽長度Lp的一不同的量值(例如，~5倍Lp)。換言之，多晶矽深度和多晶矽長度之間的關係可以表示為：

(3) 埋入的絕緣體層520具有一長度Lbi，其大於或等於介於多個閘極之間的多晶矽間隔Sp。換言之，埋入的絕緣體層520的長度與多晶矽間隔Sp之間的關係可以表示為：

(4) 埋入的絕緣體層520形成在高於基板並且具有一深度Dbi(未示出)其小於多晶矽長度Lp的一量值(例如，~30倍的Lp)，但是大於約多晶矽深度Dp的一半(例如，0.5倍Dp)。換言之，埋入的絕緣體層520的深度Dbi、多晶矽長度Lp、和多晶矽深度Dp之間的關係可以表示為：

(5) 奈米片380具有片寬度Ws其小於或等於多晶矽長度Lp的一量值(例如，~10倍Lp)，並且大於或等於約多晶矽長度Lp的一半(例如，0.5倍Lp)。換言之，片寬度Ws、和多晶矽長度Lp之間的關係可以表示為：

(6) 埋入的絕緣體層520具有一寬度Wbi其大於或等於奈米片380的片寬度Ws。換言之，埋入的絕緣體層520的寬度Wbi和片寬度Ws之間的關係可以表示為：

(7)FIG. 5 is a top view of an exemplary part of a static random access memory device 500 according to various embodiments of the present disclosure. Polysilicon (poly) or gate 550 has an associated length Lp. The distance or spacing Sp between the polysilicon or gate 550 and the other gate 555 is less than a large amount of the polysilicon length Lp (for example, ~20 times Lp), and is greater than or equal to at least twice the polysilicon length (for example, ~2 Times Lp). In other words, the relationship between the polysilicon length Lp and the polysilicon spacing Sp can be expressed as:

(2) The polysilicon or gate electrode 550 has a depth Dp (not shown) which is less than a magnitude of the polysilicon length Lp (for example, ~50 times Lp), but is greater than a different magnitude of the polysilicon length Lp (for example, ~ 5 times Lp). In other words, the relationship between polysilicon depth and polysilicon length can be expressed as:

(3) The buried insulator layer 520 has a length Lbi, which is greater than or equal to the polysilicon spacing Sp between the gates. In other words, the relationship between the length of the buried insulator layer 520 and the polysilicon spacing Sp can be expressed as:

(4) The buried insulator layer 520 is formed higher than the substrate and has a depth Dbi (not shown) which is less than a magnitude of the polysilicon length Lp (for example, ~30 times Lp), but greater than about the polysilicon depth Dp Half (for example, 0.5 times Dp). In other words, the relationship between the depth Dbi of the buried insulator layer 520, the polysilicon length Lp, and the polysilicon depth Dp can be expressed as:

(5) The nanosheet 380 has a sheet width Ws which is less than or equal to a value of the polysilicon length Lp (for example, ~10 times Lp) and greater than or equal to about half of the polysilicon length Lp (for example, 0.5 times Lp). In other words, the relationship between the wafer width Ws and the polysilicon length Lp can be expressed as:

(6) The buried insulator layer 520 has a width Wbi which is greater than or equal to the sheet width Ws of the nanosheet 380. In other words, the relationship between the width Wbi of the buried insulator layer 520 and the sheet width Ws can be expressed as:

(7)

FIG. 6 is an exemplary static random access memory having a plurality of static random access memory bit cells 602, 604, 606, 608, 610, 612, 614, and 616 according to various embodiments of the present disclosure.体装置600。 Body device 600. As shown in the figure, at least two buried insulator layers span each bit cell. For example, the bit cell 602 includes a part of the buried insulator layer 620 and a part of the buried insulator layer 622. In other words, each buried insulator layer 620, 622 spans multiple bit cells.

FIG. 7 is a cross-sectional view of the exemplary static random access memory device 600 of FIG. 6 according to various embodiments of the present disclosure, along the bit line 650 as an axis. The bit line 650 couples the bit cells 610, 612, 614, 616 together. The bit line 650 is also electrically coupled to each buried insulator layer within each bit cell. For example, the bit line 650 is electrically coupled to the buried insulator layer 620 of the bit cell 616 through the source/drain region 730. Through this electrical coupling, the current I _PD becomes reduced, as described in Figures 1 to 2.

FIG. 8 is a flowchart 800 of an exemplary method of forming a static random access memory device having a partially buried insulator layer and a plurality of nanochips according to various embodiments of the present disclosure. This method can be applied to a variety of underlying structures. However, for ease of understanding, the description will be made in conjunction with Figures 3 to 4 and Figure 8. The first nanosheet 380 is formed higher than the substrate 310. The first nanosheet 380 may be epitaxially formed on the substrate 310 (step 810). A gate electrode 390 (gate electrode layer) is formed on the first nanosheet 380. The gate electrode 390 (gate electrode layer) is deposited using chemical vapor deposition (CVD), which includes low pressure chemical vapor deposition (LPCVD) and plasma assisted chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic Layer deposition (ALD), or other suitable process (step 820). The buried insulator layer 320 is formed higher than the substrate 310 (step 830). The source region and the drain region are formed higher than the substrate 310 and the buried insulator layer 320 (step 840). The first nanosheet 380 is (i) located between the source region and the drain region in the horizontal direction, and (ii) is higher than the buried insulator layer 320 in the vertical direction.

Although 6 transistors (6T) static random access memory bit cells are described in these figures, those skilled in the art can understand that any type of bit cell can be implemented using the teachings herein. These bit cells may include, but are not limited to, 7 transistors (7T), 8 transistors (8T), 9 transistors (9T), and/or 10 transistors (10T) bit cells.

The use of various circuits and configurations as described herein can provide many advantages. For example, the embedded buried insulator layer under the source/drain region along with the use of a plurality of nanochips reduces the current flowing through the first transistor of the static random access memory bit cell. The reduction in current increases the beta ratio (beta ratio) of the static random access memory bit cell. Such improvement means that the read performance of the static random access memory bit cell is high, and no additional read auxiliary circuit is needed. Eliminating the need for any reading auxiliary circuits saves space available for other circuits within the device and/or can reduce the overall size of the device.

In one embodiment, a semiconductor device includes a source region and a drain region formed above a substrate. The buried insulator layer is formed under either the source region or the drain region. The first nanosheet is formed (i) between the source region and the drain region in the horizontal direction; and (ii) is higher than the buried insulator layer in the vertical direction. The current flowing through the buried insulator layer increases the β ratio including the rate at which this current flows.

In another embodiment, a static random access memory includes a plurality of static random access memory bit cells. Each static random access memory bit cell has a portion of a buried insulator layer formed under the first source/drain region, and a plurality of nanosheet layers which connect the first source/drain region and the first source/drain region. Two source/drain regions are separated. The bit line couples a plurality of static random access memory bit cells together. The bit line is electrically coupled to this part of the buried insulator layer.

In yet another embodiment, a method includes forming a first nanosheet above the substrate. The first gate electrode layer is deposited above the first nanosheet. A buried insulator layer is formed above the substrate. The source region and the drain region are formed above the buried insulator layer and the substrate. The buried insulator layer is located (i) between the source region and the drain region in the horizontal direction; and (ii) is higher than the buried insulator layer in the vertical direction.

Some embodiments of the present disclosure provide a semiconductor device including: a source region and a drain region, a buried insulator (BI) layer, and a first nanochip. The source region and the drain region are formed higher than the substrate. The buried insulator layer is formed under either the source region or the drain region and higher than the substrate. The first nanosheet is formed (i) between the source region and the drain region in the horizontal direction, and (ii) is higher than the buried insulator layer in the vertical direction.

In some embodiments, the semiconductor device further includes a gate electrode, an insulator layer, and a second nanosheet. The gate is formed around the first nanosheet. The insulator layer is formed vertically higher than the first nanosheet, and the insulator layer separates the first nanosheet and the second nanosheet. The second nanosheet is formed above the insulator layer, and the gate is formed above the second nanosheet.

In some embodiments, in the semiconductor device, the semiconductor device is not coupled to a read auxiliary circuit.

In some embodiments, in the semiconductor device, each of the first nanosheet and the second nanosheet includes a semiconductor material having at least one of Si, P, Ge, Ga, SiGe, or InAs .

In some embodiments, in the semiconductor device, the buried insulator layer includes a dielectric material, and the dielectric material has Si ₃ N ₄ , SiO ₂ , Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , or TiO ₂ in at least one.

In some embodiments, in the semiconductor device, the depth of the buried insulator layer is between approximately (i) 30 times the length of a gate and (ii) 0.5 times the depth of the gate.

In some embodiments, in the semiconductor device, the width of the buried insulator layer is greater than or equal to the width of the first nanosheet.

In some embodiments, in the semiconductor device, the width of the first nanosheet is between approximately (i) 10 times the length of a gate and (ii) 0.5 times the length of the gate.

In some embodiments, in the semiconductor device, the length of the buried insulator layer is greater than or equal to a gap between a gate and a gate of another semiconductor device.

Some embodiments of the present disclosure provide a static random access memory (SRAM) device, which includes a plurality of static random access memory bit cells and a bit line. Each static random access memory bit cell includes: a part of a buried insulator (BI) layer and a plurality of nanosheets. This part of the buried insulator layer is formed under the first source/drain region. A plurality of nanosheets separate the first source/drain region from the second source/drain region. The bit line couples these plural static random access memory bit cells together, and the bit line is electrically coupled to this part of the buried insulator layer.

In some embodiments, in the static random access memory device, none of the plurality of bit cells is coupled to a read auxiliary circuit.

In some embodiments, in the static random access memory device, each of the plurality of nanochips includes a semiconductor material, and the semiconductor material has at least one of Si, P, Ge, Ga, SiGe, or InAS .

In some embodiments, in the static random access memory device, the buried insulator layer includes a dielectric material including Si ₃ N ₄ , SiO ₂ , Al ₂ O ₃ , HfO ₂ , Ta ₂ At least one of O ₅ or TiO ₂ .

In some embodiments, in the static random access memory device, the plurality of nanochips are separated from each other by a plurality of insulating layers.

In some embodiments, in the static random access memory device, the plurality of nanochips are vertically higher than the buried insulator layer.

In some embodiments, in a static random access memory device, each of the static random access memory bit cells includes a first transistor coupled to a second transistor , And the first current passes through the first transistor, wherein the first current is smaller than the second current through the second transistor.

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including: forming a first nanosheet higher than a substrate; depositing a first gate electrode layer higher than the first nanosheet; forming a buried The insulator (BI) layer is higher than the substrate; and the source region and the drain region are formed which are higher than the buried insulator layer and the substrate, wherein the buried insulator layer is located (i) between the source region and the substrate in the horizontal direction Between the drain regions, and (ii) in the vertical direction higher than the buried insulator layer.

In some embodiments, the method of manufacturing a semiconductor device further includes: forming a gate extremely higher than the first nanosheet; forming an insulator layer which is higher than the first nanosheet in the vertical direction, and the insulator is the first nanosheet. Separated from a second nanosheet; and forming a second nanosheet higher than the insulator layer, wherein the gate is formed higher than the second nanosheet.

In some embodiments, in the method of manufacturing a semiconductor device, a semiconductor material is used for each of the first nanosheet and the second nanosheet. The semiconductor material has Si, P, Ge, Ga, SiGe, or InAS. At least one of.

In some embodiments, in the method of manufacturing a semiconductor device, a dielectric material is used to form the buried insulator layer, and the dielectric material includes Si ₃ N ₄ , SiO ₂ , Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , or at least one of TiO ₂ .

Several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equal constructions do not depart from the spirit and scope of the present disclosure, and they may make various changes, substitutions, and alterations to this article without departing from the spirit and scope of the present disclosure. .

100: Static random access memory device 110: Static random access memory bit cell 120: Buried insulator layer 130: Gate 140: Gate 210: Transistor 215: Storage node 220: Transistor 230: Transistor 235: Storage node 240: Transistor 250: Transistor 260: Transistor 300: Nano-chip transistor 310: Substrate 320: Buried insulator layer 330: Source region 340: Drain region 350: Gate 360: Contact Item 370: Dielectric material 380: Nanochip 385: Current path 390: Gate electrode 400: Nanochip transistor 420: Embedded insulator layer 430: Source area 500: Static random access memory device 520: Buried insulator layer 550: gate 555: gate 600: static random access memory device 602: bit cell 604: bit cell 606: bit cell 608: bit cell 610: bit cell 612: bit Meta cell 614: Bit cell 616: Bit cell 620: Buried insulator layer 622: Buried insulator layer 650: Bit line 730: Source/drain area 800: Flow chart 810: Step 820: Step 830 : Step 840: Step BI: Embedded insulator BIT: Bit BL: Bit line BLB: Bit line EPI: Epitaxy I _PD : Current I _PG : Current Lbi: Length Lp: Length Sp: Interval VDD: Supply voltage VSS: supply voltage Wbi: width WL: character line Ws: width

The various aspects of the present disclosure can be best understood by reading the following detailed description together with the accompanying drawings. It is worth noting that according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the size of each feature may be increased or decreased arbitrarily. FIG. 1 is a top view of an exemplary part of a static random access memory device according to various embodiments of the present disclosure. FIG. 2 is a schematic drawing of the exemplary static random access memory bit cell of FIG. 1 according to various embodiments of the present disclosure. Figure 3 is a cross-sectional view of an exemplary nanochip transistor that may be used in an exemplary static random access memory bit cell according to various embodiments of the present disclosure. FIG. 4 is a cross-sectional view of another exemplary nanochip transistor that may be used in an exemplary static random access memory bit cell according to various embodiments of the present disclosure. FIG. 5 is a top view of an exemplary part of a static random access memory device according to various embodiments of the present disclosure. FIG. 6 is an exemplary static random access memory device having an array of multiple static random access memory bit cells according to various embodiments of the present disclosure. FIG. 7 is a cross-sectional view of the exemplary static random access memory device of FIG. 6 according to various embodiments of the present disclosure. FIG. 8 is a flowchart of an exemplary method of forming a static random access memory device having a partially buried insulator layer and a nanochip according to various embodiments of the present disclosure.

Domestic deposit information (please note in the order of deposit institution, date and number) no Foreign hosting information (please note in the order of hosting country, institution, date and number) no

300: Nano chip transistor

310: substrate

320: Insulator layer

330: source region

340: Drain Area

350: gate

360: Contact

370: Dielectric materials

380: Nanosheet

385: Current Path

390: gate electrode

BI: buried insulator

EPI: Epitaxy

Claims (1)

A semiconductor device including: A source region and a drain region are formed higher than a substrate; A buried insulator (BI) layer is formed under either the source region or the drain region and higher than the substrate; and A first nanosheet is formed (i) between the source region and the drain region in the horizontal direction, and (ii) higher than the buried insulator layer in the vertical direction.

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