TW202101669A - Semiconductor structure, circuit and methods of fabricating the same - Google Patents

Abstract

Apparatus and circuits including transistors with different polarizations and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion and a second active portion; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first active portion has a material composition different from that of the second active portion.

Description

Semiconductor structure, circuit and manufacturing method thereof

The disclosed embodiments relate to a semiconductor structure, a circuit and a manufacturing method thereof.

In integrated circuits (IC), enhancement mode N-type transistors (such as enhancement-mode high-electron-mobility transistor (E-HEMT)) can be used as pull-up elements (Pull-up device) to minimize quiescent current. In order to achieve a pull-up voltage close to a full rail and a fast slew rate, for the N-type enhancement mode transistor, a significantly larger over-drive voltage is required. In other words, the voltage difference (Vgs) between the gate and the source should be much larger than the threshold voltage (Vt), that is, (Vgs-Vt >> 0). It is necessary to use multi-stage E-HEMT-based drivers for integrated circuits to minimize quiescent current. However, the driver based on the multi-level E-HEMT will not have enough overdrive voltage (especially for the last-level driver). This is due to a drop in the threshold voltage Vt across each stage of the E-HEMT pull-up element and bootstrap It is caused by a drop in a forward voltage (Vf) across the boot-strap diode. Although the threshold voltage Vt of the pull-up E-HEMT transistor and the forward voltage Vf of the E-HEMT rectifier connected to the diode of the multi-stage driver can be reduced to provide a significantly sufficient overdrive voltage And significantly reduce the static current, but the noise immunity will be impaired.

In the existing semiconductor wafer, the transistors formed on the wafer have the same structure so that they have the same threshold voltage Vt. When the threshold voltage Vt of one transistor decreases, the threshold voltage Vt of other transistors on the wafer also decreases accordingly. In this case, as the threshold voltage Vt decreases, the power switch HEMT driven by the HEMT-based driver will have poor noise immunity, because the power switch HEMT cannot withstand a large back feedthrough to its gate Impulse voltage (back-feed-through impulse voltage). Therefore, the existing devices and circuits including multiple transistors are not completely satisfactory.

The disclosed embodiment provides a semiconductor structure. The semiconductor structure includes: a substrate; an active layer formed on the substrate and including a first active part and a second active part; a first transistor including a first source region, a first drain region, and a first A gate structure, the first gate structure is formed on the first active portion and between the first source region and the first drain region; and a second transistor including a second source A pole region, a second drain region, and a second gate structure, the second gate structure being formed on the second active portion and between the second source region and the second drain region , Wherein the first active part has a material composition different from that of the second active part.

The following disclosure sets forth various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the content of the embodiments of the present disclosure. Of course, these are only examples and not intended to be limiting. For example, in the following description, forming the first feature on or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include An embodiment in which an additional feature can be formed between the feature and the second feature so that the first feature and the second feature may not directly contact. In addition, the contents of the embodiments of the present disclosure may reuse reference numbers and/or letters in various examples. This repeated use is for the purpose of conciseness and clarity, and does not itself represent the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of explanation, this article may use, for example, "beneath", "below", "lower", "above", and "above". (Upper)" and other spatially relative terms to describe the relationship between one element or feature shown in the figure and another (other) element or feature. In addition to the orientations depicted in the figures, the terms of spatial relativity are also intended to encompass different orientations of elements in use or operation. The device may have another orientation (rotated by 90 degrees or in another orientation), and the spatial relativity descriptors used herein may also be interpreted accordingly. Unless explicitly stated otherwise, terms such as “attached”, “affixed”, “connected” and “interconnected” refer to the structure in which the structure is directly fixed or attached to Another structure or a relationship that is indirectly fixed or attached to another structure through an intermediate structure, and a removable or rigid attachment or relationship.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the embodiments of the present disclosure belong. It should also be understood that terms (for example, terms defined in commonly used dictionaries) should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present disclosure, and they should not be interpreted unless clearly defined herein. Interpreted as having an ideal or too formal meaning.

Reference will now be made in detail to the current embodiments of the disclosed embodiments, and examples of these embodiments are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and descriptions to refer to the same or similar components.

Compared with silicon-based transistors, enhancement mode high-electron-mobility transistors (HEMT) (such as gallium nitride (GaN) HEMT) have more advantages in power conversion and RF power amplifier and power switching applications. Excellent characteristics (to enable high performance) and a smaller form factor. But there is no viable p-type HEMT available, mainly because the p-type mobility is much lower and partly because of the two dimensional hole gas (2DHG) band structure. Although n-type GaN HEMTs are used in integrated circuits, in order to minimize the quiescent current, the pull-up elements are mainly based on enhancement mode n-type transistors rather than depletion-mode n-type transistors.

Multi-stage HEMT-based drivers can be used for integrated circuits to minimize quiescent current. But the driver based on multi-level HEMT will not have enough overdrive voltage (especially for the last stage driver). This is due to a drop in the threshold voltage (Vt) across each stage of the HEMT pull-up element and two bootstrap boosts. It is caused by a drop in a forward voltage (Vf) across the pole body. Although the threshold voltage of the pull-up HEMT transistor and the forward voltage of the HEMT rectifier connected to the diode of the multi-level driver can be reduced to provide a significantly sufficient overdrive voltage and significantly reduce the quiescent current, the noise immunity will be affected. damage.

Instead of lowering a single value of the threshold voltage (Vt) of the HEMT transistor in an integrated circuit, the present teachings disclose devices and circuits including dual threshold voltage transistors or multiple threshold voltage transistors, and the manufacturing process thereof. In one embodiment, two transistors formed on the same wafer have different threshold voltages. Specifically, the two transistors have different polarization amounts between the active layer and the channel layer to obtain different threshold voltages from each other. Each transistor corresponds to an active part of the active layer, and the active part of the active layer may be an aluminum gallium nitride (AlGaN) layer disposed on the GaN channel layer of the transistor.

In one embodiment, the active parts corresponding to the two transistors have different material compositions different from each other. For example, the Al composition (y) of the Al _y Ga _1-y N active layer of one transistor is different from the Al composition (x) of the Al _x Ga _1-x N layer of another transistor. A higher Al composition introduces higher polarization and therefore generates more two dimensional electron gas (2-DEG) to lower the threshold voltage. Therefore, GaN devices with different threshold voltages can be implemented by depositing AlGaN layers with different Al compositions by epitaxial growth. In an exemplary method of fabricating a dual threshold voltage transistor, the two AlGaN layers with different Al compositions can be formed on the same channel layer.

In another embodiment, AlGaN layers of different thicknesses can change the amount of spontaneous polarization and piezoelectric polarization between the AlGaN layer and the GaN layer. A thicker AlGaN layer introduces a higher polarization and therefore produces a greater amount of 2-DEG to lower the threshold voltage. Therefore, GaN elements with different threshold voltages can be implemented by depositing AlGaN layers with different thicknesses by epitaxial growth. In yet another embodiment, GaN transistors with different threshold voltages can be implemented by depositing AlGaN layers with different thicknesses and different Al compositions.

In different embodiments, the active parts corresponding to the two transistors have different structures different from each other. For example, the active AlGaN layer of one transistor has a graded structure including a plurality of sublayers, each of which includes AlGaN with a different Al ratio, and the active AlGaN layer of the other transistor has a graded structure. The AlGaN layer has a homogeneous structure including AlGaN with a single constant Al ratio. Graded AlGaN has less polarization, introduces a smaller amount of 2-DEG, and therefore increases Vt. The graded AlGaN layer makes the interface quality between the AlGaN layer and the GaN layer significantly better. Therefore, GaN transistors with different threshold voltages can also be implemented by depositing AlGaN layers with different material structures.

The disclosed device can adjust the amount of polarization between the AlGaN layer and the GaN layer by changing the thickness, Al composition and/or material structure of the AlGaN layer to generate dual threshold voltages (or various threshold voltages) on the same semiconductor wafer Transistor; and different amounts of 2-DEG are generated for the transistor at different locations on the same wafer.

The disclosed embodiments are applicable to any integrated circuit based on transistors. The proposed device and method may be able to significantly reduce the quiescent current of the transistor-based integrated circuit, and have a significantly larger overdrive voltage for the driver of interest; it will not increase the overdrive voltage and reduce the quiescent current at the same time The noise resistance is impaired. In addition, the disclosed device and method can provide integrated circuit designers the flexibility to use different threshold voltage components for specific functions such as improving performance, reducing quiescent current, and improving noise immunity.

Figure 1 shows an exemplary circuit 100 with a multi-stage bootstrap boost driver according to some embodiments of the present disclosure. As shown in FIG. 1, the circuit 100 includes a driver having a plurality of stages 110, 120, and 130 connected in series to drive the power switch HEMT 175. Each level includes multiple transistors.

The level 110 in this example includes transistors 141, 151, 152, 153, 154, 155, 156. In one embodiment, among these transistors, the transistor 154 is a low voltage depletion-mode high electron mobility transistor (LV D-HEMT) 192; and the other transistors Each of the crystals 141, 151, 152, 153, 155, and 156 is a low voltage enhancement-mode high electron mobility transistor (LV E-HEMT) 191.

As shown in FIG. 1, the gate electrode of the transistor 151 is electrically connected to the input pin 131 of the circuit 100. The input pin 131 has an input voltage Vin ranging from a low logic state voltage (for example, 0 V) to a high logic state voltage (for example, 6 V). When the circuit 100 is turned off, the input voltage Vin is zero. After the input voltage Vin increases to 6 V, the circuit 100 turns on. The transistor 151 has a source electrically connected to the ground VSS 111 having a ground voltage of 0 V; and has a drain electrically connected to the source of the transistor 154. The transistor 152 in this example has a gate electrically connected to the input pin 131, a source electrically connected to the ground VSS 111 with a ground voltage of 0 V, and a drain electrically connected to the source of the transistor 155. Similarly, the transistor 153 in this example has a gate electrically connected to the input pin 131, a source electrically connected to the ground VSS 111 having a ground voltage of 0 V, and a drain electrically connected to the source of the transistor 156. pole.

The gate of the transistor 154 in this example is electrically connected to its own source, and the source of the transistor 154 is electrically connected to the drain of the transistor 151. The drain of the transistor 154 is electrically connected to the source of the transistor 141. The transistor 155 in this example has a gate electrically connected to the source of the transistor 154 and to the drain of the transistor 151. The transistor 155 has a source electrically connected to the drain of the transistor 152 and a drain electrically connected to the power supply pin VDD 101 having a positive power supply voltage (for example, 6 V). Similarly, the transistor 156 in this example has a gate electrically connected to the source of the transistor 154 and to the drain of the transistor 151, a source electrically connected to the drain of the transistor 153, and electrical connections To the drain of the power supply pin VDD 101 with a positive power supply voltage of 6 V.

The transistor 141 in this example has a gate electrically connected to its own drain, and the drain of the transistor 141 is electrically connected to a power supply pin VDD 101 having a positive power supply voltage of 6 V. The transistor 141 connected in this specific configuration functions like a rectifier or a diode and is traditionally called a diode-connected transistor. The source of the transistor 141 is electrically connected to the drain of the transistor 154. The level 110 also includes a capacitor 121 coupled between the source of the transistor 141 and the source of the transistor 155.

The level 120 in this example includes transistors 142, 161, 162, 163, 164, 165, 166. In one embodiment, among these transistors, the transistor 164 is a low voltage depletion mode high electron mobility transistor (LV D-HEMT) 192; and the other transistors 142, 161, 162, 163, 165 Each of 166 is a low voltage enhancement mode high electron mobility transistor (LV E-HEMT) 191.

As shown in FIG. 1, the gate of the transistor 161 is electrically connected to a node 181, and the node 181 is electrically connected to the source of the transistor 156 and the drain of the transistor 153. The voltage of the node 181 is between the ground VSS and the power supply pin VDD (0 V and 6 V). When the circuit 100 is turned off, the input voltage Vin is 0 so that the transistor 153 is turned off and the transistor 156 is turned on. The node 181 has the same voltage of 6 V as the power supply pin VDD 101. When the circuit 100 is turned on and the input voltage Vin has a voltage of 6 V, the transistor 153 is turned on and the transistor 156 is turned off. The node 181 has the same voltage 0 V as the ground VSS 111.

The transistor 161 has a source electrically connected to the ground VSS 111 having a ground voltage of 0 V; and has a drain electrically connected to the source of the transistor 164. The transistor 162 in this example has a gate electrically connected to the node 181, a source electrically connected to the ground VSS 111 with a ground voltage of 0 V, and a drain electrically connected to the source of the transistor 165. Similarly, the transistor 163 in this example has a gate electrically connected to the node 181, a source electrically connected to the ground VSS 111 with a ground voltage of 0 V, and a drain electrically connected to the source of the transistor 166.

The transistor 164 in this example has a gate electrically connected to its own source, and the source of the transistor 164 is electrically connected to the drain of the transistor 161. The drain of the transistor 164 is electrically connected to the source of the transistor 142. The transistor 165 in this example has a gate electrically connected to the node 185, which is electrically connected to the source of the transistor 164 and electrically connected to the drain of the transistor 161. Transistor 165 has a source electrically connected to the drain of transistor 162 and a drain electrically connected to the source of transistor 142. The transistor 166 in this example has a gate electrically connected to a node 186, which is electrically connected to the source of the transistor 165 and to the drain of the transistor 162, and to the drain of the transistor 163. The source of, and the drain electrically connected to the power supply pin VDD 102 having a positive power supply voltage (for example, 6 V).

The transistor 142 in this example has a gate electrically connected to its own drain (ie, the diode is connected to act as a rectifier or diode), and the drain of the transistor 142 is electrically connected to a positive supply voltage of 6 V The power supply pin VDD 102. The source of the transistor 142 is electrically connected to the drain of the transistor 164 and the drain of the transistor 165. Level 120 also includes a capacitor 122 coupled between node 184 electrically connected to the source of transistor 142 and node 183 electrically connected to the source of transistor 166.

The level 130 in this example includes transistors 143, 171, 172, 173, 174. In one embodiment, each of these transistors is a low voltage enhancement mode high electron mobility transistor (LV E-HEMT) 191. As shown in FIG. 1, the gate of transistor 171 is electrically connected to node 182, and node 182 is electrically connected to node 181, the source of transistor 156 and the drain of transistor 153. Like the node 181, the voltage of the node 182 is between the ground VSS and the power supply pin VDD (0 V and 6 V). When the circuit 100 is turned off, the input voltage Vin is 0 so that the transistor 153 is turned off and the transistor 156 is turned on. The node 181 and the node 182 have the same voltage of 6 V as the power supply pin VDD 101. When the circuit 100 is turned on and the input voltage Vin has a voltage of 6 V, the transistor 153 is turned on and the transistor 156 is turned off. The node 181 and the node 182 have the same voltage of 0 V as the ground VSS 111.

The transistor 171 has a source electrically connected to the ground VSS 111 having a ground voltage of 0 V; and has a drain electrically connected to the source of the transistor 173. The transistor 172 in this example has a gate electrically connected to the node 182, a source electrically connected to the ground VSS 111 having a ground voltage of 0 V, and a drain electrically connected to the source of the transistor 174.

Transistor 173 in this example has a gate electrically connected to node 186, and node 186 is electrically connected to the source of transistor 165. Transistor 173 has a source electrically connected to the drain of transistor 171 and a drain electrically connected to the source of transistor 143. The transistor 174 in this example has a gate electrically connected to the node 187, which is electrically connected to the source of the transistor 173 and to the drain of the transistor 171. The transistor 174 has a source electrically connected to the drain of the transistor 172 and a drain electrically connected to the power supply pin VDD 103 having a positive power supply voltage (for example, 6 V).

The transistor 143 in this example has a gate electrically connected to its own drain (ie, the diode is connected to act as a rectifier or diode), and the drain of the transistor 143 is electrically connected to a positive supply voltage of 6 V The power supply pin VDD 103. The source of the transistor 143 is electrically connected to the drain of the transistor 173. Level 130 also includes a capacitor 123 coupled between node 189 electrically connected to the source of transistor 143 and node 188 electrically connected to the source of transistor 174.

Thus, the levels 110, 120, and 130 are connected in series to form a multi-level driver for driving the power switching transistor 175. In one embodiment, the power switch HEMT 175 is a high voltage enhancement-mode high electron mobility transistor (HV E-HEMT) 193. As shown in FIG. 1, the power switch HEMT 175 has a gate electrically connected to the node 188, a source electrically connected to the ground VSS 112 having a ground voltage of 0 V, and a drain electrically connected to the output pin 133 of the circuit 100 . In some embodiments, the circuit 100 can be used as a low-side driver in a half-bridge or full-bridge power converter, where the output pin 133 is used as a low-side voltage output (low-side voltage output). voltage output, LoVout).

Most of the transistors in Figure 1 are enhancement mode N-type transistors. In other words, the circuit 100 mainly uses an enhancement mode N-type transistor as a pull-up element to minimize the quiescent current. In order to achieve a pull-up voltage close to the full rail and a fast conversion rate, for the N-type enhancement mode transistor, a significantly larger overdrive voltage is required. In other words, the voltage difference (Vgs) between the gate and the source should be much larger than the threshold voltage (Vt), that is, (Vgs-Vt >> 0). Although the multi-stage driver of the circuit 100 can minimize the quiescent current, each stage of the E-HEMT pull-up element consumes at least one threshold voltage Vt voltage drop.

As described above, the voltage of the node 181 is between the ground VSS and the power supply pin VDD (0 V and 6 V). When the circuit 100 is turned off, the input voltage Vin is 0 so that the transistor 153 is turned off and the transistor 156 is turned on. The node 181 has the same voltage of 6 V as the power supply pin VDD 101, which enables the transistors 161, 162, and 163 to be turned on. Thus, the node 185 is electrically connected to the ground VSS 111, and has a voltage close to 0V. Thus, the transistor 165 is turned off, and the node 186 is electrically connected to the ground VSS 111 and has a voltage of 0V. Therefore, the transistor 166 is turned off, and the node 183 is electrically connected to the ground VSS 111 and has a voltage of 0V. In this case, the capacitor 122 is charged by the power supply pin VDD 102 through the transistor 142. In this example, the transistor 142 is a diode-connected HEMT used as a rectifying diode, and the diode-connected HEMT naturally has a forward voltage (Vf). In other words, the voltage at node 184 will be charged to 6 V-Vf to the maximum. In the first example, assuming that the forward voltage and threshold voltage of all transistors in FIG. 1 are equal to 1.5 V, when the circuit 100 is turned off, the maximum voltage at the node 184 is 6 V-1.5 V = 4.5 V.

When the circuit 100 is turned on and the input voltage Vin has a voltage of 6 V, the transistor 153 is turned on and the transistor 156 is turned off. The node 181 has the same voltage of 0 V as the ground VSS 111, which enables the transistors 161, 162, and 163 to be turned off. Thus, the node 185 is electrically connected to the node 184 and has the same voltage as the node 184. This causes transistor 165 to turn on, which enables node 186 to be charged by the voltage at node 184. This in turn causes the transistor 166 to turn on, which enables the node 183 to be charged by the power supply pin VDD 102. Therefore, the voltage at the node 183 can be charged to 6 V as much as the voltage at the power supply pin VDD 102. Based on the 4.5 V voltage difference stored by the capacitor 122 when the circuit 100 is disconnected, the voltage at the node 184 can be charged to the maximum and increased to 6 V + 4.5 V = 10.5 V, that is, the voltage at the node 184 is bootstrapped. To 10.5 V. Therefore, the node 185 electrically connected to both the source and gate of the transistor 164 is also charged to 10.5V.

While the node 186 is also charged by the voltage of 10.5 V at the node 184, the voltage of the node 186 cannot reach 10.5 V. Since the node 186 is electrically connected to the source of the transistor 165, in order to keep the transistor 165 on, the gate-source voltage difference Vgs of the transistor 165 must be greater than the threshold voltage (Vt) of the transistor 165. Since Vt = 1.5 V is assumed in the first example, the maximum voltage that the node 186 can reach in the first example is 10.5 V-Vt = 10.5 V-1.5 V = 9 V when the circuit 100 is turned on. As a result, the enhancement mode high electron mobility transistor (E-HEMT) pull-up element consumes at least one threshold voltage drop.

The node 182 is electrically connected to the node 181 and has the same voltage as the voltage of the node 181. That is, when the circuit 100 is turned off, the node 182 has a voltage of 6 V; when the circuit 100 is turned on, the node 182 has a voltage of 0 V. When the circuit 100 is turned off, the 6 V voltage at the node 182 enables the transistors 171, 172 to be turned on. Thus, the node 187 is electrically connected to the ground VSS 111, and has a voltage of 0V. Here, as described above, when the circuit 100 is turned off, the transistor 173 is turned off due to the 0 V voltage at the node 186. Since the node 187 has a voltage of 0V, the transistor 174 is turned off, and the node 188 is electrically connected to the ground VSS 111 and has a voltage of 0V. In this case, the capacitor 123 is charged by the power supply pin VDD 103 through the transistor 143. In this example, the transistor 143 is a diode-connected HEMT serving as a rectifier diode, and the diode-connected HEMT naturally has a forward voltage (Vf). In other words, the voltage at node 189 will be charged to 6 V-Vf to the maximum. In the first example, assuming that the forward voltage and threshold voltage of all transistors in FIG. 1 are equal to 1.5 V, when the circuit 100 is turned off, the maximum voltage at the node 189 is 6 V-1.5 V = 4.5 V.

When the circuit 100 is turned on, the node 182 and the node 181 have the same voltage of 0 V as the ground VSS 111, which enables the transistors 171 and 172 to be turned off. As described above, when the circuit 100 is turned on, the node 186 electrically connected to the gate of the transistor 173 has a maximum voltage of 9V. Thus, the transistor 173 is turned on and the node 187 is charged by the node 189. This causes transistor 174 to conduct, which enables node 188 to be charged by power supply pin VDD 103. Therefore, the voltage at the node 188 can be charged to 6 V as much as the voltage at the power supply pin VDD 102. Based on the 4.5 V voltage difference stored by the capacitor 123 when the circuit 100 is disconnected, the voltage at the node 189 can be charged to the maximum and increased to 6 V + 4.5 V = 10.5 V, that is, the voltage at the node 189 is bootstrapped To 10.5 V.

While the node 187 is charged by the voltage of 10.5 V at the node 189, the voltage of the node 187 cannot reach 10.5 V. Since the node 187 is electrically connected to the source of the transistor 173, in order to keep the transistor 173 turned on, the gate-source voltage difference Vgs of the transistor 173 must be greater than the threshold voltage (Vt) of the transistor 173. The gate of the transistor 173 is electrically connected to the node 186. When the circuit 100 is turned on, the node 186 has a maximum voltage of 9V. Since Vt = 1.5 V is assumed in the first example, the maximum voltage that the node 187 can reach in the first example is 9 V-Vt = 9 V-1.5 V = 7.5 V when the circuit 100 is turned on. Now the transistor 174 has a gate-source voltage difference Vgs=7.5 V-6 V=1.5 V, and the gate-source voltage difference is exactly equal to the threshold voltage Vt=1.5 V of the transistor 174. This makes the last stage of the multi-stage bootstrap boost driver no voltage margin (voltage margin). That is, in the first example where Vf = Vt = 1.5 V, there is not enough overdrive voltage to drive the power switch HEMT 175. Even if the power switch HEMT 175 can be driven, it will be significantly slow because the current flowing through the transistor 174 and node 188 will be very slow due to the absence of a Vgs margin compared to the threshold voltage. The above conclusions do not even take into account the threshold voltage variation (such as the 3-σ variation of 0.5 V) that normally exists in all process technologies. After counting the 3-σ changes of 0.5 V, under the assumption of Vt=1.5 V, the circuit 100 may not be able to drive the power switch HEMT 175 at all.

In the second example, assume that the forward voltage and threshold voltage of all transistors in FIG. 1 are equal to 1V. In this situation, when the circuit 100 is turned off, the node 181 has the same voltage of 6 V, which enables the transistors 161, 162, 163 to be turned on. Thus, the node 185 is electrically connected to the ground VSS 111 and has a voltage of 0V. Thus, the transistor 165 is turned off, and the node 186 is electrically connected to the ground VSS 111 and has a voltage of 0V. Therefore, the transistor 166 is turned off, and the node 183 is electrically connected to the ground VSS 111 and has a voltage of 0V. The capacitor 122 is charged by the power supply pin VDD 102 through the transistor 142. Since the transistor 142 is a diode-connected HEMT used as a rectifier diode, the diode-connected HEMT naturally has a forward voltage (Vf), so the node 184 may have 6 V-Vf = 6 V-1 V = 5 V maximum voltage.

When the circuit 100 is turned on, the node 181 has the same voltage of 0 V as the ground VSS 111, which enables the transistors 161, 162, 163 to be turned off. Thus, the node 185 is electrically connected to the node 184 and has the same voltage as the node 184. This causes transistor 165 to turn on, which enables node 186 to be charged by the voltage at node 184. This in turn causes the transistor 166 to turn on, which enables the node 183 to be charged by the power supply pin VDD 102. Therefore, the node 183 has a maximum voltage of 6V as the voltage of the power supply pin VDD 102 is the same. Based on the 5 V voltage difference stored by the capacitor 122 when the circuit 100 is disconnected, the voltage at the node 184 can be charged to the maximum and increased to 6 V + 5 V = 11 V, that is, the voltage at the node 184 is bootstrapped To 11 V. Therefore, the node 185 electrically connected to both the source and gate of the transistor 164 is also charged to 11V. When node 186 is also charged by the voltage of 11V at node 184, the voltage of node 186 cannot reach 11V. Since the node 186 is electrically connected to the source of the transistor 165, in order to keep the transistor 165 on, the gate-source voltage difference Vgs of the transistor 165 must be greater than the threshold voltage (Vt) of the transistor 165. Since Vt=1 V is assumed in the second example, the maximum voltage that the node 186 can reach in the second example is 11 V−Vt=11 V−1 V=10 V when the circuit 100 is turned on.

The node 182 is electrically connected to the node 181 and has the same voltage as the voltage of the node 181. That is, when the circuit 100 is turned off, the node 182 has a voltage of 6 V; when the circuit 100 is turned on, the node 182 has a voltage of 0 V. When the circuit 100 is turned off, the 6 V voltage at the node 182 enables the transistors 171, 172 to be turned on. Thus, the node 187 is electrically connected to the ground VSS 111 and has a voltage of 0V. Here, as described above, when the circuit 100 is turned off, the transistor 173 is turned off due to the 0 V voltage at the node 186. Since the node 187 has a voltage of 0V, the transistor 174 is turned off, and the node 188 is electrically connected to the ground VSS 111 and has a voltage of 0V. In this case, the capacitor 123 is charged by the power supply pin VDD 103 through the transistor 143. Since the transistor 143 is a diode-connected HEMT used as a rectifier diode, and the diode-connected HEMT naturally has a forward voltage (Vf), the node 189 has 6 V-Vf = 6 V-1 V = 5 V maximum voltage.

When the circuit 100 is turned on, the node 182 and the node 181 have the same voltage of 0 V as the ground VSS 111, which enables the transistors 171 and 172 to be turned off. As described above, when the circuit 100 is turned on, the node 186 electrically connected to the gate of the transistor 173 has a maximum voltage of 10V. Thus, the transistor 173 is turned on and the node 187 is charged by the node 189. This causes transistor 174 to conduct, which enables node 188 to be charged by power supply pin VDD 103. Therefore, the voltage at the node 188 can be charged to 6 V as much as the voltage at the power supply pin VDD 102. Based on the 5 V voltage difference stored by the capacitor 123 when the circuit 100 is disconnected, the voltage at the node 189 can be charged to the maximum and increased to 6 V + 5 V = 11 V, that is, the voltage at the node 189 is bootstrapped To 11 V.

When the node 187 is charged by the voltage of 11 V at the node 189, the voltage of the node 187 cannot reach 11 V. Since the node 187 is electrically connected to the source of the transistor 173, in order to keep the transistor 173 turned on, the gate-source voltage difference Vgs of the transistor 173 must be greater than the threshold voltage (Vt) of the transistor 173. The gate of the transistor 173 is electrically connected to the node 186, and when the circuit 100 is turned on, the node 186 has a maximum voltage of 10V. Since Vt=1 V is assumed in the second example, when the circuit 100 is turned on, the maximum voltage that the node 187 can reach in the second example is 10 V−Vt=10 V−1 V=9 V. Now the transistor 174 has a gate-source voltage difference Vgs=9 V-6 V=3 V, and the gate-source voltage difference is much larger than the threshold voltage Vt=1 V of the transistor 174. This leaves enough voltage margin at the last stage of the multi-stage bootstrap boost driver. That is, in the second example where Vf=Vt=1 V, there is enough overdrive voltage to drive the power switch HEMT 175. However, since all transistors in Figure 1 including the power switch HEMT 175 use the same threshold voltage, the reduced threshold voltage at the power switch HEMT 175 may make the noise immunity of the output power switch 175 significantly worse. This is because it cannot withstand the large back feedthrough pulse (di/dt) voltage to the gate of the output power switch 175. Because there is an inevitable parasitic capacitance between the drain and the gate of the power switch HEMT 175, the voltage pulse will be fed back from the drain of the power switch HEMT 175 to the gate of the power switch HEMT 175 through the parasitic capacitance. As long as the noise voltage is greater than the reduced threshold voltage of the power switch HEMT 175, the power switch HEMT 175 may be accidentally turned on even when the circuit 100 is turned off.

Therefore, in the third example, the forward voltages and threshold voltages of all transistors in FIG. 1 are not all the same. In the third example, assuming that the transistors 142 and 143 have an ultra-low threshold voltage of 0.5 V, the transistors 165, 166, 173, and 174 have a low threshold voltage of 1 V, while the other transistors in Figure 1 have 1.5 V. The high threshold voltage. In this situation, when the circuit 100 is turned off, the node 181 has the same voltage of 6 V, which enables the transistors 161, 162, 163 to be turned on. Thus, the node 185 is electrically connected to the ground VSS 111 and has a voltage of 0V. Thus, the transistor 165 is turned off, and the node 186 is electrically connected to the ground VSS 111 and has a voltage of 0V. Therefore, the transistor 166 is turned off, and the node 183 is electrically connected to the ground VSS 111 and has a voltage of 0V. The capacitor 122 is charged by the power supply pin VDD 102 through the transistor 142. Since the transistor 142 has a forward voltage Vf equal to its threshold voltage, the node 184 may have a maximum voltage of 6 V-Vf = 6 V-0.5 V = 5.5 V.

When the circuit 100 is turned on, the node 181 has the same voltage of 0 V as the ground VSS 111, which enables the transistors 161, 162, 163 to be turned off. Thus, the node 185 is electrically connected to the node 184 and has the same voltage as the node 184. This causes transistor 165 to turn on, which enables node 186 to be charged by the voltage at node 184. This in turn causes the transistor 166 to turn on, which enables the node 183 to be charged by the power supply pin VDD 102. Therefore, the node 183 has a maximum voltage of 6V as the voltage of the power supply pin VDD 102 is the same. Based on the 5.5 V voltage difference stored by the capacitor 122 when the circuit 100 is disconnected, the voltage at the node 184 can be charged to the maximum and increased to 6 V + 5.5 V = 11.5 V, that is, the voltage at the node 184 is bootstrapped To 11.5 V. Therefore, the node 185 electrically connected to both the source and gate of the transistor 164 is also charged to 11.5V. While node 186 is also charged by the voltage of 11.5 V at node 184, the voltage of node 186 cannot reach 11.5 V. Since the node 186 is electrically connected to the source of the transistor 165, in order to keep the transistor 165 on, the gate-source voltage difference Vgs of the transistor 165 must be greater than the threshold voltage Vt=1V of the transistor 165. Therefore, when the circuit 100 is turned on, the maximum voltage that the node 186 can reach in the third example is 11.5 V-1 V = 10.5 V.

The node 182 is electrically connected to the node 181 and has the same voltage as the voltage of the node 181. That is, when the circuit 100 is turned off, the node 182 has a voltage of 6 V; when the circuit 100 is turned on, the node 182 has a voltage of 0 V. When the circuit 100 is turned off, the 6 V voltage at the node 182 enables the transistors 171, 172 to be turned on. Thus, the node 187 is electrically connected to the ground VSS 111, and has a voltage of 0V. Here, as described above, when the circuit 100 is turned off, the transistor 173 is turned off due to the 0 V voltage at the node 186. Since the node 187 has a voltage of 0V, the transistor 174 is turned off, and the node 188 is electrically connected to the ground VSS 111 and has a voltage of 0V. In this case, the capacitor 123 is charged by the power supply pin VDD 103 through the transistor 143 connected to the diode. Since the transistor 143 connected to the diode has a forward voltage Vf equal to its threshold voltage, the node 189 has a maximum voltage of 6 V-Vf = 6 V-0.5 V = 5.5 V.

When the circuit 100 is turned on, the node 182 and the node 181 have the same voltage of 0 V as the ground VSS 111, which enables the transistors 171 and 172 to be turned off. As described above, when the circuit 100 is turned on, the node 186 electrically connected to the gate of the transistor 173 has a maximum voltage of 10.5V. Thus, the transistor 173 is turned on and the node 187 is charged by the node 189. This causes transistor 174 to conduct, which enables node 188 to be charged by power supply pin VDD 103. Therefore, the voltage at the node 188 can be charged to 6 V as much as the voltage at the power supply pin VDD 102. Based on the 5.5 V voltage difference stored by the capacitor 123 when the circuit 100 is disconnected, the voltage at the node 189 can be charged to the maximum and increased to 6 V + 5.5 V = 11.5 V, that is, the voltage at the node 189 is bootstrapped To 11.5 V.

When the node 187 is charged by the voltage of 11.5 V at the node 189, the voltage of the node 187 cannot reach 11.5 V. Since the node 187 is electrically connected to the source of the transistor 173, in order to keep the transistor 173 on, the gate-source voltage difference Vgs of the transistor 173 must be greater than the threshold voltage Vt=1 V of the transistor 173. Since the gate of the transistor 173 is electrically connected to the node 186, when the circuit 100 is turned on, the node 186 has a maximum voltage of 10.5 V, so when the circuit 100 is turned on, the maximum voltage that the node 187 can reach in the third example is 10.5 V − Vt = 10.5 V–1 V = 9.5 V. Now the transistor 174 has a gate-source voltage difference Vgs=9.5V-6 V=3.5V, and the gate-source voltage difference is much larger than the threshold voltage Vt=1V of the transistor 174. This leaves enough voltage margin at the last stage of the multi-stage bootstrap boost driver. That is, in the third example, there is enough overdrive voltage to drive the power switch HEMT 175. In addition, since the power switch HEMT 175 has a larger threshold voltage Vt = 1.5 V, the noise immunity of the output power switch 175 will be better than that of the second example, because the larger threshold voltage Vt of the power switch HEMT 175 can obviously Withstand the pulse voltage noise that is fed back from the drain of the power switch HEMT 175 to the gate of the power switch HEMT 175. In various embodiments, the power switch HEMT 175 may have an even larger threshold voltage (eg, 2V). The disclosed circuit design of dual-threshold voltage transistors or multi-threshold voltage transistors can reduce both the threshold voltage of the pull-up E-HEMT transistor of the multi-level driver and the forward voltage of the E-HEMT rectifier connected to the diode. Provide sufficient overdrive voltage and significantly reduce quiescent current without compromising the noise immunity of the output power switch. In order to use dual threshold voltage transistors or multi-threshold voltage transistors in the same integrated circuit, the active layer parts corresponding to different transistors formed on the same wafer may be different in material composition, thickness and/or material structure of.

2A illustrates a cross-sectional view of an exemplary semiconductor element 200-1 including transistors with different polarizations according to some embodiments of the present disclosure. As shown in FIG. 2A, the semiconductor device 200-1 in this example includes a silicon layer 210 and a transition layer 220 provided on the silicon layer 210. The semiconductor element 200-1 further includes a first layer 230 including a first III-V group semiconductor material formed on the transition layer 220. For example, the first group III-V semiconductor material may be gallium nitride (GaN).

The semiconductor element 200-1 further includes an AlGaN layer (also referred to as a first sublayer) 231 and an AlGaN layer (also referred to as a second sublayer) 232 disposed on the first layer 230. The AlGaN layer in this example includes a first sublayer 231 and a second sublayer 232 disposed on the left portion of the first sublayer 231. The semiconductor device 200-1 further includes a first transistor 201 and a second transistor 202 formed on the first layer 230. The AlGaN layer has different thicknesses at different positions of the semiconductor element 200-1. For example, the AlGaN layer is thicker at the first transistor 201 and thinner at the second transistor 202.

The first transistor 201 includes a first gate structure 251, a first source region (also called a source) 281, and a first drain region (also called a drain) 291. The second transistor 202 includes a second gate structure 252, a second source region (also called a source) 282, and a second drain region (also called a drain) 292. The semiconductor element 200-1 further includes polarization modulation layers 241, 242 disposed on the AlGaN layers 231, 232, and includes partially disposed on the polarization modulation layers 241, 242 and partially disposed on the AlGaN layer. 231, 232 on the passivation layer 250. In one embodiment, the polarization modulation layers 241 and 242 include p-type doped GaN (pGaN).

The source electrodes 281 and 282 and the drain electrodes 291 and 292 of the two transistors 201 and 202 are formed through the AlGaN layers 231 and 232 and the passivation layer 250 and are disposed on the first layer 230. The first gate structure 251 is disposed on the polarization modulation layer 241 (also referred to as the pGaN portion 241) and between the first source region 281 and the first drain region 291. The second gate structure 252 is disposed on the polarization modulation layer 241 (also referred to as the pGaN portion 242) and between the second source region 282 and the second drain region 292.

In one embodiment, the first transistor 201 and the second transistor 202 are high electron mobility transistors to be used in the same multi-level driver circuit. For example, the second transistor 202 is used as a power switch transistor and has a first threshold voltage. The first transistor 201 is used as a driver transistor and has a second threshold voltage lower than the first threshold voltage. Therefore, the AlGaN layer (including both the first sub-layer 231 and the second sub-layer 232) under the first transistor 201 is higher than the AlGaN layer under the second transistor 202 (including only the first sub-layer 231) Thicker to have higher polarization.

In addition, the semiconductor device 200-1 includes an interlayer dielectric (ILD) layer 260 partially disposed on the passivation layer 250 and partially disposed on the first transistor 201 and the second transistor 202. The semiconductor device 200-1 also includes a metal contact 271 disposed on the source 281, 282 and the drain 291, 292 and in contact with the source 281, 282 and the drain 291, 292, and includes a metal contact 271 on the The first metal layer 272.

FIG. 2B illustrates a cross-sectional view of an exemplary semiconductor element 200-2 including transistors with different polarizations according to some embodiments of the present disclosure. The semiconductor element 200-2 in FIG. 2B is similar to the semiconductor element 200-1 in FIG. 2A, except that the AlGaN layer in the semiconductor element 200-2 has the same under the first transistor 201 and the second transistor 202. thickness. As shown in FIG. 2B, the active AlGaN layer in this example includes a first active part 233 under the gate of the first transistor 201 and a second active part 234 under the gate of the second transistor 202. The first active part 233 and the second active part 234 have the same thickness but different Al compositions.

In one embodiment, the first transistor 201 and the second transistor 202 are high electron mobility transistors to be used in the same multi-level driver circuit. For example, the second transistor 202 is used as a power switch transistor and has a first threshold voltage. The first transistor 201 is used as a driver transistor and has a second threshold voltage lower than the first threshold voltage. Therefore, the first active part 233 under the gate of the first transistor 201 has a higher Al composition than the second active part 234 under the gate of the second transistor 202 to introduce higher polarization.

2C shows a cross-sectional view of an exemplary semiconductor element 200-3 including transistors with different polarizations according to some embodiments of the present disclosure. The semiconductor device 200-3 in FIG. 2C is similar to the semiconductor device 200-2 in FIG. 2B, except that the active AlGaN portion of the semiconductor device 200-3 under the first transistor 201 and the second transistor 202 has a different Thickness and different Al composition. As shown in FIG. 2C, the active AlGaN layer in this example includes a first active part 235 under the gate of the first transistor 201 and a second active part 236 under the gate of the second transistor 202. The first active part 235 is thicker than the second active part 236 and has a different Al composition from the second active part 236.

In one embodiment, the first transistor 201 and the second transistor 202 are high electron mobility transistors to be used in the same multi-level driver circuit. For example, the second transistor 202 is used as a power switch transistor and has a first threshold voltage. The first transistor 201 is used as a driver transistor and has a second threshold voltage lower than the first threshold voltage. Therefore, the first active part 235 under the gate of the first transistor 201 has a higher Al composition than the second active part 236 under the gate of the second transistor 202 and is higher than that of the second transistor 202. The second active portion 236 under the gate is thick to introduce higher polarization.

2D shows a cross-sectional view of an exemplary semiconductor element 200-4 including transistors with different polarizations according to some embodiments of the present disclosure. The semiconductor device 200-4 in FIG. 2D is similar to the semiconductor device 200-2 in FIG. 2B, except that the active AlGaN portion of the semiconductor device 200-4 under the first transistor 201 and the second transistor 202 has a different Material structure. As shown in FIG. 2D, the active AlGaN layer in this example includes a first active part 237 under the gate of the first transistor 201 and a second active part 238 under the gate of the second transistor 202. Although the first active portion 237 has a homogeneous structure including AlGaN with a single constant Al ratio, the second active portion 238 has a graded structure including a plurality of sublayers, each of which includes AlGaN with different Al ratios. In one embodiment, the first transistor 201 and the second transistor 202 are high electron mobility transistors to be used in the same multi-level driver circuit. For example, the second transistor 202 is used as a power switch transistor and has a first threshold voltage. The first transistor 201 is used as a driver transistor and has a second threshold voltage lower than the first threshold voltage.

In some embodiments, when the first III-V semiconductor material is GaN in the first layer 230 and when the second III-V semiconductor material is Al _x Ga _1-x N in the second active portion 238 , The aluminum composition in the second active part 238 changes from low to high from the bottom. For example, x=0% at the interface between the second active part 238 and the first layer 230. Then for the second active part 238, x gradually increases from 0% to, for example, about 50%. The graded Al _x Ga _1-x N layer can clearly conform to the GaN layer (which is a pseudomorphic of the GaN layer) to obtain practically misfit-dislocation-free (and no penetration) Al _x Ga _1-x N/GaN interface with threading-dislocation-free, causing trap free.

Figure 3A, Figure 3B, Figure 3C, Figure 3D, Figure 3E, Figure 3F, Figure 3G, Figure 3H, Figure 3I, Figure 3J, Figure 3K, Figure 3L, Figure 3M, Figure 3N, Figure 3O and Figure 3P show that according to Cross-sectional views of exemplary semiconductor components during various stages of fabrication of some embodiments of the present disclosure. In some embodiments, the semiconductor element may be included in an integrated circuit (IC). In addition, in order to better understand the concept of the embodiments of the present disclosure, FIGS. 3A to 3P are simplified. For example, although the figure shows two transistors, it should be understood that the semiconductor element may include more than two transistors, and the integrated circuit may include many other elements (including resistors, capacitors, inductors, fuses, etc.) ), for clarity of illustration, the other elements are not shown in FIGS. 3A to 3P.

3A is a cross-sectional view of a semiconductor device including a substrate 310 according to some embodiments of the present disclosure, and the substrate 310 is provided at one of the various manufacturing stages. As shown in FIG. 3A, the substrate 310 may be formed of silicon or another semiconductor material.

3B is a cross-sectional view of a semiconductor device including a transition or buffer layer 320 formed on the substrate 310 at one of the various manufacturing stages according to some embodiments of the present disclosure. The transition or buffer layer 320 may be formed by epitaxial growth. According to various embodiments, the transition or buffer layer 320 includes a nucleation layer (nucleation layer) formed of aluminum nitride (AlN) and serves as a buffer to reduce the relationship between the substrate 310 and the top of the transition or buffer layer 320. The stress between the layers. In one embodiment, the transition or buffer layer 320 and operation steps shown in FIG. 3B are optional and the transition or buffer layer 320 shown in FIG. 3B can be removed.

3C is a cross-sectional view of a semiconductor device including a first III-V semiconductor material layer 330 according to some embodiments of the present disclosure, the first III-V semiconductor material layer 330 is optionally formed at one of the various manufacturing stages It is formed on the transition or buffer layer 320 or directly on the substrate 310. The first III-V semiconductor material layer 330 may be formed by epitaxial growth. According to various embodiments, the first III-V semiconductor material layer 330 includes gallium nitride (GaN). When the first III-V semiconductor material layer 330 (also referred to as the GaN layer 330) is formed on the transition or buffer layer 320, the transition or buffer layer 320 can reduce the substrate 310 and the first III-V semiconductor material layer 330 The stress between. After the transistor is formed on the first III-V semiconductor material layer 330, the first III-V semiconductor material layer 330 serves as a channel layer of the transistor.

3D is a cross-sectional view of a semiconductor device including a second III-V semiconductor material layer 331 according to some embodiments of the present disclosure. The second III-V semiconductor material layer 331 uses a mask 335 at one of the various production stages. It is formed on the first III-V group semiconductor material layer 330. The second III-V semiconductor material layer 331 may be formed by epitaxial growth. According to various embodiments, the second III-V semiconductor material layer 331 includes aluminum gallium nitride (AlGaN). After forming transistors on the first III-V semiconductor material layer 330 and the second III-V semiconductor material layer 331 (also referred to as the first AlGaN layer 331, AlGaN layer 331), the first III-V semiconductor material layer A two-dimensional electron gas (2-DEG) is formed at the interface between the group semiconductor material layer 330 and the second group III-V semiconductor material layer 331. As shown in FIG. 3D, while the mask 335 covers the left part of the first III-V semiconductor material layer 330, the second III-V semiconductor material layer 331 is disposed on the first III-V semiconductor material layer 330. On the middle part and the right part.

3E is a cross-sectional view of a semiconductor device including a third III-V semiconductor material layer 332 according to some embodiments of the present disclosure. The third III-V semiconductor material layer 332 utilizes a mask 335 at one of the various production stages. And the mask 336 is formed on a part of the second III-V group semiconductor material layer 331. The third III-V semiconductor material layer 332 may be formed by epitaxial growth. According to various embodiments, the third III-V semiconductor material layer 332 includes aluminum gallium nitride (AlGaN). That is, while the second III-V semiconductor material layer 331 is the first AlGaN layer on the GaN layer 330, the third III-V semiconductor material layer 332 (also referred to as the second AlGaN layer 332, AlGaN Layer 332) is the second AlGaN layer on the GaN layer 330. As shown in FIG. 3E, while the mask 336 covers the right portion of the first AlGaN layer 331, the second AlGaN layer 332 is disposed on the left portion of the first AlGaN layer 331, that is, on the first III-V semiconductor material. Above the middle part of layer 330. In this example, the second AlGaN layer 332 has the same Al composition as the first AlGaN layer 331. Thus, the AlGaN portions located on the middle portion and the right portion of the first III-V semiconductor material layer 330 have the same Al composition but different thicknesses.

3F is a cross-sectional view of a semiconductor element including a third AlGaN layer or portion 333 according to some embodiments of the present disclosure. The third AlGaN layer or portion 333 is formed on the first AlGaN layer or portion 333 using a patterned mask 337 at one of the various manufacturing stages. On a part of the III-V semiconductor material layer 330. The third AlGaN layer 333 may be formed by epitaxial growth. According to various embodiments, the third AlGaN layer 333 includes aluminum gallium nitride (AlGaN). As shown in FIG. 3F, while the patterned mask 337 covers the middle part and the right part of the first III-V semiconductor material layer 330, the third AlGaN layer 333 (also referred to as AlGaN layer 333) is disposed on the first III-V semiconductor material layer 330. -On the left part of the group V semiconductor material layer 330. In this example, the third AlGaN layer 333 has a different Al composition from the first AlGaN layer 331 and the second AlGaN layer 332. As shown in FIG. 3F, the AlGaN portions located on the left portion and the middle portion of the first III-V semiconductor material layer 330 have the same thickness but different Al composition.

3G is a cross-sectional view of a semiconductor element according to some embodiments of the present disclosure, in which at one of the various manufacturing stages, after the third AlGaN portion 333 is formed, the mask 337 is removed from the AlGaN layer. After the mask 337 is removed, the AlGaN layer located on the GaN layer 330 has different thicknesses at different positions on the wafer and different Al compositions at different positions on the wafer. Specifically, the left part of the AlGaN layer has an Al composition different from the middle and right parts of the AlGaN layer; the right part of the AlGaN layer is thinner than the middle and left parts of the AlGaN layer.

3H is a cross-sectional view of a semiconductor element including p-type doped GaN (pGaN) layers 341, 342, and 343 according to some embodiments of the present disclosure. The p-type doped GaN (pGaN) layers 341, 342, and 343 are in various production stages. One place is formed on the AlGaN layers 331, 332, and 333. The pGaN layers 341, 342, and 343 are patterned to form the island region shown in FIG. 3H. The patterning of the pGaN layer includes, for example: (i) forming a masking layer (for example, photoresist, oxide hard mask, SiN hard mask, etc.) on the pGaN layer. The masking layer includes And (ii) removing the portion of the pGaN layer exposed by the masking layer (for example, through a wet etching process or a dry etching process). The pGaN layers 341, 342, and 343 (also referred to as pGaN portions 341, 342, and 343) may be referred to as polarization modulation layers that modulate the dipole concentration in the AlGaN layers 331, 332, and 333. ) To cause a change in the concentration of 2-DEG in the AlGaN/GaN interface channel. Although the polarization modulation layer is formed for the enhancement mode (usually off) AlGaN/GaN HEMT, the polarization modulation layer is not required in the depletion mode (usually on) AlGaN/GaN HEMT.

3I is a cross-sectional view of a semiconductor device including a passivation layer 350 formed on the AlGaN layers 331, 332, 333 and the polarization modulation layer at one of the various production stages according to some embodiments of the present disclosure. The passivation layer 350 is formed on the AlGaN layers 331, 332, and 333 and on the remaining parts of the polarization modulation layers 341, 342, and 343. According to various embodiments, the passivation layer 350 is formed using a deposition process (eg, chemical deposition, physical deposition, etc.). The passivation layer 350 may include silicon oxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide, carbon-doped silicon nitride, carbon-doped silicon oxynitride, zinc oxide, zirconium oxide, hafnium oxide, titanium oxide, or another The right material. In one embodiment, after the passivation layer 350 is deposited, the passivation layer 350 undergoes a polishing and/or etching process. The polishing and/or etching process includes, for example, a chemical-mechanical planarization (CMP) (ie, chemical mechanical polishing) process, which is used to polish the surface of the passivation layer 350 and remove topographic irregularities (Topographical irregularities).

FIG. 3J shows source contacts (also referred to as source and source regions) 381, 382, 383 and drain contacts (also referred to as drain and drain regions) 391, 392 according to some embodiments of the present disclosure. A cross-sectional view of the semiconductor device of 393 and 393. At one of the various production stages, the source contacts 381, 382, 383 and the drain contacts 391, 392, 393 pass through the AlGaN layer 331, 332, 333 and the passivation layer 350 It is formed and disposed on the first III-V group semiconductor material layer 330. The source contact and the drain contact can be formed as a non-rectifying electrical junction, that is, an ohmic contact.

3K is a cross-sectional view of a semiconductor device including a mask 355 formed on the passivation layer 350 at one of the various manufacturing stages according to some embodiments of the present disclosure. At this stage, the mask 355 has a pattern for exposing the portion of the passivation layer 350 on top of the pGaN portions 341, 342, 343. Thus, by using the patterned mask 355 to etch the passivation layer 350, a first opening 357 is formed on the pGaN portion 341 between the first pair of source electrodes 381 and the drain electrode 391; The layer 350 is etched, and a second opening 358 is formed on the pGaN portion 342 between the second pair of source electrodes 382 and the drain electrode 392; and the passivation layer 350 is etched by using the patterned mask 355, in the third pair of source electrodes A third opening 359 is formed in the pGaN portion 343 between the 383 and the drain electrode 393.

3L is a cross-sectional view of a semiconductor device including a first gate 351, a second gate 352, and a third gate 353 according to some embodiments of the present disclosure. The first gate 351, the second gate 352, and the third gate 353 is deposited and polished in the first opening 357, the second opening 358, and the third opening 359 at one of the various production stages, respectively. According to various embodiments, the first gate 351, the second gate 352, and the third gate 353 may be formed of metal materials such as tungsten (W), nickel (Ni), titanium/tungsten/titanium nitride (Ti/W /TiN) metal stack or titanium/nickel/titanium nitride (Ti/Ni/TiN) metal stack.

3M is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure, in which at one of the various manufacturing stages, metal gates (ie, the first gate 351, the second gate 352, and the third gate 353 are formed. , Also known as gate structures 351, 352, 353), the mask 355 is removed from the passivation layer 350. After the mask 355 is removed, each of the source regions 381, 382, 383, drain regions 391, 392, 393, and gate structures 351, 352, 353 has an exposed portion on top of the passivation layer 350 .

3N is a cross-sectional view of a semiconductor device including an interlayer dielectric (ILD) layer 360 formed on the passivation layer 350 at one of the various manufacturing stages according to some embodiments of the present disclosure. The ILD layer 360 covers the passivation layer 350 and the exposed portions of the source regions 381, 382, 383, the drain regions 391, 392, 393, and the gate structures 351, 352, 353 formed at the stage shown in FIG. 3M. The ILD layer 360 is formed of a dielectric material and can be patterned to have metal interconnects or source contacts 381, 382, 383 and drain contacts 391, 392, 393 and gate structures 351, 352, 353 Multiple holes in the contacts.

3O is a cross-sectional view of a semiconductor device including metal contacts 371 according to some embodiments of the present disclosure. Each of the metal contacts 371 is formed on the source contact or the drain at one of the various manufacturing stages. On the contact. As described above, the ILD layer 360 is patterned to have a plurality of holes, each of which is located in one of the source contacts 381, 382, 383 and the drain contacts 391, 392, 393 on. Thus, metal contacts 371 can be formed in these holes to contact the source contacts 381, 382, and 383 and the drain contacts 391, 392, and 393, respectively.

3P is a cross-sectional view of a semiconductor device including a first metal layer 372 formed on the metal contact 371 at one of the various manufacturing stages according to some embodiments of the present disclosure. The first metal layer 372 includes a metal material and is formed on the ILD layer 360 and is in contact with the metal contact 371.

4A and 4B illustrate a flowchart of an exemplary method 400 for forming a semiconductor device including transistors with different polarizations according to some embodiments of the present disclosure. As shown in FIG. 4A, at operation 402, a transition/buffer layer is formed on the semiconductor substrate by epitaxial growth. At operation 404, a GaN layer is formed on the transition/buffer layer by epitaxial growth. At operation 406, a first Al _x Ga _1-x N layer is formed on the GaN layer by epitaxial growth using a mask. At operation 408, a second Al _x Ga _1-x N epitaxial layer is grown by using a first mask on the Al _x Ga _1-x N layer. At operation 410, an Al _y Ga _1-y N layer is formed on the GaN layer by epitaxial growth using a mask. At operation 412, the mask on the AlGaN layer is removed. At operation 414, a polarization modulation layer is deposited and defined on the AlGaN layer. At operation 415, the passivation layer is deposited and polished on the polarization modulation layer and the AlGaN layer. The process then proceeds to operation 416 in FIG. 4B.

As shown in FIG. 4B, at operation 416, a source ohmic contact and a drain ohmic contact are formed through the passivation layer and the AlGaN layer. At operation 418, an opening is defined for the metal gate region on the polarization modulation layer by etching using a mask. At operation 420, a metal gate material is deposited and polished in the opening to form a gate. At operation 422, the mask on the passivation layer is removed. At operation 424, a dielectric layer is deposited and polished on the source, drain, gate, and passivation layer. At operation 426, metal contacts are formed and defined on the source, drain, and gate. At operation 428, a first metal layer is formed and defined on the dielectric layer and the metal contact. According to different embodiments of the disclosed embodiments, the sequence of operations shown in FIG. 4A and FIG. 4B can be changed.

In an embodiment, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer formed on the substrate and including a first active part and a second active part; a first transistor including a first source region, a first drain region, and a first A gate structure, the first gate structure is formed on the first active portion and between the first source region and the first drain region; and a second transistor including a second source A pole region, a second drain region, and a second gate structure, the second gate structure being formed on the second active portion and between the second source region and the second drain region , Wherein the first active part has a material composition different from that of the second active part.

In the semiconductor structure, the first transistor and the second transistor are high electron mobility transistors used in the same multi-level driver circuit.

In the semiconductor structure, the first transistor has a first threshold voltage; and the second transistor has a second threshold voltage lower than the first threshold voltage.

In the semiconductor structure, both the first active portion and the second active portion include aluminum gallium nitride (AlGaN); the first active portion has a first Al ratio; and the second active portion It has a second Al ratio higher than the first Al ratio.

In the semiconductor structure, the first active portion has a first thickness; and the second active portion has a second thickness greater than the first thickness.

In the semiconductor structure, the first active portion has a graded structure including a plurality of sublayers, each of the plurality of sublayers includes aluminum gallium nitride (AlGaN) with a different Al ratio; and the The second active part has a homogeneous structure including aluminum gallium nitride (AlGaN) with a single constant Al ratio.

In the semiconductor structure, the semiconductor structure further includes a channel layer formed on the substrate and under the active layer, wherein: the channel layer includes a first III-V semiconductor material; and the active layer The layer includes a second group III-V semiconductor material different from the first group III-V semiconductor material.

In the semiconductor structure, the first III-V semiconductor material includes gallium nitride (GaN); and the second III-V semiconductor material includes aluminum gallium nitride (AlGaN).

In another embodiment, a circuit is disclosed. The circuit includes: a first transistor including a first gate, a first source, and a first drain; and a second transistor including a second gate, a second source, and a second drain. The first transistor and the second transistor are formed on the same semiconductor wafer including an active layer. The active layer includes a first active part under the first gate and a second The second active part under the gate. The first active part has a material thickness different from the material thickness of the second active part.

In yet another embodiment, a circuit is disclosed. The circuit includes: a first transistor including a first gate, a first source, and a first drain; and a second transistor including a second gate, a second source, and a second drain. The first transistor and the second transistor are formed on the same semiconductor wafer including an active layer. The active layer includes a first active part under the first gate and a second The second active part under the gate. The first active part has a material composition different from that of the second active part.

In the circuit, the first transistor has a first threshold voltage; and the second transistor has a second threshold voltage different from the first threshold voltage.

In the circuit, at least one of the first source and the first drain is electrically connected to a ground voltage; and at least one of the second source and the second drain is electrically connected Connect to the positive supply voltage.

In the circuit, the first threshold voltage is higher than the second threshold voltage.

In the circuit, both the first active part and the second active part include aluminum gallium nitride (AlGaN); the first active part has a first Al ratio; and the second active part has A second Al ratio higher than the first Al ratio.

In the circuit, the first active part has a graded structure including a plurality of sublayers, each of the plurality of sublayers includes aluminum gallium nitride (AlGaN) with a different Al ratio; and The two active parts have a homogeneous structure that includes aluminum gallium nitride (AlGaN) with a single constant Al ratio.

In the circuit, at least one of the first source and the first drain is electrically connected to an output pin of the circuit.

In the circuit, the first transistor is at least one of the following: high voltage enhancement mode high electron mobility transistor (HV E-HEMT), low voltage enhancement mode high electron mobility transistor (LV E -HEMT), and a low voltage depletion mode high electron mobility transistor (LV D-HEMT); and the second transistor is a low voltage enhancement mode high electron mobility transistor.

In the circuit, the first gate is physically coupled to the second source.

In yet another embodiment, a method of forming a semiconductor structure is disclosed. The method includes: forming an active layer on a substrate, wherein the active layer includes a first active portion and a second active portion; forming a first transistor, the first transistor including a first source region, a first A drain region and a first gate structure, the first gate structure being formed on the first active portion and between the first source region and the first drain region; and forming a second The second transistor includes a second source region, a second drain region, and a second gate structure. The second gate structure is formed on the second active part and the second Between the source region and the second drain region. The first active part has a material composition and thickness different from those of the second active part.

In yet another embodiment, a method of forming a semiconductor structure is disclosed. The method includes: forming an active layer on a substrate, wherein the active layer includes a first active portion and a second active portion; forming a first transistor, the first transistor including a first source region, a first A drain region and a first gate structure, the first gate structure being formed on the first active portion and between the first source region and the first drain region; and forming a second The second transistor includes a second source region, a second drain region, and a second gate structure. The second gate structure is formed on the second active part and the second Between the source region and the second drain region. The first active part has a material composition different from that of the second active part.

In the method for forming a semiconductor structure, the first transistor and the second transistor are high electron mobility transistors used in the same multi-level driver circuit; the first transistor has a first The threshold voltage; the second transistor has a second threshold voltage lower than the first threshold voltage; the first active part includes aluminum gallium nitride (AlGaN) with a first Al ratio; and the second The active part contains aluminum gallium nitride having a second Al ratio higher than the first Al ratio.

In the method for forming a semiconductor structure, forming the active layer includes: defining a first opening on a mask covering a channel layer located on the substrate; and forming a first opening including a plurality of sublayers in the first opening A graded structure, wherein each of the plurality of sublayers includes aluminum gallium nitride (AlGaN) having a different Al ratio; a second opening is defined on the mask; a homogeneous structure is formed in the second opening , Wherein the homogeneous structure includes aluminum gallium nitride with a single constant Al ratio; and the mask is removed to form the first active portion with the gradual structure and the first active portion with the homogeneous structure Two active part.

The above content summarizes the features of several embodiments or examples so that those skilled in the art can better understand the aspects of the disclosed embodiments. Those skilled in the art should understand that they can easily use the disclosed embodiments as a basis for designing or modifying other manufacturing processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations in this article without departing from the spirit and scope of the present disclosure.

100: Circuit 101, 102, 103, VDD: power supply pins 110, 120, 130: level 111, 112, VSS: ground 121, 122, 123: capacitor 131: Input pin 133: output pin 141, 142, 151, 152, 153, 154, 155, 156, 161, 162, 163, 164, 165, 166, 171, 172, 173, 174: Transistor 143: Transistor/Diode connected Transistor 175: Power switch HEMT/power switch transistor/power switch 181, 182, 183, 184, 185, 186, 187, 188, 189: nodes 191: Low voltage enhancement mode high electron mobility transistor (LV E-HEMT) 192: Low voltage depletion mode high electron mobility transistor (LV D-HEMT) 193: High Voltage Enhanced Mode High Electron Mobility Transistor (HV E-HEMT) 200-1, 200-2, 200-3, 200-4: semiconductor components 201: The first transistor/transistor 202: second transistor/transistor 210: Silicon layer 220: transition layer 230: first layer 231: AlGaN layer/first sublayer 232: AlGaN layer/second sublayer 233, 235, 237: the first active part 234, 236, 238: the second active part 241, 242: polarization modulation layer/pGaN part 250, 350: passivation layer 251: first gate structure 252: second gate structure 260, 360: Interlayer dielectric (ILD) layer 271, 371: Metal contacts 272, 372: first metal layer 281: first source region/source 282: second source region/source 291: First Drain Region/Drain 292: Second Drain Region/Drain 310: Base 320: transition/buffer layer 330: The first III-V group semiconductor material layer/GaN layer 331: Second III-V semiconductor material layer/first AlGaN layer/AlGaN layer 332: The third III-V group semiconductor material layer / the second AlGaN layer / AlGaN layer 333: Third AlGaN layer/third AlGaN part/AlGaN layer 335, 336, 337: Curtain 341, 342, 343: p-type doped GaN (pGaN) layer/polarization modulation layer/pGaN part 351: first gate/gate structure 352: second gate/gate structure 353: third gate/gate structure 357: The first opening 358: second opening 359: The Third Opening 381, 382, 383: source contact/source/source area 391, 392, 393: Drain contact/Drain/Drain area 400: method 402, 404, 406, 408, 410, 412, 414, 415, 416, 418, 420, 422, 424, 426, 428: Operation LoVout: Low-side voltage output Vin: input voltage

Reading the following detailed description in conjunction with the accompanying drawings will best understand all aspects of the embodiments of the present disclosure. It should be noted that the various features are not drawn to scale. In fact, in order to make the discussion clear, the size and geometric structure of various features can be increased or decreased arbitrarily. Throughout this specification and in all drawings, the same reference numbers indicate the same features. Figure 1 shows an exemplary circuit with a multi-stage bootstrap boost driver according to some embodiments of the present disclosure. 2A, 2B, 2C, and 2D illustrate cross-sectional views of exemplary semiconductor elements according to some embodiments of the present disclosure, the exemplary semiconductor elements each including a transistor with a different polarization. Figure 3A, Figure 3B, Figure 3C, Figure 3D, Figure 3E, Figure 3F, Figure 3G, Figure 3H, Figure 3I, Figure 3J, Figure 3K, Figure 3L, Figure 3M, Figure 3N, Figure 3O and Figure 3P show that according to Cross-sectional views of exemplary semiconductor components during various stages of fabrication of some embodiments of the present disclosure. 4A and 4B illustrate a flowchart of an exemplary method for forming a semiconductor element including transistors with different polarizations according to some embodiments of the present disclosure.

310: Base

320: transition/buffer layer

330: The first III-V group semiconductor material layer/GaN layer

331: Second III-V semiconductor material layer/first AlGaN layer/AlGaN layer

332: The third III-V group semiconductor material layer / the second AlGaN layer / AlGaN layer

333: Third AlGaN layer/third AlGaN part/AlGaN layer

341, 342, 343: p-type doped GaN (pGaN) layer/polarization modulation layer/pGaN part

350: passivation layer

351: first gate/gate structure

352: second gate/gate structure

353: third gate/gate structure

360: Interlayer dielectric (ILD) layer

371: Metal contacts

372: first metal layer

381, 382, 383: source contact/source/source area

391, 392, 393: Drain contact/Drain/Drain area

Claims (1)

A semiconductor structure including: Base An active layer formed on the substrate and including a first active part and a second active part; The first transistor includes a first source region, a first drain region, and a first gate structure. The first gate structure is formed on the first active portion and the first source region and Between the first drain regions; and The second transistor includes a second source region, a second drain region, and a second gate structure. The second gate structure is formed on the second active portion and the second source region and Between the second drain regions, the first active part has a material composition different from that of the second active part.

Images