TW202046006A - Reducing roughness of extreme ultraviolet lithography resists - Google Patents

Abstract

Provided herein are methods and systems for reducing roughness of EUV resists and improving etched features. The methods may involve depositing a thin film on a patterned EUV resist having a stress level that is less compressive than a stress level of the patterned EUV resist. The resulting composite stress may reduce buckling and/or bulging of the patterned EUV resist.

Description

Reduced roughness of extreme ultraviolet light lithography photoresist

The present invention relates to the reduction of roughness of extreme ultraviolet light lithography photoresist.

In the manufacture of micron-level and nano-level devices, such as semiconductor processing for manufacturing semiconductor devices, patterning of thin films is usually a critical step. Patterning involves lithography. In the conventional photolithography technology (for example, 193 nm photolithography), the pattern is printed in the following way: photons are emitted from the photon source onto the mask and the pattern is printed on the light-sensitive photoresist, by This causes a chemical reaction in the photoresist, which removes certain parts of the photoresist after development to form a pattern.

Advanced technology nodes (as defined in the international semiconductor technology development blueprint) include 22 nm, 16 nm and other nodes. In the 16 nm node, for example, the width of a typical via or line in a damascene structure is usually no greater than about 30 nm. The scaling of features on advanced semiconductor integrated circuits (IC) and other components is driving lithography technology to improve resolution.

Extreme Ultraviolet (EUV) lithography works with different light sources and photoresist materials at the 30 nm level. EUV lithography may cause two types of roughness in the photoresist: high-frequency roughness caused by the probability effect of secondary electrons, and due to the interaction between the size, geometry and mechanical properties of the photoresist material Low-frequency roughness (also known as "wiggling"). Both roughnesses are undesirable.

The method and equipment for reducing the roughness of EUV photoresist are disclosed herein. The roughness is reduced by reducing the compressive stress of the photoresist layer. This can be achieved by depositing a conformal film whose stress is less compressive or even stretched compared to photoresist. The resulting composite stress reduces bending and/or bumps, thereby reducing low-frequency roughness.

In one aspect of the embodiments disclosed herein, a method for reducing the roughness of EUV photoresist is proposed. The method includes: providing a substrate to a processing chamber, the substrate comprising a patterned EUV photoresist , The patterned EUV photoresist has a first stress level; and depositing a conformal film on the patterned EUV photoresist, the conformal film having a second stress level, The second stress level is less compressed than the first stress level, so that the third stress level of the patterned EUV photoresist resulting from the deposition of the conformal film is compared It is less compressive at this first stress level.

In various embodiments, the substrate is a semiconductor wafer that contains semi-finished semiconductor components. In some embodiments, the conformal film has a thickness not greater than 2 nm. In other embodiments, the conformal film has a thickness of about 1 nm.

In some implementations, the second stress level of the conformal film is tensile. In other embodiments, the second stress level of the conformal film is compressive.

In various embodiments, the patterned EUV photoresist is characterized in that the line roughness is reduced after the deposition. In some embodiments, the line roughness includes one or more of line edge roughness (LER) and line width roughness (LWR). In various embodiments, the line roughness is a low-frequency line roughness. In some implementations, the low frequency line roughness has a spatial frequency less than 0.05 nm ^-1 . In some embodiments, the line roughness is a high-frequency line roughness. In various embodiments, the high frequency line roughness has a spatial frequency greater than 0.05 nm ^-1 .

In some implementations, the conformal film includes a Si-based dielectric. In various embodiments, the dielectric is SiO ₂ . In some implementations, the conformal film is deposited by ALD. In some implementations, the ALD includes plasma-enhanced ALD, where one cycle includes the flow of oxygen plasma having a power between 10W and 2500W and a duty cycle between 25% and 50%.

In some embodiments, the EUV photoresist includes a chemically amplified photoresist (CAR), an organic metal, or an organic metal oxide. In various embodiments, the organometal oxide is an organotin oxide.

In some implementations, the line edge roughness is reduced from about 0.1 to 1 nm ⁴ (PSD). In some embodiments, the method also includes: etching the substrate layer in the processing chamber after the deposition of the conformal film.

In another aspect of the embodiments herein, a substrate processing apparatus is proposed. The apparatus includes: one or more processing chambers, each of which includes a substrate support; entering one of the processing chambers Or more gas inlets and related flow control hardware; one or more substrate handling devices; and a controller having at least one processor and a memory, wherein the at least one processor and the memory system are communicatively connected to each other, The at least one processor is at least operatively connected to the one or more substrate handling devices and the flow control hardware, the memory system stores a plurality of computer executable instructions, and the plurality of computer executable instructions is used to control the at least one processor To control at least the one or more substrate handling devices and the flow control hardware to: provide a substrate to a processing chamber, the substrate including a patterned EUV photoresist on a substrate layer to be etched, The patterned EUV photoresist has a first stress level; and depositing a conformal film on the patterned EUV photoresist, the conformal film having a second stress level, the second stress level It is less compressed than the first stress level, so that a third stress level of the patterned EUV photoresist resulting from the deposition of the conformal film is compared to the first stress level For less compressed.

These and other features of the disclosed embodiments will be described in detail below with reference to related drawings.

In the following description, several specific details will be presented to provide a thorough understanding of the embodiments. The embodiments disclosed herein can be implemented without some or all of these specific details. In other cases, the conventional processing operations are not described in detail, so as not to unnecessarily obscure the disclosed embodiments. Although specific embodiments will be used to illustrate the disclosed embodiments, it should be understood that they are not intended to limit the disclosed embodiments.

Extreme ultraviolet light (EUV) lithography can be used in semiconductor manufacturing at technology nodes of 30 nm and below. With smaller and smaller critical dimensions, reducing (for example, minimizing) the photoresist and the roughness of the resulting etching can improve the process yield and device performance. The roughness can be measured by the line edge roughness (LER) and line width roughness (LWR) of the photoresist and the resulting etching. Reducing (eg, minimizing) both LER and LWR can improve the results of the EUV lithography process.

Roughness can have high-frequency and low-frequency parts, and these parts can be represented by a power spectral density (PSD) curve. Figure 4 has a representative PSD curve 402. The PSD curve is usually drawn on a logarithmic-logarithmic graph. The horizontal axis represents the spatial frequency of the roughness (which is also the reciprocal of the wavelength of the roughness, ie 0.01 nm ^-1 = 100 nm), and the vertical axis is the PSD value, which is linearly related to LER or LWR. The area under the PSD curve represents the total variance, which should be minimized for any etching process under ideal conditions.

The post exposure of EUV lithography photoresist has two types of roughness: low frequency and high frequency. High-frequency roughness is characterized by short variations in the photoresist, and can be caused by a variety of factors, including secondary electrons that are inherently emitted during EUV lithography. This is the area on the right side of the PSD curve 402, at about 0.1 nm ^-1 or higher. The low frequency roughness is the longer wavelength variation in the photoresist, and is shown in the left part of the PSD curve 402, at approximately 0.01 nm ^-1 or less. One reason for the low frequency roughness is the compressive stress in the photoresist. The compressive stress in the photoresist causes it to bend and/or bulge, resulting in low-frequency roughness, sometimes called "wiggling".

Some solutions to reduce the roughness of photoresist include plasma processing, carbon-based deposition, silicon oxide-based deposition, and etching by-product deposition. Each of these processes has various disadvantages. Plasma treatment can reduce the roughness by reflowing the photoresist, but it also reduces the height and selectivity of the photoresist. Carbon-based deposition may cause clogging at the top of the mask, thereby interfering with the etching process. The conventional silicon oxide-based deposition is selective at high aspect ratios, which affects the critical size and may cause disconnection or merging. The etching by-products may reduce the selectivity of the etching process and prevent the successful transfer of the photoresist pattern. In addition to the various shortcomings of each scheme, they can only deal with high-frequency roughness.

An alternative to reducing the roughness is to reduce the compressive stress in the photoresist layer. This can be accomplished by depositing a conformal film, and the stress of the conformal film is less compressive than photoresist, or even stretched. The resulting composite stress reduces bending and/or bumps, thereby reducing low-frequency roughness.

Conformal thin films can be deposited by plasma enhanced atomic layer deposition (ALD) processing. By modulating O ₂ plasma during the ALD process, the internal stress of the conformal film can be changed to less compression/more tension. The resulting composite photoresist/oxide layer has less compression and reduced bending and/or bumps. In some embodiments, the conformal film can be 1-2 nm thick, but still improves the low frequency roughness.

According to the disclosed embodiment, FIG. 1 provides a process flow chart of operations for executing the method. The operation in FIG. 1 can be performed, for example, at a chamber pressure between about 1 mTorr and about 100 Torr, for example, between about 1 mTorr and about 1 Torr. The method shown in Figure 1 generally involves deposition on a semiconductor substrate. Specifically, in operation 102, the semiconductor substrate is provided to the processing chamber, and the semiconductor substrate is composed of or includes a plurality of different substrate materials (including a patterned EUV photoresist layer).

The patterned EUV photoresist layer can be composed of various materials. In some embodiments, the patterned EUV photoresist layer can be composed of organic or inorganic metal-containing oxide films, such as organotin oxides available from Inpria Corp., or from Dow/Rohm, Fujifilm and Traditional chemically amplified photoresist obtained by Shin-Etsu Polymer. The patterned EUV photoresist may also include chemically amplified photoresist. The patterned EUV photoresist layer can be, for example, 30-40 nm thick.

With reference to the chamber that received the semiconductor substrate in operation 102, the chamber may be in a multi-chamber device or a single-chamber device. The semiconductor substrate can be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including a wafer having one or more material layers (for example, dielectric, conductive, or semiconductor materials) deposited thereon . In some embodiments, the semiconductor substrate includes a cover layer of silicon (for example, amorphous silicon) or a cover layer of germanium.

In some embodiments, the layers on the substrate can be patterned. The substrate may have "features", such as vias or contact holes, which may be narrow and/or recessed openings, fillings in the features, or high aspect ratios. The features may be formed in one or more of the above-mentioned layers. An example of a feature is a hole or via in a semiconductor substrate, or a layer on the substrate. Another example is a trench in a substrate or layer. In various embodiments, the feature may have a lower layer, such as a barrier layer or an adhesion layer. Non-limiting examples of lower layers include dielectric layers and conductive layers, such as silicon oxide, silicon nitride, silicon carbide, metal oxide, metal nitride, metal carbide, and metal layer.

In operation 104, a conformal thin film is deposited on the semiconductor substrate. The conformal film can include a variety of materials. In some embodiments, the conformal film is silicon oxide. In other embodiments, the conformal film may be silicon nitride. Conformal films can also be composed of carbon-based oxides. In various embodiments, the conformal film is composed of a material that will not be removed during subsequent substrate etching. The conformal film can be less than 3 nm thick, less than 2 nm thick, 1-2 nm thick, or about 2 nm thick. The thickness is not sufficient to adversely affect the critical dimensions of the manufactured features. By changing the deposition conditions, conformal films can be designed to have different levels of internal stress. In some embodiments, the conformal film has internal tensile stress. In other embodiments, the conformal film has a lower compressive stress than a patterned EUV photoresist.

In some embodiments, conformal thin films can be deposited by plasma enhanced ALD. Generally speaking, ALD is a technique that uses sequential self-limiting reactions to deposit thin material layers. Any suitable technique can be used to implement ALD. In various embodiments, plasma may be used, or heat may be used to implement ALD. In addition, operation 104 may be implemented in a cyclic manner, that is, referred to as an "ALD cycle" herein.

Referring to FIG. 2, a schematic diagram of a thin film deposited on a substrate by ALD is shown. In various embodiments, a silicon-containing film is deposited, such as silicon oxide (eg, SiO ₂ ), silicon oxynitride, or silicon nitride. ALD is a technique that uses sequential self-limiting reactions to deposit thin layers of materials. Any suitable technique can be used to implement ALD. In various embodiments, ALD can be implemented using plasma, or can use heat, and can be cyclically.

The concept of "ALD cycle" is related to the discussion of various embodiments in this article. Generally, an ALD cycle is a minimum set of operations for performing the surface deposition reaction once. For example, as a result of one cycle, at least a portion of the silicon-containing film layer is generated on the surface of the substrate, such as the semiconductor substrate material in operation 104. Generally, an ALD cycle includes the operation of transporting and adsorbing at least one reactant to the surface of the substrate, and then reacting the adsorbed reactant with one or more reactants to form a partial film. Recycling may include certain auxiliary operations, such as purging one of the reactants or by-products, and/or processing part of the deposited film. Usually, a cycle contains one of a unique series of operations. As an example, an ALD cycle can include the following operations: (i) transport/adsorption of silicon-containing precursors, (ii) purge of silicon-containing precursors from the chamber, (iii) transport of second reactants (such as oxidants) ) And plasma, and (iv) blow off the plasma from the chamber.

According to the present disclosure, batch intermediate adjustment purge can be used at appropriate intervals between ALD cycles to increase the batch size. According to various embodiments, the deposition/batch mid-batch adjustment purge cycle can be repeated throughout the batch until the maximum accumulation limit is reached.

Figure 2 shows an exemplary schematic diagram of an ALD cycle used to deposit silicon oxide (SiO ₂ ). Figures 282a-282e show a typical ALD cycle. In 282a, a silicon substrate is provided, which includes many silicon atoms. In 282b, a silicon-containing precursor or silicon source is introduced to the substrate, and some silicon atoms will be adsorbed on the substrate. In 282c, the unadsorbed silicon-containing precursor or silicon source is purged from the chamber. In 282d, oxygen is introduced as oxygen radicals, and the adsorbed silicon reacts with the oxygen radicals on the surface of the substrate to form an SiO ₂ film. In 282e, the chamber is blown out and the by-products are removed, leaving a SiO ₂ deposited layer.

In some embodiments, the film deposited by ALD can be highly conformal. The conformality of the film can be measured by the step coverage. The step coverage can be calculated by comparing the average thickness of the deposited film on the bottom, sidewall, or top of the feature with the average thickness of the deposited film on the bottom, sidewall, or top of the feature. For example, the step coverage can be calculated by dividing the average thickness of the deposited film on the sidewall by the average thickness of the deposited film on the top, and multiplying the result by 100 to obtain a percentage.

Unlike chemical vapor deposition (CVD) technology, ALD processing uses surface media deposition reactions to deposit films layer by layer. In an example of the ALD process, the surface of the substrate containing a group of surface active sites is exposed to the vapor distribution region of the first precursor (for example, a silicon-containing precursor), and the first precursor is provided to the receiving substrate by injection The processing chamber. The molecules of the first precursor are adsorbed on the surface of the substrate, including chemically adsorbed species and/or physically adsorbed molecules of the first precursor. It should be understood that when the compound is adsorbed onto the surface of the substrate (as described herein), the adsorption layer may include the compound, as well as derivatives of the compound. For example, the adsorption layer of the silicon-containing precursor may include a silicon-containing precursor and a derivative of the silicon-containing precursor. In some embodiments, the injection of the ALD precursor partially saturates the substrate surface. In some embodiments, the injection phase of the ALD cycle ends before the precursor contacts the substrate to evenly saturate the surface. Usually, at this time, the precursor flow is closed or diverted, and only the purge gas flows. By operating in a sub-saturated state, ALD processing reduces cycle time and increases throughput. However, because the adsorption of the precursor is not saturation-limited, the concentration of the adsorbed precursor may vary slightly across the surface of the substrate. An example of an ALD process operating in a sub-saturation state is provided in: US Patent Application No. 14/061,587 with the filing date of October 23, 2013 and the name "SUB-SATURATED ATOMIC LAYER DEPOSITION AND CONFORMAL FILM DEPOSITION" , Its entire content is incorporated into this article for reference. After the injection of the first precursor, the reactor is then emptied to remove any first precursor that remains in the gas phase, leaving only the adsorbed species. The second reactant (for example, oxygen-containing or nitrogen-containing gas) is introduced into the reactor to cause some of the molecules to react with the first precursor adsorbed on the surface. In some processes, the second precursor immediately reacts with the adsorbed first precursor. In other embodiments, the second precursor only reacts after the activation source is temporarily applied. The reactor can then be emptied again to remove unbound second precursor molecules. Additional ALD cycles can be used to increase the film thickness.

In some implementations, the ALD method includes plasma activation, such as when the second reactant is delivered to the chamber. As described herein, the ALD method and equipment described herein may be a conformal film deposition (CFD) method, which is roughly described in: US Patent Application No. 13/084,399 (now US Patent No. 8,728,956), The filing date is April 11, 2011, and the name is "PLASMA ACTIVATED CONFORMAL FILM DEPOSITION"; and U.S. Patent Application No. 13/084,305, the filing date is April 11, 2011, and the name is "SILICON NITRIDE FILMS AND METHODS", the entire content of which is incorporated herein as a reference. Additional examples of ALD processing are described in Puurunen’s "Surface chemistry of atomic layer deposition: for the trimethylaluminum/water process, 97 J. Applied Physics 12301 (2005)", which is incorporated herein as a reference for providing Description of suitable ALD treatment.

In some embodiments, the carrier gas (eg, N ₂ , Ar, Ne, He, and combinations thereof) may flow continuously. The carrier gas can be used as a purge gas. Inert gas can be provided to assist the pressure and/or temperature control of the processing chamber, the evaporation of liquid reactants, to transport the reactants more quickly and/or as a purge gas to be used from the processing chamber and/or the processing chamber The pipeline removes processing gas.

In the adsorption operation of the ALD cycle, the substrate can be exposed to film precursors, such as silicon tetrachloride (SiCl ₄ ) or aminosilane, to be adsorbed on the surface of the substrate. In some embodiments, the film precursor may be a silicon-containing precursor. In some embodiments, the film precursor is bis(tert-butyl-amino)silane (BTBAS). In some embodiments, the film precursor (for example, SiCl ₄ ) can be adsorbed on about 60% of the substrate surface. In various embodiments, when the film precursor flows to the chamber, the film precursor is adsorbed on the active sites on the surface of the substrate, forming a thin layer of the film precursor on the surface. In various embodiments, this layer may be smaller than a single layer.

After adsorption, the chamber can optionally be purged to remove excess precursors in the gas phase that are not adsorbed on the surface of the substrate. Purging may involve purging gas, which may be a carrier gas used in other operations or a different gas. In some embodiments, purging may involve emptying the chamber.

In the second reactant delivery operation of the ALD cycle, the substrate can be exposed to the second reactant and optionally plasma. In various embodiments, the second reactant is oxygen (O ₂ ) or nitrogen (N ₂ ) or a combination thereof. In some embodiments where the silicon oxide layer is deposited, oxygen is used as the second reactant. In some embodiments, both the flow of the second reactant and the plasma are turned on. In some embodiments, the flow of the second reactant is turned on before the plasma is turned on, for example, to stabilize the flow of the second reactant.

In some embodiments, the optional plasma is an in-situ plasma such that the plasma is formed directly above the surface of the substrate in the chamber. In various embodiments, the plasma may be inductively coupled plasma or capacitively coupled plasma. The inductively coupled plasma can be set between about 50W and about 2000W. In some embodiments, the plasma can be turned on and off according to the duty cycle (DC), where the plasma power is turned on and off cyclically. In some embodiments, the duty cycle can vary between 25% and 50%, meaning that the plasma is turned on between 25% and 50% of the operating time. In some embodiments, a bias voltage between about 0V and about 500V may be applied. During the delivery of the second reactant, the film precursor (eg SiCl ₄ ) is turned off. The substrate can be exposed to the second reactant and optional plasma for a duration that exceeds the time for the plasma to interact with all the precursors adsorbed on the surface of the substrate, thereby forming a continuous film on the surface of the substrate.

After the second reactant delivery operation, the chamber can be purged, for example, by introducing carrier gas or inert gas. The conditions for this operation can be any of the conditions described above with regard to the blowing process.

In various embodiments, the ALD cycle can be repeated. For example, the operation for ALD can be performed for about 5 to about 70 cycles. Any suitable number of deposition cycles may be included to deposit the deposited film of the desired film thickness. In some embodiments, about 1 Å can be deposited per ALD cycle. Depending on the exposure time of the operation, a film with a thickness between about 0.05 Å and about 5 Å can be deposited per cycle, such as silicon oxide or silicon oxynitride film. In some embodiments, about two to about three ALD cycles may be performed per minute. In some embodiments, for example, in a chamber where the entrance is closer to the substrate, more than about three cycles may be performed per minute.

Returning to FIG. 1, at operation 106, the substrate is optionally etched. In some embodiments, as described above, after the EUV photoresist is patterned, the substrate under the patterned EUV photoresist is etched. The etching can be performed immediately after the EUV photoresist is patterned, in the same chamber, and does not break the vacuum. The patterned EUV photoresist and the conformal film are used as a mask for the substrate, so that the area covered by the patterned EUV photoresist is not etched. The conformal film may have a lower etching rate than the substrate material to ensure that it remains on the patterned EUV photoresist throughout the etching process. Due to the more tensile stress of the conformal film, the patterned EUV photoresist and conformal film layer have reduced LER and/or LWR, which also reduces the LER and LWR of the etched substrate below.

The following table provides example processing conditions for depositing conformal films as shown in Figure 1: First reactant Second reactant pressure 1mT to 100Torr 1mT to 100Torr power 0W 10 to 2500W bias 0V 0V to 50V temperature -10C to 200C -10C to 200C time 0.5 seconds to 4 seconds 0.5 seconds to 4 seconds Flow rate 50sccm to 5000sccm 50sccm to 5000sccm

Figures 3A and 3B are graphs with and without the roughness of the conformal film layer as described herein. In FIG. 3A, the photoresist 302a is a pattern of a part of the photoresist that can be developed on a semiconductor substrate. The photoresist 302a has internal compressive stress, which causes bending of the photoresist and therefore increases LER and LWR. The photoresist 302a can be represented by a low-frequency roughness 303-1 and a high-frequency roughness 303-2, which respectively represent two roughnesses of the photoresist 302a. The low frequency roughness 303-1 is partly caused by the compressive stress of the photoresist 302a, which causes bending and/or bumps.

FIG. 3B is a diagram of EUV photoresist according to the embodiment disclosed herein. The photoresist 302b has a conformal film 305 deposited thereon. The conformal film 305 is characterized by less tensile stress or less compressive stress than the photoresist 302b, and the addition of the conformal film 305 produces a composite photoresist 306, which has a smaller compressive stress than the photoresist 302b. Due to the reduced compressive stress, the composite photoresist 306 has reduced low frequency roughness.

In some embodiments, the conformal film 305 is silicon oxide deposited by plasma enhanced ALD. The plasma-enhanced ALD process can be changed to deposit films with various levels of internal stress (from compression to tension). By depositing a film with a smaller compressive stress than the photoresist, the film cancels the compressive stress of the photoresist and reduces the possible bending and/or bumps, resulting in less low-frequency roughness. In other embodiments, different dielectric materials can be used as long as they have a compressive stress smaller than that of the photoresist.

According to an example of the present disclosure, FIG. 4 is a graph and chart showing the effect of the conformal film deposited on the EUV photoresist under different ALD conditions. Graph 402 shows power spectral density (PSD) curves for four different deposition conditions. Since the PSD value is directly related to the line edge roughness (LER), a lower PSD value also means a smaller LER. Line 404 is a PSD of EUV photoresist without any treatment. Line 405 is the PSD of EUV photoresist after a conformal film composed of silicon oxide is deposited at 300W 50%DC. Line 406 is a PSD of EUV photoresist after a conformal film composed of silicon oxide is deposited at 75W 3%DC. Line 407 is a PSD of EUV photoresist after a conformal film composed of silicon oxide is deposited at 75W 50%DC. As shown in graph 402, line 404 does not have a conformal film and has the largest PSD value, while lines 405-407 show improved PSD values. The following table shows the processing conditions of the reactants in the ALD cycle of each conformal film in this example. The processing conditions of the first reactant of each conformal film are the same on all conformal films, but the processing conditions of the second reactant are different. The first reactant (all the same) The second reactant 75W 50%DC The second reactant 300W 50%DC The second reactant 75W 3%DC pressure 90mT 30mT 30mT 30mT power 0W 75W 50%DC 300W 50%DC 75W 3%DC bias 0V 0V 0V 0V temperature 60C 60C 60C 60C time 1 second 1.5 seconds 1.5 seconds 1.5 seconds Flow rate 50µL/min BTBAS, 500 sccm He 200sccm O ₂ , 1000sccm He, 1000sccm Ar 200sccm O ₂ , 1000sccm He, 1000sccm Ar 200sccm O ₂ , 1000sccm He, 1000sccm Ar Number of cycles 10 10 10 10 thickness no 1.3nm 1.3nm 0.9nm

Graph 412 provides additional information related to graph 402. Rows 414-417 show the correlation between processing conditions, film internal stress and PSD value at a spatial frequency of 0.01 nm ^-1 . Roughness with a spatial frequency of 0.01 nm ^-1 is considered low-frequency roughness, so a lower PSD value at this spatial frequency is usually associated with reduced low-frequency roughness. Row 414 is related to line 404, showing data for EUV photoresist without any conformal film, and its PSD value is 13.4 nm ⁴ . Line 415 is related to line 405, showing the data of the conformal film deposited on EUV photoresist at 75W 50%DC, the internal stress is +25MPa (positive number is tensile stress, and negative number is compressive stress), and the resulting The PSD value is 5.4 nm ⁴ , which is 60% better than the PSD value of EUV photoresist without conformal film. Row 416 is related to line 406, showing the data of the conformal film deposited on EUV photoresist at 300W 50%DC, the internal stress is -25MPa, and the PSD value obtained is 8.12 nm ⁴ , an improvement of 40%. Finally, line 417 is related to line 407, showing the data of the conformal film deposited on EUV photoresist at 75W 3%DC. The internal stress is -46MPa and the PSD value is 11.5 nm ⁴ , which is better than EUV without conformal film. The original PSD value of photoresist has been improved by 14%.

It can be clearly seen from the graphs and graphs that the EUV photoresist of the conformal film with the largest tensile stress has the lowest PSD value and therefore the lowest LER. EUV photoresist without any conformal film or conformal film with less tensile stress has a larger PSD value and therefore a larger LER.

Figure 5 is a schematic diagram of an application of EUV photoresist. Stack 502 is a series of substrate layers with EUV photoresist 503 on top. The EUV photoresist is patterned so that features are formed in the substrate layer during the etching process. The feature is etched to a depth 504, which in this example is about 185 nm, but the feature depth may be larger or smaller. When features are etched through the layers, the roughness of the EUV photoresist will affect the roughness of the etched layer. Image 506 represents an image of etched features in the substrate, where each feature has a deformation. By improving the roughness of EUV photoresist, the roughness of etched features will also be improved.

Figure 6 is a graph and table showing the influence of the deposited film on the LER of the target layer under different ALD conditions. Graph 602 shows the PSD curve under four different conditions. Since the PSD value is directly related to the LER, a lower PSD value also means a smaller LER. Line 604 is the PSD without the EUV photoresist layer of conformal film before etching the substrate. Line 605 is the PSD of the target layer after etching with EUV photoresist without conformal film. Line 606 is the PSD of the target layer after etching using EUV photoresist with conformal film (made of 75W 50%DC silicon oxide). Line 607 is the PSD of the target layer after etching the substrate using EUV photoresist with conformal film (made of 75W 3%DC silicon oxide). As shown, line 604 does not have a conformal film and has the largest PSD value, while lines 605-607 show improved PSD values. The two conformal films were deposited under the same or similar processing conditions as shown in Figure 4 above.

Graph 612 provides additional information related to graph 602. Rows 614-617 provide the stress, the PSD value at a spatial frequency of 0.01 nm ^-1 , and the percentage improvement of the PSD value before etching, and the percentage improvement of the PSD value after etching. The roughness with a spatial frequency of 0.01 nm ^-1 is considered low-frequency roughness, so a lower PSD value at this spatial frequency is usually associated with reduced low-frequency roughness. Row 614 shows the data for EUV photoresist layer before etching and without conformal film. Row 615 shows the data of the target layer after etching with EUV photoresist layer without conformal film. Row 616 shows the data on the conformal film (75W 50%DC) deposited on the EUV photoresist, and its internal stress is +25MPa (positive numbers are related to tensile stress, while negative numbers represent compressive stress). Finally, row 617 shows the data of conformal film (75W 3%DC) deposited on EUV photoresist, and its internal stress is -46MPa.

Columns 618 and 619 show the improvement of using the conformal film disclosed herein. The value in column 618 represents the improvement of the PSD value of EUV photoresist with conformal film (compared to EUV photoresist without conformal film). For the same processing conditions, these numbers are the same as those shown in the figure. The value in column 619 represents the improvement of the PSD value after etching the target layer with and without the conformal film. Through etching treatment, the roughness can be slightly reduced by 10%. However, the addition of a conformal film can greatly reduce the roughness. Conformal film deposition at 75W and 50% DC will result in a 60% reduction in roughness before etching and a 72% reduction in roughness after etching. Conformal film deposition at 75W and 3% DC will result in a relatively low 14% reduction in roughness before etching, but etching treatment will result in a 37% reduction in roughness after etching.

From the graphs and graphs, it can be clearly seen that the EUV photoresist of the conformal film with larger tensile stress has higher tensile stress than the EUV photoresist without conformal film or conformal film with lower tensile stress. A small PSD value, so a small LER. Then, the reduction of the LER of the EUV photoresist can be transferred to the target layer during the subsequent etching process, thereby reducing the LER and LWR of the etched features. equipment

FIG. 7A is a schematic cross-sectional view showing a plasma processing system that can be used for etching operations according to various embodiments. The system includes a chamber 732 which includes a cavity 714, a chuck 716, and a dielectric window 706. The chamber 732 includes a processing area, and the dielectric window 706 is disposed above the processing area. The chuck 716 may be an electrostatic chuck for supporting the substrate 712 and is disposed under the processing area in the chamber. In some embodiments, an internal Faraday shield (not shown) is disposed inside the cavity 732 under the dielectric window 706. The TCP coil 734 is disposed above the dielectric window 706 and connected to the matching circuit 702.

The system includes a bias RF generator 720, which can be defined by one or more generators. If multiple generators are provided, different frequencies can be used to achieve various tuning characteristics. The bias matching member 718 is coupled between the RF generator 720 and the conductive plate defining the components of the chuck 716. The chuck 716 also includes electrostatic electrodes to allow wafer clamping and de-chucking. Broadly speaking, a filter and a DC clamp power supply can be provided. Other control systems for lifting the wafer from the chuck 716 can also be provided.

The first gas injector 704 provides two different channels to inject the two separate flows of the process gas or liquid precursor (in the form of vapor) from the top of the chamber into the chamber. It should be understood that multiple gas supplies may be provided to supply different gases to the chamber for various types of operations, such as on-wafer processing operations, waferless automatic cleaning (WAC) operations, and other operations. The second gas injector 710 provides another gas flow that enters the chamber via the side instead of from the top.

In the embodiment of Figure 7A, independent gas streams can be delivered into the chamber. A flow can be injected through the center of the syringe 704. The second flow can also be injected through the syringe 704, but through a different path around the center of the syringe 704. The third flow can be injected into the side of the chamber via the side injector 710. In one embodiment, the gas injector 704 also provides optical access into the processing chamber, for example, along an axial path from a diagnostic end point outside the processing chamber through the optical access window. For more details on the optical access into the chamber, please refer to the announcement date April 19, 2011, and the title is "Methods of and Apparatus for Accessing a Process Chamber Using a Dual Zone Gas Injector with Improved Optical Access" US Patent No. 7,928,366, the disclosure of which is incorporated herein as a reference.

Various ways of injecting gas into the chamber have been described to illustrate that the etching gas and/or liquid precursor can be provided into the chamber from various locations. In some examples, only syringe 704 is used. In other examples, only the side syringe 710 is used. In other examples, both syringe 704 and side syringe 710 may be used. In one configuration, the manifold 722 controls which gas is supplied to each of the three different gas lines. The manifold 722 allows any type of gas (reactant, modifier, precursor, etc.) to be supplied to any of the three different gas pipelines. In some embodiments, the adjustment gas may include a gas such as oxygen (O ₂ ) or helium (He). The gas can be delivered into the chamber without mixing before being introduced into the chamber, or mixed with other gases.

A vacuum pump 730 is connected to the chamber 732 to allow vacuum pressure control and removal of gas by-products from the chamber during operation of the plasma processing. The valve 726 is disposed between the exhaust portion 724 and the vacuum pump 730 to control the amount of vacuum suction applied to the chamber.

The dielectric window 706 may be defined by ceramic materials or ceramic materials. Other dielectric materials are also possible, as long as they can withstand the conditions of the semiconductor etching chamber. Typically, the chamber operates at elevated temperatures, ranging between zero degrees Celsius and approximately 200 degrees Celsius. The temperature will depend on the etching process operation and the specific recipe. The chamber 732 will also operate under vacuum conditions, ranging between about 1 millitorr (mT) and about 500 millitorr (mT). When used in this article, the terms "about" and "approximately" mean that the specified parameters can vary within a reasonable tolerance (for example, ± 20%).

Although not all are shown in detail, when installed in a clean room or a processing facility, the chamber 732 is usually coupled to a plurality of facilities. Facilities include pipeline systems that provide processing gas, vacuum, temperature control, and environmental particle control, etc. When the chamber 732 is installed in the target processing facilities, these facilities are coupled to the chamber 732. In addition, the chamber 732 may be coupled to the transfer chamber, which allows the robotic arm to transfer semiconductor wafers in and out of the chamber 732 using automated operations.

The programmable controller 708 is provided for controlling the operation of the chamber 732 and related components. Broadly speaking, the controller 708 can be programmed to perform the chamber operations defined by the recipe. A given recipe can specify various parameters for operation, such as the application of power to the TCP coil, the flow of gas into the chamber, and the application of vacuum. It should be understood that the timing, duration, size, or any other adjustable parameters or controllable features can be defined by recipes and executed by the controller to control the operation of the chamber 732 and its related components. In addition, a series of recipes can be programmed into the controller 708. In one embodiment, the recipe is used to process the etching operation and includes one or more cycles of atomic layer deposition (ALD) processing performed between each of the etching operations.

7B is a schematic cross-sectional view of a plasma processing system that can be used for etching operations according to various embodiments. As shown in FIG. 7B, the chuck 716 is disposed in a cavity 714 which is provided with a dielectric window 706. In one embodiment, the chuck 716 is an electrostatic chuck for supporting the substrate 712. The TCP coil 734 is disposed above the dielectric window 706 and connected to the matching circuit 702, and the matching circuit 702 is coupled to the RF generator 721. In the embodiment of FIG. 7B, the delivery system 728 includes an etching gas delivery system 727 and a liquid delivery system 729. The etching gas delivery system 727 delivers the etchant gas to the manifold 722 via the conduit 703. The liquid delivery system 729 delivers the liquid precursor (in vapor form) to the manifold 722 via the conduit 701, as described in more detail below with reference to FIG. 7C. The manifold 722, in response to the control from the controller 708, selects, switches, and/or mixes these outputs by using, for example, multiple valves for switching between gas and/or steam, so that the outputs are The output of the delivery system can flow to the cavity 714 via the conduit 705 at an appropriate time. The outputs from the respective delivery systems flow from the conduit 705 through the gas injector 704 into the cavity 714, which is located at the top of the cavity. In order to assist the cleaning of the chamber, the base of the cavity 714 is provided with an outlet 715 which is connected to the pump 717 in flow communication. In one embodiment, the pump 717 is a turbo pump. Those skilled in the art will understand that the base of the cavity 714 can be provided with multiple outlets, each of which is connected to a suitable pump.

Figure 7C is a schematic diagram depicting additional details of the liquid delivery system according to various embodiments. As shown in FIG. 7C, the liquid delivery system 729 includes a liquid precursor source 758, a liquid flow controller 760, and a vaporizer 762. The liquid precursor source 758 may be coupled in flow communication to a facility that provides a suitable liquid precursor. As mentioned above, any liquid precursor capable of forming a conformal atomic monolayer can be used. The liquid precursor flows from the source 758 to the liquid flow controller 760, which adjusts the flow based on instructions received from the controller 708 (see, for example, Figure 7B). In one embodiment, the amount of liquid precursor is in the range of about 50 microliters to about 1,000 microliters. The liquid precursor flows from the liquid flow controller 760 to the vaporizer 762, which converts the liquid precursor from liquid to gas. The vaporized precursor flows to the manifold 722, which, based on the control received from the controller 708, supplies the vaporized precursor to the gas injector 704 at an appropriate time (see, for example, FIG. 7A). The vaporized precursor flows through the gas injector 704 into the chamber 732 defined by the cavity 714 (see, for example, FIG. 7A).

As mentioned above, one or more processing workstations may be included in a multi-workstation processing tool. 8 shows a schematic diagram of an embodiment of a multi-station processing tool 800, which has an inbound loading room 802 and an outbound loading room 804. Either or both of the inbound loading room 802 and the outbound loading room 804 may include remote End plasma source (not shown in Figure 8). The robotic arm 806 under atmospheric pressure is used to move the wafer from the cassette (loaded through the cassette 808) to the inbound loading chamber 802 via the atmospheric port 810. The wafer (not shown in FIG. 8) is placed on the base 812 in the inbound loading chamber 802 by the robotic arm 806, the atmospheric port 810 is closed, and the inbound loading chamber 802 is evacuated. In the case where the inbound load chamber 802 includes a remote plasma source, the wafer may be exposed to the remote plasma processing in the inbound load chamber 802 before being introduced into the processing chamber 814. In addition, the wafer may also be heated in the inbound loading chamber 802, for example, to remove moisture and adsorbed gas. Next, open the chamber transfer port 816 to the processing chamber 814, and another robot arm (not shown) places the wafer in the reactor and at the base of the first workstation (shown in the reactor for processing) To proceed. Although the embodiment depicted in FIG. 8 includes a loading chamber, it should be understood that in some embodiments, the wafers can be directly entered into the processing station.

In the embodiment shown in FIG. 8, the depicted processing chamber 814 includes four processing workstations, numbered 1 to 4. Each workstation has a heated base (shown at 818 of workstation 1) and a gas pipeline inlet. It should be understood that in some embodiments, each processing workstation may have different or multiple purposes. For example, in some embodiments, the processing workstation can switch between ALC, ALD, and plasma enhanced ALD processing modes. In some embodiments, the exposure to the deposition precursor and the exposure to the second reactant and plasma are performed in the same workstation. Additionally or alternatively, in some embodiments, the processing chamber 814 may include one or more matched pairs of ALD and plasma enhanced ALD processing workstations. Although the depicted processing chamber 814 includes four workstations, it should be understood that the processing chamber according to the present disclosure may have any suitable number of workstations. For example, in some embodiments, the processing chamber may have five or more workstations, while in other embodiments, the processing chamber may have three or fewer workstations.

FIG. 8 depicts an embodiment of a wafer handling system 890 for transferring wafers in the processing chamber 814. In some embodiments, the wafer handling system 890 can transfer wafers between various processing workstations and/or between processing workstations and load chambers. It should be understood that any suitable wafer handling system can be used. Non-limiting examples include wafer carousels and wafer handling robots. FIG. 8 also depicts an embodiment of the system controller 850 for controlling the processing conditions and hardware status of the processing tool 800. The system controller 850 may include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processor 852 may include a CPU or a computer, analog and/or digital input/output connections, stepper motor controller boards, etc.

In some embodiments, the system controller 850 controls all activities of the processing tool 800. The system controller 850 executes the system control software 858, which is stored in the mass storage device 854, loaded into the memory device 856, and executed on the processor 852. Alternatively, the control logic can be hard-coded in the controller 850. For these purposes, application-specific integrated circuits, programmable logic devices (for example, field programmable gate arrays, or FPGAs), and the like can be used. In the following discussion, in any situation where "software" or "coding" is used, functionally comparable hard-coded logic can be used appropriately. The system control software 858 may include commands to control the following: timing, gas mixing, gas flow rate, chamber and/or workstation pressure, chamber and/or workstation temperature, wafer temperature, target power level, RF Power level, substrate base, chuck and/or bracket position, and other parameters of the specific process performed by the process tool 800. The system control software 858 can be configured in any suitable way. For example, various processing tool component subroutines or control objects can be written to control the operation of processing tool components used to implement various processing tool processing. The system control software 858 can be coded in any suitable computer-readable programming language.

In some embodiments, the system control software 858 may include input/output control (IOC) sequence commands to control the various parameters mentioned above. In some embodiments, other computer software and/or programs stored on the mass storage device 854 and/or the memory device 856 associated with the system controller 850 may be used. Examples of programs or program fragments used for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

The substrate positioning program may include a program code for processing tool components. The processing tool components are used to load the substrate on the base 818 and control the distance between the substrate and other parts of the processing tool 800.

The process gas control program may include codes to control the gas composition (for example, silicon-containing gas, oxygen-containing gas, and purge gas as described herein) and flow rate, and optionally, to make the gas before deposition Code that flows to one or more processing workstations to stabilize processing workstation pressure. The pressure control program may include a code for controlling the pressure in the processing workstation by adjusting, for example, the throttle valve in the exhaust system of the processing workstation, the gas flow entering the processing workstation, etc.

The heater control program may include a code for controlling the current to the heating unit, and the heating unit is used for heating the substrate. Alternatively, the heater control program can control the transfer of heat transfer gas (for example, helium) to the substrate.

According to the embodiments herein, the plasma control program may include a code for setting the RF power level applied to the processing electrodes in one or more processing workstations.

According to the embodiments herein, the pressure control program may include a code for maintaining pressure in the reaction chamber.

In some embodiments, there may be a user interface associated with the system controller 850. The user interface may include display screens, graphical software displays of equipment and/or processing conditions, and user input devices, such as pointing devices, keyboards, touch screens, microphones, etc.

In some embodiments, the parameters adjusted by the system controller 850 may be related to processing conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (for example, RF bias power level), etc. These parameters can be provided to the user in the form of a formula, and the formula can be input through the user interface.

With the analog and/or digital input connection of the system controller 850, various processing tool sensors can provide signals for monitoring processing. The signal used to control the processing can be output on the analog and digital output connections of the processing tool 800. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (eg, pressure gauges), thermocouples, etc. Properly programmed feedback and control algorithms can be used with data from these sensors to maintain processing conditions.

The system controller 850 can provide program instructions for implementing the aforementioned deposition process. Program instructions can control various processing parameters, such as DC power level, RF bias power level, pressure, temperature, etc. According to various embodiments described herein, the instructions may control parameters to operate the in-situ deposition of the film stack.

Typically, the system controller 850 will include one or more memory devices, and one or more processors for executing instructions, so that the device will execute the method according to the disclosed embodiment. A machine-readable medium may be coupled to the system controller 850, and the machine-readable medium includes instructions to control processing operations according to the disclosed embodiments.

In some implementations, the system controller 850 is part of the system, which may be part of the above example. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms for processing, and/or specific processing components (wafer base, gas flow System, etc.). These systems can be integrated with electronic components, which are used to control the operation of semiconductor wafers or substrates before, during, and after processing. Electronic components can be called "controllers", which can control various components or sub-parts of one or more systems. According to the processing conditions and/or system type, the system controller 850 can be programmed to control any processing disclosed in this article, including the delivery of processing gas, temperature setting (for example, heating and/or cooling), pressure setting, and vacuum setting , Power setting, radio frequency (RF) generator setting, RF matching circuit setting, frequency setting, flow rate setting, fluid delivery setting, positioning and operation setting, wafer transfer entering and leaving tools connected to or connected to a specific system And other transfer tools and/or loading rooms.

Broadly speaking, the system controller 850 is related to various integrated circuits, logic, memory, and various integrated circuits for receiving instructions, issuing instructions, controlling operations, performing cleaning operations, enabling end-point measurement, and achieving similar functions. ∕Or software electronic components. The integrated circuit may include a chip in the form of firmware storing program instructions, a digital signal processor (DSP), a chip defined as a special application integrated circuit (ASIC), and/or one or more microprocessors, or executing programs Command (for example, software) microcontroller. The program command can be a command communicated to the system controller 850 in the form of various individual settings (or program files), and defines the operating parameters used to perform specific processing on the semiconductor wafer, or the semiconductor wafer, or the system. In some embodiments, the operating parameters can be defined by the process engineer for the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies on the wafer A part of a formula that completes one or more processing steps during the period.

In some implementations, the system controller 850 may be part of a computer or coupled to a computer, the computer is integrated with the system, is coupled to the system, is networked to the system in other ways, or a combination thereof. For example, the system controller 850 may be in the "cloud" or all or a part of the fab host computer system to enable remote control of wafer processing. The computer allows remote control of the system to monitor the current processing of manufacturing operations, check the history of past manufacturing operations, check the trend or performance evaluation of multiple manufacturing operations, change the parameters of the current processing, and set after the current processing The processing steps, or start a new processing. In some examples, a remote computer (such as a server) can provide processing recipes to the system via a network, and the network can include a local area network or the Internet. The remote computer may include a user interface that enables input or programming of parameters and/or settings, which are then transferred from the remote computer to the system. In some examples, the system controller 850 receives instructions in the form of data, which specify parameters for each of the processing steps to be executed during one or more operation periods. It should be understood that these parameters may be specific to the type of processing to be performed and the type of tool that the system controller 850 interfaces with or controls. Therefore, as described above, the system controller 850 may be decentralized, for example by including one or more independent controls connected together by a network and working toward a common goal (such as the processing and control described herein) Device. An example of a distributed controller for such a goal would be one or more integrated circuits in the chamber, which are connected to the remote (for example, at the platform level or as a remote computer) Part) One or more integrated circuits are connected and combined to control the processing in the chamber.

Without limitation, exemplary systems may include plasma etching chambers or modules, deposition chambers or modules, rotary cleaning chambers or modules, metal plating chambers or modules, cleaning chambers or modules, oblique Edge etching chamber or module, physical vapor deposition (PVD) chamber or module, chemical vapor deposition (CVD) chamber or module, ALD chamber or module, atomic layer cleaning (ALC) chamber or Modules, ion implantation chambers or modules, orbital chambers or modules, and any other semiconductor processing systems related to or used in the processing and/or manufacturing of semiconductor wafers.

As described above, depending on the processing steps to be executed by the tool, the system controller 850 can communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools , Proximity tools, tools located at various locations in the factory, host computer, another controller, or tools used for material transfer in semiconductor manufacturing plants to move wafer containers in and out of tool positions and/or load ports.

Suitable equipment for implementing the method disclosed herein is further discussed and described in the United States Patent Application No. 13/084,399 (currently) filed on April 11, 2011 and entitled "PLASMA ACTIVATED CONFORMAL FILM DEPOSITION" U.S. Patent No. 8,728,956) and U.S. Patent Application No. 13/084,305 filed on April 11, 2011 and titled "SILICON NITRIDE FILMS AND METHODS", the entire contents of each are incorporated herein in.

The equipment/processing described herein can be used with, for example, lithographic patterning tools or processes used to process or manufacture semiconductor components, displays, LEDs, photovoltaic panels, etc. Generally speaking, although not necessary, such tools/processing will be used or performed together in a common manufacturing facility. Film lithography patterning usually includes some or all of the following operations, and each operation is provided by several possible tools: (1) The photoresist coating on the work piece (ie, the substrate), using spin coating (2) For curing of photoresist, use a hot plate or furnace or UV curing tool; (3) Use tools (for example, wafer stepper) to expose photoresist to visible light or UV light or x Ray light; (4) to develop the photoresist, so as to use tools (for example, wet cleaning table) to selectively remove the photoresist and thereby pattern it; (5) to use dry or plasma-assisted etching tools to remove the photoresist Transfer the resist pattern to the underlying film or work piece; and (6) Use a tool (for example, RF or microwave plasma photoresist stripper) to remove the photoresist. in conclusion

Although the above embodiments have been described in detail for the purpose of clear understanding, it is obvious that certain changes and modifications can be implemented within the scope of the appended patent application. It should be noted that there are many alternative ways to implement the processing, system, and equipment of the embodiment of this case. Therefore, the embodiments of this case should be regarded as illustrative rather than restrictive, and the embodiments of this case should not be limited to the details set forth herein.

1-4: Processing Station 102, 104, 106: Operation 282a-282e: Figure 302a, 302b: photoresist 303-1: Low frequency roughness 303-2: High frequency roughness 305: Conformal Film 306: Composite photoresist 402: Curve 404,405,406,407: line 412: Chart 414,415,416,417: OK 502: Stack 503: EUV photoresist 504: Depth 506: Image 602: Curve 604,605,606,607: line 612: chart 614,615,616,617: OK 618,619: columns 701: Catheter 702: matching circuit 703: Catheter 704: Gas Syringe 705: Catheter 706: Dielectric Window 708: Controller 710: Gas Syringe 712: substrate 714: cavity 715: exit 716: Chuck 717: Pump 718: Bias matching parts 720: Bias voltage RF generator 721: RF generator 722: Manifold 724: Exhaust Department 726: Valve 727: Etching Gas Delivery System 728: Conveying System 729: Liquid Delivery System 730: Vacuum pump 732: chamber 734: TCP coil 758: Source of Liquid Precursor 760: Liquid flow controller 762: Vaporizer 800: Multi-station processing tool 802: Inbound loading room 804: Outbound loading room 806: Robotic Arm 808: box 810: atmospheric port 812: Pedestal 814: processing chamber 816: Chamber Transmission Port 818: Pedestal 850: System Controller 852: processor 854: Mass storage device 856: Memory Device 858: system control software 890: Wafer Handling System

According to the disclosed embodiment, FIG. 1 is a processing flow chart depicting the operation of the method.

Fig. 2 is a schematic diagram of an embodiment of atomic layer deposition.

Figure 3A is a diagram of the high frequency and low frequency roughness.

FIG. 3B is a diagram of using the embodiments disclosed herein to reduce high frequency roughness.

Figure 4 is a data graph showing the influence of various conformal films on LER.

Figure 5 is a diagram showing a plurality of layers etched using the embodiments herein.

Figure 6 is a data graph showing the influence of various conformal films on LER after etching.

7A, 7B, and 7C are schematic diagrams of exemplary processing chambers used to implement the disclosed embodiments.

Figure 8 is a schematic diagram of an exemplary processing device used to implement the disclosed embodiments.

102, 104, 106: Operation

Claims (21)

A substrate processing method, the method comprising: Providing a substrate to a processing chamber, the substrate including a patterned EUV photoresist on a substrate layer to be etched, the patterned EUV photoresist having a first stress level; and Deposit a conformal film on the patterned EUV photoresist, the conformal film has a second stress level, the second stress level is less compressed than the first stress level, so A third stress level of the patterned EUV photoresist resulting from the deposition of the conformal film is less compressed than the first stress level. The substrate processing method of claim 1, wherein the substrate includes a semi-finished semiconductor device and a semiconductor wafer. The substrate processing method of claim 1, wherein the conformal film has a thickness not greater than 2 nm. The substrate processing method of claim 1, wherein the conformal film has a thickness of about 1 nm. The substrate processing method of claim 1, wherein the second stress level of the conformal film is tensile. The substrate processing method of claim 1, wherein the second stress level of the conformal film is compressive. The substrate processing method of claim 1, wherein the patterned EUV photoresist is characterized in that the line roughness is reduced after the deposition. According to the substrate processing method of any one of claims 1-7, wherein the line roughness includes one or more of line edge roughness (LER) and line width roughness (LWR). The substrate processing method of claim 8, wherein the line roughness is a low-frequency line roughness. The substrate processing method of claim 9, wherein the low-frequency line roughness has a spatial frequency less than 0.05 nm ^-1 . The substrate processing method of claim 8, wherein the line roughness is a high-frequency line roughness. The substrate processing method of claim 11, wherein the high-frequency line roughness has a spatial frequency greater than 0.05 nm ^-1 . The substrate processing method of claim 8, wherein the line edge roughness is reduced from about 0.1 to 1 nm ⁴ (PSD). The substrate processing method according to any one of claims 1-7, wherein the conformal film includes a Si-based dielectric. The substrate processing method of claim 14, wherein the dielectric substance is SiO ₂ . The substrate processing method of any one of claims 1-7, wherein the conformal thin film is deposited by ALD. The substrate processing method of claim 16, wherein the ALD includes plasma-enhanced ALD, and one of the cycles includes oxygen having a power between 10W and 2500W and a duty cycle between 25% and 50% Plasma flows. The substrate processing method of claim 17, wherein the EUV photoresist includes a chemically amplified photoresist (CAR), an organic metal, or an organic metal oxide. The substrate processing method of claim 18, wherein the organic metal oxide is an organic tin oxide. The substrate processing method of any one of claims 1-7, further comprising: etching the substrate layer in the processing chamber after the deposition of the conformal thin film. A substrate processing equipment, which includes: One or more processing chambers, each processing chamber includes a substrate support; Access to one or more gas inlets of the processing chambers and related flow control hardware; One or more substrate handling devices; and A controller having at least one processor and one memory, wherein The at least one processor and the memory system are communicatively connected to each other, The at least one processor is at least operatively connected to the one or more substrate handling devices and the flow control hardware, and The memory system stores a plurality of computer-executable instructions, and the plurality of computer-executable instructions are used to control the at least one processor to at least control the one or more substrate handling devices and the flow control hardware to: Providing a substrate to a processing chamber, the substrate including a patterned EUV photoresist on a substrate layer to be etched, the patterned EUV photoresist having a first stress level; and Deposit a conformal film on the patterned EUV photoresist, the conformal film has a second stress level, the second stress level is less compressed than the first stress level, so A third stress level of the patterned EUV photoresist resulting from the deposition of the conformal film is less compressed than the first stress level.

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