TW202044513A - Interconnection structure and method of manufacturing the same - Google Patents

Abstract

An interconnection structure includes a wiring layer, a first insulation layer, a conformal covering layer, a second insulation layer, and a cavity. The wiring layer includes two parallel traces. The first insulation layer includes a recess formed between the two parallel traces. The width of the recess is under 1 μm. The conformal covering layer is formed on the first insulation layer and comformally covers the first insulation layer and the recess along the upper surface of the first insulation layer, the sidewall and the bottom of the recess. The second insulation layer is formed on the conformal covering layer. The cavity in the recess is formed by the second insulation layer and the conformal covering layer, where the top of the cavity is flush with the upper surface of the conformal covering layer. In addition, a method of manufacturing the interconnection structure is herein provided.

Description

Inner wiring structure and manufacturing method thereof

The invention relates to a semiconductor manufacturing process, and more particularly to an interconnection layer structure and a manufacturing method thereof.

At present, some semiconductor manufacturing processes form a cavity in a via or trench to reduce the capacitance value in the circuit, so as to weaken the influence of the RC delay. At present, most of the methods for forming such cavities are to accelerate the deposition rate of the insulating layer to facilitate the formation of cavities in the insulating layer. However, this method of accelerating the deposition rate to form the cavity is not easy to control the size of the cavity, so that the capacitance value that the cavity can reduce is limited, and it may also affect the structure of the subsequent circuit layer, resulting in the occurrence of upper and lower circuit layers. Possibility of open circuit.

The present invention provides an interconnection structure, which includes a cavity between two adjacent parallel wiring lines to help reduce the capacitance value between two adjacent wiring lines.

The present invention provides a method for manufacturing an interconnect structure, which uses a conformal covering layer to form the cavity.

The interconnection structure provided by the present invention includes a first circuit layer, a first insulating layer, a conformal covering layer, a second insulating layer and a cavity. The first circuit layer includes two parallel wirings, and the first insulating layer includes a groove, wherein the two parallel wirings are located in the first insulating layer, and the groove is formed between the two parallel wirings. The width of the groove is below 1 micron. The conformal covering layer is formed on the first insulating layer, and conformally covers the first insulating layer and the groove along the upper surface of the first insulating layer, the groove wall and the bottom of the groove. The second insulating layer is formed on the conformal cover layer. The cavity is located in the groove, and the cavity is formed by the second insulating layer and the conformal cover layer. The top of the cavity is aligned with the upper surface of the conformal cover layer.

In an embodiment of the present invention, the aforementioned interconnect structure further includes a second circuit layer, wherein the second circuit layer is formed on the conformal cover layer.

In an embodiment of the present invention, the thickness of the conformal coating layer is between 100 Angstroms (Angstrom, Å) and 500 Angstroms.

In an embodiment of the present invention, the above-mentioned groove is a groove or a via.

In an embodiment of the present invention, the interconnection structure described above includes a plurality of grooves, wherein the grooves are a plurality of parallel grooves, and the grooves are located between two parallel traces.

In an embodiment of the present invention, the aspect ratio of the groove is between 1 to 5.

The present invention also provides a method for manufacturing the above-mentioned interconnection structure. In this method, a groove is formed on the first insulating layer, and the width of the groove is less than 1 micrometer. Next, a conformal covering layer is formed on the first insulating layer, wherein the conformal covering layer conformally covers the first insulating layer and the groove along the surface of the first insulating layer, the wall and the bottom of the groove. After that, a second insulating layer is formed on the conformal cover layer. During the formation of the second insulating layer, the cavity is formed in the groove, wherein the top end of the cavity is aligned with the upper surface of the conformal cover layer.

In an embodiment of the present invention, the above-mentioned first insulating layer covers the first circuit layer. The first circuit layer includes two parallel wiring lines, and the groove is formed between the two parallel wiring lines.

In an embodiment of the present invention, after forming the second insulating layer, a second circuit layer is formed on the conformal cover layer.

In an embodiment of the present invention, the above-mentioned conformal cover layer is formed by a high aspect ratio process (HARP) or atomic layer deposition (Atomic Layer Deposition, ALD).

In an embodiment of the present invention, the deposition rate for forming the second insulating layer is between 100 angstroms/minute (Å/min) and 1000 angstroms/minute.

The present invention utilizes the poor step coverage generated by the above-mentioned conformal covering layer to form a cavity in the groove of the first insulating layer, wherein the cavity is located between two adjacent parallel wiring lines. Since the cavity has a relatively low dielectric coefficient, it can help reduce the capacitance between two adjacent traces, thereby weakening the adverse effects caused by the RC delay.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific examples are given in conjunction with the accompanying drawings, which are described in detail as follows.

1A to 1E are schematic cross-sectional views of a manufacturing method of an interconnect structure according to an embodiment of the present invention. 1A, in the manufacturing method of the interconnect structure of this embodiment, first, a wafer 10 and a first circuit layer 110 and a first insulating layer 130 formed on the wafer 10 are provided. The first circuit layer 110 includes a plurality of wires 111, of which at least two wires 111 are arranged in parallel. The first insulating layer 130 covers the first circuit layer 110, so these wires 111 will be covered by the first insulating layer 130 and can be formed in the first insulating layer 130, as shown in FIG. 1A. The wafer 10 may be a semiconductor substrate, such as a silicon wafer.

The wafer 10 is a semi-finished product, and it may only complete the front end of line (FEOL) or be in the middle of the back end of line (BEOL). Taking FIG. 1A as an example, the wafer 10 is a semi-finished product that only completes the front-end manufacturing process, and includes an insulating layer 12 and a plurality of plugs 13. These plugs 13 penetrate through the insulating layer 12 and connect to a plurality of components (not shown) below, where these components may include at least one of an active component and a passive component. In other non-illustrated embodiments, the wafer 10 may be a semi-finished product undergoing a subsequent process, and includes a multilayer circuit layer, a multilayer insulating layer, and a plurality of metal columns for electrically connecting these circuit layers. Therefore, the wafer 10, the insulating layer 12, and the plug 13 shown in FIG. 1A are for illustration only, and it is not a limitation that the wafer 10 can only be a semi-finished product that only completes the previous process.

The first insulating layer 130 may be a multilayer film. Taking FIG. 1A as an example, the first insulating layer 130 may include insulating layers 131, 132, 133, and 134, wherein the materials of at least two of the insulating layers 131, 132, 133, and 134 may be different from each other. For example, the insulating layer 131 may be a silicon oxynitride layer, and the insulating layers 132 and 134 may be silicon carbide layers. The insulating layer 133 may be a low dielectric constant layer, such as black diamond. However, in other embodiments, the first insulating layer 130 may also be a single film layer, so the first insulating layer 130 is not limited to the multilayer film shown in FIG. 1A.

Please refer to FIGS. 1A and 1B. Next, a groove 130h is formed on the first insulating layer 130, wherein the number of grooves 130h can be only one or more, and the groove 130h can be formed by photolithography etching or electron beam etching . The width W11 of the groove 130h is less than 1 micrometer, and the groove 130h may extend from the insulating layer 131 to the wafer 10, and the aspect ratio of the groove 130h may be between 1 to 5. In addition, the groove 130h is formed between the two parallel traces 111, and may be a trench or a hole.

Please refer to FIG. 1B and FIG. 1C. Then, a conformal cover layer 150 is formed on the first insulating layer 130, wherein the thickness 150t of the conformal cover layer 150 may be between 100 angstroms and 500 angstroms. The conformal covering layer 150 conformally covers the first insulating layer 130 and the groove 130h along the surface 131a of the first insulating layer 130, the groove wall S13 and the bottom B13 of the groove 130h. In detail, the thickness 150t of the conformal covering layer 150 is substantially constant, so that the conformal covering layer 150 can uniformly cover the groove wall S13 and the bottom B13 of the groove 130h. Therefore, the thickness of the conformal cover layer 150 at the groove wall S13 and the bottom B13 are substantially equal. In addition, the conformal capping layer 150 can be formed by a high aspect ratio process (HARP) or atomic layer deposition (ALD), and the conformal capping layer 150 can be an insulating layer, and its constituent material is, for example, silicon oxide or silicon nitride.

Please refer to FIGS. 1C and 1D. Then, a second insulating layer 140 is formed on the conformal cover layer 150, wherein the second insulating layer 140 can be formed by chemical vapor deposition. During the formation of the second insulating layer 140, the cavity 160 is formed in the groove 130h, wherein the cavity 160 in the groove 130h is formed by the second insulating layer 140 and the conformal cover layer 150. In detail, before forming the second insulating layer 140, the conformal covering layer 150 has covered the groove wall S13 and the bottom B13 of the groove 130h, so the conformal covering layer 150 will fill up part of the space of the groove 130h to make the concave The width W11 of the groove 130h is reduced to the width W12, resulting in poor step coverage. In this way, the cavity 160 is formed in the groove 130h

Since the conformal covering layer 150 conformally covers the groove 130h along the groove wall S13 of the groove 130h, the width W12 can be adjusted by changing the thickness 150t of the conformal covering layer 150. In this way, not only can the groove 130h produce poor step coverage to promote the formation of the cavity 160, but also the width W12 can be adjusted to control the size and position of the cavity 160. For example, the conformal cover layer 150 can make the top 161t of the cavity 160 and the upper surface 150a of the conformal cover layer 150 align with each other, so that the cavity 160 can be confined within the groove 130h as much as possible, thereby effectively reducing the adjacent two traces 111 And avoid affecting the formation of the subsequent second circuit layer 120 (see FIG. 1E).

In addition, the conformal capping layer 150 enables the deposition rate of the second insulating layer 140 to be between 100 angstroms/min and 1000 angstroms/min. Compared with the deposition rate of the insulating layer generally used to form cavities, the deposition rate of the second insulating layer 140 is lower, so that the formed second insulating layer 140 can have a flat upper surface 142 without noticeable Bump. Therefore, the upper surface 142 of the formed second insulating layer 140 does not need to be chemically polished (Chemical-Mechanical Planarization, CMP).

1E, after the second insulating layer 140 is formed, a second circuit layer 120 is formed on the conformal cover layer 150. The second circuit layer 120 may include a plurality of traces 121, and these traces 121 A metal pillar 170 is connected to the wiring 111 below, so that the first circuit layer 110 can be electrically connected to the second circuit layer 120. In addition, the second circuit layer 120 can be formed by the Damascene method. That is, the second insulating layer 140 may be lithographically and etched first to form a plurality of grooves. Afterwards, a metal material is formed in these grooves to form the second circuit layer 120, wherein the metal material can be formed by physical vapor deposition (for example, sputtering or evaporation). After the second circuit layer 120 is formed, one includes the first circuit layer 110, the second circuit layer 120, the first insulating layer 130, the second insulating layer 140, the cavity 160 located in the groove 130h, and the conformal cover layer 150 The interconnect structure 100 is basically completed.

2A to 2D are schematic cross-sectional views of a manufacturing method of an interconnect structure according to another embodiment of the present invention. This embodiment is similar to the previous embodiment, and the main difference between the two is that the groove 230h of the first insulating layer 230 in this embodiment is a plurality of parallel grooves.

Referring to FIG. 2A, in the manufacturing method of the interconnect structure of this embodiment, first, a wafer 10 and a first circuit layer 210 and a first insulating layer 230 formed on the wafer 10 are provided. The first circuit layer 210 includes a plurality of traces 211, of which at least two traces 211 are arranged in parallel, and the wafer 10 may include an insulating layer 12 and a plurality of plugs 13. The first insulating layer 230 covers the first circuit layer 210. The film structures and materials of the first insulating layers 130 and 230 can be the same as each other. Taking FIG. 2A as an example, the first insulating layer 230 may include insulating layers 231, 232, 233, and 234. The material of the insulating layer 231 may be the same as that of the insulating layer 131, and the material of the insulating layer 232 may be the same as that of the insulating layer 132. Material, the material of the insulating layer 233 may be the same as the material of the insulating layer 133, and the material of the insulating layer 234 may be the same as the material of the insulating layer 134.

Next, a plurality of grooves 230h are formed on the first insulating layer 230, wherein the grooves 230h can be formed by photolithography etching or electron beam etching. These grooves 230h are a plurality of parallel grooves, and they are all located between two parallel traces 211, and each groove 230h can extend from the insulating layer 231 to the wafer 10, and the width W2 of each groove 230h is Below 1 micron.

2A and 2B, afterwards, a conformal covering layer 250 is formed on the first insulating layer 230, wherein the thickness of the conformal covering layer 250 can be the same as the thickness of the conformal covering layer 150, and the conformal covering layer 150 The forming methods and materials of both and 250 can also be the same as each other. The conformal covering layer 250 conformally covers the first insulating layer 230 and the grooves 230h along the surface 231a of the first insulating layer 230, the walls (not marked) and the bottom (not marked) of the grooves 230h. In other words, as in the previous embodiment, the conformal covering layer 250 can evenly cover the walls and bottom of the groove 230h, so that the thickness of the conformal covering layer 250 at the walls and bottom of the groove 230h is substantially equal. .

Please refer to FIG. 2C. Next, a second insulating layer 140 is formed on the conformal cover layer 250, wherein the second insulating layer 140 can also be formed by chemical vapor deposition. During the formation of the second insulating layer 140, a plurality of cavities 260 are respectively formed in the grooves 230h and are formed by the second insulating layer 140 and the conformal cover layer 250. The conformal cover layer 250 and the aforementioned conformal cover layer 150 have the same functions. For example, changing the thickness of the conformal cover layer 250 can adjust the width of each groove 230h. Therefore, the conformal cover layer 250 can make the groove 230h have poor step coverage to promote the formation of the cavity 260, and can also adjust the width of the groove 230h to control the size and position of the cavity 260, so that the top of each cavity 260 It can be aligned with the upper surface 250a of the conformal cover layer 250. In addition, the conformal cover layer 250 can also enable the deposition rate of the second insulating layer 140 to be between 100 angstroms/min and 1000 angstroms/min, so that the second insulating layer 140 has a flat upper surface without chemical polishing.

Referring to FIG. 2D, afterwards, a second circuit layer 120 is formed on the conformal covering layer 250, wherein the plurality of wires 121 included in the second circuit layer 120 can use a plurality of metal pillars 170 to connect the wires 211 below. So that the first circuit layer 210 can be electrically connected to the second circuit layer 120. After the second circuit layer 120 is formed, an interconnection line including a first circuit layer 210, a second circuit layer 120, a first insulating layer 230, a second insulating layer 140, a plurality of cavities 260, and a conformal cover layer 250 The structure 200 is basically completed.

In summary, the present invention utilizes the poor step coverage produced by the above-mentioned conformal coating layer to form a cavity between two adjacent parallel traces. Since the cavity has a relatively low dielectric constant, the cavity can help reduce the capacitance between two adjacent traces to weaken the adverse effects caused by the resistance-capacitance delay. Secondly, the thickness of the conformal cover layer can adjust the groove width of the first insulating layer to control the size and position of the cavity. In this way, not only can the capacitance value between two adjacent wires be effectively reduced, but also the formation of the subsequent second circuit layer can be avoided. In addition, the conformal cover layer enables the deposition rate of the second insulating layer to be between 100 angstroms/min and 1000 angstroms/min, so that the formed second insulating layer has a flat upper surface, thereby eliminating the need for chemicals. Flattening process such as polishing.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of invention protection shall be subject to the scope of the attached patent application.

10: Wafer 12, 131, 132, 133, 134, 231, 232, 233, 234: insulating layer 13: plug 100, 200: internal connection structure 110, 210: the first circuit layer 111, 121, 211: routing 120: second circuit layer 130, 230: first insulating layer 130h, 230h: groove 131a, 231a: surface 140: second insulating layer 142, 150a, 250a: upper surface 150, 250: Conformal overlay 150t: thickness 160, 260: cavity 161t: top 170: metal column B13: bottom S13: Slot wall W2, W11, W12: width

1A to 1E are schematic cross-sectional views of a manufacturing method of an interconnect structure according to an embodiment of the present invention. 2A to 2D are schematic cross-sectional views of a manufacturing method of an interconnect structure according to another embodiment of the present invention.

10: Wafer

110: First circuit layer

111: routing

130: first insulating layer

130h: groove

131, 132, 133, 134: insulating layer

140: second insulating layer

142, 150a: upper surface

150: Conformal overlay

160: cavity

161t: top

Claims (11)

An internal wiring structure, including: A first circuit layer, including two parallel wiring; A first insulating layer includes a groove, wherein the two parallel wires are located in the first insulating layer, and the groove is formed between the two parallel wires, and the width of the groove is 1 Below micron A conformal covering layer formed on the first insulating layer and conformally covering the first insulating layer and the groove along the upper surface of the first insulating layer, the groove wall and the bottom of the groove; A second insulating layer formed on the conformal covering layer; and A cavity is located in the groove, wherein the cavity is formed by the second insulating layer and the conformal covering layer, and a top end of the cavity is aligned with the upper surface of the conformal covering layer. The interconnect structure according to claim 1, further comprising a second circuit layer, wherein the second circuit layer is formed on the conformal cover layer. The interconnect structure according to claim 1, wherein the thickness of the conformal covering layer is between 100 angstroms and 500 angstroms. The interconnection structure according to claim 1, wherein the groove is a groove or a hole (via). The interconnect structure according to claim 1 includes a plurality of the grooves, wherein the grooves are a plurality of parallel grooves, and the grooves are located between the two parallel traces. The interconnect structure according to claim 1, wherein the aspect ratio of the groove is between 1 and 5. A manufacturing method of interconnection structure, including Forming a groove on a first insulating layer, wherein the width of the groove is less than 1 micron; A conformal covering layer is formed on the first insulating layer, wherein the conformal covering layer conformally covers the first insulating layer and the recess along the surface of the first insulating layer, the wall and the bottom of the groove. Slot; and A second insulating layer is formed on the conformal covering layer, wherein during the formation of the second insulating layer, a cavity is formed in the groove, wherein a top end of the cavity and the upper surface of the conformal covering layer Chopped. The method for manufacturing an interconnect structure according to claim 7, wherein the first insulating layer covers a first circuit layer, the first circuit layer includes two parallel wirings, and the groove is formed in the Between two parallel traces. The method for manufacturing an interconnect structure according to claim 8, wherein after forming the second insulating layer, a second circuit layer is formed on the conformal cover layer. The method for manufacturing an interconnect structure according to claim 7, wherein the conformal cover layer is formed by a high aspect ratio process or atomic layer deposition. The method for manufacturing the interconnect structure according to claim 7, wherein the deposition rate for forming the second insulating layer is between 100 angstroms/min and 1000 angstroms/min.

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