TW202038353A - 晶片封裝結構及其形成方法 - Google Patents

晶片封裝結構及其形成方法 Download PDF

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TW202038353A
TW202038353A TW108146864A TW108146864A TW202038353A TW 202038353 A TW202038353 A TW 202038353A TW 108146864 A TW108146864 A TW 108146864A TW 108146864 A TW108146864 A TW 108146864A TW 202038353 A TW202038353 A TW 202038353A
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dummy
substrate
bump
cutting
package structure
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TW108146864A
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TWI724703B (zh
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黃松輝
黃冠育
侯上勇
林于順
黃賀昌
許書嘉
李百淵
葉宮辰
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種晶片封裝結構之形成方法。此方法包含將晶片接合至第一基底的第一表面。此方法包含在第一基底的第二表面上形成虛設凸塊。第一表面與第二表面相反，且虛設凸塊與晶片電氣絕緣。此方法包含切穿第一基底與虛設凸塊以形成切割基底與切割虛設凸塊。切割虛設凸塊位於切割基底的角部之上，切割虛設凸塊的第一側壁與切割基底的第二側壁大致上共平面，且切割虛設凸塊的第三側壁與切割基底的第四側壁大致上共平面。

Description

晶片封裝結構及其形成方法
本發明實施例是關於半導體裝置及其形成方法，且特別關於晶片封裝結構及其形成方法。
半導體裝置被使用於各種電子產品中，例如個人電腦、手機、數位相機以及其他電子設備。一般而言，在半導體基底上依序沉積絕緣或介電層、導電層以及半導體層，並且以微影之方式將各材料層圖案化以於其上形成電路組件及元件，藉此製造半導體裝置。
通常在半導體晶圓之上製造許多積體電路。可以在晶圓級（wafer level）加工與封裝晶圓的晶粒，且已發展用於晶圓級封裝的各種技術。
本發明實施例包含一種晶片封裝結構的形成方法。此方法包含將晶片接合至第一基底的第一表面、在第一基底的第二表面之上形成虛設凸塊。第一表面與第二表面相反，且虛設凸塊與晶片電氣絕緣。此方法亦包含切穿第一基底與虛設凸塊以形成切割基底與切割虛設凸塊。切割虛設凸塊位於切割基底的角部之上，切割虛設凸塊的第一側壁與切割基底的第二側壁大致上共平面，且切割虛設凸塊的第三側壁與切割基底的第四側壁大致上共平面。
本發明實施例亦包含一種晶片封裝結構的形成方法。此方法包含將晶片接合至第一基底的第一表面、在第一基底的第二表面之上形成凸塊與虛設凸塊。第一表面與第二表面相反，凸塊電性連接至晶片，且虛設凸塊與晶片電氣絕緣。此方法亦包含切穿第一基底與虛設凸塊以形成切割基底與切割虛設凸塊。切割虛設凸塊位於切割基底的角部之上，切割虛設凸塊的第一側壁與切割基底的第二側壁大致上共平面。此方法亦包含經由凸塊與虛設凸塊將切割基底接合至第二基底。
本發明實施例亦包含一種晶片封裝結構。此晶片封裝結構包含第一基底。第一基底具有第一表面以及與第一表面相反的第二表面。此晶片封裝結構亦包含位於第一表面之上的晶片、位於第二表面之上的虛設凸塊。虛設凸塊與晶片電氣絕緣，虛設凸塊位於第一基底的角部之上，虛設凸塊的第一側壁與第一基底的第二側壁大致上共平面，且虛設凸塊的第三側壁與第一基底的第四側壁大致上共平面。
以下內容提供許多不同實施例或範例，用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用於限定本發明實施例。舉例來說，敘述中若提及第一部件形成於第二部件上或上方，可能包含形成第一部件和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一部件和第二部件之間，使得第一部件和第二部件不直接接觸的實施例。另外，本發明實施例在不同範例中可重複使用參考數字及/或字母。此重複是為了簡化和清楚之目的，並非代表所討論的不同實施例及/或組態之間有特定的關係。
此外，本文可能使用空間相對用語，例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」及類似的用詞，這些空間相對用語係為了便於描述如圖所示之一個（些）元件或部件與另一個（些）元件或部件之間的關係。這些空間相對用語包含使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），則在此所使用的空間相對形容詞也將依轉向後的方位來解釋。應理解的是，可以在所述方法之前、期間或之後進行額外的操作步驟，且在所述方法的一些其他實施例中，可以取代或省略一些所述的操作步驟。
描述本發明一些實施例。可以在這些實施例中所述階段之前、期間及/或之後進行額外的操作步驟。針對不同的實施例，一些所述的階段可被取代或省略。額外的部件可被併入半導體裝置結構。針對不同的實施例，一些後文所述的部件可被取代或省略。雖然以特定順序進行之操作步驟說明一些實施例，但可以其他合理之順序進行這些操作步驟。
第1A～1G圖係根據一些實施例之形成晶片封裝結構之製程之各階段的剖面示意圖。根據一些實施例，如第1A圖所示，提供基底110。在一些實施例中，基底110是中介層晶圓（interposer wafer）。根據一些實施例，基底110包含半導體結構111、導孔112、絕緣層113、重分布結構114以及導電墊115。
根據一些實施例，半導體結構111具有表面111a與表面111b。在一些實施例中，半導體結構111係由元素半導體材料所形成，元素半導體材料包含單晶、多晶或非晶結構中的矽或鍺。
在一些其他的實施例中，半導體結構111係由化合物半導體（例如碳化矽、砷化鎵、磷化鎵、磷化銦或砷化銦）、合金半導體（例如SiGe或GaAsP）或前述之組合所形成。半導體結構111亦可包含多層半導體、絕緣層上覆半導體（semiconductor on insulator，SOI，例如絕緣層上覆矽或絕緣層上覆鍺）或前述之組合。
根據一些實施例，在半導體結構111中形成導孔112。所形成之導孔112可從表面111a延伸進入半導體結構111。根據一些實施例，在半導體結構111之上形成絕緣層113。根據一些實施例，絕緣層113位於導孔112與半導體結構111之間。
根據一些實施例，絕緣層113被配置來使導孔112與半導體結構111電氣絕緣。根據一些實施例，絕緣層113係由含氧化物之材料形成，例如氧化矽。可以使用氧化製程、沉積製程或其他適當之製程形成絕緣層113。
在一些實施例中，基底110是裝置晶圓，其包含各種裝置元件。在一些實施例中，在基底110之中及/或之上形成各種裝置元件。為了簡明起見，於圖式中未繪示裝置元件。舉例而言，各種裝置元件包含主動裝置、被動裝置、其他適當之元件或前述之組合。主動裝置可以包含形成於表面111a的電晶體或二極體（未繪示）。被動裝置包含電阻器、電容器或其他適當之被動裝置。
舉例而言，電晶體可以是金屬氧化物半導體場效電晶體（metal oxide semiconductor field effect transistors，MOSFET）、互補式金屬氧化物半導體（complementary metal oxide semiconductor，CMOS）電晶體、雙極性接面電晶體（bipolar junction transistors，BJT）、高壓電晶體、高頻電晶體、p通道及/或n通道場效電晶體（PFETs/NFETs）等。進行各種製程（例如前段（front-end-of-line，FEOL）半導體製造流程）以形成各種裝置元件。前段半導體製造流程可以包含沉積、蝕刻、佈植、微影、退火、平坦化、一或多個其他適當之製程或前述之組合。
在一些實施例中，在基底110中形成隔離部件（未繪示）。隔離部件被用來定義主動區域並且使形成於主動區域中之各裝置元件電氣絕緣。在一些實施例中，隔離部件包含淺溝槽隔離（shallow trench isolation，STI）部件、局部矽氧化（local oxidation of silicon，LOCOS）部件、其他適當的隔離部件或前述之組合。
根據一些實施例，在半導體結構111之上形成重分布結構114。根據一些實施例，在重分布結構114之上形成導電墊115。根據一些實施例，重分布結構114包含介電層114a、線路層114b以及導孔114c。根據一些實施例，在表面111a之上形成介電層114a。根據一些實施例，在介電層114a之中形成線路層114b。
根據一些實施例，如第1A圖所示，導孔114c於不同的線路層114b之間提供電性連接並於線路層114b與導電墊115之間提供電性連接。為了簡明起見，第1A圖根據一些實施例僅繪示出線路層114b之一者。根據一些實施例，導孔112經由線路層114b與導孔114c電性連接至導電墊115。
根據一些實施例，如第1A圖所示，經由晶片結構120與基底110之間的導電凸塊130將晶片結構120接合至基底110。根據一些實施例，晶片結構120與基底110分隔開。根據一些實施例，晶片結構120與基底110之間具有間隙G1。根據一些實施例，導電凸塊130位於間隙G1中。
根據一些實施例，晶片結構120彼此分隔開。根據一些實施例，各晶片結構120包含晶片（例如系統單晶片（system on chip，SoC））。根據一些實施例，晶片結構120包含各種裝置元件。在一些實施例中，在晶片結構120中形成各種裝置元件。為了簡明起見，於圖式中未繪示裝置元件。舉例而言，各種裝置元件包含主動裝置、被動裝置、其他適當之元件或前述之組合。主動裝置可以包含電晶體或二極體（未繪示）。被動裝置包含電阻器、電容器或其他適當之被動裝置。
舉例而言，電晶體可以是金屬氧化物半導體場效電晶體（MOSFET）、互補式金屬氧化物半導體（CMOS）電晶體、雙極性接面電晶體（BJT）、高壓電晶體、高頻電晶體、p通道及/或n通道場效電晶體（PFETs/NFETs）等。進行各種製程（例如前段（FEOL）半導體製造流程）以形成各種裝置元件。前段半導體製造流程可以包含沉積、蝕刻、佈植、微影、退火、平坦化、一或多個其他適當之製程或前述之組合。
在一些實施例中，在晶片結構120中形成隔離部件（未繪示）。隔離部件被用來定義主動區域並且使形成於主動區域中之各裝置元件電氣絕緣。在一些實施例中，隔離部件包含淺溝槽隔離部件、局部矽氧化部件、其他適當之隔離部件或前述之組合。在一些其他的實施例中，晶片結構120包含晶片封裝結構。
根據一些實施例，如第1A圖所示，底部填充層（underfill layer）140形成於基底110與各晶片結構120之間的間隙G1中。根據一些實施例，底部填充層140圍繞導電凸塊130與晶片結構120。根據一些實施例，底部填充層140包含高分子材料。
根據一些實施例，如第1A圖所示，在基底110之上形成模封層（molding layer）150。根據一些實施例，模封層150圍繞晶片結構120、底部填充層140以及導電凸塊130。根據一些實施例，模封層150包含高分子材料。根據一些實施例，晶片結構120與模封層150的頂表面122與152大致上共平面。
根據一些實施例，如第1B圖所示，移除半導體結構111之下部。根據一些實施例，移除製程包含化學機械研磨（chemical mechanical polishing，CMP）製程。根據一些實施例，在移除製程之後，導孔112與絕緣層113露出。
根據一些實施例，導孔112與絕緣層113穿過半導體結構111。根據一些實施例，當半導體結構111為矽基底時，導孔112亦稱為穿基底導孔（through-substrate vias）或穿矽導孔（through-silicon vias）。
根據一些實施例，如第1C圖所示，將半導體結構111上下倒置（flipped upside down）。根據一些實施例，如第1C圖所示，在表面111b之上形成絕緣層116。根據一些實施例，絕緣層116被配置來使後續將形成於其上之線路層與半導體結構111電氣絕緣。根據一些實施例，絕緣層116係由含氧化物之材料形成，例如氧化矽。可以使用氧化製程、沉積製程或其他適當之製程形成絕緣層116。
在一些實施例中，在半導體結構111的表面111b之上形成重分布結構117。根據一些實施例，重分布結構117包含介電層117a、線路層117b以及導孔117c。根據一些實施例，在介電層117a中形成線路層117b。
根據一些實施例，如第1C圖所示，在重分布結構117之上形成導電墊118a與118b。根據一些實施例，導孔117c於不同的線路層117b之間提供電性連接，且於線路層117b與導電墊118a之間提供電性連接。為了簡明起見，第1C圖根據一些實施例僅繪示出線路層117b之一者。根據一些實施例，導孔112經由線路層117b與導孔117c電性連接至導電墊118a。
根據一些實施例，如第1C圖所示，在導電墊118a與118b之上形成緩衝環119。根據一些實施例，緩衝環119具有開口119a，開口119a暴露出下方之導電墊118a或118b。根據一些實施例，緩衝環119被配置來緩衝基底110與後續將形成於其上之凸塊之間的應力。
根據一些實施例，緩衝環119係由彈性材料所形成，例如高分子材料（例如聚亞醯胺（polyimide））。在一些其他的實施例中（未繪示），以緩衝層取代緩衝環119，緩衝層具有暴露出導電墊118a與118b的開口。
根據一些實施例，如第1C圖所示，晶種層10形成於重分布結構117、緩衝環119以及導電墊118a與118b之上。晶種層10的材料可以包含銅或銅合金。晶種層10的材料可以包含其他金屬，例如銀、金、鋁以及前述之組合。
根據一些實施例，如第1C圖所示，在晶種層10之上形成遮罩層160。根據一些實施例，遮罩層160具有開口162與164，開口162與164暴露出位於導電墊118a與118b之上的晶種層10以及與導電墊118a與118b相鄰的緩衝環119。根據一些實施例，遮罩層160係由高分子材料所形成，例如光阻材料。
根據一些實施例，如第1C圖所示，凸塊172與虛設凸塊174分別形成於開口162與164中且位於導電墊118a與118b之上。在一些實施例中，凸塊172經由基底110電性連接至晶片結構120。在一些實施例中，虛設凸塊174與晶片結構120電氣絕緣。根據一些實施例，虛設凸塊174較凸塊172薄。也就是說，根據一些實施例，虛設凸塊174的厚度T1小於凸塊172的厚度T2。
根據一些實施例，凸塊172與虛設凸塊174係由導電材料所形成，例如銅（Cu）、鋁（Al）、鎢（W）、鈷（Co）或鎳（Ni）。根據一些實施例，可以使用鍍覆製程（例如電鍍製程）形成凸塊172與虛設凸塊174。
根據一些實施例，如第1C圖所示，焊料層182與虛設焊料層184分別形成於凸塊172與虛設凸塊174之上。根據一些實施例，虛設焊料層184較焊料層182薄。也就是說，根據一些實施例，虛設焊料層184的厚度T3小於焊料層182的厚度T4。
根據一些實施例，焊料層182與虛設焊料層184係由Sn或其他適當之熔點低於凸塊172與虛設凸塊174的導電材料所形成。根據一些實施例，可以使用鍍覆製程（例如電鍍製程）形成焊料層182與虛設焊料層184。
根據一些實施例，第1D-1圖係第1D圖之晶片封裝結構的上視示意圖。根據一些實施例，第1D圖係沿著第1D-1圖中的剖面線I-I’繪示出晶片封裝結構的剖面示意圖。根據一些實施例，如第1D與1D-1圖所示，移除遮罩層160。
根據一些實施例，如第1D與1D-1圖所示，移除原本被遮罩層160所覆蓋的晶種層10。根據一些實施例，使用蝕刻製程移除晶種層10。根據一些實施例，虛設凸塊174的寬度W1大於凸塊172的寬度W2。根據一些實施例，虛設焊料層184的寬度W3大於焊料層182的寬度W4。
根據一些實施例，如第1D與1E圖所示，進行切割製程以沿著預定之切割線SC切穿模封層150、基底110、導電墊118b、緩衝環119、晶種層10、虛設凸塊174以及虛設焊料層184，以形成晶片封裝結構100。
根據一些實施例，在切割製程之後，基底110、虛設凸塊174以及虛設焊料層184經切割而形成切割基底110c、切割虛設凸塊174c以及切割虛設焊料層184c。在一些實施例中，切割基底110c、切割虛設凸塊174c以及切割虛設焊料層184c亦可稱為基底、虛設凸塊以及虛設焊料層。
根據一些實施例，第1E-1圖係第1E圖之晶片封裝結構100之一者的上視示意圖。根據一些實施例，第1E圖係沿著第1E-1圖中的剖面線I-I’繪示出晶片封裝結構100的剖面示意圖。根據一些實施例，第1E-2圖係沿著第1E-1圖中的剖面線II-II’繪示出晶片封裝結構100的剖面示意圖。
根據一些實施例，如第1E與1E-1圖所示，各切割虛設凸塊174c與各切割虛設焊料層184c位於切割基底110c之角部C之一者之上。根據一些實施例，如第1E與1E-1圖所示，切割虛設焊料層184c具有兩相鄰之側壁S1與S2。根據一些實施例，切割虛設凸塊174c具有兩相鄰之側壁S3與S4。根據一些實施例，切割基底110c具有兩相鄰之側壁S5與S6。根據一些實施例，模封層150具有兩相鄰之側壁154與156。
根據一些實施例，如第1E與1E-1圖所示，側壁S1、S3、S5與154大致上共平面。本文中的用語「大致上共平面」可以包含共平面幾何形狀之微小偏差。此偏差可能是由製造過程所造成。根據一些實施例，如第1E-1與1E-2圖所示，側壁S2、S4、S6與156大致上共平面。
根據一些實施例，如第1E與1E-1圖所示，切割虛設凸塊174c的寬度W5大於凸塊172的寬度W2。根據一些實施例，切割虛設焊料層184c的寬度W6大於焊料層182的寬度W4。
在一些其他的實施例中，切割虛設凸塊174c的寬度W5等於或小於凸塊172的寬度W2。根據一些實施例，切割虛設焊料層184c的寬度W6等於或小於焊料層182的寬度W4。
根據一些實施例，第1F-1圖為第1F圖之晶片封裝結構的上視示意圖。根據一些實施例，如第1E、1F與1F-1圖所示，於焊料層182與切割虛設焊料層184c之上進行回焊（reflow）製程，以將焊料層182與切割虛設焊料層184c轉換成焊球182b與虛設焊球184b。根據一些實施例，虛設焊球184b較焊球182b薄。也就是說，根據一些實施例，虛設焊球184b的厚度T5小於焊球182b的厚度T6。
根據一些實施例，如第1F-1圖所示，虛設焊球184b具有L形。根據一些實施例，如第1F-1圖所示，虛設焊球184b具有彎曲的側壁S7。根據一些實施例，第1F-2圖係沿著第1F-1圖中的剖面線II-II’繪示出晶片封裝結構100的剖面示意圖。
根據一些實施例，如第1F與1F-2圖所示，虛設焊球184b大致上為半圓形。根據一些實施例，虛設焊球184b具有彎曲的頂表面184t。根據一些實施例，具有彎曲頂表面184t的虛設焊球184b圓化晶片封裝結構100的角部。因此，根據一些實施例，虛設焊球184b避免或減少後續將形成於晶片封裝結構100之周圍的底部填充層中之裂縫的形成，相反地，具有尖銳角部之晶片封裝結構將導致裂縫的形成。因此，虛設焊球184b之形成增進底部填充層的良率。
根據一些實施例，如第1F與1F-1圖所示，虛設焊球184b的寬度W7大於焊球182b的寬度W8。在一些其他的實施例中，虛設焊球184b的寬度W7等於或小於焊球182b的寬度W8。
根據一些實施例，如第1G圖所示，將晶片封裝結構100上下倒置。根據一些實施例，如第1G圖所示，經由焊球182b將晶片封裝結構100接合至基底190。根據一些實施例，虛設焊球184b與基底190分隔開。根據一些實施例，虛設焊球184b與基底190電氣絕緣。
根據一些實施例，虛設焊球184b與基底190之間具有距離D1。根據一些實施例，切割基底110c與基底190之間具有距離D2。在一些實施例中，距離D1對距離D2的比值為約0.3至約0.7。根據一些實施例，若距離D1對距離D2的比值小於0.3，虛設焊球184b可能會阻礙後續切割基底110c與基底190之間之底部填充層之形成。
根據一些實施例，基底190包含介電層192、線路層194、導孔196以及導電墊198。根據一些實施例，在介電層192中形成線路層194與導電墊198。根據一些實施例，導孔196於不同之線路層194之間提供電性連接且於線路層194與導電墊198之間提供電性連接。為了簡明起見，第1G圖根據一些實施例僅繪示出線路層194之一者。
根據一些實施例，如第1G圖所示，在切割基底110c與基底190之間形成底部填充層210。在一些實施例中，底部填充層210的一部分形成於基底190之上且圍繞晶片封裝結構100。根據一些實施例，底部填充層210係由絕緣材料所形成，例如高分子材料。
根據一些實施例，第2圖係晶片封裝結構200的上視示意圖。根據一些實施例，如第2圖所示，晶片封裝結構200類似於第1F-1圖的晶片封裝結構100，除了晶片封裝結構200的虛設焊球184b具有圓端E1與E2。
根據一些實施例，第3A～3B圖係形成晶片封裝結構之製程之各階段的剖面示意圖。根據一些實施例，第3A-1圖係第3A圖之晶片封裝結構的底視示意圖。根據一些實施例，第3A圖係沿著第3A-1圖的剖面線I-I’繪示出晶片封裝結構的剖面示意圖。根據一些實施例，如第3A與3A-1圖所示，提供晶片封裝結構300。
根據一些實施例，晶片封裝結構300類似於第1F圖的晶片封裝結構100，除了切割虛設凸塊174c的厚度T1大致上等於凸塊172的厚度T2，且虛設焊球184b的厚度T5大致上等於焊球182b的厚度T6。
根據一些實施例，本文中的用語「大致上等於」指的是「10%以內」。舉例而言，根據一些實施例，用語「大致上等於」指的是厚度T1與T2之間的差異在切割虛設凸塊174c與凸塊172之平均厚度之間是10%以內。此差異可能是製程所造成。根據一些實施例，如第3A-1圖所示，虛設焊球184b大致上為四分之一圓形。
根據一些實施例，如第3A-1圖所示，虛設焊球184b的寬度W9大於焊球182b的寬度W8。在一些其他的實施例中，虛設焊球184b的寬度W9等於或小於焊球182b的寬度W8。
根據一些實施例，如第3B圖所示，經由焊球182b與虛設焊球184b將晶片封裝結構300接合至基底190。根據一些實施例，因為切割基底110c基底190之間的應力傾向於集中在切割基底110c之角部C之上的虛設焊球184b上，虛設焊球184b承受切割基底110c與基底190之間大多數的應力。因此，根據一些實施例，虛設焊球184b降低了焊球182b上的應力。焊球182b的良率變好。
根據一些實施例，基底190包含介電層192、線路層194、導孔196以及導電墊198a與198b。根據一些實施例，在介電層192中形成線路層194以及導電墊198a與198b。根據一些實施例，導孔196於不同線路層194之間提供電性連接，且於線路層194與導電墊198a之間提供電性連接。為了簡明起見，第3B圖根據一些實施例僅繪示出線路層194之一者。
根據一些實施例，如第3B圖所示，在切割基底110c與基底190之間形成底部填充層210。在一些實施例中，底部填充層210之一部分形成於基底190之上且圍繞晶片封裝結構300。根據一些實施例，底部填充層210係由絕緣材料形成，例如高分子材料。
用於形成晶片封裝結構200與300的製程與材料可類似於或相同於前述用於形成晶片封裝結構100的製程與材料。
根據一些實施例，提供晶片封裝結構及其形成方法。此（用於形成晶片封裝結構的）方法在基底之角部之上形成虛設焊球以圓化晶片封裝結構之角部，以避免或減少後續將形成於晶片封裝結構周圍之底部填充層中裂縫的形成，相反地，具有尖銳角部之晶片封裝結構將導致裂縫的形成。因此，虛設焊球之形成增進底部填充層之良率。
根據一些實施例，提供晶片封裝結構的形成方法。此方法包含將晶片接合至第一基底的第一表面。此方法包含在第一基底的第二表面之上形成虛設凸塊。第一表面與第二表面相反，且虛設凸塊與晶片電氣絕緣。此方法包含切穿第一基底與虛設凸塊以形成切割基底與切割虛設凸塊。切割虛設凸塊位於切割基底之角部之上，切割虛設凸塊的第一側壁與切割基底的第二側壁大致上共平面，且切割虛設凸塊的第三側壁與切割基底的第四側壁大致上共平面。
在一些實施例中，第一側壁鄰近第三側壁，且第二側壁鄰近第四側壁。
在一些實施例中，此方法更包含：在切穿第一基底與虛設凸塊之前，在虛設凸塊之上形成虛設焊料層，其中切穿第一基底與虛設凸塊的步驟更包含切穿虛設焊料層以形成切割虛設焊料層。
在一些實施例中，此方法更包含：回焊切割虛設焊料層以形成虛設焊球。
在一些實施例中，在虛設焊球的上視圖中，虛設焊球具有L形或實質上四分之一圓形。
在一些實施例中，此方法更包含：在第一基底的第二表面之上形成虛設凸塊期間，在第一基底的第二表面之上形成凸塊，其中凸塊電性連接至晶片。
在一些實施例中，虛設凸塊較凸塊薄。
在一些實施例中，此方法更包含：在切穿第一基底與虛設凸塊之前，在凸塊之上與虛設凸塊之上分別形成焊料層與虛設焊料層，其中虛設焊料層較焊料層薄，且切穿第一基底與虛設凸塊的步驟更包含切穿虛設焊料層以形成切割虛設焊料層。
在一些實施例中，此方法更包含：在切穿第一基底、虛設凸塊以及虛設焊料層之後，回焊焊料層與切割虛設焊料層以分別形成焊球與虛設焊球，其中虛設焊球較焊球薄。
在一些實施例中，此方法更包含：經由焊球將切割基底接合至第二基底。
在一些實施例中，虛設焊球與第二基底分隔開，且虛設焊球與第二基底電氣絕緣。
根據一些實施例，提供晶片封裝結構的形成方法。此方法包含將晶片接合至第一基底的第一表面。此方法包含在第一基底的第二表面之上形成凸塊與虛設凸塊。第一表面與第二表面相反，凸塊電性連接至晶片，且虛設凸塊與晶片電氣絕緣。此方法包含切穿第一基底與虛設凸塊以形成切割基底與切割虛設凸塊。切割虛設凸塊位於切割基底之角部之上，且切割虛設凸塊的第一側壁與切割基底的第二側壁大致上共平面。此方法包含經由凸塊與虛設凸塊將切割基底接合至第二基底。
在一些實施例中，切割虛設凸塊的第三側壁與切割基底的第四側壁大致上共平面。
在一些實施例中，此方法更包含：在切穿第一基底與虛設凸塊之前，在凸塊之上與虛設凸塊之上分別形成焊料層與虛設焊料層，其中切穿第一基底與虛設凸塊的步驟更包含切穿虛設焊料層以形成切割虛設焊料層。
在一些實施例中，此方法更包含：在切穿第一基底、虛設凸塊以及虛設焊料層之後，回焊焊料層與切割虛設焊料層以分別形成焊球與虛設焊球。
根據一些實施例，提供晶片封裝結構。此晶片封裝結構包含第一基底，第一基底具有第一表面以及與第一表面相反的第二表面。此晶片封裝結構包含位於第一表面之上的晶片。此晶片封裝結構包含位於第二表面之上的虛設凸塊。虛設凸塊與晶片電氣絕緣，虛設凸塊位於第一基底之角部之上，虛設凸塊的第一側壁與第一基底的第二側壁大致上共平面，且虛設凸塊的第三側壁與第一基底的第四側壁大致上共平面。
在一些實施例中，此晶片封裝結構更包含：位於第二表面之上的凸塊，其中凸塊電性連接至晶片，且虛設凸塊較凸塊薄。
在一些實施例中，此晶片封裝結構更包含：位於凸塊之上的焊球；以及位於虛設凸塊之上的虛設焊球，其中虛設焊球較焊球薄。
在一些實施例中，此晶片封裝結構更包含：第二基底，其中焊球連接至第二基底，且虛設焊球與第二基底分隔開。
在一些實施例中，此晶片封裝結構更包含：位於虛設凸塊之上的虛設焊球；以及第二基底，其中虛設焊球連接至第二基底。
以上概述數個實施例之部件，使得發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的面向。發明所屬技術領域中具有通常知識者應該理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優點。發明所屬技術領域中具有通常知識者也應該理解到，此類等效的結構並未悖離本發明實施例的精神與範圍，且他們能在不違背本發明實施例的精神和範圍下，做各式各樣的改變、取代和置換。
10:晶種層 100,200,300:晶片封裝結構 110:基底 110c:切割基底 111:半導體結構 111a,111b:表面 112:導孔 113:絕緣層 114:重分布結構 114a:介電層 114b:線路層 114c:導孔 115:導電墊 116:絕緣層 117:重分布結構 117a:介電層 117b:線路層 117c:導孔 118a,118b:導電墊 119:緩衝環 119a:開口 120:晶片結構 122:頂表面 130:導電凸塊 140:底部填充層 150:模封層 152:頂表面 154,156:側壁 162,164:開口 172:凸塊 174:虛設凸塊 174c:切割虛設凸塊 182:焊料層 182b:焊球 184:虛設焊料層 184b:虛設焊球 184c:切割虛設焊料層 184t:頂表面 190:基底 192:介電層 194:線路層 196:導孔 198,198a,198b:導電墊 210:底部填充層 C:角部 D1,D2:距離 E1,E2:圓端 G1:間隙 I-I’,II-II’:剖面線 S1,S2,S3,S4,S5,S6,S7:側壁 SC:切割線 T1,T2,T3,T4,T5,T6:厚度 W1,W2,W3,W4,W5,W6,W7,W8,W9:寬度
藉由以下的詳細描述配合所附圖式，可以更加理解本發明實施例的內容。需強調的是，根據產業上的標準慣例，許多部件（feature）並未按照比例繪製且僅用於說明的目的。事實上，為了能清楚地討論，各種部件的尺寸可能被任意地增加或減少。 根據一些實施例，第1A～1D、1E、1F、1G圖係形成晶片封裝結構之製程之各階段的剖面示意圖。 根據一些實施例，第1D-1圖係第1D圖之晶片封裝結構的上視示意圖。 根據一些實施例，第1E-1圖係第1E圖之晶片封裝結構的上視示意圖。 根據一些實施例，第1E-2圖係沿著第1E-1圖中的剖面線II-II’繪示出晶片封裝結構的剖面示意圖。 根據一些實施例，第1F-1圖係第1F圖之晶片封裝結構的上視示意圖。 根據一些實施例，第1F-2圖係沿著第1F-1圖中的剖面線II-II’繪示出晶片封裝結構的剖面示意圖。 根據一些實施例，第2圖係第1F圖之晶片封裝結構的上視示意圖。 根據一些實施例，第3A、3B圖係形成晶片封裝結構之製程之各階段的剖面示意圖。 根據一些實施例，第3A-1圖係第3A圖之晶片封裝結構的底視示意圖。
100:晶片封裝結構
110c:切割基底
119:緩衝環
120:晶片結構
154,156:側壁
174c:切割虛設凸塊
182:焊料層
184c:切割虛設焊料層
C:角部
I-I’,II-II’:剖面線
S1,S2,S3,S4,S5,S6:側壁
W4,W6:寬度

Claims (20)

  1. 一種晶片封裝結構的形成方法，包括： 將一晶片接合至一第一基底的一第一表面； 在該第一基底的一第二表面之上形成一虛設凸塊，其中該第一表面與該第二表面相反，且該虛設凸塊與該晶片電氣絕緣；以及 切穿該第一基底與該虛設凸塊以形成一切割基底與一切割虛設凸塊，其中該切割虛設凸塊位於該切割基底的一角部之上，該切割虛設凸塊的一第一側壁與該切割基底的一第二側壁大致上共平面，且該切割虛設凸塊的一第三側壁與該切割基底的一第四側壁大致上共平面。
  2. 如請求項1之晶片封裝結構的形成方法，其中該第一側壁鄰近該第三側壁，且該第二側壁鄰近該第四側壁。
  3. 如請求項1之晶片封裝結構的形成方法，更包括： 在切穿該第一基底與該虛設凸塊之前，在該虛設凸塊之上形成一虛設焊料層，其中切穿該第一基底與該虛設凸塊的步驟更包括切穿該虛設焊料層以形成一切割虛設焊料層。
  4. 如請求項3之形成晶片封裝結構的方法，更包括： 回焊該切割虛設焊料層以形成一虛設焊球。
  5. 如請求項4之形成晶片封裝結構的方法，其中在該虛設焊球的一上視圖中，該虛設焊球具有一L形或一實質上之四分之一圓形。
  6. 如請求項1之晶片封裝結構的形成方法，更包括： 在該第一基底的該第二表面之上形成該虛設凸塊時，在該第一基底的該第二表面之上形成一凸塊，其中該凸塊電性連接至該晶片。
  7. 如請求項6之晶片封裝結構的形成方法，其中該虛設凸塊較該凸塊薄。
  8. 如請求項6之晶片封裝結構的形成方法，更包括： 在切穿該第一基底與該虛設凸塊之前，在該凸塊之上與該虛設凸塊之上分別形成一焊料層與一虛設焊料層，其中該虛設焊料層較該焊料層薄，且切穿該第一基底與該虛設凸塊的步驟更包括切穿該虛設焊料層以形成一切割虛設焊料層。
  9. 如請求項8之晶片封裝結構的形成方法，更包括： 在切穿該第一基底、該虛設凸塊以及該虛設焊料層之後，回焊該焊料層與該切割虛設焊料層以分別形成一焊球與一虛設焊球，其中該虛設焊球較該焊球薄。
  10. 如請求項9之晶片封裝結構的形成方法，更包括： 經由該焊球將該切割基底接合至一第二基底。
  11. 如請求項10之晶片封裝結構的形成方法，其中該虛設焊球與該第二基底分隔開，且該虛設焊球與該第二基底電氣絕緣。
  12. 一種晶片封裝結構的形成方法，包括： 將一晶片接合至一第一基底的一第一表面； 在該第一基底的一第二表面之上形成一凸塊與一虛設凸塊，其中該第一表面相對於該第二表面， 該凸塊電性連接至該晶片，且該虛設凸塊與該晶片電氣絕緣； 切穿該第一基底與該虛設凸塊以形成一切割基底與一切割虛設凸塊，其中該切割虛設凸塊位於該切割基底的一角部之上，該切割虛設凸塊的一第一側壁與該切割基底的一第二側壁大致上共平面；以及 經由該凸塊與該虛設凸塊將該切割基底接合至一第二基底。
  13. 如請求項12之晶片封裝結構的形成方法，其中該切割虛設凸塊的一第三側壁與該切割基底的一第四側壁大致上共平面。
  14. 如請求項12之晶片封裝結構的形成方法，更包括： 在切穿該第一基底與該虛設凸塊之前，於該凸塊之上與該虛設凸塊之上分別形成一焊料層與一虛設焊料層，其中切穿該第一基底與該虛設凸塊的步驟更包括切穿該虛設焊料層以形成一切割虛設焊料層。
  15. 如請求項14之晶片封裝結構的形成方法，更包括： 在切穿該第一基底、該虛設凸塊以及該虛設焊料層之後，回焊該焊料層與該切割虛設焊料層以分別形成一焊球與一虛設焊球。
  16. 一種晶片封裝結構，包括： 一第一基底，具有一第一表面以及相對於該第一表面的一第二表面； 一晶片，位於該第一表面之上；以及 一虛設凸塊，位於該第二表面之上，其中該虛設凸塊與該晶片電氣絕緣，該虛設凸塊位於該第一基底的一角部之上，該虛設凸塊的一第一側壁與該第一基底的一第二側壁大致上共平面，且該虛設凸塊的一第三側壁與該第一基底的一第四側壁大致上共平面。
  17. 如請求項16之晶片封裝結構，更包括： 一凸塊，位於該第二表面之上，其中該凸塊電性連接至該晶片，且該虛設凸塊較該凸塊薄。
  18. 如請求項17之晶片封裝結構，更包括： 一焊球，位於該凸塊之上；以及 一虛設焊球，位於該虛設凸塊之上，其中該虛設焊球較該焊球薄。
  19. 如請求項18之晶片封裝結構，更包括： 一第二基底，其中該焊球連接至該第二基底，且該虛設焊球與該第二基底分隔開。
  20. 如請求項16之晶片封裝結構，更包括： 一虛設焊球，位於該虛設凸塊之上；以及 一第二基底，其中該虛設焊球連接至該第二基底。
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