TW202036578A - Memory device and error detection method thereof - Google Patents

Abstract

A memory device includes a memory array having at least one memory bank, where the at least one memory bank includes a target memory array and a clone memory array. The clone memory array corresponds to the target memory array and is configured to store the same data as in the target memory array. When a command that is applied to the target memory array to perform an operation, the command is also applied to the clone memory array. An error detection method adapted to a memory device having at least one memory bank that comprises a target memory array and a clone memory array is also introduced.

Description

Memory device and its error detection method

The invention relates to a memory device and an error detection method for detecting errors or failures on the memory device.

Memory devices, especially Random Access Memory (RAM) and Dynamic Random Access Memory (DRAM) devices are used in a wide range of applications, such as: motor vehicles, computers, digital cameras , Smart phones, etc. For a high-reliability system, it needs a highly reliable memory device, which can detect possible errors or failures in the memory device. Generally speaking, Error Correction Code (ECC) is used to detect error bits and correct the detected error bits. However, ECC cannot properly handle multiple error bits that may be caused by multiple failures, such as: Word Line Failure, Cell-to-cell Failure, Lumped Particle Failure, Bitline-to-bitline Short, etc. In this case, ECC cannot correct the error or failure, and the system cannot recognize the existence of the failure. As a result, the reliability of the memory device is reduced.

With the popularity of memory devices, it is necessary to obtain a reliable error detection solution to improve the performance and reliability of the memory devices.

The invention introduces a memory device and an error detection method for detecting errors or failures on the memory device.

The present invention provides a memory device including a memory array having at least one memory group, wherein the at least one memory group includes a target memory array and a clone memory array corresponding to the target memory array. The target memory array is used to store data, and the clone memory array is used to store the same data as the data of the target memory array. The commands applied to the target memory array to perform operations are applied to the clone memory array.

The present invention provides an error detection method suitable for a memory device having at least one memory bank, wherein the memory bank includes a target memory array and a clone memory array. Read error detection includes the steps of reading the target memory unit of the target memory array to obtain the target memory data: reading the clone memory unit of the clone memory array to obtain the clone memory data, wherein the clone of the memory array is cloned The memory unit corresponds to the target memory unit of the target memory array; compares the target memory data with the clone memory data to output a comparison signal; and determines whether the target memory data includes an error based on the comparison signal.

Based on the above, the clone memory array is used to store the same data as the data in the target memory array, so the error detection method can compare the data stored in the target memory array with the data stored in the clone memory array to detect Error in the memory device. In this way, the reliability of the data stored in the memory device is improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

It should be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. Also, it should be understood that the wording and terminology used here are for the purpose of description and should not be considered restrictive. The use of "including", "including" or "having" and their variations in this article is intended to cover the items listed thereafter, their equivalents, and their additional items. Unless otherwise limited, the terms "connection", "coupling", "configuration" and their variations are widely used herein, and include direct and indirect connection, coupling, and configuration.

Please refer to FIG. 1, the memory device 100 includes a memory array 110, a comparator 120, a peripheral memory circuit 130, a memory controller 140 and a module register 150. The memory array 110 includes memory groups 112, 114, 116, and 118 (also referred to as memory group i, memory group j, memory group k, and memory group 1 respectively). At least one of the memory groups 112, 114, 116, and 118 includes a clone memory array 1121, which corresponds to a target memory array (not shown) located in the memory array 110. The clone memory array 1121 stores the same data as the data stored in the target memory array. As shown in FIG. 1, the clone memory array 1121 is located in the memory group 112 (memory group i) of the memory array 110, but the present invention is not limited to this. The clone memory array 1121 can be located in any memory group 112, 114, 116, and 118 of the memory array 110.

In the embodiment of the present invention, the memory device 100 is a dynamic random access memory (DRAM) device, and the memory device 100 is compatible with the Joint Electron Device Engineering Council (JEDEC) standard.

The comparator 120 is coupled to the memory array 110 and is used to compare data read from the memory array 110. For example, the comparator 120 can compare the target memory data D1 and the cloned memory data D2, wherein the comparator 120 reads the target memory data D1 from the target memory array, and the comparator 120 reads the cloned memory data from the cloned memory array. Memory data D2. As shown in FIG. 1, the comparator 120 is a separate circuit, but the comparator 120 can also be integrated into other circuits of the memory device 110. The comparator 120 outputs the data mask signal DM1 and the data output signal DQ1 to the peripheral memory circuit 130.

The data mask signal DM1 can indicate whether the target memory data D1 is the same as the clone memory data D2, and the data output signal DQ1 can be the target memory data D1 or can be related to the target memory data D1. The target memory data D1 and the clone memory data D2 are N-bit data, where N is an integer of 8, 16, 32, and 64, for example. The data D1 and D2 may be data executed using an error correction code (ECC) operation, or data directly read from the memory array 110.

The peripheral memory circuit 130 is coupled to the comparator 120 to receive the data mask signal DM1 and the data output signal DQ1 from the comparator 120. The peripheral memory circuit 130 can output the data mask signal DM and the data output signal DQ to the memory controller 140. The data mask signal DM and the data output signal DQ are the same as or related to the data mask signal DM1 and the data output signal DQ1, respectively.

For the memory device 100, the peripheral memory circuit 130 includes other circuits required for cooperative operation. For example, the peripheral memory circuit 130 may include Row and Column Decoders (not shown) of the memory device 100, and Bit-line Pre-charge Circuits (not shown) ), Sense Amplifiers (not shown), timing controller (not shown), and Read-write Circuit (not shown). These circuits are necessary for performing operations on the memory device 100, and those skilled in the art can clearly understand the functions of these circuits, so detailed descriptions of these circuits are omitted below.

In the embodiment of the present invention, the data mask signal DM is sent to the data mask pin (not shown) of the memory device 100, and the data output signal DQ is output to the data output pin ( Not shown). In another embodiment, the data mask signal DM and the data output signal DQ are transmitted to additional pins instead of being transmitted to the data mask pins and data output pins of the memory device 100.

The memory controller 140 is coupled to the peripheral memory circuit 130 to receive the data mask signal DM and the data output signal DQ from the peripheral memory circuit 130. Based on the received data mask signal DM and data output signal DQ, the controller 140 can determine whether the target memory data D1 stored in the memory array 110 contains errors. The memory controller 140 is also used to control the operation of the memory device 100 through commands.

The module register 150 is used to set the position and size of the target memory array and the clone memory array in the memory device 100. The target memory array and the clone memory array are located in the same memory group or different memory groups of the memory device 100. In addition, the size of the target memory array and the clone memory array are modified according to design needs. The module register 150 can also select memory bank addresses and column addresses to access the cells in the target memory array and clone memory array. The module register 150 can also disable the function of cloning the memory array, or disable the function of cloning the memory array and the target memory array. In this way, the memory array 110 can be used as a conventional memory array. In addition to the module register 150, selective circuits such as Option Fuse or Internal Wiring can be used to select the target memory array and clone the memory array.

Please refer to FIGS. 2A to 2C, which illustrate exemplary embodiments of a memory array including a target memory array and clone memory arrays located in different memory groups. 2A, the memory array 210a includes target memory arrays T1, T2 and clone memory arrays C1, C2, wherein the target memory arrays T1, T2 and clone memory arrays are located in different memory groups.

Specifically, the memory array 210a includes a first target memory array T1 located in the memory group 212a, a first clone memory array C1 located in the memory group 214a, and a second target memory located in the memory group 216a. The volume array T2 and the second clone memory array C2 located in the memory group 218a. The first clone memory array C1 has the same size as the first target memory array T1, and stores the same data as the first target memory array T1. The second clone memory array C2 has the same size as the second target memory array T2, and stores the same data as the second target memory array T2. The module register 150 shown in FIG. 1 controls the positions, sizes, and access addresses of the clone memory arrays C1, C2 and the target memory arrays T1, T2. In FIG. 2A, the clone memory arrays C1 and C2 occupy 50% of the memory groups 212a to 218a.

2B, the memory array 210b includes a target memory array T1 in the memory group 212b and a clone memory array C1 in the memory group 214b. The clone memory array C1 has the same size as the target memory array T1, and stores the same data as the target memory array T1. The difference between the memory array 210a shown in FIG. 2A and the memory array 210b shown in FIG. 2B is that the memory array 210b includes memory groups 216b and 218b, and the memory groups 216b and 218b are general memory groups . In other words, the general memory groups 216b and 218b do not include any target memory arrays or clone memory arrays. In FIG. 2B, the clone memory array C1 occupies 25% of the memory groups 212b to 218b.

2C, the memory array 210c includes a target memory array T1 in the memory group 212c and a clone memory array C1 in the memory group 214c. The difference between the memory array 210c shown in FIG. 2C and the memory array 210b in FIG. 2B is that the size of the clone memory array and the target memory array in FIG. 2B is the same as the size of the memory group, and The size of the clone memory array and the target memory array in 2C is smaller than the size of the memory bank. The memory group 212c includes the target memory array T1 and the general array, and the memory group 214c includes the clone memory array C1 and the general array. The clone memory array C1 occupies 12.55% of the memory groups 212c to 218c.

Figures 2A to 2C illustrate embodiments in which the clone memory array has 50%, 25%, and 12.5%. However, the present invention is not limited to this, and the ratio of the clone memory array to the total memory array can be adjusted according to design requirements.

Please refer to FIGS. 3A to 3D, which illustrate exemplary embodiments of a memory array including a target memory array and a clone memory array in the same memory group. 3A, the memory array 310a includes memory groups 312a, 314a, 316a, and 318a. Each of the memory groups 312a, 314a, 316a, and 318a includes a target memory array and a clone corresponding to the target memory array Memory array. Specifically, the memory group 312a includes a target memory array T1 and a clone memory array C1 corresponding to the target memory array T1. The memory group 314a includes a target memory array T2 and a clone memory array C2 corresponding to the target memory array T2. The memory set 316a includes a target memory array T3 and a clone memory array C3 corresponding to the target memory array T3, and the memory set 318a includes a target memory array T4 and a clone memory array C4 corresponding to the target memory array T4 . In the embodiment shown in FIG. 3A, the clone memory arrays C1 to C4 occupy 50% of the memory groups 312a to 318a.

Referring to FIG. 3B, the memory array 310b includes memory groups 312b, 314b, 316b, and 318b, wherein each of the memory groups 312b and 316b includes a target memory array and a clone memory array corresponding to the target memory array. The memory banks 314b and 318b only include general memory arrays. The memory group 312b includes a target memory array T1 and a clone memory array C1 corresponding to the target memory array T1. The memory group 316a includes a target memory array T3 and a clone memory array C3 corresponding to the target memory array T3. In the embodiment shown in FIG. 3B, the clone memory arrays C1 and C3 occupy 25% of the memory groups 312b to 318b.

Referring to FIG. 3C, the memory array 310c includes memory groups 312c, 314c, 316c, and 318c. The memory group 312c includes a target memory array T1 and a clone memory array C1 corresponding to the target memory array T1. The memory groups 314c, 316c, and 318c only include general memory arrays. In the embodiment shown in FIG. 3C, the clone memory array C1 occupies 12.5% of the memory groups 312c to 318c.

Referring to FIG. 3D, the memory array 310d includes memory groups 312d, 314d, 316d, and 318d. The memory group 312d includes a target memory array T1, a clone memory array C1, and a general memory array. The memory groups 314d, 316d, and 318d only include general memory arrays. In the embodiment shown in FIG. 3D, the clone memory array C1 occupies 8.33% of the memory groups 312d to 318d.

4A, the memory device 400a includes a memory group 412a and a memory group 414a. The memory group 412a includes the target memory array T, and the memory group 414a includes the clone memory array C. The clone memory array C has the same size as the target memory T, and stores the same data as the target memory T.

The memory device 400a further includes a comparator 420a and a peripheral memory circuit 430a. The comparator 420a is used to compare the data D1 and D2 to output the data mask signal DM1 and the data output signal DQ1. The data D1 and D2 can be data executed using EEC operations, or data directly read from the target memory array 412a and the clone memory array 414a. The peripheral memory circuit 430a is coupled to the comparator 420, and is used to output the data mask signal DM and the data output signal DQ according to the received data mask signal DM1 and the data output signal DQ1.

In the operation of the memory device 400a, if a command is applied to the target memory array T in the memory group 412a, the same command is also applied to the clone memory array of the memory group 414a.

For example, when the memory device 400a receives a trigger command and a write command for writing data into the target memory array T, both memory groups 412a and 414a are enabled. The selected target unit of the target memory array T and the corresponding clone unit of the clone memory array C are triggered at the same time, so that data is written into the target unit of the target memory array T and the corresponding clone of the clone memory array C at the same time Clone the unit.

If the trigger command and the write command are applied to write data on a general memory array different from the target memory array T, only the memory group containing the selected general memory array is activated. Therefore, the memory data is only written into the general memory array.

In another embodiment, when the memory device 400 receives a read command to read data stored in the target cell of the target memory array T, the memory groups 412a and 414a are both activated, and the target memory array The selected target unit in T and the corresponding clone unit in the clone memory array C are triggered at the same time. The read command is applied to the target unit and the corresponding clone unit to obtain the data D1 and D2. Using ECC operation, data D1 and D2 can be executed.

The data D1 and D2 (with or without ECC operation) are output to the comparator 420a, and the comparator 420a compares the data D1 and D2 to determine whether the data D1 is the same as the data D2. If the data D1 and D2 are the same, the comparator 420a sets the data mask signal DM1 to the preset voltage (for example, the ground voltage) to indicate that there is no error in the data stored in the target memory array T and the clone memory array C . If the data D1 and D2 are different, the comparator 420a outputs a pulse signal on the data mask signal to indicate that there is an error in the data stored in the target memory array T and the clone memory array C. Therefore, the data mask signal can be used to determine whether there is an error in reading the data.

Table 1 and Table 2 show the comparison between the target data read from the target memory array of the memory group <i> and the clone data read from the corresponding clone memory array of the memory group <j> Examples of error detection. Each data bit of the target data will be compared with the corresponding bit of the cloned data. For example, compare Data0 of the target data with Data0 of the corresponding cloned data, compare Data1 of the target data with Data1 of the corresponding cloned data, and so on. Table 1 and Table 2 show the 128-bit target data and clone data, but the present invention does not limit the data to any specific number of bits.

When the target data is the same as the corresponding cloned data, the data mask signal DM outputs a first logical value (for example, 0), and the first logical value is used to indicate that there is no error in the target data and the cloned data. When the target data is different from the corresponding cloned data, the data mask signal DM outputs a second logical value (for example, 1) to indicate that there is an error in the target data and the cloned data.

4B, the memory device 400b includes a memory bank 412b, a comparator 420b, and a peripheral memory circuit 430b. The memory bank 412b includes a target memory array T and a clone memory array C corresponding to the target memory array T . In other words, the target memory array T and the clone memory array C are both located in the same memory group 412b. The comparator 420b and the peripheral memory circuit 430b shown in FIG. 4B are similar to the comparator 420a and the peripheral memory circuit 430a shown in FIG. 4A. Therefore, detailed descriptions of the comparator 420b and the peripheral memory circuit 430b are omitted below description.

In operation, when the trigger command and the write command are applied to the target memory array T of the memory group 412b, both the target memory array T and the clone memory array C are activated. The selected target unit of the target memory array T and the clone unit corresponding to the clone memory array C are triggered at the same time. In this way, the data to be written is written into the target cell selected by the target memory array T and the corresponding clone unit of the clone memory array C.

If the trigger command and the write command are applied to write data on a general memory array different from the target memory array T, the clone memory array C will not be triggered, and the write command of the general array will not be applied to another Memory array.

In another embodiment, when the memory device 400 receives a read command to read data stored in the selected target cell in the target memory array T, the selected target cell in the target memory array T And the corresponding clone unit in the clone memory array C is triggered at the same time. The read command is applied to the target unit and the corresponding clone unit to obtain the data D1 and D2. The data D1 and D2 (with or without ECC operation) are output to the comparator 420, and the comparator 420a compares the data D1 and D2 to determine whether the data stored in the target memory array T and the clone memory array C has errors.

In some embodiments of the present invention, a data bus inversion (DBI) algorithm can be enabled in the memory device to reduce the power consumption of the memory device. The DBI algorithm is used to determine whether the current data character is to be reversed based on the conversion times of the current data character from the previously sent data character (Data Word). Generally, if the number of conversions of the current data character from the previously sent data character is greater than or equal to half the number of bits of the current data, the current data character is reversed. For example, if the data character is 8-bit data, when the number of conversions of the current data character from the previously sent data character is greater than or equal to 4, the current data character will be reversed. In DRAM memory devices, the data mask signal is used to indicate whether the data characters are inverted. In particular, when the data mask signal has the logical value "1", the data character is inverted, and when the data mask signal has the logical value "0", the data character is not inverted.

5A and 5B show the signal waveforms in the memory device when the DBI algorithm is disabled. The signals shown include clock signal CLK, data selection communication signal DQS, data output signal DQ, and data mask signal DM. When the DBI algorithm is disabled, only the data mask signal DM can be used to determine whether the data read from the target memory array has errors.

As shown in FIG. 5A, if there is no error in the stored data, the data mask signal DM is output with a preset voltage (for example, the ground voltage level or the logical value “0”). As shown in FIG. 5B, when an error is detected in the stored data, a pulse signal is generated in the data mask signal DM. The pulse signals P51 and P52 generated on the data mask signal DM indicate that the data read from the target memory array is wrong. The wrong data characters of the read data can be determined according to the positions of the pulse signals P51 and P52.

6A to 6B show the signal waveforms in the memory device when the DBI algorithm is enabled. Similar to FIG. 5A and FIG. 5B, the signal shown includes the clock signal CLK, the data selection communication signal DQS, the data output signal DQ, and the data mask signal DM.

Since the data mask signal DM is also used to indicate the inverted data characters through the DBI algorithm in the DRAM device, when the DBI algorithm is enabled, the data mask signal DM alone is not sufficient to detect the storage in the target memory array The information is wrong. Please refer to FIG. 6A. Even if there is no error in reading the data, there are two pulse signals P60 in the data mask signal DM. These pulse signals only indicate that the data characters corresponding to these pulse signals are reversed by the DBI algorithm.

When the DBI algorithm is enabled in the memory device, the data mask signal DM and the data output signal DQ are both used to detect errors in the data stored in the target memory array. When a pulse signal is generated in the data mask signal DM, determine the current data character corresponding to the pulse signal, and calculate the number of bits with the preset logical value (for example, logical value "1") of the current data character . Then the number of bits with a preset logical value is compared with a threshold (for example, half of the total number of data bits) to determine whether the current data character has errors. For example, if the number of bits with a preset logical value is greater than or equal to the threshold, the current data character is judged as an error data character. Otherwise, the current data character is not wrong.

Please refer to FIG. 6B, the data characters corresponding to the pulse signals P61 and P62 have a preset logic value greater than the threshold number of bits (for example, all high bits). Therefore, the data characters corresponding to the pulse signals P61 and P62 are wrong data.

Please refer to FIG. 7, which illustrates an error detection method according to an embodiment of the present invention. In step S710, read the target memory cells of the target memory array to obtain target memory data. In step S720, the clone memory unit of the clone memory array is read to obtain clone memory data, where the clone memory unit of the clone memory array corresponds to the target memory unit of the target memory array. The clone memory unit of the clone memory array and the target memory unit of the target memory array can be triggered at the same time, so that steps S710 and S720 can be executed at the same time.

In step S730, the target memory data is compared with the clone memory data to output a comparison signal, and in step S740, it is determined whether the target memory data includes an error according to the comparison signal.

In summary, the embodiments of the present invention provide a memory device having a target memory array and a clone memory array, and an error detection method thereof. The clone memory array stores the same data as the target memory array, and the clone memory array and the target memory array can be located in the same memory group or different memory groups. The commands applied to the target memory array to perform operations are applied to the clone memory array. In order to detect errors in the data of the target memory array, the target memory data stored in the target memory array and the clone memory data stored in the clone memory array are read and compared to output a comparison signal. The output comparison signal is used to judge whether there is an error.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Memory device 112: memory group i 1121: Clone memory array 114: memory group j 116: memory group k 118: Memory group l 120: Comparator 130: peripheral memory circuit 140: Memory Controller 150: module register D1: Target memory data D2: Clone memory data DQ, DQ1: data output signal DM, DM1: Data mask signal 210a, 210b, 210c, 310a, 310b, 310c, 310d: memory array 212a~218a, 212b~218b, 212c~218c, 312a~318a, 312b~318b, 312c~318c, 312d~318d, 412a, 414a, 412b: memory group 420a, 420b: comparator 430a, 430b: peripheral memory circuit CLK: Clock signal DQS: data selection communication number GND: Ground voltage P51, P52, P60, P61, P62: pulse signal S710~S740: Flow of error detection method

The present invention includes drawings to provide a further understanding of the present invention, and the drawings are incorporated into this specification and constitute a part of this specification. The drawings illustrate embodiments of the present invention, and together with the disclosure of this specification, are used to explain the principle of the present invention. FIG. 1 is a schematic diagram showing a memory device according to an embodiment of the invention. 2A to 3D are schematic diagrams illustrating a memory device having a target memory array and a clone memory array according to an embodiment of the invention. 4A is a schematic diagram showing a memory device having a target memory array and clone memory arrays in different memory groups according to an embodiment of the present invention. 4B is a schematic diagram illustrating a memory device having a target memory array and a clone memory array in the same memory group according to an embodiment of the present invention. 5A to 5B are waveform diagrams of signals in the memory device when the data bus inversion algorithm is disabled according to an embodiment of the present invention. 6A to 6B are diagrams showing waveforms of signals in the memory device when the data bus inversion algorithm is enabled according to an embodiment of the present invention. Fig. 7 is a flowchart showing an error detection method according to an embodiment of the present invention.

100: Memory device

112: memory group i

1121: Clone memory array

114: memory group j

116: memory group k

118: Memory group l

120: Comparator

130: peripheral memory circuit

140: Memory Controller

150: module register

D1: Target memory data

D2: Clone memory data

DQ, DQ1: data output signal

DM, DM1: Data mask signal

Claims (18)

A memory device includes: The memory array includes at least one memory bank, wherein the at least one memory bank includes: Target memory array for storing data; and A clone memory array, corresponding to the target memory array, for cloning the data stored in the target memory array; Wherein, commands applied to the target memory array to perform operations are applied to the clone memory array. The memory device described in item 1 of the scope of patent application, wherein The at least one memory group includes a first memory group and a second memory group, The target memory array is located in the first memory group, and The clone memory array is located in the second memory group. The memory device described in item 1 of the scope of patent application also includes: The module register is coupled to the memory array for setting the size and position of the clone memory array, wherein, The command includes a trigger command, When the trigger command is applied to the target memory array, the module register activates the target memory array and the clone memory array, and simultaneously triggers the selection of the target memory array The target unit of and the clone unit corresponding to the clone memory array, When the trigger command is applied to write data on a general memory array different from the target memory array, the module register does not trigger the clone memory array. The memory device according to claim 1, wherein the target memory array and the clone memory array are also located in one of the at least one memory group. The memory device described in item 1 of the scope of patent application also includes: Peripheral memory circuit; and The memory controller is used to generate commands for performing operations on the target memory array and the cloned memory array. The memory device described in item 5 of the scope of patent application, wherein The command includes a write command for writing memory data into a target memory cell of the target memory array, In response to receiving the write command, the peripheral memory circuit simultaneously writes the memory data into the target memory cell of the target memory array and the clone memory cell of the clone memory array , Wherein the cloned memory unit corresponds to the target memory unit. The memory device described in item 5 of the scope of patent application, wherein The command includes a read command for reading a target memory cell of the target memory array, In response to receiving the read command, the peripheral memory circuit reads the target memory cell of the target memory array and the clone memory cell of the clone memory array to obtain target memory data and Clone memory data, wherein the clone memory unit of the clone memory array corresponds to the target memory unit of the target memory array. The memory device described in item 7 of the scope of patent application also includes: A comparator, coupled to the memory array and the peripheral memory circuit, is used to compare the target memory data with the cloned memory data to output a comparison signal, wherein When the target memory data is the same as the clone memory data, the comparison signal is set to a preset voltage, and When the target memory data is different from the clone memory data, a pulse signal is set on the comparison signal. The memory device according to claim 8, wherein the predetermined voltage is a first logical value, the first logical value is used to indicate that the target memory data does not include errors, and the pulse signal Is a second logical value, and the second logical value is used to indicate that the target memory data includes an error. The memory device described in item 8 of the scope of patent application, wherein When the comparison signal does not include the pulse signal, the memory controller determines that the target memory data does not include errors; and When the comparison signal includes the pulse signal, the memory controller determines that the target memory data includes the error. The memory device described in item 8 of the scope of patent application, wherein The data bus inversion algorithm is applied to transmit and read data through the bus in the memory device, and The memory controller is also used to: Calculating the number of bits in the target memory data with a preset logic value; Determining whether the number of bits in the target memory data with a preset logic value is greater than a threshold, When the number of bits in the target memory data with a preset logic value is greater than the threshold and the comparison signal includes the pulse signal, the memory controller determines that the target memory data includes Said error; When the number of bits in the target memory data with a preset logic value is not greater than the threshold or the comparison signal does not include the pulse signal, the memory controller determines the target memory The data does not include the error. The memory device described in item 7 of the scope of patent application, wherein The peripheral memory circuit reads the target memory cell to obtain first data, wherein a first error correction code operation is performed on the first data to obtain the target memory data, and The peripheral memory circuit reads the clone memory unit to obtain second data, wherein a second error correction code operation is performed on the second data to obtain the clone memory data. An error detection method is suitable for a memory device having at least one memory bank, the memory device includes a target memory array and a clone memory array, and the error detection includes the following steps: Reading target memory cells of the target memory array to obtain target memory data; Reading the clone memory unit of the clone memory array to obtain clone memory data, wherein the clone memory unit of the clone memory array corresponds to the target memory unit of the target memory array; Comparing the target memory data with the cloned memory data to output a comparison signal; and Determine whether the target memory data includes errors according to the comparison signal. The error detection method as described in item 13 of the scope of patent application, wherein the step of comparing the target memory data with the cloned memory data to output the comparison signal includes: Determine whether the target memory data is the same as the cloned memory data; When the target memory data is different from the clone memory data, setting a pulse signal on the comparison signal; and When the target memory data is the same as the clone memory data, the comparison signal is set to a preset voltage. According to the error detection method described in claim 14, wherein the step of judging whether the target memory data includes the error according to the comparison signal includes: When the comparison signal does not include the pulse signal, determining that the target memory data does not include the error; and When the comparison signal includes the pulse signal, it is determined that the target memory data includes the error. The error detection method as described in item 14 of the scope of patent application, where The data bus inversion algorithm is applied to transmit and read data through the bus in the memory device, and The step of determining whether the target memory data includes the error according to the comparison signal includes: Calculating the number of bits in the target memory data with a preset logic value; Determining whether the number of bits in the target memory data with a preset logic value is greater than a threshold, When the number of bits in the target memory data with a predetermined logic value is greater than the threshold and the comparison signal includes the pulse signal, determining that the target memory data includes the error; When the number of bits in the target memory data with a preset logic value is not greater than the threshold or the comparison signal does not include the pulse signal, it is determined that the target memory data does not include the error . The error detection method as described in item 13 of the scope of patent application, where Reading the target memory unit of the target memory array to obtain the target memory data and reading the clone memory unit of the clone memory array to obtain the clone memory data includes: Reading the target memory cell to obtain first data, and performing a first error correction code operation on the first data to obtain the target memory cell of the target memory array; and The cloned memory unit is read to obtain second data, and a second error correction code operation is performed on the second data to obtain the cloned memory data. The error detection method as described in item 13 of the scope of patent application, where The memory device also includes data output pins and data mask pins, and The comparison signal is sent to the data mask pin, and the read data is sent to the data output pin.

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