TW202034482A - Resistive random access memory structure - Google Patents

Abstract

A resistive random access memory structure includes a semiconductor substrate, a transistor, a bottom electrode, a plurality of top electrodes, and a resistive switching layer. The transistor is disposed over the semiconductor substrate. The bottom electrode is disposed over the semiconductor substrate and is in electrical connection with a drain region of the transistor. The plurality of top electrodes is disposed along a sidewall of the bottom electrode. The resistive switching layer is disposed between the bottom electrode and the plurality of top electrodes.

Description

Resistive random access memory structure

The present disclosure relates to a non-volatile memory structure, and particularly relates to a resistive random access memory structure.

Many new non-volatile memory materials and devices are currently being actively developed. New non-volatile memory devices include, for example, magnetic random access memory (MRAM), phase change memory (PCM), and resistive random access memory (RRAM), and so on. Resistive random access memory (RRAM) has low power consumption, low operating voltage, short write and erase time, long endurance, long memory time, non-destructive reading, multi-state memory, simple manufacturing process, and scalability Etc. Therefore, further reducing the area of the components in the resistive memory and increasing the capacity of the memory are the goals that the industry needs to develop.

The embodiment of the present invention provides a resistive random access memory structure. The resistive random access memory structure includes a semiconductor substrate, a transistor, a bottom electrode, a plurality of top electrodes, and a resistance conversion layer. The transistor is arranged on the semiconductor substrate. The bottom electrode is disposed on the semiconductor substrate and is electrically connected to the drain region of the transistor. These top electrodes are arranged along the sidewalls of the bottom electrodes. The resistance conversion layer is arranged between the top electrode and the bottom electrode.

The embodiment of the present invention provides a resistive random access memory structure. The resistive random access memory structure includes a semiconductor substrate, multiple metal layers, and a memory cell. The multiple metal layers are arranged on the semiconductor substrate. The memory cell is arranged on the semiconductor substrate and includes a bottom electrode, a plurality of top electrodes arranged along the sidewall of the bottom electrode, and a resistance conversion layer arranged between the top electrode and the bottom electrode. These top electrodes are electrically connected to at least two of the multilayer metal layers.

The following describes the present disclosure more fully with reference to the drawings of the embodiments of the present invention. However, the present disclosure can also be implemented in various different embodiments and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawings may be enlarged for clarity, and the same or similar reference numbers in the drawings indicate the same or similar elements.

Please refer to FIG. 1, which is a three-dimensional schematic diagram of a resistive random access memory structure 100 according to some embodiments of the present invention. In some embodiments, the resistive random access memory structure 100 includes a semiconductor substrate 102, a transistor 104, a contact 114, an interconnect structure 117, and a memory cell 145. Figure 1 shows only the above components, and the remaining components can be seen in the cross-sectional schematic diagrams of Figures 2H-1, 2H-2, 3H-1 or 3H-2.

In some embodiments, the transistor 104 is disposed on the semiconductor substrate 102. The transistor 104 includes a gate structure 106 disposed on the upper surface of the semiconductor substrate 102, and a source region 108 and a drain region 110 disposed in the semiconductor substrate 102. The source region 108 and the drain region 110 are disposed on the gate. Polar structure 106 on both sides. In some embodiments, the gate structure 106 extends in the Y direction. In the embodiment shown in Figure 1, the X direction and the Y direction are horizontal directions, and the Z direction is a vertical direction, where the X direction is not parallel to the Y direction. In one embodiment, the X direction is perpendicular to the Y direction.

In some embodiments, the interconnect structure 117 is disposed on the semiconductor substrate 102. The interconnect structure 117 includes multiple metal layers 118, 138, and 144, and vias 120, 136, and 142.

In some embodiments, the first metal layer 118 includes metal lines 118a, 118b, and 118c. The metal line 118b is a source line and is electrically connected to the source region 108 of the transistor 106 through the metal line 118c and the contact 114. In some embodiments, the metal line 118b extends in the X direction, and the metal line 118c extends in the Y direction.

The memory cell 145 is disposed on the semiconductor substrate 102 and between the first metal layer 118 and the second metal layer 138. In some embodiments, the memory cell 145 includes a bottom electrode 133, a plurality of top electrodes 122, and a resistance conversion layer 128 disposed between the bottom electrode 133 and the top electrode 122. The resistance conversion layer 128 surrounds the bottom electrode 133. In some embodiments, the bottom electrode 133 is electrically connected to the drain region 110 of the transistor 106 through the via 120, the metal wire 118 a and the contact 114.

In some embodiments, the top electrode 122 includes a first top electrode 122P1, a second top electrode 122P2, a third top electrode 122P3, and a fourth top electrode 122P4. The top electrodes 122P1, 122P2, 122P3, and 122P4 are spaced apart from each other and arranged laterally along the sidewall of the bottom electrode 133 to form a ring shape. In some embodiments, the top electrodes 122P1, 122P2, 122P3, and 122P4 are elongated.

In some embodiments, the first top electrode 122P1 and the third top electrode 122P3 extend in the Y direction, and are arranged opposite to the bottom electrode 133 in the Y direction. The first top electrode 122P1 and the third top electrode 122P3 are respectively electrically connected to the two bit lines 144B1 and 144B2 of the third metal layer 144 through the via 142, and the bit lines 144B1 and 144B2 extend in the X direction.

In some embodiments, the second top electrode 122P2 and the fourth top electrode 122P4 extend in the X direction, and are disposed opposite to the bottom electrode 133 in the X direction. The second top electrode 122P2 and the fourth top electrode 122P4 are respectively electrically connected to the two bit lines 138B2 and 138B1 of the second metal layer 138 through the via 136, and the bit lines 138B2 and 138B1 extend in the Y direction.

In the embodiment shown in FIG. 1, four top electrodes 122 are arranged along the sidewalls of the bottom electrode 133, so that the resistive random access memory structure 100 realizes a 1T4R structure. In some embodiments, the number of top electrodes disposed along the sidewall of the bottom electrode 133 may be greater than four.

For example, please refer to FIGS. 4A and 4B. FIGS. 4A and 4B are schematic top views showing memory cells 145A and 145B according to some embodiments of the present invention. The six top electrodes 122 are arranged annularly along the sidewall of the bottom electrode 133. In some embodiments, the top electrodes 122P1, 122P2, 122P3, 122P4, 122P5, and 122P6 are rotationally symmetric with each other about the rotation axis of the center 133C of the bottom electrode 133.

In the embodiment shown in FIG. 4A, the bottom electrode 133 is hexagonal when viewed from above, and the top electrodes 122P1, 122P2, 122P3, 122P4, 122P5, and 122P6 are arranged on the sides of the hexagon. In the embodiment shown in FIG. 4B, the bottom electrode 133 is circular. In some embodiments, the shape of the bottom electrode 133 depends on design requirements or limitations of etching process capabilities.

In some embodiments, the first top electrode 122P1 and the fourth top electrode 122P4 are opposed to each other, and are electrically connected to the two bit lines (not shown) of the second metal layer; the second top electrode 122P2 and the fifth The top electrode 122P5 is arranged oppositely and electrically connected to the two bit lines (not shown) of the third metal layer; the third top electrode 122P3 and the sixth top electrode 122P6 are arranged oppositely and electrically connected to the fourth Two bit lines (not shown) of the metal layer.

In the embodiment of the present invention, the resistive random access memory structure 100 includes a plurality of top electrodes 122 arranged along the sidewalls of the bottom electrode 133 to implement a 1TnR structure (where n is equal to or greater than 4), so that the resistive random access The storage capacity per unit area of the memory structure can be improved. In addition, these top electrodes are electrically connected to at least two layers of the multilayer metal layer, which saves the use space of the semiconductor substrate 102 and further improves the storage capacity per unit area. For example, the storage capacity of the 1T4R structure (that is, four top electrodes) in the embodiment of the present invention is twice that of the 1T1R (that is, one top electrode) structure.

The method for forming the resistive random access memory structure is described in detail below. Figures 2A-1 to 2H-1 are schematic top views illustrating the formation of a resistive random access memory structure 100A at different stages according to some embodiments of the present invention, and Figures 2A-2 to 2H-2 illustrate A schematic cross-sectional view of 2A-1 to 2H-1 along line II.

Please refer to Figures 2A-1 and 2A-2 to provide the semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, the semiconductor substrate 102 may be a semiconductor-on-insulator (SOI) substrate.

In some embodiments, the transistor 104 is formed on the substrate 102. Forming the transistor 104 includes forming a gate structure 106 on the semiconductor substrate 102 and forming a source region 108 and a drain region 110 in the semiconductor substrate 102. In some embodiments, the gate structure 106 may include a gate dielectric layer (not shown) formed on the upper surface of the semiconductor substrate 102, and a gate electrode (not shown) formed on the gate dielectric layer . In some embodiments, the gate dielectric layer is formed of silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or a combination of the foregoing. The gate electrode is made of conductive material, such as polysilicon, metal, metal nitride, conductive metal oxide, or a combination of the foregoing. In some embodiments, the source region 108 and the drain region 110 may be formed through an implantation process (for example, with p-type or n-type dopants).

Next, an interlayer dielectric (ILD) 112 is formed on the upper surface of the semiconductor substrate 102. The interlayer dielectric layer 112 covers the transistor 104. In some embodiments, the interlayer dielectric layer 112 is made of silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate It is formed of borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), low-k dielectric material, or a combination of the foregoing.

Next, a contact 114 is formed in the interlayer dielectric layer 112. The contact 114 passes through the interlayer dielectric layer 112 and falls on the source region 108 and the drain region 110. In some embodiments, the contact 114 is formed of a metal material (for example, tungsten (W), aluminum (Al), or copper (Cu)), metal alloy, polysilicon, or a combination of the foregoing. In some embodiments, the contact 114 is formed by an etching process, a deposition process, and a planarization process.

Next, an inter-metal dielectric (IMD) 116 is formed on the upper surface of the inter-metal dielectric layer 112. In some embodiments, the intermetal dielectric layer 116 is composed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, low-k dielectric materials, spin It is formed by spin-on-glass (SOG), the aforementioned multiple layers, or a combination of the aforementioned. The intermetal dielectric layer 116 is formed by a deposition process (such as chemical vapor deposition (CVD)), a spin coating process, or a combination of the foregoing.

Next, a first metal layer 118 and vias 120 are formed in the intermetal dielectric layer 116. The via 120 is formed on the first metal layer 118. In some embodiments, the first metal layer 118 and the via 120 are made of metal materials, such as tungsten (W), nickel (Ni), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu) , Titanium Nitride (TiN), Tantalum Nitride (TaN), similar materials, the aforementioned alloys, the aforementioned multilayers, or a combination of the aforementioned. In some embodiments, the first metal layer 118 and the via 120 may be formed through a deposition process, an etching process, electroplating, a single damascene process, a dual damascene process, or a combination of the foregoing.

Next, a top electrode material 121 is formed on the upper surface of the intermetal dielectric layer 116. In some embodiments, the top electrode material 121 is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), tungsten (W), aluminum (Al), Or a combination of the foregoing. In some embodiments, the top electrode can be deposited by physical vapor deposition (PVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), or a combination of the foregoing Material 121.

Please refer to Figures 2B-1 and 2B-2 to pattern the top electrode material 121. The patterned top electrode material 121' includes a central portion 122C and a plurality of protruding portions 122P1, 122P2, 122P3, and 122P4 connected to the central portion 122C. In some embodiments, the patterning process includes a lithography process and an etching process.

Then, an intermetal dielectric layer 124 is formed on the intermetal dielectric layer 116. The intermetal dielectric layer 124 covers the patterned top electrode material 121'. In some embodiments, the material and formation method of the intermetal dielectric layer 124 may be the same as or similar to the intermetal dielectric layer 116.

Please refer to Figures 2C-1 and 2C-2 to pattern the intermetal dielectric layer 124 and the top electrode material 121'. The patterning process removes the central portion 122C of the top electrode material 121' to form the opening 126. The protruding portions 122P1, 122P2, 122P3, and 122P4 of the top electrode material 121' are left unremoved to serve as top electrodes.

In some embodiments, the opening 126 exposes the intermetal dielectric layer 116 and the via 120. The opening 126 separates these top electrodes 122P1, 122P2, 122P3, and 122P4 from each other. In the embodiment shown in Figure 2C-1, the opening 126 is rectangular. In some other embodiments, the opening 126 may have other shapes, such as polygonal or circular. In some embodiments, the patterning process may include a lithography process and an etching process.

Referring to FIGS. 2D-1 and 2D-2, the resistance conversion layer 128 is formed along the sidewall of the opening 126. In some embodiments, the resistance conversion layer 128 contacts the respective sidewalls of the top electrodes 122P1, 122P2, 122P3, and 122P4. In some embodiments, the resistance conversion layer 128 is formed of a transition metal oxide, such as Ta ₂ O ₅ , HfO ₂ , HSiO _x , Al ₂ O ₃ , InO ₂ , La ₂ O ₃ , ZrO ₂ , TaO ₂ , or the foregoing的组合。 The combination. The step of forming the resistance switching layer 128 includes conformally depositing a transition metal oxide along the upper surface of the intermetal dielectric layer 124 and the sidewall and bottom surface of the opening 126. Next, an etching process is performed to remove the transition metal oxide along the upper surface of the intermetal dielectric layer 124 and the bottom surface of the opening 126. After the etching process, the upper surface of the resistance conversion layer 128 may be lower than the upper surface of the intermetal dielectric layer 124.

Please refer to FIGS. 2E-1 and 2E-2 to form the bottom electrode material 130 on the upper surface of the intermetal dielectric layer 124 and fill the remaining part of the opening 126. In some embodiments, the bottom electrode material 130 is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), tungsten (W), aluminum (Al), Or a combination of the foregoing. In some embodiments, the bottom electrode material 130 may be deposited by physical vapor deposition (PVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), or a combination of the foregoing.

Please refer to FIGS. 2F-1 and 2F-2 to remove the portion of the bottom electrode material 130 covering the intermetal dielectric layer 124 to expose the upper surface of the intermetal dielectric layer 124. After the removal process, a bottom electrode 133 is formed in the opening 126. In some embodiments, the upper surface of the bottom electrode 133 and the intermetal dielectric layer 124 are coplanar. In some embodiments, the bottom electrode 133 includes an upper portion covering the upper surface of the resistance conversion layer 128 and a lower portion surrounded by the resistance conversion layer 128. In some embodiments, the removal process may be a chemical mechanical polish (CMP) or an etch-back process.

Please refer to FIGS. 2G-1 and 2G-2 to form an intermetal dielectric layer 134 on the intermetal dielectric layer 124. The intermetal dielectric layer 134 covers the bottom electrode 133. In some embodiments, the material and formation method of the intermetal dielectric layer 134 may be the same as or similar to the intermetal dielectric layer 116.

In some embodiments, the via 136 is formed through the intermetal dielectric layers 124 and 134 and falls on the second top electrode 122P2 and the fourth top electrode 122P4, and a second metal layer 138 is formed on the intermetal dielectric layer 134 and above the guide hole 136. The second metal layer 138 includes a bit line 138B1 and a bit line 138B2. In some embodiments, the bit line 138B2 and the bit line 138B1 of the second metal layer 138 extend in the Y direction and are electrically connected to the second top electrode 122P2 and the fourth top electrode 122P4, respectively. In some embodiments, the material and formation method of the via 136 and the second metal layer 138 may be the same as or similar to the via 120 and the first metal layer 118.

Please refer to FIGS. 2H-1 and 2H-2 to form an IMD layer 140 on the IMD layer 134. The intermetal dielectric layer 140 covers the second metal layer 138. In some embodiments, the material and formation method of the intermetal dielectric layer 140 may be the same or similar to the intermetal dielectric layer 116.

In some embodiments, the via 142 is formed through the intermetal dielectric layers 124, 134, and 140 and falls on the first top electrode 122P1 and the third top electrode 122P3, and a third metal layer 144 is formed between the intermetal dielectric layers. In the electrical layer 140 and above the via 142. The third metal layer 144 includes a bit line 144B1 and a bit line 144B2. In some embodiments, the bit line 144B1 and the bit line 144B2 of the third metal layer 144 extend in the X direction and are electrically connected to the first top electrode 122P1 and the third top electrode 122P3, respectively. In some embodiments, the materials and formation methods of the via 142 and the third metal layer 144 may be the same as or similar to the via 120 and the first metal layer 118. After the via 142 and the third metal layer 144 are formed, a resistive random access memory structure 100A is fabricated.

Figures 3A-1 to 3H-1 are schematic top views of different stages of forming a resistive random access memory structure 100B according to other embodiments of the present invention, and Figures 3A-2 to 3H-2 are A schematic cross-sectional view taken along line II in FIGS. 3A-1 to 3H-1 is shown. The same reference numerals are used for the components of the embodiment that are the same as those of the foregoing FIGS. 2A-1 to 2A-2, and the description thereof is omitted. In the embodiment of FIGS. 2A-1 to 2H-2, the bottom electrode is formed after forming a plurality of top electrodes, and in the embodiment of FIGS. 3A-1 to 3H-2, a plurality of top electrodes are formed after the bottom electrode is formed. electrode.

Please refer to FIGS. 3A-1 and 3A-2 to form a bottom electrode material 130 (not shown) on the upper surface of the intermetal dielectric layer 116. Next, the bottom electrode material 130 is patterned to form the bottom electrode 133 on the via hole 120.

Referring to FIGS. 3B-1 and 3B-2, a resistance conversion layer 128 is formed along the sidewall of the bottom electrode 133. The resistance conversion layer 128 surrounds the bottom electrode 133. The resistance conversion layer 128 can be formed by conformally depositing transition metal oxide along the upper surface of the intermetal dielectric layer 116 and the sidewall and upper surface of the bottom electrode 133. Next, an etching process is performed to remove portions of the transition metal oxide along the upper surface of the intermetal dielectric layer 116 and the upper surface of the bottom electrode 133. After the etching process, the upper surface of the resistance conversion layer 128 may be lower than the upper surface of the bottom electrode 133.

Please refer to FIGS. 3C-1 and 3C-2 to form a top electrode material 121 on the intermetal dielectric layer 116 and cover the resistance conversion layer 128 and the bottom electrode 133.

Please refer to FIGS. 3D-1 and 3D-2 to remove the part of the top electrode material 121 covering the resistance conversion layer 128 and the bottom electrode 133. In some embodiments, the removal process may be a chemical mechanical polishing (CMP) or etch-back process.

Referring to FIGS. 3E-1 and 3E-2, the top electrode material 121 is patterned to form a plurality of top electrodes 122P1, 122P2, 122P3, and 122P4 along the sidewalls of the bottom electrode 133.

Please refer to FIGS. 3F-1 and 3F-2 to form an IMD layer 124 on the IMD layer 116. The intermetal dielectric layer 124 covers the bottom electrode 133, the resistance conversion layer 128, and the top electrodes 122P1, 122P2, 122P3, and 122P4.

Please refer to FIGS. 3G-1 and 3G-2 to form an intermetal dielectric layer 134 on the intermetal dielectric layer 124. Next, a via 136 is formed through the intermetal dielectric layers 124 and 134 and falls on the second top electrode 122P2 and the fourth top electrode 122P4, and a second metal layer 138 is formed in the intermetal dielectric layer 134 and in the Above the guide hole 136. The bit line 138B2 and the bit line 138B1 of the second metal layer 138 extend in the Y direction and are electrically connected to the second top electrode 122P2 and the fourth top electrode 122P4, respectively.

Please refer to FIGS. 3H-1 and 3H-2 to form an intermetal dielectric layer 140 on the intermetal dielectric layer 134. Next, a via 142 is formed to pass through the intermetal dielectric layers 124, 134, and 140 and fall on the first top electrode 122P1 and the third top electrode 122P3, and a third metal layer 144 is formed in the intermetal dielectric layer 140 And above the guide hole 142. The bit line 144B1 and the bit line 144B2 of the third metal layer 144 extend in the X direction and are electrically connected to the first top electrode 122P1 and the third top electrode 122P3, respectively. After the via 142 and the third metal layer 144 are formed, a resistive random access memory structure 100B is fabricated.

In summary, the resistive random access memory structure includes a plurality of top electrodes arranged along the sidewalls of the bottom electrode to realize a 1TnR structure (where n is equal to or greater than 4), so that the resistive random access memory structure is The storage capacity per unit area can be improved.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100, 100A, 100B: Resistive random access memory structure 102: Semiconductor substrate 110: Drain region 104: Transistor 112: Interlayer dielectric layer 106: Gate structure 114: Contact 108: source region 116, 124, 134, 140: intermetal dielectric layer 117: Internal connection structure 118: The first metal layer 118a, 118b, 118c: metal wire 120, 136, 142: pilot hole 121, 121’: Top electrode material 122, 122P1, 122P2, 122P3, 122p4, 122P5, 122P6: top electrode 122C: Central part 126: opening 133: bottom electrode 128: Resistance conversion layer 133C: Center 130: bottom electrode material 138: second metal layer 138B1, 138B2, 144B1, 144B2: bit line 144: The third metal layer 145, 145A, 145B: memory cell X, Y, Z: direction

In order to make the features and advantages of the present invention more comprehensible, different embodiments are specifically cited below, together with the accompanying drawings, for detailed descriptions as follows: FIG. 1 is a three-dimensional schematic diagram of a resistive random access memory structure according to some embodiments of the present invention. Figures 2A-1 to 2H-1 are schematic top views showing the formation of a resistive random access memory structure at different stages according to some embodiments of the present invention; Figures 2A-2 to 2H-2 show the secondA -1 to 2H-1 are schematic cross-sectional views along line II. Figures 3A-1 to 3H-1 are schematic top views showing the formation of a resistive random access memory structure at different stages according to some embodiments of the present invention; Figures 3A-2 to 3H-2 show the 3A -1 to 3H-1 are schematic cross-sectional views along line II. 4A and 4B are schematic top views showing memory cell according to some embodiments of the present invention.

100: Resistive random access memory structure

102: Semiconductor substrate

104: Transistor

106: Gate structure

108: source region

110: Drain region

114: Contact

117: Internal connection structure

118: The first metal layer

118a, 118b, 118c: metal wire

120, 136, 142: pilot hole

122, 122P1, 122P2, 122P3, 122p4: top electrode

128: Resistance conversion layer

133: bottom electrode

138: second metal layer

138B1, 138B2, 144B1, 144B2: bit line

144: The third metal layer

145: Memory cell

X, Y, Z: direction

Claims (14)

A resistive random access memory structure, including: A semiconductor substrate; A transistor arranged on the semiconductor substrate; A bottom electrode disposed on the semiconductor substrate, wherein the bottom electrode is electrically connected to a drain region of the transistor; A plurality of top electrodes are arranged along the sidewall of the bottom electrode; and A resistance conversion layer is arranged between the top electrodes and the bottom electrodes. According to the resistive random access memory structure described in claim 1, wherein the top electrodes include a first top electrode, a second top electrode, a third top electrode, and a fourth top electrode. In the resistive random access memory structure described in claim 2, wherein the first top electrode and the third top electrode are arranged opposite to each other in a first direction, and the second top electrode and the first top electrode The four top electrodes are arranged oppositely in a second direction, and the second direction is not parallel to the first direction. The resistive random access memory structure described in item 2 of the scope of patent application further includes: A first metal layer is disposed on the bottom electrode, the resistance conversion layer and the top electrodes, wherein the second top electrode and the fourth top electrode are respectively electrically connected to two positions of the first metal layer Element line A second metal layer is disposed on the first metal layer, wherein the first top electrode and the third top electrode are respectively electrically connected to two bit lines of the second metal layer. The resistive random access memory structure described in claim 4, wherein the two bit lines of the first metal layer extend in a first direction, and the two bit lines of the second metal layer The bit line extends in a second direction, and the second direction is not parallel to the first direction. In the resistive random access memory structure described in claim 1, wherein the bottom electrode covers the upper surface of the resistance conversion layer. The resistive random access memory structure described in the first item of the scope of patent application, wherein the upper surface of the bottom electrode, the respective upper surfaces of the top electrodes, and the upper surface of the resistance conversion layer are coplanar. A resistive random access memory structure, including: A semiconductor substrate; A multi-layer metal layer disposed on the semiconductor substrate; and A memory cell is disposed on the semiconductor substrate and includes: A bottom electrode; A plurality of top electrodes are arranged along the sidewall of the bottom electrode; and A resistance conversion layer disposed between the top electrodes and the bottom electrodes; The top electrodes are electrically connected to at least two layers of the multi-layer metal layer. In the resistive random access memory structure described in claim 8, wherein the top electrodes are rotationally symmetric with each other about a rotation axis at the center of the bottom electrode. The resistive random access memory structure described in item 8 of the scope of patent application, wherein the top electrodes are arranged in a ring shape. In the resistive random access memory structure described in item 8 of the scope of patent application, the number of the top electrodes is equal to or greater than 4. The resistive random access memory structure described in item 8 of the scope of patent application, wherein the memory cell is disposed between the first layer and the second layer of the multilayer metal layer. The resistive random access memory structure described in claim 12, wherein the first layer of the multilayer metal layer includes a source line, and the source line is electrically connected to a source region in the semiconductor substrate Sexual connection. As for the resistive random access memory structure described in claim 12, wherein two of the top electrodes are electrically connected to the second layer of the multilayer metal layer, and two of the top electrodes Each is electrically connected to the third layer of the multilayer metal layer.

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