TW202032566A - Non-volatile memory and program method thereof - Google Patents
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本發明是有關於一種非揮發性記憶體及其程式化方法,且特別是有關於一種可加快程式化速度的非揮發性記憶體及其程式化方法。The present invention relates to a non-volatile memory and its programming method, and more particularly to a non-volatile memory and its programming method that can speed up programming.
隨著電子科技的進步,電子產品成為人們生活中的重要工具。相同的,為提供更多的功能,以及傳送更多的資訊,電子產品中的記憶裝置的容量也越來越大,對於存取效率的要求,也日漸提升。With the advancement of electronic technology, electronic products have become important tools in people's lives. Similarly, in order to provide more functions and transmit more information, the capacity of memory devices in electronic products is also increasing, and the requirements for access efficiency are also increasing.
以非揮發式記憶體為例,隨著容量需求的增加,非揮發式記憶體的晶片佈局密度也隨之升高。這也造成在進行記憶胞的資料存取動作時,字元線間所具有的寄生電容,將嚴重的影響到字元線的電壓的調整動作。特別關於在程式化(program)的部分,在針對非揮發性記憶胞進行程式化動作時,常需要將程式化字元線的電壓提升到一個足夠高的電壓值,以完成程式化動作。在習知技術領域中,常發生程式化字元線的電壓,因字元線間的寄生電容的影響,而降低其電壓的上升速率。如此一來,程式化動作的速率被降低,影響到非揮發式記憶體的工作效率。Taking non-volatile memory as an example, as the capacity demand increases, the chip layout density of the non-volatile memory also increases. This also causes the parasitic capacitance between the word lines when the data access operation of the memory cell is performed, which will seriously affect the adjustment of the voltage of the word line. Especially in the part of programming, when performing programming actions on non-volatile memory cells, it is often necessary to increase the voltage of the programming character line to a sufficiently high voltage value to complete the programming action. In the conventional technical field, the voltage of the programmed word line often occurs, and the rising rate of the voltage is reduced due to the influence of the parasitic capacitance between the word lines. As a result, the rate of programming actions is reduced, which affects the efficiency of the non-volatile memory.
本發明提供一種非揮發性記憶體及其程式化方法,可有效縮減程式化所需的時間。The invention provides a non-volatile memory and its programming method, which can effectively reduce the time required for programming.
本發明的非揮發性記憶體的程式化方法包括:設定多條字元線的其中之一為一程式化字元線,設定字元線中非程式化字元線者為多個未選中字元線;在程式化時間區間中的第一子時間區間中,使程式化字元線上的電壓由參考電壓被提升至第一程式化電壓;在程式化時間區間中的第二子時間區間中,使程式化字元線上的電壓由第一程式化電壓被提升至第二程式化電壓,其中第二程式化電壓大於第一程式化電壓;以及,在第二子時間區間,提供使至少部分的未選中字元線的電壓由參考電壓被提升至通過電壓。其中第一子時間區間發生在第二子時間區間之前。The programming method of the non-volatile memory of the present invention includes: setting one of the multiple character lines as a stylized character line, and setting the non-programmed character lines in the character line as multiple unselected characters Element line; in the first sub-time interval of the stylized time interval, the voltage on the stylized character line is raised from the reference voltage to the first stylized voltage; in the second sub-time interval of the stylized time interval , So that the voltage on the programmed character line is increased from the first programmed voltage to the second programmed voltage, wherein the second programmed voltage is greater than the first programmed voltage; and, in the second sub-time interval, at least part of the The voltage of the unselected word line is raised from the reference voltage to the pass voltage. The first sub-time interval occurs before the second sub-time interval.
本發明的非揮發性記憶體包括多條字元線、多個字元線驅動器以及控制器。各字元線耦接至少一記憶胞串。多個字元線驅動器分別耦接字元線,用以調整該些字源線上的電壓。控制器耦接字元線驅動器,用以:設定多條字元線的其中之一為一程式化字元線,設定字元線中非程式化字元線者為多個未選中字元線;在程式化時間區間中的第一子時間區間中,使程式化字元線上的電壓由參考電壓被提升至第一程式化電壓;在程式化時間區間中的第二子時間區間中,使程式化字元線上的電壓由第一程式化電壓被提升至第二程式化電壓,其中第二程式化電壓大於第一程式化電壓;以及,在第二子時間區間,提供使至少部分的未選中字元線的電壓由參考電壓被提升至通過電壓。其中第一子時間區間發生在第二子時間區間之前。The non-volatile memory of the present invention includes a plurality of word lines, a plurality of word line drivers and a controller. Each character line is coupled to at least one memory cell string. A plurality of word line drivers are respectively coupled to the word lines for adjusting the voltages on the word source lines. The controller is coupled to the character line driver for: setting one of the plurality of character lines as a programmed character line, and setting the non-programmed character lines in the character line as multiple unselected character lines ; In the first sub-time interval in the stylized time interval, the voltage on the stylized character line is raised from the reference voltage to the first stylized voltage; in the second sub-time interval in the stylized time interval, The voltage on the programmed character line is raised from the first programmed voltage to the second programmed voltage, wherein the second programmed voltage is greater than the first programmed voltage; and, in the second sub-time interval, at least part of the The voltage of the selected word line is raised from the reference voltage to the pass voltage. The first sub-time interval occurs before the second sub-time interval.
基於上述,本發明程式化時間區間中,在當程式化字元線的電壓上升至足夠大的第二程式化電壓時,至少部分的未選中字元線的電壓由參考電壓同步被提升至通過電壓。如此一來,未選中字元線與程式化字元線間寄生電容的影響可以有效被減低,並使程式化字元線的電壓可快速提升至足夠大的電壓值,並提升記憶胞的程式化的速度。Based on the above, in the programming time interval of the present invention, when the voltage of the programming word line rises to a sufficiently large second programming voltage, the voltage of at least part of the unselected word lines is synchronized from the reference voltage to pass Voltage. In this way, the influence of the parasitic capacitance between the unselected character line and the programmed character line can be effectively reduced, and the voltage of the programmed character line can be quickly increased to a sufficiently large voltage value, and the memory cell program can be improved Speed.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
請參照圖1,圖1繪示本發明一實施例的非揮發性記憶體的程式化方法的流程圖。在圖1中,當要針對非揮發性記憶體進行程式化動作時,步驟S110設定非揮發性記憶體中的多條字元線的其中之一為程式化字元線,並設定上多條字元線中,非上述程式化字元線的字元線為多條未選中字元線。接著,在步驟S120中,在程式化時間區間中的第一子時間區間中,使程式化字元線上的電壓由參考電壓被提升至第一程式化電壓。接著,在步驟S130中,在上述的程式化時間區間中的第二子時間區間中,使程式化字元線上的電壓由第一程式化電壓被提升至第二程式化電壓,其中第二程式化電壓大於第一程式化電壓。在此請注意,步驟S130的第二子時間區間發生在步驟S120的第一子時間區間之後,其中,第一子時間區間與第二子時間區間不相重疊。此外,在步驟S140中,在上述的第二子時間區間,提供使至少部分的未選中字元線的電壓由參考電壓被提升至通過電壓。Please refer to FIG. 1. FIG. 1 is a flowchart of a programming method of a non-volatile memory according to an embodiment of the present invention. In FIG. 1, when a programming action is to be performed on the non-volatile memory, step S110 sets one of the multiple character lines in the non-volatile memory as a programming character line, and sets the multiple Among the character lines, the character lines other than the above-mentioned stylized character lines are multiple unselected character lines. Then, in step S120, in the first sub-time interval of the programming time interval, the voltage on the programming word line is raised from the reference voltage to the first programming voltage. Next, in step S130, in the second sub-time interval of the above-mentioned programmed time interval, the voltage on the programmed character line is increased from the first programmed voltage to the second programmed voltage, wherein the second program The voltage is greater than the first programming voltage. Please note here that the second sub-time interval of step S130 occurs after the first sub-time interval of step S120, wherein the first sub-time interval and the second sub-time interval do not overlap. In addition, in step S140, in the aforementioned second sub-time interval, it is provided that the voltage of at least part of the unselected word lines is raised from the reference voltage to the pass voltage.
在此請注意,本發明實施例透過在第二子時間區間中,使程式化字元線以及至少部分的未選中字元線上的電壓,同時進行電壓拉升的動作。如此一來,程式化字元線以及其他的未選中字元線間的寄生電容,對於程式化字元線上的電壓的拉升所產生的影響,可以有效的被降低,提升程式化字元線的電壓被提升至第二程式化電壓的速度。同時,可加快記憶胞的被程式化的速度。Please note here that, in the embodiment of the present invention, the voltage on the stylized word line and at least part of the unselected word lines is increased during the second sub-time interval. In this way, the parasitic capacitance between the stylized character line and other unselected character lines can effectively reduce the influence of the voltage rise on the stylized character line and increase the stylized character line. The voltage is raised to the speed of the second programmed voltage. At the same time, it can speed up the programming speed of memory cells.
值得一提的,步驟S130中關於使程式化字元線上的電壓由第一程式化電壓被提升至第二程式化電壓,以及步驟S140中關於提供使至少部分的未選中字元線的電壓由參考電壓被提升至通過電壓的動作可以是同步的。並透過使程式化字元線以及其他的未選中字元線間的各寄生電容的兩端點上的電壓同步提升,來減低寄生電容所造成的影響。It is worth mentioning that in step S130, the voltage on the programmed word line is increased from the first programmed voltage to the second programmed voltage, and in step S140, the voltage on at least part of the unselected word lines is changed from The action of raising the reference voltage to the pass voltage may be synchronized. And by simultaneously increasing the voltages at the two ends of the parasitic capacitances between the stylized word line and other unselected word lines, the influence caused by the parasitic capacitance is reduced.
請同步參照圖1以及圖2A~2C,圖2A~2C分別繪示本發明不同實施方式的非揮發性記憶體的程式化方法的動作波形圖。在圖2A中,在程式化時間區間TA1中的第一子時間區間T1中,程式化字元線WLn的電壓由參考電壓(例如為參考接地電壓)被提升至第一程式化電壓VPG1,並被維持在第一程式化電壓VPG1。相對的,未選中字元線WLo的電壓在程式化時間區間TA1中的第一子時間區間T1中,則維持等於參考電壓。接著,在程式化時間區間TA1中的第二子時間區間Tpgm中,程式化字元線WLn的電壓由第一程式化電壓VPG1被提升至第二程式化電壓VPG2,而相對應的,在程式化時間區間TA1中的第二子時間區間Tpgm中,未選中字元線WLo的電壓則由參考電壓,同步被提升至通過電壓VPASS。Please refer to FIG. 1 and FIGS. 2A to 2C simultaneously. FIGS. 2A to 2C respectively illustrate the action waveform diagrams of the programming method of the non-volatile memory in different embodiments of the present invention. In FIG. 2A, in the first sub-time interval T1 in the programming time interval TA1, the voltage of the programming word line WLn is raised from the reference voltage (for example, the reference ground voltage) to the first programming voltage VPG1, and It is maintained at the first programming voltage VPG1. In contrast, the voltage of the unselected word line WLo remains equal to the reference voltage in the first sub-time interval T1 in the programmed time interval TA1. Then, in the second sub-time interval Tpgm in the programming time interval TA1, the voltage of the programming word line WLn is raised from the first programming voltage VPG1 to the second programming voltage VPG2, and correspondingly, in the programming In the second sub-time interval Tpgm in the time interval TA1, the voltage of the unselected word line WLo is synchronously increased from the reference voltage to the pass voltage VPASS.
值得一提的,在第二子時間區間Tpgm中,程式化字元線WLn的電壓提升動作,與未選中字元線WLo的電壓提升動作,示同步發生在轉態時間區間TR中,並藉此降低程式化字元線WLn與未選中字元線WLo間的寄生電容所產生的影響。It is worth mentioning that in the second sub-time interval Tpgm, the voltage raising action of the programmed word line WLn and the voltage raising action of the unselected word line WLo show that the synchronization occurs in the transition time interval TR and borrow This reduces the influence of the parasitic capacitance between the programmed word line WLn and the unselected word line WLo.
此外,程式化字元線WLn上連接的記憶胞串,可在第二子時間區間Tpgm中,在當程式化字元線WLn的電壓被提升至第二程式化電壓VPG2時執行並完成的程式化動作。因此,在程式化字元線WLn的電壓可快速被提升至第二程式化電壓VPG2的前提下,記憶胞串的程式化動作也可快速的被完成。In addition, the memory cell string connected to the programming word line WLn can be executed and completed when the voltage of the programming word line WLn is raised to the second programming voltage VPG2 in the second sub-time interval Tpgm化动。 To move. Therefore, under the premise that the voltage of the programming word line WLn can be quickly raised to the second programming voltage VPG2, the programming action of the memory cell string can also be completed quickly.
在本實施例中,通過電壓VPASS的電壓值小於第二程式化電壓VPG2的電壓值。在本發明一些實施例中,通過電壓VPASS的電壓值可設置為實質上等於第二程式化電壓VPG2的電壓值以及第一程式化電壓VPG1的電壓值的差值。In this embodiment, the voltage value of the pass voltage VPASS is smaller than the voltage value of the second programming voltage VPG2. In some embodiments of the present invention, the voltage value of the pass voltage VPASS can be set to be substantially equal to the difference between the voltage value of the second programming voltage VPG2 and the voltage value of the first programming voltage VPG1.
附帶一提的,在圖2A中,程式化字元線WLn以外的所有的字元線皆可設定為未選中字元線WLo,並搭配圖2A的波形進行動作。Incidentally, in FIG. 2A, all character lines other than the programmed character line WLn can be set as unselected character lines WLo, and act in accordance with the waveform of FIG. 2A.
在圖2B中,程式化字元線WLn以外的字元線另被區分為相鄰於程式化字元線WLn的相鄰未選中字元線WLn+1、WLn-1以及其他未選中字元線WLo。在動作細節上,在程式化時間區間TA1中的第一子時間區間T1中,程式化字元線WLn的電壓由參考電壓被提升至第一程式化電壓VPG1,並被維持在第一程式化電壓VPG1。相對的,未選中字元線WLo的電壓在程式化時間區間TA1中的第一子時間區間T1中,則由參考電壓被提升至通過電壓VPASS。在此,未選中字元線WLo的電壓提升動作與程式化字元線WLn的電壓提升動作可以是同步的。接著,在程式化時間區間TA1中的第二子時間區間Tpgm中,程式化字元線WLn的電壓由第一程式化電壓VPG1被提升至第二程式化電壓VPG2,而相對應的,在程式化時間區間TA1中的第二子時間區間Tpgm中,相鄰未選中字元線WLn+1、WLn-1上的電壓則由參考電壓,同步被提升至通過電壓VPASS。In FIG. 2B, word lines other than the stylized word line WLn are divided into adjacent unselected word lines WLn+1, WLn-1, and other unselected characters adjacent to the stylized word line WLn. Line WLo. In terms of operation details, in the first sub-time interval T1 in the programming time interval TA1, the voltage of the programming word line WLn is raised from the reference voltage to the first programming voltage VPG1, and is maintained at the first programming voltage VPG1. Voltage VPG1. In contrast, the voltage of the unselected word line WLo is raised from the reference voltage to the pass voltage VPASS in the first sub-time interval T1 in the programmed time interval TA1. Here, the voltage raising action of the unselected word line WLo and the voltage raising action of the programmed word line WLn may be synchronized. Then, in the second sub-time interval Tpgm in the programming time interval TA1, the voltage of the programming word line WLn is raised from the first programming voltage VPG1 to the second programming voltage VPG2, and correspondingly, in the programming In the second sub-time interval Tpgm in the time interval TA1, the voltages on the adjacent unselected word lines WLn+1 and WLn-1 are synchronously raised to the pass voltage VPASS from the reference voltage.
在本實施方式中,基於相鄰未選中字元線WLn+1、WLn-1與程式化字元線WLn間的寄生電容,貢獻相對大的寄生效應至程式化字元線WLn。因此,透過使相鄰未選中字元線WLn+1、WLn-1以及程式化字元線WLn在程式化時間區間TA1中的第二子時間區間Tpgm進行同步的電壓提升動作,可有效減低寄生電容所產生的效應。In this embodiment, based on the parasitic capacitance between adjacent unselected word lines WLn+1, WLn-1 and the programmed word line WLn, a relatively large parasitic effect is contributed to the programmed word line WLn. Therefore, by causing the adjacent unselected word lines WLn+1, WLn-1, and the programmed word line WLn to perform a synchronous voltage boosting operation in the second sub-time interval Tpgm of the programmed time interval TA1, the parasitic can be effectively reduced. The effect of capacitance.
在圖2C中,程式化字元線WLn以外的字元線同樣被區分為相鄰於程式化字元線WLn的相鄰未選中字元線WLn+1、WLn-1以及其他未選中字元線WLo。在動作細節上,在程式化時間區間TA1中的第一子時間區間T1中,程式化字元線WLn的電壓由參考電壓被提升至第一程式化電壓VPG1,並被維持在第一程式化電壓VPG1。相對的,相鄰未選中字元線WLn+1、WLn-1的電壓在程式化時間區間TA1中的第一子時間區間T1中,則由參考電壓被提升至通過電壓VPASS。在此,相鄰未選中字元線WLn+1、WLn-1的電壓提升動作與程式化字元線WLn的電壓提升動作可以是同步的。接著,在程式化時間區間TA1中的第二子時間區間Tpgm中,程式化字元線WLn的電壓由第一程式化電壓VPG1被提升至第二程式化電壓VPG2,而相對應的,在程式化時間區間TA1中的第二子時間區間Tpgm中,其他未選中字元線WLo上的電壓則由參考電壓,同步被提升至通過電壓VPASS。In FIG. 2C, word lines other than the stylized word line WLn are also divided into adjacent unselected word lines WLn+1, WLn-1, and other unselected characters adjacent to the stylized word line WLn. Line WLo. In terms of operation details, in the first sub-time interval T1 in the programming time interval TA1, the voltage of the programming word line WLn is raised from the reference voltage to the first programming voltage VPG1, and is maintained at the first programming voltage VPG1. Voltage VPG1. In contrast, the voltages of adjacent unselected word lines WLn+1 and WLn-1 are raised from the reference voltage to the pass voltage VPASS in the first sub-time interval T1 in the programming time interval TA1. Here, the voltage raising action of the adjacent unselected word lines
以下請參照圖2D,圖2D繪示本發明另一實施例的非揮發性記憶體的程式化方法的動作波形圖。在圖2D中,在程式化時間區間TA1前設置一預充電時間區間TPRE。在預充電時間區間TPRE中,使字元線WLo、WLn對應的多條源極線SSSL、USSL以及位元線BL上的電壓,由參考電壓被提升至預充電電壓VCC。並且,在預充電時間區間TPRE開始後一個延遲時間TD後,程式化時間區間TA1可以被啟動。Please refer to FIG. 2D below. FIG. 2D illustrates an action waveform diagram of a programming method of a non-volatile memory according to another embodiment of the present invention. In FIG. 2D, a precharge time interval TPRE is set before the programmed time interval TA1. In the precharge time interval TPRE, the voltages on the multiple source lines SSSL, USSL and bit line BL corresponding to the word lines WLo and WLn are raised from the reference voltage to the precharge voltage VCC. Moreover, after a delay time TD after the start of the precharge time interval TPRE, the programmed time interval TA1 can be started.
在另一方面,在預充電時間區間TPRE中,多條源極線SSSL、USSL以及位元線BL上的電壓可同步被提升至預充電電壓VCC。其中,源極線SSSL為選中源極線(對應被選中以進行程式化的記憶胞)而源極線USSL則為未選中源極線(對應未被選中以進行程式化的記憶胞)。在預充電時間區間TPRE中,源極線SSSL的電壓可維持等於預充電電壓VCC,而源極線USSL的電壓則在預充電時間區間TPRE結束前被拉低至參考電壓。位元線BL的電壓在預充電時間區間TPRE中則維持等於預充電電壓VCC。On the other hand, in the precharge time interval TPRE, the voltages on the multiple source lines SSSL, USSL, and the bit line BL can be synchronously raised to the precharge voltage VCC. Among them, the source line SSSL is the selected source line (corresponding to the memory cell selected for programming) and the source line USSL is the unselected source line (corresponding to the memory cell that is not selected for programming) Cell). In the precharge time interval TPRE, the voltage of the source line SSSL can be maintained equal to the precharge voltage VCC, and the voltage of the source line USSL is pulled down to the reference voltage before the precharge time interval TPRE ends. The voltage of the bit line BL remains equal to the precharge voltage VCC during the precharge time interval TPRE.
附帶一提的,在本實施例中,位元線BL可以是遮罩位元線BLMA或程式化位元線BLA,其中遮罩位元線BLMA對應被遮罩且不被進行程式化的記憶胞,程式化位元線BLA則要進行程式化的記憶胞。Incidentally, in this embodiment, the bit line BL can be a masked bit line BLMA or a programmed bit line BLA, where the masked bit line BLMA corresponds to a memory that is masked and not programmed. BLA is a memory cell that needs to be programmed.
接著,在預充電時間區間TPRE結束後,在程式化時間區間TA1中的第一子時間區間T1中,遮罩位元線BLMA的電壓維持等於預充電電壓VCC,程式化位元線BLA的電壓則被拉低為參考電壓。另外,源極線SSSL的電壓可維持等於預充電電壓VCC。並且,在程式化時間區間TA1中的第一子時間區間T1中,程式化字元線WLn的電壓由參考電壓被提升至第一程式化電壓VPG1。Then, after the precharge time interval TPRE ends, in the first sub-time interval T1 in the programming time interval TA1, the voltage of the mask bit line BLMA remains equal to the precharge voltage VCC, and the voltage of the programming bit line BLA It is pulled down as the reference voltage. In addition, the voltage of the source line SSSL can be maintained equal to the precharge voltage VCC. Moreover, in the first sub-time interval T1 in the programming time interval TA1, the voltage of the programming word line WLn is raised from the reference voltage to the first programming voltage VPG1.
在程式化時間區間TA1中的第二子時間區間Tpgm中,程式化字元線WLn以及未選中字元線WLo的電壓同步被拉高,其中未選中字元線WLo的電壓由參考電壓被提高至通過電壓VPASS,程式化字元線WLn的電壓則由第一程式化電壓VPG1被提升至第二程式化電壓VPG2。In the second sub-time interval Tpgm in the stylized time interval TA1, the voltages of the stylized word line WLn and the unselected word line WLo are simultaneously pulled up, and the voltage of the unselected word line WLo is raised by the reference voltage To the pass voltage VPASS, the voltage of the programmed word line WLn is raised from the first programmed voltage VPG1 to the second programmed voltage VPG2.
在本實施例中,圖2D繪示的程式化字元線WLn以及未選中字元線WLo的電壓調整方式,與圖2A的繪示相類似。在本發明其他實施例中,也可將圖2B、圖2C的電壓調整方式,應用在圖2D的實施例中。In this embodiment, the voltage adjustment method of the stylized word line WLn and the unselected word line WLo shown in FIG. 2D is similar to that shown in FIG. 2A. In other embodiments of the present invention, the voltage adjustment methods of FIG. 2B and FIG. 2C can also be applied to the embodiment of FIG. 2D.
請參照圖3,圖3繪示本發明一實施例的非揮發性記憶體的示意圖。非揮發性記憶體300包括控制器310、多個字元線驅動器321~32N以及多條字元線WL1~WLN。字元線WL1~WLN分別耦接一個或多個的記憶胞串MS1~MSN,字元線驅動器321~32N並分別耦接至字元線WL1~WLN。字元線驅動器321~32N分別用以調整字元線WL1~WLN上的電壓。Please refer to FIG. 3. FIG. 3 is a schematic diagram of a non-volatile memory according to an embodiment of the present invention. The
控制器310耦接至字元線驅動器321~32N,並用以操控字元線驅動器321~32N以分別調整字元線WL1~WLN上的電壓。在本實施例中,控制器310可依據圖2A~圖2D的波形來進行字元線驅動器321~32N的控制動作,並完成記憶胞串MS1~MSN的程式化動作。The
在本實施例中,控制器310可以為具運算能力的處理器。或者,控制器310可以是透過硬體描述語言(Hardware Description Language, HDL)或是其他任意本領域具通常知識者所熟知的數位電路的設計方式來進行設計,並透過現場可程式邏輯門陣列(Field Programmable Gate Array, FPGA)、複雜可程式邏輯裝置(Complex Programmable Logic Device, CPLD)或是特殊應用積體電路(Application-specific Integrated Circuit, ASIC)的方式來實現的硬體電路,沒有特別的限制。In this embodiment, the
值得一提的,本發明實施例的非揮發性記憶體可以為二維架構的快閃記憶體或為三維架構的快閃記憶體。以下請分別參照圖4以及圖5,圖4以及圖5分別繪示本發明實施例的非揮發性記憶體的不同實施架構的示意圖。It is worth mentioning that the non-volatile memory in the embodiment of the present invention may be a flash memory with a two-dimensional structure or a flash memory with a three-dimensional structure. Please refer to FIG. 4 and FIG. 5 respectively. FIG. 4 and FIG. 5 respectively illustrate schematic diagrams of different implementation architectures of the non-volatile memory according to the embodiment of the present invention.
在圖4中,非揮發性記憶體400為二維架構的快閃記憶體。非揮發性記憶體400具有多個由電晶體建構的字元線驅動器WDo11、WDo12、WDn-1、WDn、WDn+1、WDo22、WDo21以及源極線驅動器SD1。字元線驅動器WDo11、WDo12用以驅動其他未選中字元線WLo1;字元線驅動器WDo21、WDo22用以驅動其他未選中字元線WLo2;字元線驅動器WDn-1、WDn+1用以分別驅動相鄰未選中字元線Wn-1、Wn+1;字元線驅動器WDn則用以驅動程式化字元線WLn。另外,源極線驅動器SD1用以驅動源極線SSL。另外,非揮發性記憶體400並具有多條位元線BL1~BLM。在圖4中,位元線BL1~BLM與字元線WLo1、WLo2、WLn-1、WLn、WLn+1的交錯位置上,可設置非揮發性記憶胞。In FIG. 4, the
在圖5中,非揮發性記憶體500為三維架構的快閃記憶體。非揮發性記憶體500具有多個由電晶體建構的字元線驅動器WDo11、WDo12、WDn-1、WDn、WDn+1、WDo22、WDo21以及源極線驅動器SD1、SD2。字元線驅動器WDo11、WDo12用以驅動其他未選中字元線WLo1;字元線驅動器WDo21、WDo22用以驅動其他未選中字元線WLo2;字元線驅動器WDn-1、WDn+1用以分別驅動相鄰未選中字元線Wn-1、Wn+1;字元線驅動器WDn則用以驅動程式化字元線WLn。另外,源極線驅動器SD1、SD2分別用以驅動未選中源極線USSL以及選中位元線SSSL。另外,非揮發性記憶體500並具有多條位元線BL11~BL1M以及BL21~BL2M。在圖5中,位元線BL11~BL1M、BL21~BL2M與字元線WLo1、WLo2、WLn-1、WLn、WLn+1的交錯位置上,可設置非揮發性記憶胞。In FIG. 5, the
在本實施方式中,一個字元線驅動器可用以驅動的多個不同的子區塊所共同使用的同一條字元線。以字元線驅動器WDo12為範例,字元線驅動器WDo12可用以驅動其他未選中字元線WLo1,其中其他未選中字元線WLo1由兩個子區塊SBL所共同使用。In this embodiment, one word line driver can be used to drive the same word line commonly used by multiple different sub-blocks. Taking the word line driver WDo12 as an example, the word line driver WDo12 can be used to drive other unselected word lines WLo1, and the other unselected word lines WLo1 are shared by the two sub-blocks SBL.
在本實施方式中,基於三維架構,字元線WLo1、WLo2、WLn-1、WLn、WLn+1可分別依據不同高度層級來進行配置。各字元線WLo1、WLo2、WLn-1、WLn、WLn+1並以水平方向進行延伸。位元線BL11~BL1M、BL21~BL2M則可與字元線WLo1、WLo2、WLn-1、WLn、WLn+1正交的方式來進行配置。In this embodiment, based on the three-dimensional architecture, the word lines WLo1, WLo2, WLn-1, WLn, WLn+1 can be configured according to different height levels, respectively. The word lines WLo1, WLo2, WLn-1, WLn, and WLn+1 extend in the horizontal direction. The bit lines BL11~BL1M, BL21~BL2M can be arranged orthogonally to the word lines WLo1, WLo2, WLn-1, WLn,
以下請參照圖6,圖6繪示本發明實施例的位元線間的寄生電容的示意圖。由圖6的繪示可知,字元線WLo1、WLo2、WLn-1、WLn、WLn+1彼此間具有寄生電容CP1,而字元線WLo1、WLo2、WLn-1、WLn、WLn+1與位元線BLx間則分別具有寄生電容CP2。因此,當字元線WLo1、WLo2、WLn-1、WLn、WLn+1上的電壓以及位元線BLx上的電壓進行變化時,都會因寄生電容CP1、CP2上的耦合效應,而造成程式化位元線WLn上的電壓變化受到干擾。而透過本發明前述實施例的方法,則可克服寄生電容CP1、CP2的影響,加速程式化動作的執行。Please refer to FIG. 6 below. FIG. 6 is a schematic diagram of parasitic capacitance between bit lines according to an embodiment of the present invention. It can be seen from the drawing in FIG. 6 that the word lines WLo1, WLo2, WLn-1, WLn, WLn+1 have parasitic capacitance CP1 between each other, and the word lines WLo1, WLo2, WLn-1, WLn, WLn+1 and the bit There are parasitic capacitance CP2 between the cell lines BLx. Therefore, when the voltage on the word lines WLo1, WLo2, WLn-1, WLn, WLn+1 and the voltage on the bit line BLx change, the coupling effect of the parasitic capacitances CP1 and CP2 will cause programming. The voltage change on the bit line WLn is disturbed. Through the method of the foregoing embodiment of the present invention, the influence of the parasitic capacitances CP1 and CP2 can be overcome, and the execution of the programmed action can be accelerated.
綜上所述,本發明透過使程式化字元線的電壓在由第一程式化電壓提升至第二程式化電壓時,同步提升未選中字元線的電壓至通過電壓。如此一來,程式化字元線以及未選中字元線間的寄生電容所產生的寄生效應可有效被減低,加速非揮發性記憶胞程式化動作的進行。In summary, the present invention raises the voltage of the unselected word line to the pass voltage when the voltage of the programmed word line is raised from the first programmed voltage to the second programmed voltage. In this way, the parasitic effect generated by the parasitic capacitance between the programmed character line and the unselected character line can be effectively reduced, and the program operation of the non-volatile memory cell can be accelerated.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.
S110~S140:非揮發性記憶體的程式化步驟
TA1:程式化時間區間
T1、Tpgm:子時間區間
WLn、WLo、WLo1、WLo2、WLo11、WLo12、WLo21、WLo22、WLn+1、WLn-1、WL1~WLN:字元線
VPG1、VPG2:程式化電壓
TR:轉態時間區間
VPASS:通過電壓
TPRE:預充電時間區間
TD:延遲時間
VCC:預充電電壓
SSL、SSSL、USSL:源極線
BL、BLMA、BLA、BL1~BLM、BL11~BL1M、BL21~BL2M、BLx:位元線
MS1~MSN:記憶胞串
300:非揮發性記憶體
310:控制器
321~32N、WDo11、WDo12、WDn-1、WDn、WDn+1、WDo22、WDo21:字元線驅動器
SD1、SD2:源極線驅動器
500、600:非揮發性記憶體
CP1、CP2:寄生電容
S110~S140: Programming steps for non-volatile memory
TA1: Programmatic time interval
T1, Tpgm: sub-time interval
WLn, WLo, WLo1, WLo2, WLo11, WLo12, WLo21, WLo22, WLn+1, WLn-1, WL1~WLN: character lines
VPG1, VPG2: programmed voltage
TR: Transition time interval
VPASS: Pass voltage
TPRE: Precharge time interval
TD: Delay time
VCC: Precharge voltage
SSL, SSSL, USSL: source line
BL, BLMA, BLA, BL1~BLM, BL11~BL1M, BL21~BL2M, BLx: bit lines
MS1~MSN: memory cell string
300: Non-volatile memory
310:
圖1繪示本發明一實施例的非揮發性記憶體的程式化方法的流程圖。 圖2A~2C分別繪示本發明不同實施方式的非揮發性記憶體的程式化方法的動作波形圖。 圖2D繪示本發明另一實施例的非揮發性記憶體的程式化方法的動作波形圖。 圖3繪示本發明一實施例的非揮發性記憶體的示意圖。 圖4以及圖5分別繪示本發明實施例的非揮發性記憶體的不同實施架構的示意圖。 圖6繪示本發明實施例的位元線間的寄生電容的示意圖。FIG. 1 shows a flowchart of a programming method of non-volatile memory according to an embodiment of the present invention. 2A to 2C respectively show the operation waveform diagrams of the programming method of the non-volatile memory in different embodiments of the present invention. FIG. 2D shows an action waveform diagram of a programming method of non-volatile memory according to another embodiment of the present invention. FIG. 3 is a schematic diagram of a non-volatile memory according to an embodiment of the invention. FIG. 4 and FIG. 5 respectively show schematic diagrams of different implementation architectures of the non-volatile memory according to an embodiment of the present invention. FIG. 6 is a schematic diagram of parasitic capacitance between bit lines according to an embodiment of the present invention.
S110~S140:非揮發性記憶體的程式化步驟 S110~S140: Programming steps for non-volatile memory
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