TW202027243A - Package structure and manufacturing method thereof - Google Patents

Package structure and manufacturing method thereof Download PDF

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Publication number
TW202027243A
TW202027243A TW108100785A TW108100785A TW202027243A TW 202027243 A TW202027243 A TW 202027243A TW 108100785 A TW108100785 A TW 108100785A TW 108100785 A TW108100785 A TW 108100785A TW 202027243 A TW202027243 A TW 202027243A
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Taiwan
Prior art keywords
line segment
wire
die
sealing body
package structure
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TW108100785A
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Chinese (zh)
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江家緯
方立志
范文正
黄建文
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力成科技股份有限公司
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Priority to TW108100785A priority Critical patent/TW202027243A/en
Publication of TW202027243A publication Critical patent/TW202027243A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A package structure including a die, an encapsulant, a redistribution layer, a first conductive connector, and a second conductive connector is provided. The encapsulant encapsulates the die. The encapsulant has a first surface and a second surface opposite the first surface. The redistribution layer is disposed on the first surface of the encapsulant. The first conductive connector is electrically connected to the die and the redistribution layer. The second conductive connector is electrically connected to the redistribution layer. The second conductive connector includes a second end portion and a second wire segment that are connected to each other. The second end portion is exposed to the second surface of the encapsulant. A method of manufacturing a package structure is also provided.

Description

封裝結構及其製造方法Packaging structure and manufacturing method thereof

本發明是有關於一種電子元件及其製造方法，且特別是有關於一種封裝結構及其製造方法。The invention relates to an electronic component and a manufacturing method thereof, and more particularly to a packaging structure and a manufacturing method thereof.

在電子產品及其製造過程中，如何降低的生產成本、具有較佳的細間距（fine pitch）、在配置上可以具有較大的彈性及/或較佳的製作良率等，一直是亟欲解決的課題。In electronic products and their manufacturing processes, how to reduce production costs, have better fine pitches, have greater flexibility in configuration and/or better production yield, etc., has always been an urgent need Problem solved.

本發明提供一種具有較低的生產成本，可以具有較佳的細間距、在配置上可以具有較大的彈性及/或較佳的製作良率的封裝結構及其製造方法。The present invention provides a package structure with lower production cost, better fine pitch, greater flexibility in configuration and/or better manufacturing yield, and a manufacturing method thereof.

本發明提供一種封裝結構，其包括晶粒、密封體、重佈線路層、第一導電連接件以及第二導電連接件。密封體包覆晶粒。密封體具有第一表面及相對於第一表面的第二表面。重佈線路層位於密封體的第一表面上。第一導電連接件電性連接於晶粒與重佈線路層。第二導電連接件電性連接於重佈線路層。第二導電連接件包括彼此相連的第二端部與第二線段。第二端部暴露出密封體的第二表面。The present invention provides a package structure, which includes a die, a sealing body, a redistributed circuit layer, a first conductive connector and a second conductive connector. The sealing body covers the crystal grains. The sealing body has a first surface and a second surface opposite to the first surface. The redistributed circuit layer is located on the first surface of the sealing body. The first conductive connecting member is electrically connected to the die and the redistributed circuit layer. The second conductive connecting member is electrically connected to the redistributed circuit layer. The second conductive connector includes a second end and a second line segment connected to each other. The second end exposes the second surface of the sealing body.

本發明提供一種封裝結構的製造方法。本製造方法至少包括以下步驟。提供載板。配置晶粒於載板上。晶粒具有主動面及相對於主動面的背面，且背面面向載板。形成至少一導線。導線的兩端分別連接至晶粒的主動面或載板。形成密封材料以包覆晶粒及導線。進行薄化製程，以減少密封材料的厚度直到至少移除部分的導線的至少一部分，以形成密封體及至少一導電連接件。導電連接件包括彼此相連的端部與線段，且線段暴露出密封體。形成重佈線路層於密封體上。重佈線路層電性連接於線段。The invention provides a manufacturing method of a package structure. The manufacturing method includes at least the following steps. Provide carrier board. Dispose the die on the carrier board. The die has an active surface and a back surface opposite to the active surface, and the back surface faces the carrier board. At least one wire is formed. The two ends of the wire are respectively connected to the active surface or the carrier board of the die. The sealing material is formed to cover the die and the wires. The thinning process is performed to reduce the thickness of the sealing material until at least a part of at least part of the wire is removed to form a sealing body and at least one conductive connection member. The conductive connector includes an end and a line segment that are connected to each other, and the line segment exposes the sealing body. A re-distributed circuit layer is formed on the sealing body. The redistributed circuit layer is electrically connected to the line segment.

基於上述，本發明的封裝結構及其製造方法可以具有較低的生產成本，可以具有較佳的細間距（fine pitch），在配置上可以具有較大的彈性及/或較佳的製作良率。Based on the above, the package structure and manufacturing method of the present invention can have lower production costs, can have a better fine pitch, and can have greater flexibility in configuration and/or better production yield. .

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

本文所使用之方向用語（例如，上、下、右、左、前、後、頂部、底部）僅作為參看所繪圖式使用且不意欲暗示絕對定向。The directional terms used herein (for example, up, down, right, left, front, back, top, bottom) are only used as a reference drawing and are not intended to imply absolute orientation.

除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。Unless expressly stated otherwise, any method described herein is in no way intended to be interpreted as requiring its steps to be performed in a specific order.

參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。The present invention is explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, size, or size of the layers or regions in the drawings are exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

圖1A至圖1G是依據本發明第一實施例的封裝結構的製造方法的剖視示意圖。1A to 1G are schematic cross-sectional views of the manufacturing method of the package structure according to the first embodiment of the present invention.

請參照圖1A，提供載板10。在一實施例中，載板10可以由矽、聚合物、金屬或其他適宜的材料所構成。換句話說，載板10可以為玻璃基板、矽基板、塑膠基板或金屬板，但本發明不限於此。在一未繪示的實施例中，載板10可以為線路板或具有線路層的基板。其他適宜的基板也可以作為載板10，只要前述的基板能夠承受施行於其上的製程即可。Please refer to FIG. 1A, a carrier board 10 is provided. In one embodiment, the carrier 10 may be made of silicon, polymer, metal or other suitable materials. In other words, the carrier 10 can be a glass substrate, a silicon substrate, a plastic substrate or a metal plate, but the invention is not limited thereto. In an embodiment not shown, the carrier 10 may be a circuit board or a substrate with a circuit layer. Other suitable substrates can also be used as the carrier board 10, as long as the aforementioned substrates can withstand the processes performed on them.

請繼續參照圖1A，配置晶粒110於載板10上。晶粒110具有主動面110a及相對於主動面110a的背面110b，且晶粒110是以其背面110b面向載板10的方式配置於載板10上。晶粒110可以包括連接墊（contact pad）111及暴露出連接墊111的保護層（passivation layer）112，但本發明不限於此。另外，在本實施例中對於晶粒110的種類及配置於載板10上的晶粒110個數並不加以限制。Please continue to refer to FIG. 1A to configure the die 110 on the carrier board 10. The die 110 has an active surface 110 a and a back surface 110 b opposite to the active surface 110 a, and the die 110 is disposed on the carrier board 10 with the back surface 110 b facing the carrier board 10. The die 110 may include a contact pad 111 and a passivation layer 112 exposing the contact pad 111, but the present invention is not limited thereto. In addition, in this embodiment, the type of the die 110 and the number of the die 110 arranged on the carrier board 10 are not limited.

在本實施例中，載板10可以具有晶粒黏著膜（die attach film；DAF）（未繪示），且晶粒110可以貼附於與載板10的晶粒黏著膜上，但本發明不限於此。In this embodiment, the carrier 10 may have a die attach film (DAF) (not shown), and the die 110 may be attached to the die attach film of the carrier 10, but the present invention Not limited to this.

在一實施例中，載板10可以具有離型膜（release film）（未繪示），以於後續的製程中可以使載板10較容易與晶粒110移除，但本發明不限於此。In an embodiment, the carrier 10 may have a release film (not shown), so that the carrier 10 can be easily removed from the die 110 in the subsequent manufacturing process, but the invention is not limited to this .

請參照圖1B，在將晶粒110配置於載板10上之後，於載板10上形成導線120。導線120包括線段123及連接於線段123相對兩端的兩個端部131、142（如：第一端部131及第二端部142）。兩個端部131、142分別連接於不同處。舉例而言，第一端部131可以連接於晶粒110的主動面110a，且第二端部142可以連接於載板10，但本發明不限於此。Please refer to FIG. 1B, after the die 110 is disposed on the carrier board 10, a wire 120 is formed on the carrier board 10. The wire 120 includes a line segment 123 and two end portions 131 and 142 (eg, a first end portion 131 and a second end portion 142) connected to opposite ends of the line segment 123. The two ends 131 and 142 are respectively connected at different places. For example, the first end 131 may be connected to the active surface 110a of the die 110, and the second end 142 may be connected to the carrier board 10, but the invention is not limited thereto.

一般而言，打線機（wire bonder）可以形成的導電連接件包括導線，且由打線機所形成的導線的兩端的截面積大於線段的截面積。舉例而言，導線120可以經由打線機（未繪示）形成。依據設計上的需求，打線機可以是楔型接合（wedge bond）、球形接合（ball bond）或其他適宜的打線機。在一些實施例中，打線機可以包括焊接導線120的自動化裝置。舉例來說，每一條導線120可以藉由例如瓷嘴（capillary）（未繪示）的接合工具饋送，接合工具施加熱、超音波能量、壓力或上述之組合，以將導線120與晶粒110的主動面110a或載板10接合。在一些實施例中，可以依據設計上的需求，經由球形接合、楔型接合或其他適宜的接合方式，以形成每一條導線120的一端（如：第一端部131）與相對於一端的另一端（如：第二端部142）。以圖1B為例，將導線120的一端（如：第一端部131）接合至晶粒110的主動面110a之後，耦接至一端（如：第一端部131）的線段123可以透過打線機的接合工具而被遞送出（deliver out）。然後，打線機的接合工具可以先朝遠離晶粒110的方向移動，再朝接近載板10的方向移動，以形成線段123。之後，形成耦接至線段123且接合至載板10的另一端（如：第二端部142）。Generally speaking, the conductive connector that can be formed by a wire bonder includes a wire, and the cross-sectional area of both ends of the wire formed by the wire bonder is larger than the cross-sectional area of the wire segment. For example, the wire 120 can be formed by a wire bonding machine (not shown). According to design requirements, the wire bonding machine can be a wedge bond, a ball bond or other suitable wire bonding machines. In some embodiments, the wire bonding machine may include an automated device for welding the wires 120. For example, each wire 120 can be fed by a bonding tool such as a capillary (not shown). The bonding tool applies heat, ultrasonic energy, pressure, or a combination of the above to bond the wire 120 and the die 110 The active surface 110a or the carrier board 10 is joined. In some embodiments, ball bonding, wedge bonding, or other suitable bonding methods can be used according to design requirements to form one end (such as the first end 131) of each wire 120 and the other opposite to one end. One end (eg, the second end 142). Taking FIG. 1B as an example, after one end of the wire 120 (such as the first end 131) is bonded to the active surface 110a of the die 110, the wire segment 123 coupled to one end (such as the first end 131) can be wire-bonded The bonding tool of the machine is delivered out. Then, the bonding tool of the wire bonding machine can first move in a direction away from the die 110 and then move in a direction closer to the carrier 10 to form a line segment 123. After that, it is formed to be coupled to the line segment 123 and joined to the other end of the carrier board 10 (eg, the second end 142 ).

在本實施例中，線段123可以包括在晶粒110的主動面110a上方的一直線段部分、從晶粒110的主動面110a上方至未與晶粒110重疊的載板10上方的曲線段部分以及未與晶粒110重疊的載板10上方的另一直線段部分。在一實施例中，每條導線120的高度H1可以介於150微米（micrometer；μm）與400微米之間，而可以使前述在晶粒110的主動面110a上方的一直線段部分基本上垂直於晶粒110的主動面110a，且/或使前述未與晶粒110重疊的載板10上方的另一直線段部分基本上垂直於載板10。In this embodiment, the line segment 123 may include a straight line section above the active surface 110a of the die 110, a curved section from above the active surface 110a of the die 110 to above the carrier board 10 that does not overlap the die 110, and Another straight line section above the carrier board 10 that does not overlap the die 110. In an embodiment, the height H1 of each wire 120 can be between 150 microns (micrometer; μm) and 400 microns, and the aforementioned straight line section above the active surface 110a of the die 110 can be substantially perpendicular to The active surface 110 a of the die 110 and/or the other straight section above the carrier 10 that does not overlap the die 110 is substantially perpendicular to the carrier 10.

在本實施例中，導線120的兩端（如：第一端部131及第二端部142）分別連接至晶粒110的主動面110a及載板10，但本發明不限於此。在其他未繪示的實施例中，可以形成多條導線。部分的導線的兩端可以分別連接至晶粒110的主動面110a，且/或部分的導線的兩端可以分別連接至載板10。唯需至少一導線（如：導線120）的至少一端（如：第一端部131）需連接至晶粒110的主動面110a，且至少一導線（如：導線120）的至少一端（如：第二端部142）需連接至載板10。換句話說，導線的兩端分別連接且固定於晶粒110的主動面110a及/或載板10上，而不會有另一端懸空的狀態。In this embodiment, both ends of the wire 120 (eg, the first end 131 and the second end 142) are respectively connected to the active surface 110a of the die 110 and the carrier board 10, but the invention is not limited thereto. In other unillustrated embodiments, multiple conductive lines may be formed. The two ends of part of the wires may be respectively connected to the active surface 110a of the die 110, and/or the two ends of the part of the wires may be respectively connected to the carrier board 10. Only at least one end (such as the first end 131) of at least one wire (such as the wire 120) needs to be connected to the active surface 110a of the die 110, and at least one end (such as: the wire 120) of at least one wire (such as: the wire 120) The second end 142) needs to be connected to the carrier board 10. In other words, the two ends of the wire are respectively connected and fixed on the active surface 110a of the die 110 and/or the carrier board 10, without the other end being suspended.

請參照圖1C，在形成多條導線120之後，於載板10上形成密封材料165。在一實施例中，密封材料165例如是藉由模塑製程（molding process）或其他適宜的方法將熔融的模塑化合物（molding compound）形成於載板10上。然後，使熔融的模塑化合物冷卻並且固化。在本實施例中，密封材料165包封晶粒110以及導線120。換言之，晶粒110以及導線120並不會露出來，且導線120可以藉由密封材料165而固定。另外，由於，導線120的兩端（如：第一端部131及第二端部142）分別連接且固定於晶粒110的主動面110a及/或載板10上，而不會有懸空的狀態。因此，在形成密封材料165的過程中，導線120的線段123的位置受模流（molding flow）的影響而造成的偏移量可以較小。可以使前述在晶粒110的主動面110a上方的一直線段部分基本上仍可以垂直於晶粒110的主動面110a，且/或使前述未與晶粒110重疊的載板10上方的另一直線段部分基本上仍可以垂直於載板10。1C, after forming a plurality of wires 120, a sealing material 165 is formed on the carrier board 10. In one embodiment, the sealing material 165 is formed by forming a molten molding compound on the carrier 10 by a molding process or other suitable methods. Then, the molten molding compound is cooled and solidified. In this embodiment, the sealing material 165 encapsulates the die 110 and the wire 120. In other words, the die 110 and the wire 120 are not exposed, and the wire 120 can be fixed by the sealing material 165. In addition, since the two ends of the wire 120 (such as the first end 131 and the second end 142) are respectively connected and fixed on the active surface 110a of the die 110 and/or the carrier board 10, there is no dangling status. Therefore, in the process of forming the sealing material 165, the offset of the position of the line segment 123 of the wire 120 affected by the molding flow can be small. The aforementioned straight line section above the active surface 110a of the die 110 can still be substantially perpendicular to the active surface 110a of the die 110, and/or another straight section above the carrier board 10 that does not overlap the die 110 The part can still be substantially perpendicular to the carrier board 10.

請參照圖1D，在形成密封材料165之後，可以進行薄化製程。進行薄化製程例如包括裁切、研磨、蝕刻或其他適宜的方式，但本發明不限於此。薄化製程可以減少密封材料165的厚度，以形成密封體160。一般而言，由打線機所形成的導線（如：導線120）在將非兩端的部分線段移除後可以形成柱形凸塊（stud bump）。換句話說，柱形凸塊可以是另一種形式的導電連接件。舉例而言，薄化製程也可以至少移除其中一導線120的至少一部分，以形成柱形凸塊130、140。1D, after the sealing material 165 is formed, a thinning process can be performed. The thinning process includes cutting, grinding, etching or other suitable methods, but the present invention is not limited thereto. The thinning process can reduce the thickness of the sealing material 165 to form the sealing body 160. Generally speaking, the wire formed by the wire bonding machine (such as the wire 120) can form a stud bump after removing some of the wire segments at the non-ends. In other words, the stud bump can be another form of conductive connection. For example, the thinning process can also remove at least a part of one of the wires 120 to form the stud bumps 130 and 140.

舉例而言，以圖1C至圖1D為例，薄化製程可以移除導線120的線段123的至少一部分，但本發明不限於此。並且，在將導線120的線段123的至少一部分移除之後，可以形成第一柱形凸塊130與第二柱形凸塊140。第一柱形凸塊130可以包括彼此相連的第一端部131與第一線段134。第二柱形凸塊140可以包括彼此相連的第二端部142與第二線段145。第一線段134與第二線段145暴露出密封體160的第一表面160a。也就是說，第一柱形凸塊130的第一線段134可以是前述導線120的線段123在晶粒110的主動面110a上方的一直線段部分的一部分，且第二柱形凸塊140的第二線段145可以是前述導線120的線段123在未與晶粒110重疊的載板10上方的另一直線段部分的一部分。For example, taking FIGS. 1C to 1D as an example, the thinning process can remove at least a part of the line segment 123 of the wire 120, but the present invention is not limited thereto. Moreover, after at least a part of the line segment 123 of the wire 120 is removed, the first stud bump 130 and the second stud bump 140 may be formed. The first stud bump 130 may include a first end 131 and a first line segment 134 connected to each other. The second stud bump 140 may include a second end 142 and a second line segment 145 connected to each other. The first line segment 134 and the second line segment 145 expose the first surface 160 a of the sealing body 160. That is, the first line segment 134 of the first stud bump 130 may be a part of the line segment 123 of the wire 120 above the active surface 110a of the die 110, and the second stud bump 140 The second line segment 145 may be a part of another line segment portion of the line segment 123 of the aforementioned wire 120 above the carrier board 10 that does not overlap the die 110.

在一實施例中，可以對密封體160、第一柱形凸塊130及/或第二柱形凸塊140實施平坦化製程（planarization process），以使密封體160的第一表面160a、第一柱形凸塊130的頂面（即，第一線段134暴露出密封體160的表面）以及第二柱形凸塊140的頂面（即，第二線段145暴露出密封體160的表面）可以齊平或共面（coplanar）。In one embodiment, the sealing body 160, the first stud bump 130 and/or the second stud bump 140 may be subjected to a planarization process, so that the first surface 160a and the second stud bump 140 of the sealing body 160 The top surface of one stud bump 130 (ie, the first line segment 134 exposes the surface of the sealing body 160) and the top surface of the second stud bump 140 (ie, the second line segment 145 exposes the surface of the sealing body 160) ) Can be flush or coplanar.

請參照圖1E，在形成密封體160及柱形凸塊130、140之後，於密封體160的第一表面160a上形成重佈線路層170。重佈線路層170可以與第一柱形凸塊130的第一線段134及/或第二柱形凸塊140的第二線段145電性連接。重佈線路層170可以藉由一般常用的半導體製程所形成，故於此不加以贅述。1E, after the sealing body 160 and the columnar bumps 130 and 140 are formed, a redistributed circuit layer 170 is formed on the first surface 160a of the sealing body 160. The redistributed circuit layer 170 may be electrically connected to the first line segment 134 of the first stud bump 130 and/or the second line segment 145 of the second stud bump 140. The redistributed circuit layer 170 can be formed by a commonly used semiconductor manufacturing process, so it will not be repeated here.

在本實施例中，由於第一柱形凸塊130的第一線段134可以是垂直於晶粒110的主動面110a上方的直線段，且第二柱形凸塊140的第二線段145可以是垂直於載板10的表面上方的另一直線段。因此，可以在密封體160上直接形成重佈線路層170，且使重佈線路層170可以物理連接（physically connected）第一柱形凸塊130的第一線段134以及第二柱形凸塊140的第二線段145。而可以依需求省略在密封體160的第一表面160a上直接配置段面截面積遠大於第一線段134或第二線段145的接墊或端子，或是可以依需求省略在密封體160的第一表面160a上直接配置厚度較大的基板（如：中介板或電路板）。相較於前述的接墊或端子，重佈線路層170在線路設計（layout design）上可以具有較佳的彈性。相較於前述的基板，重佈線路層170可以具有較薄的厚度。In this embodiment, since the first line segment 134 of the first stud bump 130 may be a straight line section perpendicular to the active surface 110a of the die 110, and the second line segment 145 of the second stud bump 140 may be It is another straight line section perpendicular to the upper surface of the carrier board 10. Therefore, the redistributed circuit layer 170 can be directly formed on the sealing body 160, and the redistributed circuit layer 170 can be physically connected to the first line segment 134 and the second stud bump of the first stud bump 130 The second line segment 145 of 140. However, it is possible to omit pads or terminals directly arranged on the first surface 160a of the sealing body 160 with a cross-sectional area much larger than the first line segment 134 or the second line segment 145 according to requirements, or the sealing body 160 can be omitted as required A substrate with a relatively large thickness (such as an interposer or a circuit board) is directly disposed on the first surface 160a. Compared with the aforementioned pads or terminals, the redistributed circuit layer 170 can have better flexibility in the layout design. Compared with the aforementioned substrate, the redistributed circuit layer 170 may have a thinner thickness.

在一實施例中，可以在重佈線路層170上形成多個導電件191。在一實施例中，導電件191藉由凸塊底金屬（under-ball metallurgy；UBM）圖案電性連接至重佈線路層170。在另一實施例中，可以省略凸塊底金屬圖案。在又一實施例中，導電件191例如是焊球（solder ball）或球柵陣列封裝（ball grid array；BGA）。在又另一實施例中，導電件191例如可以藉由植球製程（ball mounting process）以及回焊製程（reflow process）來形成。In an embodiment, a plurality of conductive members 191 may be formed on the redistributed circuit layer 170. In one embodiment, the conductive member 191 is electrically connected to the redistributed circuit layer 170 through an under-ball metallurgy (UBM) pattern. In another embodiment, the under-bump metal pattern may be omitted. In another embodiment, the conductive member 191 is, for example, a solder ball (solder ball) or a ball grid array (BGA) package. In yet another embodiment, the conductive member 191 can be formed by, for example, a ball mounting process and a reflow process.

請參照圖1F，於本實施例中，在形成重佈線路層170之後，可以移除載板10，以暴露出密封體160的第二表面160b及第二柱形凸塊140的第二端部142，但本發明不限於此。1F, in this embodiment, after the redistribution circuit layer 170 is formed, the carrier 10 can be removed to expose the second surface 160b of the sealing body 160 and the second end of the second stud bump 140 Section 142, but the present invention is not limited to this.

在本實施例中，密封體160的第二表面160b及第二柱形凸塊140的第二端部142的底面可以齊平或共面。In this embodiment, the second surface 160b of the sealing body 160 and the bottom surface of the second end 142 of the second cylindrical bump 140 may be flush or coplanar.

在一實施例中，在移除載板10之後，可以暴露出密封體160的第二表面160b、第二柱形凸塊140的第二端部142及晶粒110的背面110b。In one embodiment, after the carrier board 10 is removed, the second surface 160b of the sealing body 160, the second end 142 of the second stud bump 140, and the back surface 110b of the die 110 may be exposed.

在一實施例中，密封體160的第二表面160b、第二柱形凸塊140的第二端部142的底面及晶粒110的背面110b可以齊平或共面。In an embodiment, the second surface 160b of the sealing body 160, the bottom surface of the second end 142 of the second columnar bump 140, and the back surface 110b of the die 110 may be flush or coplanar.

在其他未繪示的實施例中，也可以不移除載板10。舉例而言，若載板10為線路板或具有線路層的基板，也可以不移除載板10。In other embodiments not shown, the carrier board 10 may not be removed. For example, if the carrier board 10 is a circuit board or a substrate with a circuit layer, the carrier board 10 may not be removed.

請參照圖1F，於本實施例中，在形成重佈線路層170之後，可以進行切割製程（dicing process）或切單製程（singulation process），以構成多個封裝結構100，但本發明不限於此。在一實施例中，切割製程可以為包括機械刀片鋸切（mechanical blade sawing）或雷射切割的切割製程。1F, in this embodiment, after the re-layout circuit layer 170 is formed, a dicing process or a singulation process may be performed to form a plurality of package structures 100, but the present invention is not limited to this. In one embodiment, the cutting process may be a cutting process including mechanical blade sawing or laser cutting.

經過上述製程後即可大致上完成本實施例之封裝結構100的製作。請參照圖1G，封裝結構100包括晶粒110、密封體160、重佈線路層170、第一柱形凸塊130以及第二柱形凸塊140。密封體160包覆晶粒110。密封體160具有第一表面160a及相對於第一表面160a的第二表面160b。重佈線路層170位於密封體160的第一表面160a上。第一柱形凸塊130電性連接於晶粒110與重佈線路層170。第二柱形凸塊140電性連接於重佈線路層170。第二柱形凸塊140包括彼此相連的第二端部142與第二線段145，且第二端部142暴露出密封體160的第二表面160b。After the above-mentioned manufacturing process, the manufacturing of the package structure 100 of this embodiment can be substantially completed. 1G, the package structure 100 includes a die 110, a sealing body 160, a redistributed circuit layer 170, a first stud bump 130, and a second stud bump 140. The sealing body 160 covers the die 110. The sealing body 160 has a first surface 160a and a second surface 160b opposite to the first surface 160a. The redistributed circuit layer 170 is located on the first surface 160 a of the sealing body 160. The first stud bump 130 is electrically connected to the die 110 and the redistributed circuit layer 170. The second stud bump 140 is electrically connected to the redistributed circuit layer 170. The second stud bump 140 includes a second end 142 and a second line segment 145 connected to each other, and the second end 142 exposes the second surface 160 b of the sealing body 160.

在本實施例中，第一柱形凸塊130包括彼此相連的第一端部131與第一線段134。第一柱形凸塊130的第一線段134物理連接（physically connected）及/或電性連接（electrically contacted）於重佈線路層170。In this embodiment, the first cylindrical bump 130 includes a first end 131 and a first line segment 134 connected to each other. The first line segment 134 of the first stud bump 130 is physically connected and/or electrically contacted to the redistributed circuit layer 170.

在本實施例中，第一柱形凸塊130的第一線段134基本上延著一方向D1延伸，且前述的方向D1垂直於晶粒110的主動面110a。換句話說，第一柱形凸塊130的第一線段134的外觀基本上可以為直線狀，但本發明不限於此。In this embodiment, the first line segment 134 of the first stud bump 130 extends substantially along a direction D1, and the aforementioned direction D1 is perpendicular to the active surface 110a of the die 110. In other words, the appearance of the first line segment 134 of the first stud bump 130 may be substantially linear, but the present invention is not limited thereto.

在本實施例中，第二柱形凸塊140的第二線段145物理連接及/或電性連接於重佈線路層170。In this embodiment, the second line segment 145 of the second stud bump 140 is physically and/or electrically connected to the redistributed wiring layer 170.

在本實施例中，第二柱形凸塊140的第二線段145、153基本上延著方向D1延伸。換句話說，第二柱形凸塊140的第二線段145的外觀基本上可以為直線狀，但本發明不限於此。In this embodiment, the second line segments 145 and 153 of the second stud bump 140 extend substantially along the direction D1. In other words, the appearance of the second line segment 145 of the second stud bump 140 may be substantially linear, but the present invention is not limited thereto.

在本實施例中，柱形凸塊（如：第一柱形凸塊130及第二柱形凸塊140）可以為藉由打線機所形成。在一般的穿塑孔（through mold via；TMV）技術中，通常是先行成模塑化合物，接著再以雷射裝置以雷射鑽孔（laser drilling）的方式形成通孔（through via），而後再以電鍍、沉積或其他將導電物質填充的類似方式形成導電通孔（conductive via）。相較於上述的穿塑孔技術，本實施例可以省略使用雷射裝置以形成的雷射鑽孔，因此可以降低生產成本。或是，以蝕刻、機械鑽孔（mechanical drill）、雷射鑽孔（laser drill）或其他似的移除方式常會因通孔內所留下的膠渣（smear），而使導電通孔的導電性降低。因此，在一般的穿塑孔技術中常需要使用額外的去膠渣製程（desmear process）。由於在本實施例中，用於與晶粒110電性連接的第一柱形凸塊130的第一端部131可以是在形成密封體160之前已與晶粒110電性連接，因此可以具有較佳的導電性，且可以省略模塑化合物的移除製程以及後續的導電物質填充製程，而可以提升生產率。除此之外，相較於預先成型（preformed）的導電柱，藉由打線機所形成的柱形凸塊（如：第一柱形凸塊130及第二柱形凸塊140）可以具有較低的生產成本，且可以具有較佳的細間距（fine pitch），因此在配置上可以具有較大的彈性。另外，相較於包覆成型的焊料互連件（over-molded solder interconnection），在藉由打線機而形成柱形凸塊（如：第一柱形凸塊130及第二柱形凸塊140）的過程中，可以較容易控制接點的位置，而具有較佳的製作良率。In this embodiment, the stud bumps (such as the first stud bump 130 and the second stud bump 140) can be formed by a wire bonding machine. In the general through mold via (TMV) technology, a molding compound is usually formed first, and then a through via is formed by means of laser drilling with a laser device, and then Then, conductive vias are formed by plating, deposition or other similar methods of filling conductive materials. Compared with the above-mentioned piercing technology, this embodiment can omit the laser drilling formed by using the laser device, so the production cost can be reduced. Or, etching, mechanical drill, laser drill, or other similar removal methods often cause the conductive vias to be damaged due to the smear left in the vias. Decrease in conductivity. Therefore, it is often necessary to use an additional desmear process in general piercing technology. Since in this embodiment, the first end portion 131 of the first stud bump 130 for electrically connecting with the die 110 may be electrically connected with the die 110 before the sealing body 160 is formed, it may have Better conductivity, and the removal process of the molding compound and the subsequent filling process of the conductive material can be omitted, and the productivity can be improved. In addition, compared to preformed conductive pillars, the pillar bumps formed by a wire bonding machine (such as the first pillar bump 130 and the second pillar bump 140) can have a higher Low production cost, and can have a better fine pitch (fine pitch), so the configuration can have greater flexibility. In addition, compared with over-molded solder interconnection, stud bumps (such as the first stud bump 130 and the second stud bump 140) are formed by a wire bonding machine. In the process of ), it is easier to control the position of the contact point, and has a better production yield.

圖2A是依據本發明第二實施例的封裝結構的剖視示意圖。圖2B是依據本發明第二實施例中的某一實施例的封裝結構的部分立體示意圖。第二實施例的封裝結構200類似於第一實施例的封裝結構100，因此採用相同的標號來表示相同或近似的元件，故於此不加以贅述。2A is a schematic cross-sectional view of a package structure according to a second embodiment of the invention. 2B is a partial perspective view of a package structure according to one of the second embodiments of the present invention. The packaging structure 200 of the second embodiment is similar to the packaging structure 100 of the first embodiment, and therefore the same reference numerals are used to denote the same or similar components, and therefore, no further description is given here.

第二實施例的封裝結構200的製造方法可以類似於第一實施例的封裝結構100的製造方法。舉例而言，請參照圖1A至圖1E及圖2A至圖2B，第二實施例的封裝結構200的製造方法可以包括以下步驟。類似於圖1A，提供載板10，且晶粒110以背面110b面向載板10的方式配置於載板10上。類似於圖1B，形成多條導線120、250，其中一條導線120的兩端分別連接至晶粒110的主動面110a或載板10，另一條導線250的兩端分別連接至晶粒110的主動面110a及載板10。類似於圖1C，形成密封材料165以包覆晶粒110及多條導線120、250。類似於圖1D，進行薄化製程，以減少密封材料165的厚度直到至少移除一條導線120的至少一部分，以形成密封體160、第一柱形凸塊130及第二柱形凸塊140。第一柱形凸塊130包括彼此相連的第一端部131與第一線段134。第二柱形凸塊140包括彼此相連的第二端部142與第二線段145。第一線段134與第二線段145暴露出密封體160的第一表面160a。並且，於薄化製程之後，另一條導線250未暴露出密封體160的第一表面160a。類似於圖1E，形成重佈線路層170於密封體160上，其中重佈線路層170電性連接於第一線段134與第二線段145。The manufacturing method of the package structure 200 of the second embodiment may be similar to the manufacturing method of the package structure 100 of the first embodiment. For example, referring to FIGS. 1A to 1E and FIGS. 2A to 2B, the manufacturing method of the package structure 200 of the second embodiment may include the following steps. Similar to FIG. 1A, a carrier board 10 is provided, and the die 110 is disposed on the carrier board 10 in such a manner that the back surface 110 b faces the carrier board 10. Similar to FIG. 1B, a plurality of wires 120 and 250 are formed, and two ends of one wire 120 are respectively connected to the active surface 110a of the die 110 or the carrier board 10, and two ends of the other wire 250 are respectively connected to the active surface of the die 110.面110a and carrier board 10. Similar to FIG. 1C, a sealing material 165 is formed to cover the die 110 and the plurality of wires 120 and 250. Similar to FIG. 1D, a thinning process is performed to reduce the thickness of the sealing material 165 until at least a part of one wire 120 is removed to form the sealing body 160, the first stud bump 130 and the second stud bump 140. The first stud bump 130 includes a first end 131 and a first line segment 134 connected to each other. The second stud bump 140 includes a second end 142 and a second line segment 145 connected to each other. The first line segment 134 and the second line segment 145 expose the first surface 160 a of the sealing body 160. Furthermore, after the thinning process, the other wire 250 does not expose the first surface 160 a of the sealing body 160. Similar to FIG. 1E, a redistributed circuit layer 170 is formed on the sealing body 160, wherein the redistributed circuit layer 170 is electrically connected to the first line segment 134 and the second line segment 145.

在本實施例中，封裝結構200可以更包括導線250。導線250包括線段253及連接於線段253相對兩端的兩個端部251、252。兩個端部251、252中的其中一個端部251連接於晶粒110的主動面110a，且兩個端部251、252中的其中另一個端部252暴露出密封體160的第二表面160b。In this embodiment, the package structure 200 may further include wires 250. The wire 250 includes a line segment 253 and two ends 251 and 252 connected to opposite ends of the line segment 253. One of the two end portions 251, 252 is connected to the active surface 110a of the die 110, and the other end 252 of the two end portions 251, 252 exposes the second surface 160b of the sealing body 160 .

在本實施例中，導線250的形成方式可以相同或相似於前述實施例的導線120。在封裝結構200的製造過程中，導線250的兩端（如：端部251、252）可以分別連接至晶粒110的主動面110a及載板10。In this embodiment, the formation of the wire 250 can be the same or similar to the wire 120 of the previous embodiment. During the manufacturing process of the package structure 200, two ends of the wire 250 (such as the ends 251 and 252) may be connected to the active surface 110a of the die 110 and the carrier 10, respectively.

就封裝結構200的結構上而言，導線250的一端（如：端部251）基本上可以是以朝向晶粒110的主動面110a的方式物理連接及/或電性連接於晶粒110的主動面110a。導線250的另一端（如：端部252）基本上可以是以朝向密封體160的第二表面160b的方式暴露出密封體160的第二表面160b。換句話說，導線250可以不貫穿密封體160。也就是說，線段253的外觀基本上不為直線狀。In terms of the structure of the package structure 200, one end of the wire 250 (such as the end 251) can basically be physically and/or electrically connected to the active surface 110a of the die 110 in a manner that faces the active surface 110a of the die 110.面110a. The other end of the wire 250 (for example, the end 252) may basically expose the second surface 160 b of the sealing body 160 in a manner facing the second surface 160 b of the sealing body 160. In other words, the wire 250 may not penetrate the sealing body 160. In other words, the appearance of the line segment 253 is basically not linear.

在某一實施例中，如圖2B所示，線段253於第一表面160a或第二表面160b上的投影不重疊於第一柱形凸塊130於第一表面160a或第二表面160b上的投影；或是，線段253於第一表面160a或第二表面160b上的投影不重疊於第二柱形凸塊140於第二表面160b或第二表面160b上的投影。換句話說，第一柱形凸塊130與導線250在結構上可以彼此分離；或是，第二柱形凸塊140與導線250在結構上可以彼此分離。前述的配置方式可能可以降低打線過程中，因線段碰撞而造成斷線或端點剝離的可能。In an embodiment, as shown in FIG. 2B, the projection of the line segment 253 on the first surface 160a or the second surface 160b does not overlap with the first cylindrical bump 130 on the first surface 160a or the second surface 160b. Projection; or, the projection of the line segment 253 on the first surface 160a or the second surface 160b does not overlap with the projection of the second cylindrical bump 140 on the second surface 160b or the second surface 160b. In other words, the first stud bump 130 and the wire 250 may be structurally separated from each other; or, the second stud bump 140 and the wire 250 may be structurally separated from each other. The foregoing configuration method may reduce the possibility of wire breakage or endpoint peeling due to line segment collision during wire bonding.

在本實施例中，導線250可以藉由晶粒110的連接墊111而與第一柱形凸塊130電性連接，但本發明不限於此。在其他未繪示的實施例中，導線250與第一柱形凸塊130可以與晶粒110上的不同連接墊分別電性連接。In this embodiment, the wire 250 may be electrically connected to the first stud bump 130 through the connection pad 111 of the die 110, but the invention is not limited thereto. In other embodiments not shown, the wires 250 and the first stud bump 130 may be electrically connected to different connection pads on the die 110 respectively.

在本實施例中，晶粒110可以藉由第一柱形凸塊130電性連接至密封體160的第一表面160a上的電子元件（如：重佈線路層170），晶粒110可以藉由線段253電性連接至密封體160的第二表面160b上的電子元件（未繪示），且位於密封體160的第一表面160a上的電子元件（如：重佈線路層170）及位於密封體160的第二表面160b上的電子元件（未繪示）可以藉由第二柱形凸塊140而電性連接。並且，第一柱形凸塊130、第二柱形凸塊140及導線250可以藉由相同或相似的方式所形成。因此，在上述的條件搭配下，封裝結構200的製造方法可以較為簡單，且可使晶粒110、位於密封體160的第一表面160a上的電子元件（如：重佈線路層170）以及位於密封體160的第二表面160b上的電子元件（未繪示）可以藉由對應的導電連接件（如：第一柱形凸塊130、第二柱形凸塊140及/或導線250）而彼此電性連接。In this embodiment, the die 110 can be electrically connected to the electronic components on the first surface 160a of the sealing body 160 (such as the redistributed circuit layer 170) through the first stud bump 130, and the die 110 can be The line 253 is electrically connected to the electronic components (not shown) on the second surface 160b of the sealing body 160, and the electronic components (such as the redistribution circuit layer 170) on the first surface 160a of the sealing body 160 and The electronic components (not shown) on the second surface 160 b of the sealing body 160 can be electrically connected by the second stud bump 140. Moreover, the first stud bump 130, the second stud bump 140 and the wire 250 can be formed in the same or similar manner. Therefore, under the above-mentioned conditions, the manufacturing method of the package structure 200 can be relatively simple, and the die 110, the electronic components located on the first surface 160a of the sealing body 160 (such as the redistributed circuit layer 170) and the Electronic components (not shown) on the second surface 160b of the sealing body 160 can be formed by corresponding conductive connections (such as the first stud bump 130, the second stud bump 140 and/or the wire 250) Electrically connected to each other.

圖3A是依據本發明第三實施例的封裝結構的剖視示意圖。圖2B是依據本發明第三實施例中的某另一實施例的封裝結構的部分立體示意圖。第三實施例的封裝結構300類似於第一實施例的封裝結構100或類似於第二實施例的封裝結構200，因此採用相同的標號來表示相同或近似的元件，故於此不加以贅述。3A is a schematic cross-sectional view of a package structure according to a third embodiment of the invention. 2B is a partial perspective view of a package structure according to another embodiment of the third embodiment of the present invention. The package structure 300 of the third embodiment is similar to the package structure 100 of the first embodiment or the package structure 200 of the second embodiment, and therefore the same reference numerals are used to denote the same or similar components, and thus will not be repeated here.

第三實施例的封裝結構300的製造方法可以類似於第一實施例的封裝結構100的製造方法。舉例而言，請參照圖1A至圖1E及圖3A至圖3B，第三實施例的封裝結構300的製造方法可以包括以下步驟。類似於圖1A，提供載板10，且晶粒110以背面110b面向載板10的方式配置於載板10上。類似於圖1B，形成多條導線（如類似於導線120的導線及導線250）。一條導線（如類似於導線120的導線）的兩端分別連接至同一晶粒110的主動面110a的不同處；或是，分別連接至一晶粒110的主動面110a及另一晶粒110的主動面110a。另一條導線250的兩端分別連接至晶粒110的主動面110a及載板10。類似於圖1C，形成密封材料165以包覆晶粒110及多條導線（如類似於導線120的導線及導線250）。類似於圖1D，進行薄化製程，以減少密封材料165的厚度直到至少移除一條導線（如類似於導線120的導線）的至少一部分，以形成密封體160及柱形凸塊130。柱形凸塊130包括彼此相連的端部131與線段134。線段134暴露出密封體160的第一表面160a。並且，於薄化製程之後，另一條導線250未暴露出密封體160的第一表面160a。類似於圖1E，形成重佈線路層170於密封體160上，其中重佈線路層170電性連接於線段134。The manufacturing method of the package structure 300 of the third embodiment may be similar to the manufacturing method of the package structure 100 of the first embodiment. For example, referring to FIGS. 1A to 1E and FIGS. 3A to 3B, the manufacturing method of the package structure 300 of the third embodiment may include the following steps. Similar to FIG. 1A, a carrier board 10 is provided, and the die 110 is disposed on the carrier board 10 in such a manner that the back surface 110 b faces the carrier board 10. Similar to FIG. 1B, a plurality of wires (such as wires similar to wires 120 and wires 250) are formed. Two ends of a wire (such as a wire similar to the wire 120) are respectively connected to different places of the active surface 110a of the same die 110; or, respectively connected to the active surface 110a of one die 110 and the other die 110 Active surface 110a. Two ends of the other wire 250 are respectively connected to the active surface 110 a of the die 110 and the carrier 10. Similar to FIG. 1C, a sealing material 165 is formed to cover the die 110 and a plurality of wires (such as the wires similar to the wires 120 and the wires 250). Similar to FIG. 1D, a thinning process is performed to reduce the thickness of the sealing material 165 until at least a part of a wire (such as a wire similar to the wire 120) is removed to form the sealing body 160 and the stud bump 130. The stud bump 130 includes an end 131 and a line segment 134 connected to each other. The line segment 134 exposes the first surface 160 a of the sealing body 160. Furthermore, after the thinning process, the other wire 250 does not expose the first surface 160 a of the sealing body 160. Similar to FIG. 1E, a redistributed circuit layer 170 is formed on the sealing body 160, wherein the redistributed circuit layer 170 is electrically connected to the line segment 134.

在本實施例中，封裝結構200可以更包括導線250。導線250包括線段253及連接於線段253相對兩端的兩個端部251、252。兩個端部251、252中的其中一個端部251連接於晶粒110的主動面110a，且兩個端部251、252中的其中另一個端部252暴露出密封體160的第二表面160b。In this embodiment, the package structure 200 may further include wires 250. The wire 250 includes a line segment 253 and two ends 251 and 252 connected to opposite ends of the line segment 253. One of the two end portions 251, 252 is connected to the active surface 110a of the die 110, and the other end 252 of the two end portions 251, 252 exposes the second surface 160b of the sealing body 160 .

在本實施例中，導線250可以相同或相似於前述實施例的導線250，故於此不加以贅述。In this embodiment, the wire 250 may be the same or similar to the wire 250 of the previous embodiment, so it will not be repeated here.

在某另一實施例中，如圖3B所示，線段253於第一表面160a或第二表面160b上的投影不重疊於柱形凸塊130於第一表面160a或第二表面160b上的投影。換句話說，柱形凸塊130與導線250在結構上可以彼此分離。前述的配置方式可能可以降低打線過程中，因線段碰撞而造成斷線或端點剝離的可能。In another embodiment, as shown in FIG. 3B, the projection of the line segment 253 on the first surface 160a or the second surface 160b does not overlap the projection of the cylindrical bump 130 on the first surface 160a or the second surface 160b . In other words, the stud bump 130 and the wire 250 may be structurally separated from each other. The foregoing configuration method may reduce the possibility of wire breakage or endpoint peeling due to line segment collision during wire bonding.

在本實施例中，導線250可以藉由晶粒110的連接墊111而與柱形凸塊130電性連接，但本發明不限於此。在其他未繪示的實施例中，導線250與柱形凸塊130可以與晶粒110上的不同連接墊分別連性連接。In this embodiment, the wire 250 may be electrically connected to the stud bump 130 through the connection pad 111 of the die 110, but the invention is not limited thereto. In other embodiments not shown, the wires 250 and the stud bumps 130 may be respectively connected to different connection pads on the die 110.

在本實施例中，晶粒110可以藉由柱形凸塊130電性連接至密封體160的第一表面160a上的電子元件（如：重佈線路層170），且晶粒110可以藉由線段253電性連接至密封體160的第二表面160b上的電子元件（未繪示）。並且，柱形凸塊130及導線250可以藉由相同或相似的方式所形成。因此，在上述的條件搭配下，封裝結構300的製造方法可以較為簡單，且可使晶粒110、位於密封體160的第一表面160a上的電子元件（如：重佈線路層170）以及位於密封體160的第二表面160b上的電子元件（未繪示）可以藉由對應的導電連接件（如：柱形凸塊130及/或導線250）而彼此電性連接。In this embodiment, the die 110 can be electrically connected to the electronic components on the first surface 160a of the sealing body 160 (such as the redistributed circuit layer 170) through the pillar bumps 130, and the die 110 can be electrically connected by The line segment 253 is electrically connected to the electronic element (not shown) on the second surface 160 b of the sealing body 160. Moreover, the stud bump 130 and the wire 250 can be formed in the same or similar manner. Therefore, under the above conditions, the manufacturing method of the package structure 300 can be relatively simple, and the die 110, the electronic components (such as the redistributed circuit layer 170) on the first surface 160a of the sealing body 160 and the The electronic components (not shown) on the second surface 160b of the sealing body 160 can be electrically connected to each other through corresponding conductive connections (such as the stud bump 130 and/or the wire 250).

圖4A是依據本發明第四實施例的封裝結構的剖視示意圖。圖4B是依據本發明第四實施例中的某又一實施例的封裝結構的部分立體示意圖。第四實施例的封裝結構400類似於第一實施例的封裝結構100或類似於第二實施例的封裝結構200，因此採用相同的標號來表示相同或近似的元件，故於此不加以贅述。4A is a schematic cross-sectional view of a package structure according to a fourth embodiment of the invention. 4B is a partial three-dimensional schematic diagram of a package structure according to still another embodiment of the fourth embodiment of the present invention. The package structure 400 of the fourth embodiment is similar to the package structure 100 of the first embodiment or the package structure 200 of the second embodiment, and therefore the same reference numerals are used to denote the same or similar components, and therefore will not be repeated here.

第四實施例的封裝結構400的製造方法可以類似於第一實施例的封裝結構100的製造方法。舉例而言，請參照圖1A至圖1E及圖4A至圖4B，第四實施例的封裝結構400的製造方法可以包括以下步驟。類似於圖1A，提供載板10，且晶粒110以背面110b面向載板10的方式配置於載板10上。類似於圖1B，形成多條導線（如類似於導線120的導線及導線250）。一條導線（如類似於導線120的導線）的兩端分別連接載板10的不同處。另一條導線250的兩端分別連接至晶粒110的主動面110a及載板10。類似於圖1C，形成密封材料165以包覆晶粒110及多條導線（如類似於導線120的導線及導線250）。類似於圖1D，進行薄化製程，以減少密封材料165的厚度直到至少移除一條導線（如類似於導線120的導線）的至少一部分，以形成密封體160及柱形凸塊140。柱形凸塊140包括彼此相連的端部142與線段145。線段145暴露出密封體160的第一表面160a。並且，於薄化製程之後，另一條導線250未暴露出密封體160的第一表面160a。類似於圖1E，形成重佈線路層170於密封體160上，其中重佈線路層170電性連接於線段145。The manufacturing method of the package structure 400 of the fourth embodiment may be similar to the manufacturing method of the package structure 100 of the first embodiment. For example, referring to FIGS. 1A to 1E and FIGS. 4A to 4B, the manufacturing method of the package structure 400 of the fourth embodiment may include the following steps. Similar to FIG. 1A, a carrier board 10 is provided, and the die 110 is disposed on the carrier board 10 in such a manner that the back surface 110 b faces the carrier board 10. Similar to FIG. 1B, a plurality of wires (such as wires similar to wires 120 and wires 250) are formed. Two ends of a wire (such as a wire similar to the wire 120) are respectively connected to different parts of the carrier board 10. Two ends of the other wire 250 are respectively connected to the active surface 110 a of the die 110 and the carrier 10. Similar to FIG. 1C, a sealing material 165 is formed to cover the die 110 and a plurality of wires (such as the wires similar to the wires 120 and the wires 250). Similar to FIG. 1D, a thinning process is performed to reduce the thickness of the sealing material 165 until at least a part of a wire (such as a wire similar to the wire 120) is removed to form the sealing body 160 and the stud bump 140. The stud bump 140 includes an end 142 and a line segment 145 connected to each other. The line segment 145 exposes the first surface 160 a of the sealing body 160. Furthermore, after the thinning process, the other wire 250 does not expose the first surface 160 a of the sealing body 160. Similar to FIG. 1E, a redistributed circuit layer 170 is formed on the sealing body 160, wherein the redistributed circuit layer 170 is electrically connected to the line segment 145.

在本實施例中，導線250可以相同或相似於前述實施例的導線250，故於此不加以贅述。In this embodiment, the wire 250 may be the same or similar to the wire 250 of the previous embodiment, so it will not be repeated here.

在本實施例中，如圖4B所示，線段253於第一表面160a或第二表面160b上的投影不重疊於第二柱形凸塊140於第一表面160a或第二表面160b上的投影。換句話說，柱形凸塊140與導線250在結構上可以彼此分離。前述的配置方式可能可以降低打線過程中，因線段碰撞而造成斷線或端點剝離的可能。In this embodiment, as shown in FIG. 4B, the projection of the line segment 253 on the first surface 160a or the second surface 160b does not overlap the projection of the second cylindrical bump 140 on the first surface 160a or the second surface 160b . In other words, the stud bump 140 and the wire 250 may be separated from each other in structure. The foregoing configuration method may reduce the possibility of wire breakage or endpoint peeling due to line segment collision during wire bonding.

在一實施例中，第二柱形凸塊140與導線250可以藉由導電件492而彼此電性連接。導電件492例如為導電膜層，但本發明不限於此。In an embodiment, the second stud bump 140 and the wire 250 may be electrically connected to each other through the conductive member 492. The conductive member 492 is, for example, a conductive film layer, but the present invention is not limited thereto.

在本實施例中，晶粒110可以藉由導線250電性連接至密封體160的第二表面160b上的電子元件（未繪示），且位於密封體160的第一表面160a上的電子元件（如：重佈線路層170）及位於密封體160的第二表面160b上的電子元件（未繪示）可以藉由柱形凸塊140而電性連接。並且，柱形凸塊140及導線250可以藉由相同或相似的方式所形成。因此，在上述的條件搭配下，封裝結構400的製造方法可以較為簡單，且可使晶粒110、位於密封體160的第一表面160a上的電子元件（如：重佈線路層170）以及位於密封體160的第二表面160b上的電子元件（未繪示）可以藉由對應的導電連接件（如：柱形凸塊140及/或導線250）而彼此電性連接。In this embodiment, the die 110 can be electrically connected to the electronic components (not shown) on the second surface 160b of the sealing body 160 through the wires 250, and the electronic components on the first surface 160a of the sealing body 160 (For example, the redistributed circuit layer 170) and the electronic components (not shown) located on the second surface 160b of the sealing body 160 can be electrically connected by the stud bump 140. Moreover, the stud bump 140 and the wire 250 can be formed in the same or similar manner. Therefore, under the above-mentioned conditions, the manufacturing method of the package structure 400 can be relatively simple, and the die 110, the electronic components (such as the redistributed circuit layer 170) on the first surface 160a of the sealing body 160 and the The electronic components (not shown) on the second surface 160b of the sealing body 160 can be electrically connected to each other through corresponding conductive connections (such as the stud bump 140 and/or the wire 250).

圖5是依據本發明第五實施例的封裝結構的剖視示意圖。第五實施例的封裝結構500類似於第一實施例的封裝結構100，因此採用相同的標號來表示相同或近似的元件，故於此不加以贅述。5 is a schematic cross-sectional view of a packaging structure according to a fifth embodiment of the invention. The packaging structure 500 of the fifth embodiment is similar to the packaging structure 100 of the first embodiment, and therefore, the same reference numerals are used to denote the same or similar components, and thus will not be repeated here.

在本實施例中，封裝結構500可以更包括封裝件580。封裝件580可以配置於密封體160的第一表面160a上，且電性連接至重佈線路層170。也就是說，封裝結構500可以是具有封裝疊層（Package on Package；PoP）堆疊排列的半導體封裝。In this embodiment, the package structure 500 may further include a package 580. The package 580 may be disposed on the first surface 160 a of the sealing body 160 and electrically connected to the redistributed circuit layer 170. That is, the package structure 500 may be a semiconductor package with a package on package (PoP) stack arrangement.

在本實施例中，封裝件580可以藉由多個導電件191電性連接至重佈線路層170。導電件191可以包括銅、鎳或其他類型的導電凸塊材料。舉例而言，導電件191可以包括銅柱、位於銅柱上的錫銀合金凸塊、位於銅柱以及錫銀合金凸塊之間的鎳層及/或焊球，但本發明不限於此。In this embodiment, the package 580 can be electrically connected to the redistributed circuit layer 170 through a plurality of conductive members 191. The conductive member 191 may include copper, nickel, or other types of conductive bump materials. For example, the conductive member 191 may include copper pillars, tin-silver alloy bumps on the copper pillars, nickel layers and/or solder balls between the copper pillars and the tin-silver alloy bumps, but the invention is not limited thereto.

在一實施例中，位於密封體160的第一表面160a上的封裝件580及位於密封體160的第二表面160b上的導電件592可以藉由第二柱形凸塊140而電性連接。導電件592可以包括銅柱、位於銅柱上的錫銀合金凸塊、位於銅柱以及錫銀合金凸塊之間的鎳層及/或焊球，但本發明不限於此。In an embodiment, the package 580 on the first surface 160a of the sealing body 160 and the conductive member 592 on the second surface 160b of the sealing body 160 may be electrically connected by the second stud bump 140. The conductive member 592 may include copper pillars, tin-silver alloy bumps on the copper pillars, nickel layers and/or solder balls between the copper pillars and the tin-silver alloy bumps, but the invention is not limited thereto.

圖6是依據本發明第六實施例的封裝結構的剖視示意圖。第六實施例的封裝結構600類似於第二實施例的封裝結構200或第五實施例的封裝結構500，因此採用相同的標號來表示相同或近似的元件，故於此不加以贅述。6 is a schematic cross-sectional view of a packaging structure according to a sixth embodiment of the invention. The packaging structure 600 of the sixth embodiment is similar to the packaging structure 200 of the second embodiment or the packaging structure 500 of the fifth embodiment, and therefore the same reference numerals are used to denote the same or similar components, and thus will not be repeated here.

在本實施例中，封裝結構600可以更包括封裝件680。封裝件680可以配置於密封體160的第二表面160b上，且電性連接至導電件592。也就是說，封裝結構600可以是具有封裝疊層堆疊排列的半導體封裝。In this embodiment, the package structure 600 may further include a package 680. The packaging member 680 may be disposed on the second surface 160 b of the sealing body 160 and electrically connected to the conductive member 592. That is, the package structure 600 may be a semiconductor package having a package stack arrangement.

在本實施例中，封裝件680可以藉由多個導電件592電性連接至第二柱形凸塊140的第二端部142。In this embodiment, the package 680 can be electrically connected to the second end 142 of the second stud bump 140 through a plurality of conductive members 592.

在一實施例中，封裝件680可以藉由多個導電件592電性連接至導線250的端部252（繪示於圖2B）。In an embodiment, the package 680 may be electrically connected to the end 252 of the wire 250 (shown in FIG. 2B) through a plurality of conductive members 592.

綜上所述，本發明的封裝結構及其製造方法可以具有較低的生產成本，可以具有較佳的細間距，在配置上可以具有較大的彈性及/或較佳的製作良率。In summary, the packaging structure and manufacturing method of the present invention can have a lower production cost, can have a better fine pitch, and can have greater flexibility in configuration and/or better production yield.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100、200、300、400、500、600:封裝結構 10:載板 110:晶粒 110a:主動面 110b:背面 111:連接墊 112:保護層 120:導線 123:線段 130:第一柱形凸塊 131:第一端部 134:第一線段 140:第二柱形凸塊 142:第二端部 145:第二線段 250:導線 251、252:端部 253:線段 165:密封材料 160:密封體 160a:第一表面 160b:第二表面 170:重佈線路層 580、680:封裝件 191、492、592:導電件 H1:高度 D1:方向100, 200, 300, 400, 500, 600: package structure 10: Carrier board 110: Die 110a: active side 110b: back 111: connection pad 112: protective layer 120: wire 123: line segment 130: The first cylindrical bump 131: first end 134: first line segment 140: The second cylindrical bump 142: second end 145: second line segment 250: Wire 251, 252: End 253: Line Segment 165: Sealing material 160: Seal body 160a: first surface 160b: second surface 170: Relay line layer 580, 680: Package 191, 492, 592: conductive parts H1: height D1: Direction

圖1A至圖1G是依據本發明第一實施例的封裝結構的製造方法的剖視示意圖。 圖2A是依據本發明第二實施例的封裝結構的剖視示意圖。 圖2B是依據本發明一實施例的封裝結構的部分立體示意圖。 圖3A是依據本發明第三實施例的封裝結構的剖視示意圖。 圖3B是依據本發明另一實施例的封裝結構的部分立體示意圖。 圖4A是依據本發明第四實施例的封裝結構的剖視示意圖。 圖4B是依據本發明又一實施例的封裝結構的部分立體示意圖。 圖5是依據本發明第五實施例的封裝結構的剖視示意圖。 圖6是依據本發明第六實施例的封裝結構的剖視示意圖。1A to 1G are schematic cross-sectional views of the manufacturing method of the package structure according to the first embodiment of the present invention. 2A is a schematic cross-sectional view of a package structure according to a second embodiment of the invention. 2B is a partial perspective view of a package structure according to an embodiment of the invention. 3A is a schematic cross-sectional view of a package structure according to a third embodiment of the invention. 3B is a partial perspective view of a package structure according to another embodiment of the invention. 4A is a schematic cross-sectional view of a package structure according to a fourth embodiment of the invention. 4B is a partial perspective view of a package structure according to another embodiment of the present invention. 5 is a schematic cross-sectional view of a packaging structure according to a fifth embodiment of the invention. 6 is a schematic cross-sectional view of a packaging structure according to a sixth embodiment of the invention.

100:封裝結構 100: Package structure

110:晶粒 110: Die

110a:主動面 110a: active side

110b:背面 110b: back

111:連接墊 111: connection pad

112:保護層 112: protective layer

130:第一柱形凸塊 130: The first cylindrical bump

131:第一端部 131: first end

134:第一線段 134: first line segment

140:第二柱形凸塊 140: The second cylindrical bump

142:第二端部 142: second end

145:第二線段 145: second line segment

160:密封體 160: Seal body

160a:第一表面 160a: first surface

160b:第二表面 160b: second surface

170:重佈線路層 170: Relay line layer

191:導電件 191: conductive parts

D1:方向 D1: Direction

Claims (10)

一種封裝結構，包括： 晶粒； 密封體，包覆所述晶粒且具有第一表面及相對於所述第一表面的第二表面； 重佈線路層，位於所述密封體的所述第一表面上； 第一導電連接件，電性連接於所述晶粒與所述重佈線路層；以及 第二導電連接件，電性連接於所述重佈線路層，其中所述第二導電連接件包括彼此相連的第二端部與第二線段，且所述第二端部暴露出所述密封體的所述第二表面。A packaging structure, including: Grain A sealing body covering the crystal grains and having a first surface and a second surface opposite to the first surface; The re-distributed circuit layer is located on the first surface of the sealing body; A first conductive connector electrically connected to the die and the redistributed circuit layer; and The second conductive connector is electrically connected to the redistributed circuit layer, wherein the second conductive connector includes a second end and a second line segment connected to each other, and the second end exposes the seal The second surface of the body. 如申請專利範圍第1項所述的封裝結構，其中： 所述第一導電連接件為由彼此相連的第一端部與第一線段組成的柱形凸塊（stud bump）； 所述第二導電連接件為由彼此相連的所述第二端部與所述第二線段組成的柱形凸塊； 所述第一線段連接於所述重佈線路層；且 所述第二線段連接於所述重佈線路層。The package structure described in item 1 of the scope of patent application, in which: The first conductive connecting member is a stud bump composed of a first end and a first line segment connected to each other; The second conductive connecting member is a columnar bump composed of the second end and the second line segment that are connected to each other; The first line segment is connected to the redistributed circuit layer; and The second line segment is connected to the redistributed circuit layer. 如申請專利範圍第2項所述的封裝結構，更包括： 導線，包括線段及連接於所述線段相對兩端的兩個端部，其中所述兩個端部的其中之一連接於所述晶粒，且所述兩個端部的其中另一暴露出所述密封體的所述第一表面。The package structure described in item 2 of the scope of patent application includes: The wire includes a wire segment and two ends connected to opposite ends of the wire segment, wherein one of the two ends is connected to the die, and the other of the two ends exposes the The first surface of the sealing body. 如申請專利範圍第3項所述的封裝結構，其中所述線段於所述第一表面或所述第二表面上的投影不重疊於所述第一導電連接件或所述第二導電連接件於所述第一表面或所述第二表面上的投影。The package structure according to item 3 of the scope of patent application, wherein the projection of the line segment on the first surface or the second surface does not overlap the first conductive connection member or the second conductive connection member Projection on the first surface or the second surface. 如申請專利範圍第1項所述的封裝結構，其中： 所述第一導電連接件為由彼此相連的第一端部與第一線段組成的柱形凸塊； 所述第一線段連接於所述重佈線路層； 所述第二導電連接件為導線；且 所述第二線段電性連接於所述第一端部。The package structure described in item 1 of the scope of patent application, in which: The first conductive connecting member is a columnar bump composed of a first end and a first line segment that are connected to each other; The first line segment is connected to the redistributed circuit layer; The second conductive connecting member is a wire; and The second line segment is electrically connected to the first end. 如申請專利範圍第5項所述的封裝結構，其中所述第二線段於所述第一表面或所述第二表面上的投影不重疊於所述第一導電連接件於所述第一表面或所述第二表面上的投影。The package structure according to claim 5, wherein the projection of the second line segment on the first surface or the second surface does not overlap the first conductive connection member on the first surface Or a projection on the second surface. 如申請專利範圍第1項所述的封裝結構，其中： 所述第一導電連接件為導線； 所述第一導電連接件包括彼此相連的第一端部與第一線段； 所述第一線段電性連接於所述第二端部； 所述第二導電連接件為由彼此相連的所述第二端部與所述第二線段組成的柱形凸塊；且 所述第二線段連接於所述重佈線路層。The package structure described in item 1 of the scope of patent application, in which: The first conductive connecting member is a wire; The first conductive connecting member includes a first end and a first line segment that are connected to each other; The first line segment is electrically connected to the second end; The second conductive connecting member is a columnar bump composed of the second end portion and the second line segment that are connected to each other; and The second line segment is connected to the redistributed circuit layer. 如申請專利範圍第7項所述的封裝結構，其中所述第一線段於所述第一表面或所述第二表面上的投影不重疊於所述第二導電連接件於所述第一表面或所述第二表面上的投影。The package structure according to item 7 of the scope of patent application, wherein the projection of the first line segment on the first surface or the second surface does not overlap the second conductive connection member on the first surface The projection on the surface or the second surface. 如申請專利範圍第1項所述的封裝結構，更包括： 封裝件，其中： 所述封裝件配置於所述密封體的所述第一表面上且電性連接至所述重佈線路層；或 所述封裝件配置於所述密封體的所述第二表面上且電性連接至所述第二導電連接件的所述第二端部。The package structure described in item 1 of the scope of patent application includes: Package, where: The package is disposed on the first surface of the sealing body and is electrically connected to the redistributed circuit layer; or The package is disposed on the second surface of the sealing body and is electrically connected to the second end of the second conductive connector. 一種封裝結構的製造方法，包括： 提供載板； 配置晶粒於所述載板上，所述晶粒具有主動面及相對於所述主動面的背面，且所述背面面向所述載板； 形成至少一導線，其中每一所述至少一導線的兩端分別連接至所述晶粒的所述主動面或所述載板； 形成密封材料以包覆所述晶粒及所述至少一導線； 進行薄化製程，以減少所述密封材料的厚度直到至少移除部分的所述至少一導線的至少一部分，以形成密封體及至少一導電連接件，其中所述至少一導電連接件包括彼此相連的端部與線段，且所述線段暴露出所述密封體；以及 形成重佈線路層於密封體上，其中所述重佈線路層電性連接於所述線段。A manufacturing method of a package structure includes: Provide carrier board; Disposing a die on the carrier board, the die having an active surface and a back surface opposite to the active surface, and the back surface faces the carrier board; Forming at least one wire, wherein two ends of each of the at least one wire are respectively connected to the active surface or the carrier plate of the die; Forming a sealing material to cover the die and the at least one wire; A thinning process is performed to reduce the thickness of the sealing material until at least a part of at least a part of the at least one wire is removed to form a sealing body and at least one conductive connection member, wherein the at least one conductive connection member includes interconnections The end and the line segment of, and the line segment exposes the sealing body; and A redistributed circuit layer is formed on the sealing body, wherein the redistributed circuit layer is electrically connected to the line segment.
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