TW202022625A - Data transmission method, slave device with serial peripheral interface and data processing device wherein the data transmission method further includes performing a parallel-to-serial operation - Google Patents

Abstract

A data transmission method for enabling a slave device with a serial peripheral interface to transmit serial data through a serial output terminal under the control of a first serial clock output by a master control device during an enabling period. The method includes using a first logic unit to perform a parallel-to-serial operation according to a system clock and temporarily store a first bit data; using a second logic unit to perform a bit buffer operation over the bit data generated by the parallel-to-serial operation based on a second serial clock to generate a second bit data. The second serial clock is an in-phase signal or an opposite phase signal of the first serial clock. The method further includes using a multiplexer to select outputting the first bit data or the second bit data to the serial output terminal under a control of a mode signal during an enabling period.

Description

Data sending method, slave device with serial peripheral interface and information processing device

The present invention relates to a data transmission method, in particular to a data transmission method for a slave device with a serial peripheral interface.

SPI (serial peripheral interface; serial peripheral interface) is a master-slave synchronous serial communication interface, which has the advantages of fast transmission rate, simple structure, full-duplex communication, etc., so it is widely used in many fields. The existing serial peripheral interface slave devices can use different methods such as master input slave output (MISO) and master output slave input (MOSI) in data transmission.

In addition, the working mode of SPI can be divided into a first mode (including mode 0 and mode 2) and a second mode (including mode 1 and mode 3). In the first mode, because the first bit of data needs to be sent before the first SPI serial clock transmission edge, the first bit of data must be latched; and in the second mode, because the first bit of data The data is pushed out by the first sending edge, so there is no need to latch the first bit of data.

The following table 1 illustrates the difference between SPI mode 0-3:

Table 1

Among them, the push clock of SPI mode 0 is inverse to the SPI serial clock; the push clock of SPI mode 1 is in phase with the SPI serial clock; the push clock of SPI mode 2 is in phase with the SPI serial clock; and the push clock of SPI mode 3 is in phase with the SPI serial clock. The SPI serial clock is inverted.

Taking the traditional MISO transmission method as an example, its structure is shown in Figure 1. A slave device 100 contains a transmission edge detection module 110, a data storage module 120 and a transmission logic module 130; 2 shows a working waveform diagram of one of the slave devices 100 in FIG. 1.

The slave device 100 internally uses a system clock SYSCLK that is several times higher in frequency than the serial clock SCLK of the SPI, and the transmission edge detection module 110 detects the drive edge transition of the serial clock SCLK to obtain a transmission edge signal SIG1. The sending edge signal SIG1 only maintains one clock cycle of the system clock SYSCLK to be active high to drive the transmission logic module 130, thereby shifting the output data DATAOUT of the data storage module 120 by the element and outputting one bit of data To the output.

Figure 2 is a working timing diagram of SPI mode 0. The serial clock SCLK usually only works when SPI is transmitting data (that is, when the pin is selected during the effective period of CS), and usually remains at a fixed level at other times (even if there is a change, you can use the pin to select CS to disable). In addition, the SPI needs to prepare the data DATAOUT when the first serial clock SCLK arrives, and it cannot read the data DATAOUT from the data storage module 120 with the serial clock SCLK to perform the data transmission program.

However, it can be seen from Figure 2 that since the MISO delay time occurs after the sending edge, the time between the sending edge and the sampling edge must be allocated to the MISO delay time and the signal propagation delay time (by the conductive pad (PAD) ) And the circuit board (board)) and MISO setup time, that is, the MISO setup time will be compressed, so that when the frequency of the serial clock SCLK is fixed, the system clock SYSCLK needs a higher frequency, or in the system When the clock SYSCLK is fixed, the serial clock SCLK can only support a lower frequency, that is, this situation will make the frequency ratio of the system clock/serial clock higher.

To solve the above-mentioned problems, a novel data transmission method for serial peripheral interface slave devices is urgently needed in the art.

An object of the present invention is to provide a data transmission method for a slave device of a serial peripheral interface, which can buffer the bit data to be sent to a master device or another slave device by a buffer mechanism, so as to relax the slave device The timing requirements of the relevant logic circuits in the device can be used to correctly complete serial data transmission while reducing the system clock frequency.

Another object of the present invention is to provide a slave device with a serial peripheral interface, which can buffer the bit data to be sent to a master device or another slave device by a buffering mechanism, so as to relax the correlation in the slave device The timing requirements of the logic circuit enable the transmission of serial data to be correctly completed while reducing the system clock frequency.

Another object of the present invention is to provide an information processing device, which can realize at least one peripheral device inside the information processing device through the aforementioned slave device, and the peripheral device can be a memory module or a display.

To achieve the above-mentioned purpose, a data transmission method is proposed, which is implemented by a slave device (Serial Peripheral Interface; SPI). The slave device is based on a master during a consistent performance period. A first serial clock output by the control device is controlled to transmit serial data via a serial output terminal. The data sending method includes the following steps:

A first logic unit is used to perform a parallel-to-serial operation based on a system clock. The parallel-to-serial operation includes: detecting each transmission edge of the first serial clock to obtain a transmission edge signal, and the transmission edge is a A rising edge or a falling edge; according to the control of the sending edge signal, a serial shift element operation is sequentially performed on a plurality of byte data, and an output bit data is sequentially provided by a shift output terminal; and using A first buffer unit is coupled to the shift element output terminal to temporarily store one of the output bit data and provide a first buffer bit data through a first buffer output terminal;

A second logic unit is used to perform a bit buffer operation on the shift element output terminal according to a second serial clock, and a second buffer bit data is sequentially provided through a second buffer output terminal, wherein the second The serial clock is the in-phase or inverted signal of the first serial clock; and

Use a multiplexer to select the first buffer output terminal to be coupled to the serial output terminal or the second buffer output terminal to be coupled to the serial output terminal under the control of a mode signal during the enabling period Line output terminal.

In one embodiment, when the mode signal presents a first mode, the multiplexer selects to couple the first buffer output terminal to the serial output terminal before an initial time in the enabling period , And choosing to couple the second buffer output terminal to the serial output terminal after the initial time.

In one embodiment, when the mode signal presents a second mode, the multiplexer selects to couple the second buffer output terminal to the serial output terminal during the enabling period.

To achieve the above objective, the present invention further provides a slave device with a serial peripheral interface to implement a data transmission method. The slave device has a serial output terminal, a first logic unit, a second logic unit, and The first logic unit and the second logic unit are coupled to a multiplexer to transmit serial data through the serial output terminal under the control of a first serial clock output by a master control device during the unanimous period, The data sending method includes the following steps:

A first logic unit is used to perform a parallel-to-serial operation based on a system clock. The parallel-to-serial operation includes: detecting each transmission edge of the first serial clock to obtain a transmission edge signal, and the transmission edge is a A rising edge or a falling edge; according to the control of the sending edge signal, a serial shift element operation is sequentially performed on a plurality of byte data, and an output bit data is sequentially provided by a shift output terminal; and using A first buffer unit is coupled to the shift element output terminal to temporarily store one of the output bit data and provide a first buffer bit data through a first buffer output terminal;

A second logic unit is used to perform a bit buffer operation on the shift element output terminal according to a second serial clock, and a second buffer bit data is sequentially provided through a second buffer output terminal, wherein the second The serial clock is the in-phase or inverted signal of the first serial clock; and

Use a multiplexer to select the first buffer output terminal to be coupled to the serial output terminal or the second buffer output terminal to be coupled to the serial output terminal under the control of a mode signal during the enabling period Line output terminal.

In one embodiment, when the mode signal presents a first mode, the multiplexer selects to couple the first buffer output terminal to the serial output terminal before an initial time in the enabling period , And choosing to couple the second buffer output terminal to the serial output terminal after the initial time.

In one embodiment, when the mode signal presents a second mode, the multiplexer selects to couple the second buffer output terminal to the serial output terminal during the enabling period.

In addition, the present invention further discloses an information processing device, which has at least one slave device with a sequence of peripheral interfaces as described above.

In order to enable your reviewer to further understand the structure, features and purpose of the present invention, drawings and detailed descriptions of preferred specific embodiments are attached as follows.

Please refer to FIG. 3, which shows a flowchart of an embodiment of the data sending method of the present invention, wherein the data sending method is implemented by a slave device having a serial peripheral interface; the slave device has a system clock SYSCLK; and The slave device transmits serial data via a serial output terminal under the control of a first serial clock output by a master control device during the unanimous period.

As shown in FIG. 3, this embodiment includes the following steps: using a first logic unit to perform a parallel-to-serial operation according to a system clock, and using a shift output terminal to sequentially provide an output bit data, and using a The first buffer unit is coupled to the shift element output terminal to temporarily store one of the output bit data and provide a first buffer bit data through a first buffer output terminal (step S302); use a second The logic unit performs a bit buffer operation on the shift element output terminal according to a second serial clock, and sequentially provides a second buffer bit data via a second buffer output terminal, wherein the second serial clock is The in-phase or inverted signal of the first serial clock (step S304); and using a multiplexer to select the first buffer output terminal to be coupled to the serial under the control of a mode signal during the enabling period Row output terminal, or couple the second buffer output terminal to the serial output terminal (step S306).

In step S302, the parallel-to-serial operation includes: detecting each transmission edge of the first serial clock to obtain a transmission edge signal, wherein the transmission edge is a rising edge or a falling edge; Control to sequentially perform a serial shift element operation on a plurality of byte data, and sequentially provide an output bit data with the shift output terminal; and use the first buffer unit and the shift element to output Terminal coupled to temporarily store one of the output bit data, and provide the first buffer bit data via the first buffer output terminal.

In addition, in step S306, when the mode signal presents a first mode, the multiplexer selects to couple the first buffer output terminal to the serial output before an initial time in the enabling period Terminal, and select to couple the second buffer output terminal to the serial output terminal after the initial time; and when the mode signal presents a second mode, the multiplexer selects during the enable period The second buffer output terminal is coupled to the serial output terminal.

In detail, please refer to FIG. 4 and FIG. 5 at the same time. FIG. 4 is a block diagram of an embodiment of the slave device of the present invention; and FIG. 5 is a working sequence diagram of the slave device of FIG. 4.

As shown in FIG. 4, a slave device 200 includes: a first logic unit composed of a transmission edge detection module 210, a data storage module 220, a transmission logic module 230, and a first buffer unit 240; A second logic unit composed of a second buffer unit 250 and a data output selection module 260; a control gate 270; and a multiplexer 280.

In the first logic unit, the sending edge detection module 210 is used to receive a serial clock SCLK from a master control device having a serial peripheral interface, and detect the sending edge in the serial clock SCLK to obtain a sending edge Signal SIG1, wherein the sending edge can be a rising edge or a falling edge; the transmission logic module 230 is used to perform a byte data DATAOUT provided by the data storage module 220 under the control of the sending edge signal SIG1 The serial shift element is operated to sequentially provide one output bit data BITDATA to a shift output terminal; and the first buffer unit 240 is coupled to the shift output terminal to temporarily store one output bit data BITDATA , And provide a first buffer bit data through a first buffer output terminal.

In the second logic unit, the second buffer unit 250 performs a bit buffer operation on the bit data output from the shift element output terminal according to a second serial clock GSCLK, and passes through a second buffer output terminal Provide a second buffer bit data in sequence, where the second serial clock GSCLK is a clock signal processed by the control gate 270 of the first serial clock SCLK, which is the in-phase or inverted phase of the first serial clock SCLK Signal (determined by a mode signal MODE), and can be enabled or disabled by the enable signal CS; the data output selection module 260 is used to provide a selection signal SEL to drive the multiplexer 280, wherein, when the mode signal MODE When presenting a first mode (mode 0 or 2), the multiplexer 280 selects to couple the first buffer output terminal to all the first buffer output before an initial time in the unison period (the activation period of the enable signal CS) The serial output terminal, and after the initial time, choose to couple the second buffer output terminal to the serial output terminal, thereby providing a serial data signal MISO; when the mode signal MODE presents a second mode ( In mode 1 or 3), the multiplexer 280 selects to couple the second buffer output terminal to the serial output terminal during the enabling period to provide a serial data signal MISO.

In addition, it can be seen from the working sequence diagram of mode 0 in FIG. 5 that, because the present invention moves the BITDATA setup time before the sending edge, compared with the conventional technical solution in FIG. 2, the technical solution of the present invention can be used in sending Provide a generous time ratio between the edge and the sampling edge for the MISO setup time, thereby greatly reducing the frequency ratio of the system clock/serial clock.

In addition, please refer to Table 2 and Table 3, which record two comparison results between the present invention and the original solution (prior art).

Table 2: SYSCLK is the highest frequency of SPI SCLK that 50MHz can support

It can be seen from Table 2 that the same SYSCLK is 50MHz, the original solution supports the highest frequency of SPI SCLK is 6.25MHz, and the present invention supports the highest frequency of SPI SCLK to 16.6MHz.

Table 3: SPI SCLK is 10MHz minimum frequency requirement for SYSCLK

Similarly, the SPI SCLK is 10 MHz, the original solution requires the minimum frequency of SYSCLK to be 100 MHz, and the present invention requires the minimum frequency of SYSCLK to be 33 MHz.

Based on the above description, the present invention further provides an information processing device, which can realize at least one peripheral device inside the information processing device through the aforementioned slave device.

With the design disclosed above, the present invention has the following advantages:

1. With the internal high-frequency system clock, according to the detected SPI serial clock transmission edge, the pre-shift element prepares the data bits to be transmitted, so that the clock edge can be used when the SPI serial clock transmission edge arrives. In the push trigger, the data to be sent is latched and pushed, and output is selected by the selector. In other words, by shifting the preparation delay of sending data to before the arrival of the sending edge, the sending data will only have a PAD/board delay in the process of reaching the receiving end, so that the most relaxed sending data can be established. Time, thereby reducing the frequency ratio of the high-frequency system clock/SPI serial clock.

2. The pre-shift element prepares the data to be sent based on the transmission edge of the SPI serial clock detected by the internal high-frequency system clock. The maximum delay time is 3 cycles of the internal high-frequency system clock. A sending edge interval (that is, period) is greater than 3 internal high-frequency system clock cycles, and the sending edge of the SPI serial clock (converted to the push clock according to the mode) is used to directly latch and push the internal high-frequency system clock. The data to be sent is sufficient to meet the requirements of the establishment time and hold time of the push trigger, and ensure the correct delivery of the data.

3. Use the internal high-frequency system clock to operate the memory module, which solves the problem of reading, preparing, and sending the first bit data when there is no SPI serial clock before the SPI transmission starts, and the memory module does not have SPI serial Manipulation issues during the clock (such as clearing, synchronization, etc.).

4. Add the first bit data latch module to solve the problem that the first bit data of SPI mode 0/2 is sent before the first SPI serial clock transmission edge, and the first bit data latch module only With a trigger, the overhead is minimal.

5. Increase the shift element relay data latch push module to ensure that each bit of the transmitted data is sent out after each SPI serial clock transmission edge, which ensures the retention time of the transmitted data at the receiving end (Hold time), to ensure that the data transmission will not be misaligned, and the shift relay data latch push module only uses one trigger, and the overhead is very small.

6. The selection signal generation module and the data selection module have been added to ensure the correct output of the first bit data of the SPI mode 0/2 and the bit of the shift element relay data, and the selection shift of the SPI mode 1/3 Following the data bit output.

The disclosure in this case is a preferred embodiment, and any partial changes or modifications that are derived from the technical ideas of the case and can be easily inferred by those familiar with the art will not deviate from the scope of the patent right of the case.

To sum up, regardless of the purpose, means and effect of this case, it is shown that it is very different from the conventional technology, and its first invention is suitable for practicality, and it does meet the patent requirements of the invention. Please check it out and grant the patent as soon as possible. Society is for the best prayer.

100: Slave device 110: Sending edge detection module 120: Data storage module 130: Transmission logic module 200: Slave device 210: Sending edge detection module 220: Data storage module 230: Transmission logic module 240: First Buffer unit 250: Second buffer unit 260: Data output selection module 270: Control gate 280: Multiplexer Step S302: Use a first logic unit to perform a parallel-to-serial operation according to a system clock, the parallel-to-serial The operation includes: detecting each sending edge of the first serial clock to obtain a sending edge signal, the sending edge being a rising edge or a falling edge; according to the control of the sending edge signal, a plurality of byte data are sequentially processed Perform a serial shift element operation, and sequentially provide an output bit data with a shift output terminal; and use a first buffer unit to couple with the shift element output terminal to temporarily store one output bit Metadata and provide a first buffer bit data through a first buffer output terminal. Step S304: Use a second logic unit to perform a bit buffer operation on the shift element output terminal according to a second serial clock, and pass A second buffer output terminal sequentially provides a second buffer bit data, wherein the second serial clock is the in-phase or inverted signal of the first serial clock. Step S306: Use a multiplexer to enable During the period, according to the control of a mode signal, it is selected to couple the first buffer output terminal to the serial output terminal, or to couple the second buffer output terminal to the serial output terminal

Fig. 1 shows a schematic diagram of a slave device in the prior art; Fig. 2 shows a working sequence diagram of a slave device in Fig. 1; Fig. 3 shows a flowchart of an embodiment of the data sending method of the present invention; Fig. 4 shows the present invention A block diagram of an embodiment of the slave device; and FIG. 5 shows a working sequence diagram of the slave device of FIG. 4.

Step S302: Use a first logic unit to perform a parallel-to-serial operation according to a system clock. The parallel-to-serial operation includes: detecting each transmission edge of the first serial clock to obtain a transmission edge signal, the transmission The edge is a rising edge or a falling edge; according to the control of the sending edge signal, a serial shift element operation is sequentially performed on a plurality of byte data, and an output bit data is sequentially provided with a shift output terminal And using a first buffer unit coupled to the output end of the shift element to temporarily store one of the output bit data and provide a first buffer bit data via a first buffer output end

Step S304: Use a second logic unit to perform a bit buffer operation on the shift element output terminal according to a second serial clock, and sequentially provide a second buffer bit data through a second buffer output terminal, wherein, The second serial clock is the in-phase or inverted signal of the first serial clock

Step S306: Use a multiplexer to select whether to couple the first buffer output terminal to the serial output terminal or to couple the second buffer output terminal to the serial output terminal under the control of a mode signal during the enabling period The serial output

Claims (7)

A data transmission method is realized by using a slave device with a serial peripheral interface. The slave device is controlled by a first serial clock output by a master control device during a consistent energy period through a serial output terminal To transmit serial data, the data sending method includes the following steps: A first logic unit is used to perform a parallel-to-serial operation according to a system clock, and the parallel-to-serial operation includes: detecting each transmission edge of the first serial clock To obtain a sending edge signal, the sending edge is a rising edge or a falling edge; according to the control of the sending edge signal, a series of shift element operations are sequentially performed on a plurality of byte data, and a shift is performed The output terminal sequentially provides an output bit data; and a first buffer unit is used to couple the shift element output terminal to temporarily store one of the output bit data and provide a second output bit data through a first buffer output terminal A buffer bit data; a second logic unit is used to perform a bit buffer operation on the shift element output terminal according to a second serial clock, and a second buffer bit data is sequentially provided through a second buffer output terminal , Wherein the second serial clock is the in-phase or inverted signal of the first serial clock; and a multiplexer is used to select the first buffer output terminal under the control of a mode signal during the enabling period Is coupled to the serial output terminal, or the second buffer output terminal is coupled to the serial output terminal. The data transmission method according to claim 1, wherein when the mode signal presents a first mode, the multiplexer selects to couple the first buffer output terminal before an initial time in the enabling period To the serial output terminal, and select to couple the second buffer output terminal to the serial output terminal after the initial time. The data transmission method according to claim 1, wherein when the mode signal presents a second mode, the multiplexer selects to couple the second buffer output terminal to the serial port during the enabling period The output terminal. A slave device with a serial peripheral interface for realizing a data transmission method. The slave device has a serial output terminal, a first logic unit, a second logic unit, and the first logic unit and the second logic unit. The logic unit is coupled to a multiplexer to transmit serial data through the serial output terminal under the control of a first serial clock output by a master control device during the unanimous period. The data transmission method includes the following steps: A first logic unit is used to perform a parallel-to-serial operation based on a system clock. The parallel-to-serial operation includes: detecting each transmission edge of the first serial clock to obtain a transmission edge signal, and the transmission edge is a A rising edge or a falling edge; according to the control of the sending edge signal, a serial shift element operation is sequentially performed on a plurality of byte data, and an output bit data is sequentially provided by a shift output terminal; and using A first buffer unit is coupled to the shift element output terminal to temporarily store one of the output bit data and provide a first buffer bit data through a first buffer output terminal; a second logic unit is used according to A second serial clock performs a bit buffer operation on the shift element output terminal, and sequentially provides a second buffer bit data through a second buffer output terminal, wherein the second serial clock is the first The in-phase or inverted signal of the serial clock; and the use of a multiplexer in the enabling period under the control of a mode signal to select whether the first buffer output terminal is coupled to the serial output terminal, or the The second buffer output terminal is coupled to the serial output terminal. The slave device with a sequence of peripheral interfaces according to claim 4, wherein, when the mode signal presents a first mode, the multiplexer selects the first mode before an initial time in the enable period The buffer output terminal is coupled to the serial output terminal, and the second buffer output terminal is selected to be coupled to the serial output terminal after the initial time. The slave device with a serial peripheral interface as described in claim 4, wherein, when the mode signal presents a second mode, the multiplexer selects to couple the second buffer output terminal during the enabling period To the serial output An information processing device, which has at least one slave device with a sequence of peripheral interfaces as described in any one of items 4-6 of the scope of patent application.

Images