TW202020600A - Lookup table configuration method that can reduce the number of multiplexers and information processing device using the same including a preselected vertices generation step, a vertices selection step and an interpolation operation step - Google Patents

Abstract

A lookup table configuration method that can reduce the number of multiplexers is used to perform an n-dimensional linear interpolation operation on multiple interpolation nodes arranged in n dimensions, where n is a positive integer greater than or equal to 3. The method includes the following steps: (1b) using 2^n first-level multiplexer circuits to perform a preselected vertex selection operation on the n dimensionally arranged interpolation nodes to generate 2^n preselected vertices; (2b) performing a vertex selection operation on the 2^n preselected vertices using a second-level multiplexer circuit to generate 2^n vertices; and (3b) performing the n-dimensional linear interpolation operation based on the 2^n vertices.

Description

Lookup table configuration method capable of reducing the number of multiplexers and information processing device using the same

The invention relates to the technical field of interpolation method and look-up table (LUT), in particular to a look-up table configuration method capable of reducing the number of multiplexers and an information processing device using the same.

The method of using interpolation and look-up tables to reduce circuit components and shorten data processing time has been widely used in various electronic products, especially those with display and touch functions. As far as the display technology is concerned, H.264 is the latest digital video compression standard. It introduces different encoding methods to obtain higher compression efficiency. Among them, H.264/SVC adjustable video encoding uses various interpolations. Algorithms to improve the coding efficiency of digital video. The most commonly used interpolation algorithms include: Nearest-neighbor interpolation, Bi-linear interpolation, and double-square interpolation Interpolation (Bi-cubic interpolation).

In order to improve the image processing speed, it is known to configure a look-up table (LUT) and other necessary image processing programs in a Field Programmable Gate Array (FPGA) chip In order to use this FPGA chip as an image processing chip. It is worth noting that the look-up table of the register will load the reference samples pre-calculated by the interpolation algorithm from the external memory when the FPGA chip is activated. In this way, when the image processing chip performs image processing or video encoding on a specific source image, the core processor or controller in the image processing chip can quickly complete the image by means of table lookup Processing or video encoding.

The minimum precision of the H.264 video coding standard is 1/4 pixel (Pixel), that is to say, a pixel can be further divided into 4x4 sub-pixels. Therefore, when one-dimensional interpolation algorithm is used to perform image processing or encoding on an image frame, the same image frame can be divided into 1x16 pixel blocks, and these pixel blocks are regarded as 16 Interpolation prediction unit (PU) is used to continuously perform motion estimation or compensation on these 16 interpolation estimation units during image processing or video encoding. Please refer to FIG. 1, which is a schematic diagram of performing a conventional one-dimensional linear interpolation operation using 17 interpolation nodes. When performing the conventional one-dimensional linear interpolation described above, you must first select (P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16 )The 16 interpolating nodes find a left boundary, and then by (P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17) 16 interpolation nodes find the right boundary.

Please refer to FIG. 2, which illustrates a look-up table architecture for implementing the conventional one-dimensional linear interpolation operation of FIG. 1. As shown in FIG. 2, in order to speed up the setting of the left boundary of an interpolation point, the look-up table architecture is configured with a set of 4-input look-up tables including 16 registers 11 ′ and 15 multiplexers 12 ′ (4 -input LUT)1', called 4 input LUT, and (P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16) 16 The values of the interpolation nodes are temporarily stored in 16 registers 11'. Similarly, in order to speed up the setting of the right boundary of the interpolation point, the look-up table architecture is configured with another group of 4-input look-up tables 1′ (also including 16 registers 11′ and 15 multiplexers 12′ ( Refer to Figure 2). Simply put, the lookup table architecture must use 30 multiplexers 12' to calculate an interpolation value by one-dimensional interpolation.

In addition, please refer to FIG. 3, which is a schematic diagram of performing a conventional two-dimensional linear interpolation operation using 17×17 interpolation nodes. When performing the conventional two-dimensional linear interpolation operation, the values of the four corners (vertices) must be determined by four multiplexer circuits (each containing 255 (=16x16-1) 2 to 1 multiplexers), Including: P(UR), P(DR), P(UL) and P(DL), and then perform a two-dimensional interpolation algorithm (Bi-linear interpolation). Simply put, in this conventional two-dimensional linear interpolation operation, 255 x 4=1020 multiplexers must be used to calculate an interpolated value by two-dimensional interpolation.

However, in addition to the large number and complexity of wires and nets, the aforementioned conventional technical solutions not only occupy a lot of chip area but also increase a lot of chip power consumption.

Therefore, a novel lookup table configuration method is urgently needed in the art.

The main purpose of the present invention is to propose a lookup table configuration method that can reduce the number of multiplexers, which can first perform a preselection of a plurality of odd interpolation nodes and a plurality of even interpolation nodes by a first-level multiplex circuit Boundary search operation, and then perform a boundary point determination operation on a plurality of preselected boundary points by a second-level multiplexing circuit, and then perform a linear interpolation operation on the plurality of determined boundary points to greatly reduce the multiplexer's Quantity, thereby simplifying connection lines (wires, nets).

To achieve the above objective, a lookup table configuration method capable of reducing the number of multiplexers is proposed. It is used to perform a one-dimensional linear interpolation operation on N interpolation nodes, and the N interpolation nodes include N1 Odd nodes and N2 even nodes, N, N1 and N2 are all positive integers and N=N1+N2, the method includes the following steps:

(1) Configure a first lookup table unit including N1-1 first multiplexers to perform a left boundary preselection operation on the N1 odd nodes to obtain a left boundary preselected value;

(2) Configure a second lookup table unit including N2-1 second multiplexers to perform a right boundary preselection operation on the N2 even nodes to obtain a right boundary preselected value;

(3) Configure a third lookup table unit including a third multiplexer to perform a left boundary selection operation on the left boundary preselected value and the right boundary preselected value to obtain a left boundary value;

(4) Configure a fourth lookup table unit including a fourth multiplexer to perform a right boundary selection operation on the left boundary preselected value and the right boundary preselected value to obtain a right boundary value; and

(5) Perform the one-dimensional linear interpolation operation according to the left boundary value and the right boundary value.

In an embodiment, the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer are all 2-to-1 multiplexers.

To achieve the above purpose, another lookup table configuration method that can reduce the number of multiplexers is proposed, which is used to perform a two-dimensional linear interpolation operation on M×N interpolation nodes, the M×N Each column in the interpolation node includes N1 odd nodes and N2 even nodes, and each row in the M×N interpolation nodes includes M1 odd nodes and M2 even nodes, where N, N1, N2, M, M1, and M2 are all positive integers, N=N1+N2, and M=M1+M2; the method includes the following steps:

(1a) Configure a first lookup table unit containing M1×N1-1 first multiplexers to perform a top-left vertex preselection operation on the M1×N1 interpolation nodes to obtain a top-left vertex preselection value;

(2a) Configure a second look-up table unit containing M2×N1-1 second multiplexers to perform an upper-right vertex preselection operation on the M2×N1 interpolated nodes to obtain an upper-right vertex preselection value;

(3a) Configure a third lookup table unit including M1×N2-1 third multiplexers to perform a lower left vertex preselection operation on the M1×N2 interpolation nodes to obtain a lower left vertex preselection value;

(4a) Configure a fourth lookup table unit containing M2×N2-1 fourth multiplexers to perform a pre-selection of the lower right vertex on the M2×N 2 interpolation nodes to obtain a pre-selected value of the lower right vertex ;

(5a) Configure a fifth lookup table unit including three fifth multiplexers to perform an upper left vertex on the upper left vertex preselected value, the upper right vertex preselected value, the lower left vertex preselected value, and the lower right vertex preselected value Select the job to obtain a top left vertex value;

(6a) Configure a sixth lookup table unit including three sixth multiplexers to perform an upper right vertex on the upper left vertex preselected value, the upper right vertex preselected value, the lower left vertex preselected value, and the lower right vertex preselected value Select the job to obtain a top right vertex value;

(7a) Configure a seventh lookup table unit including three seventh multiplexers to perform a lower left vertex on the upper left vertex preselected value, the upper right vertex preselected value, the lower left vertex preselected value, and the lower right vertex preselected value Select the job to obtain a lower left vertex value;

(8a) Configure an eighth lookup table unit including three eighth multiplexers to perform a lower right on the upper left vertex preselected value, the upper right vertex preselected value, the lower left vertex preselected value, and the lower right vertex preselected value Vertex selection operation to obtain a lower right vertex value; and

(9a) Perform the two-dimensional linear interpolation operation according to the upper left vertex value, the upper right vertex value, the lower left vertex value, and the lower right vertex value.

In an embodiment, the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, the fifth multiplexer, the sixth The multiplexer, the seventh multiplexer, and the eighth multiplexer are all 2-to-1 multiplexers.

To achieve the above objective, another lookup table configuration method that can reduce the number of multiplexers is proposed, which is used to perform an n-dimensional linear interpolation operation on a plurality of interpolation nodes arranged in n-dimension, where n is greater than or A positive integer equal to 3, the method includes the following steps:

(1b) Using 2^n first-level multiplexer circuits to perform a preselected vertex selection operation on the plurality of n-dimensionally arranged interpolation nodes to generate 2^n preselected vertices;

(2b) Perform a vertex selection operation on the 2^n preselected vertices using a second layer multiplexer circuit to generate 2^n vertices; and

(3b) Perform the n-dimensional linear interpolation operation according to the 2^n vertices.

In an embodiment, the first multiplexer circuit and the second multiplexer circuit are both composed of a plurality of 2 to 1 multiplexers.

In addition, the present invention further provides an information processing device having a processor to perform a lookup table configuration method that can reduce the number of multiplexers as described above.

In a possible embodiment, the information processing device may be a smart phone or a portable computer.

In order to enable your review committee to further understand the structure, features, objectives, and extreme advantages of the present invention, the drawings and the detailed description of the preferred embodiments are attached as follows.

First embodiment

Please refer to FIGS. 4 and 5 together. FIG. 4 shows a flowchart of an embodiment of a lookup table configuration method that can reduce the number of multiplexers of the present invention, and FIG. 5 shows a method built using the method of FIG. 4. The architecture diagram of the look-up table module includes a storage unit 10, a first look-up table unit 11, a second look-up table unit 12, a third look-up table unit 13, and a fourth look-up table unit 14. The method shown in FIG. 4 is used to perform a one-dimensional linear interpolation operation on N interpolation nodes. The N interpolation nodes include N1 odd nodes and N2 even nodes, and N, N1, and N2 are all positive Integer and N=N1+N2, the method includes the following steps: configuring a first lookup table unit 11 including N1-1 first multiplexers to perform a left boundary preselection operation on the N1 odd nodes to obtain A left boundary preselected value, and a second lookup table unit 12 including N2-1 second multiplexers is configured to perform a right boundary preselected operation on the N2 even nodes to obtain a right boundary preselected value (S1 ); configure a third lookup table unit 13 including a third multiplexer to perform a left boundary selection operation on the left boundary preselected value and the right boundary preselected value to obtain a left boundary value, and the configuration includes a first A fourth lookup table unit 14 of the four multiplexers performs a right boundary selection operation on the left boundary preselected value and the right boundary preselected value to obtain a right boundary value (S2); and according to the left boundary value and the The value of the right boundary is subjected to the one-dimensional linear interpolation operation (S3).

Please also refer to FIG. 1. The method shown in FIG. 4 is mainly used to perform a one-dimensional linear interpolation operation on N interpolation nodes. The N (17) interpolation nodes include N1 (9) odd nodes and N2(8) even-numbered nodes, N, N1, and N2 are all positive integers and N=N1+N2, and the values of the N(17) interpolation nodes are stored in a storage unit 10 (such as a scratchpad) Unit or a static random access memory (SRAM; static random access memory).

When performing step S1, the present invention configures a first lookup table unit 11 including N1-1 (8) first multiplexers to perform a left-boundary preselection operation on the N1 (9) odd nodes to obtain A left boundary preselection value; and configure a second lookup table unit 12 including N2-1 (7) second multiplexers to perform a right boundary preselection operation on the N2 (8) even nodes to obtain a Preselected value for the right boundary. Taking the 17 interpolation nodes shown in FIG. 1 as an example, when step S1 is executed, the present invention is based on (P1, P3, P5, P7, P9, P11, P13, P15, P17). Out the preselected value of the left boundary, and find out the preselected value of the right boundary based on the 8 interpolated nodes (P2, P4, P6, P8, P10, P12, P14, P16), among which the first multiplex Both the multiplexer and the second multiplexer are 2 to 1 multiplexers.

When performing step S2, the present invention configures a third lookup table unit 13 including a third multiplexer to perform a left boundary selection operation on the left boundary preselected value and the right boundary preselected value to obtain a left boundary value ; And configuring a fourth lookup table unit 14 including a fourth multiplexer to perform a right boundary selection operation on the left boundary preselected value and the right boundary preselected value to obtain a right boundary value, wherein the first Both the three multiplexer and the fourth multiplexer are 2 to 1 multiplexers.

When performing step S3, the present invention performs the one-dimensional linear interpolation operation according to the left boundary value and the right boundary value.

As can be seen from the above description, the technical solution of the present invention can greatly reduce the number of multiplexers. Referring to Table 1, the present invention uses a total of 17 multiplexers, the number of which is much lower than the number of multiplexers (30) used in the conventional one-dimensional linear interpolation operation. In fact, in terms of one-dimensional linear interpolation, when N is large, the present invention can save about N/2 multiplexers.

Table 1

Second embodiment

Please refer to FIG. 6 and FIG. 7 together, where FIG. 6 shows a flowchart of another embodiment of a lookup table configuration method for reducing the number of multiplexers of the present invention, which includes: performing four preselected vertex selection operations (step S1a ); Perform four vertex selection operations (step S2a); and perform a two-dimensional linear interpolation operation (step S3a); and FIG. 7 shows the architecture diagram of a lookup table module built using the method of FIG. 6, which includes A storage unit 10a, a first look-up table unit 11a, a second look-up table unit 12a, a third look-up table unit 13a, a fourth look-up table unit 14a, a fifth look-up table unit 15a, a sixth look-up table Unit 16a, a seventh lookup table unit 17a and an eighth lookup table unit 18a.

Please also refer to FIG. 3 and FIG. 6 for a lookup table configuration method that can reduce the number of multiplexers is mainly used to perform a two-dimensional linear interpolation operation on M×N interpolation nodes. The M×N(17×17 ) Each column of the interpolation nodes includes N1(9) odd nodes and N2(8) even nodes, and each row of the M×N interpolation nodes includes M1(9) odd nodes and M2(8) even-numbered nodes, where N, N1, N2, M, M1, and M2 are all positive integers, N=N1+N2, and M=M1+M2. Moreover, the values of the M×N (17×17) interpolation nodes are pre-stored in the storage unit 10a. The storage unit 10a may be an SRAM or a register unit, and is not limited.

When performing step S1a, the present invention is configured with a first lookup table unit 11a including M1×N1-1 first multiplexers to perform a top-left vertex preselection operation on the M1×N1 interpolation nodes to obtain A top left vertex preselection value; a second lookup table unit 12a including M2×N1-1 second multiplexers is configured to perform a top right vertex preselection operation on the M2×N1 interpolation nodes to obtain a top right Vertex preselection value; a third lookup table unit 13a containing M1×N2-1 third multiplexers is configured to perform a lower left vertex preselection operation on the M1×N2 interpolation nodes to obtain a lower left vertex preselection Value; and a fourth lookup table unit 14a including M2×N2-1 fourth multiplexers is configured to perform a lower right vertex preselection operation on the M2×N 2 interpolation nodes to obtain a lower right vertex Preselected value.

When performing step S2a, the present invention is configured with a fifth lookup table unit 15a including three fifth multiplexers to preselect values for the upper left vertex, preselected values for the upper right vertex, preselected values for the lower left vertex, and the lower right vertex A pre-selected value performs an upper-left vertex selection operation to obtain an upper-left vertex value; a sixth lookup table unit 16a including three sixth multiplexers is configured to pre-select the upper-left vertex, the upper-right vertex pre-selected value, and the lower left The vertex preselected value and the lower right vertex preselected value perform an upper right vertex selection operation to obtain an upper right vertex value; a seventh lookup table unit 17a including three seventh multiplexers is configured to preselect the upper left vertex value, The upper right vertex preselected value, the lower left vertex preselected value, and the lower right vertex preselected value perform a lower left vertex selection operation to obtain a lower left vertex value; and an eighth lookup table unit including three eighth multiplexers 18a Perform a lower right vertex selection operation on the upper left vertex preselected value, the upper right vertex preselected value, the lower left vertex preselected value, and the lower right vertex preselected value to obtain a lower right vertex value.

When performing step S3a, the present invention performs the two-dimensional linear interpolation operation according to the upper left vertex value, the upper right vertex value, the lower left vertex value and the lower right vertex value.

It is added that the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, the fifth multiplexer, the sixth multiplexer The multiplexer, the seventh multiplexer, and the eighth multiplexer are all 2-to-1 multiplexers.

As can be seen from the above description, the technical solution of the present invention can greatly reduce the number of multiplexers. Referring to Table 2, the present invention uses a total of 297 multiplexers, the number of which is much lower than the number of multiplexers (1020) used in the conventional two-dimensional linear interpolation operation. In fact, as far as two-dimensional linear interpolation is concerned, assuming M=N, when N is large, the present invention can save about 3N^2/4 multiplexers.

Table 2)

Third embodiment

Although the two embodiments described above are used to implement a one-dimensional linear interpolation algorithm and a two-dimensional linear interpolation algorithm, however, the method of the present invention can also be extended to an n-dimensional (nD) interpolation algorithm .

Please refer to FIG. 8, which is a flowchart of another embodiment of a lookup table configuration method that can reduce the number of multiplexers of the present invention. This embodiment is mainly used to perform an n-dimensional linear interpolation operation on a plurality of interpolation nodes arranged in n dimensions, where n is a positive integer greater than or equal to 3. As shown in FIG. 8, the method includes: using 2^n first-level multiplexer circuits to perform a preselected vertex selection operation on the plurality of n-dimensionally arranged interpolation nodes to generate 2^n preselected vertices ( Step 1b); use a second-level multiplexer circuit to perform a vertex selection operation on the 2^n preselected vertices to generate 2^n vertices (step 2b); and perform the operations according to the 2^n vertices The n-dimensional linear interpolation operation is described (step 3b).

According to the above description, the present invention further provides an information processing device. Please refer to FIG. 9, which illustrates a block diagram of an embodiment of the information processing device of the present invention. As shown in FIG. 9, an information processing device 100 (which may be a smartphone or a portable computer) has a processor 110 and a multiplexer circuit 120, wherein the multiplexer circuit 120 has the two The hierarchical structure, and the processor 110 is used to implement a lookup table configuration method that can reduce the number of multiplexers as described above.

In this way, the above has completely and clearly explained the method and the step composition and technical characteristics of the lookup table configuration method which can reduce the number of multiplexers of the present invention; and, through the above, it can be known that the present invention has the following advantages:

The lookup table configuration method of the present invention can first perform a preselected boundary search operation on a plurality of odd interpolation nodes and a plurality of even interpolation nodes through a first-level multiplex circuit, and then through a second-level multiplex circuit Perform a boundary point determination operation on a plurality of preselected boundary points, and then perform a linear interpolation operation on the plurality of determined boundary points to greatly reduce the number of multiplexers, thereby simplifying connection lines (wires, nets).

It must be emphasized that the aforementioned disclosure in this case is a preferred embodiment, and any part of the modification or modification that originates from the technical idea of this case and is easily inferred by those who are familiar with the skill, does not deviate from the patent of this case. Power category.

In summary, regardless of the purpose, means and effectiveness of this case, it shows that it is very different from the conventional technology, and its first invention is practical and practical, and it does meet the patent requirements of the invention. I urge your review committee to investigate and give the patent to the AirPlus as soon as possible. Society is for supreme prayer.

<Invention> S1: Configure a first lookup table unit to perform a left border preselection operation on the N1 odd nodes to obtain a left border preselection value, and configure a second lookup table unit to perform N2 Even nodes perform a right boundary preselection operation to obtain a right boundary preselection value S2: configure a third lookup table unit to perform a left boundary selection operation on the left boundary preselection value and the right boundary preselection value to obtain a left boundary preselection value Value, and configure a fourth look-up table unit to perform a right boundary selection operation on the left boundary preselected value and the right boundary preselected value to obtain a right boundary value S3: perform one based on the left boundary value and the right boundary value One-dimensional linear interpolation operation S1a: perform four pre-selected vertex selection operations S2a: perform four vertex selection operations S3a: perform a two-dimensional linear interpolation operation S1b: use 2^n first-level multiplexer circuit pairs to n A plurality of interpolation nodes arranged in a dimension perform a preselected vertex selection operation to generate 2^n preselected vertices S2b: use a second-level multiplexer circuit to perform a vertex selection operation on the 2^n preselected vertices to generate 2 ^n vertices S3b: perform an n-dimensional linear interpolation operation according to the 2^n vertices 10: storage unit 11: first lookup table unit 12: second lookup table unit 13: third lookup table unit 14: Four lookup table unit 10a: storage unit 11a: first lookup table unit 12a: second lookup table unit 13a: third lookup table unit 14a: fourth lookup table unit 15a: fifth lookup table unit 16a: sixth lookup table unit 17a: seventh lookup table unit 18a: eighth lookup table unit 100: information processing device 110: processor 120: multiplexer circuit

＜Xizhi＞1’:4 input lookup table 11’: scratchpad 12’: multiplexer

FIG. 1 is a schematic diagram of a conventional one-dimensional linear interpolation operation using 17 interpolation nodes. FIG. 2 illustrates a look-up table architecture for implementing the conventional one-dimensional linear interpolation operation of FIG. 1. FIG. 3 is a schematic diagram of performing a conventional two-dimensional linear interpolation operation with 17×17 interpolation nodes. FIG. 4 shows a flowchart of an embodiment of a lookup table configuration method that can reduce the number of multiplexers of the present invention. FIG. 5 shows an architecture diagram of a look-up table module built using the method of FIG. 4. FIG. 6 shows a flowchart of another embodiment of the method for configuring a lookup table that can reduce the number of multiplexers according to the present invention. FIG. 7 shows an architecture diagram of a look-up table module built using the method of FIG. 6. 8 is a flowchart of another embodiment of a lookup table configuration method that can reduce the number of multiplexers according to the present invention. 9 is a block diagram of an embodiment of the information processing device of the present invention.

S1b: use 2^n first-level multiplexer circuits to perform a preselected vertex selection operation on the plurality of n-dimensionally arranged interpolation nodes to generate 2^n preselected vertices

S2b: Use a second layer multiplexer circuit to perform a vertex selection operation on the 2^n preselected vertices to generate 2^n vertices

S3b: Perform an n-dimensional linear interpolation operation according to the 2^n vertices

Claims (8)

A lookup table configuration method capable of reducing the number of multiplexers is used to perform a one-dimensional linear interpolation operation on N interpolation nodes, the N interpolation nodes including N1 odd nodes and N2 even nodes, N, Both N1 and N2 are positive integers and N=N1+N2. The method includes the following steps: (1) Configure a first lookup table unit including N1-1 first multiplexers to perform the N1 odd-numbered nodes A left border preselection operation to obtain a left border preselection value; (2) configuring a second lookup table unit including N2-1 second multiplexers to perform a right border preselection operation on the N2 even-numbered nodes, To obtain a right border preselected value; (3) configure a third lookup table unit including a third multiplexer to perform a left border select operation on the left border preselected value and the right border preselected value to obtain a left border Boundary value; (4) Configure a fourth lookup table unit including a fourth multiplexer to perform a right boundary selection operation on the left boundary preselected value and the right boundary preselected value to obtain a right boundary value; and ( 5) Perform the one-dimensional linear interpolation operation according to the left boundary value and the right boundary value. A lookup table configuration method capable of reducing the number of multiplexers as described in item 1 of the patent application scope, wherein the first multiplexer, the second multiplexer, the third multiplexer, and all The fourth multiplexers are all 2 to 1 multiplexers. A lookup table configuration method capable of reducing the number of multiplexers to perform a two-dimensional linear interpolation operation on M×N interpolation nodes, each column in the M×N interpolation nodes contains N1 odd numbers Nodes and N2 even nodes, and each row of the M×N interpolation nodes includes M1 odd nodes and M2 even nodes, where N, N1, N2, M, M1, and M2 are all positive integers, N=N1+N2, and M=M1+M2; the method includes the following steps: (1a) Configure a first lookup table unit containing M1×N1-1 first multiplexers to describe the M1×N1 The interpolation node performs a pre-selection of the upper left vertex to obtain a pre-selected value of the upper left vertex; (2a) Configure a second lookup table unit containing M2×N1-1 second multiplexers to match the M2×N1 The interpolation node performs an upper right vertex preselection operation to obtain an upper right vertex preselection value; (3a) Configure a third lookup table unit including M1×N2-1 third multiplexers to interpolate the M1×N2 said The node performs a lower left vertex preselection operation to obtain a lower left vertex preselection value; (4a) configure a fourth lookup table unit including M2×N2-1 fourth multiplexers to match the M2×N2 interpolated nodes Perform a lower right vertex preselection operation to obtain a lower right vertex preselection value; (5a) Configure a fifth lookup table unit including three fifth multiplexers to preselect the upper left vertex value, the upper right vertex preselection value, The lower left vertex preselected value and the lower right vertex preselected value perform an upper left vertex selection operation to obtain an upper left vertex value; (6a) configure a sixth lookup table unit including three sixth multiplexers to the upper left Vertex preselection value, the upper right vertex preselection value, the lower left vertex preselection value, and the lower right vertex preselection value perform an upper right vertex selection operation to obtain an upper right vertex value; (7a) The configuration includes three seventh multiplexers A seventh lookup table unit to perform a lower left vertex selection operation on the upper left vertex preselected value, the upper right vertex preselected value, the lower left vertex preselected value, and the lower right vertex preselected value to obtain a lower left vertex value; (8a) Configure an eighth lookup table unit including three eighth multiplexers to perform a lower right vertex selection operation on the upper left vertex preselected value, the upper right vertex preselected value, the lower left vertex preselected value, and the lower right vertex preselected value To obtain a lower right vertex value; and (9a) perform the two-dimensional linear interpolation operation according to the upper left vertex value, the upper right vertex value, the lower left vertex value and the lower right vertex value. The method for configuring a lookup table that can reduce the number of multiplexers as described in item 3 of the patent application scope, wherein the first multiplexer, the second multiplexer, the third multiplexer, the The fourth multiplexer, the fifth multiplexer, the sixth multiplexer, the seventh multiplexer, and the eighth multiplexer are all 2-to-1 multiplexers. A lookup table configuration method capable of reducing the number of multiplexers to perform an n-dimensional linear interpolation operation on a plurality of interpolation nodes arranged in n-dimension, where n is a positive integer greater than or equal to 3, the method includes the following steps : (1b) use 2^n first-level multiplexer circuits to perform a preselected vertex selection operation on the n-dimensionally arranged interpolated nodes to generate 2^n preselected vertices; (2b) use a first The two-level multiplexer circuit performs a vertex selection operation on the 2^n preselected vertices to generate 2^n vertices; and (3b) performs the n-dimensional linear interpolation operation according to the 2^n vertices. A lookup table configuration method that can reduce the number of multiplexers as described in item 5 of the patent application scope, in which the first multiplexer circuit and the second multiplexer circuit are each multiplexed 2 to 1 multiplexed Composed of devices. An information processing device having a processor to execute a lookup table configuration method that can reduce the number of multiplexers as described in any one of items 1-6 of the patent application range. The information processing device described in item 7 of the patent application scope is a smart phone or a portable computer.

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