TW202018716A - Circuit and method for memory operation - Google Patents

Abstract

A memory device including a plurality of memory units; at least one geometric mean operator coupled to at least two of the plurality of memory units; and a memory state reader coupled to the at least one geometric mean operator to read a memory state of the plurality of memory units.

Description

Circuit and method for memory operation

The present disclosure relates to a circuit configuration and method for reading memory cells of a memory device, and more particularly, to a circuit configuration and method for reading states of a plurality of memory cells of a memory device.

Non-volatile memory devices store information by changing the electrical characteristics of the electronic components that make up the memory unit. For example, flash memory stores information by modifying the threshold voltage of transistors in memory cells. In flash memory, a low threshold voltage in a cell may represent a logic "0", and a high threshold voltage may represent a logic "1". Therefore, in order to retrieve the information stored in the memory unit, it is necessary to query the electrical characteristics of the electronic components in the memory unit. For example, reading the state of the flash memory involves measuring the threshold voltage of the transistor to determine whether it stores "0" or "1".

Nowadays, reading the state of a memory cell can be challenging because the memory cell is designed to store several states. For example, a quad-level cell (quad-level cell) stores 16 different states. In the case where there are multiple states in each cell, the difference between the electrical characteristics associated with each state may be extremely small, and a high-precision reading circuit is required to resolve the difference. In addition, the intrinsic fluctuation or noise of electronic components complicates the determination of the state of the memory. For example, some memory cells include resistance switches that can have overlapping memory state distributions. For example, in a resistive memory, the memory state "0" can be associated with a 10 Ω to 20 Ω distribution, and the memory state "1" can be associated with a 15 Ω to 25 Ω distribution. These overlapping memory state distributions make reading operations unreliable when obtaining overlapping readings (eg 18 Ω) from memory cells. In such cases, it may be necessary to add error correction circuits or perform multiple read operations before the memory state can be accurately identified.

These problems are particularly difficult to solve in non-Neumann computer architectures. In the von Neumann architecture, the storage wall separates the memory from the processing unit. This arrangement allows the use of memory reading techniques, including data correction, filtering, or signal amplification, because data from the memory can be accessed, processed, and then stored in cache memory for later access before operation. However, in a non-von Neumann architecture, there is no storage wall between the memory and the processing unit, and it is difficult to effectively correct errors or buffer the data from the memory device before sending it to the processing unit. In non-von Neumann architectures (such as neural-inspired architectures), the memory unit is placed next to the processing unit to avoid storage bottlenecks. Therefore, there is no opportunity to effectively buffer the data from the memory for the processing unit. In fact, any attempt to buffer or correct the data from the memory for the processing unit can result in a significant delay that secretly damages the operation of the computer.

In addition, the non-von Neumann architecture can benefit from memory types that are challenging to read due to intrinsic fluctuations. For example, the neural-inspired architecture will benefit from the use of resistive switching non-volatile memory elements. These memory elements are difficult to read because they can have the memory state as described above. However, such memory elements need to be employed in neural-inspired architectures to facilitate the execution of neural network operations because the memory elements are similar to biologically-inspired synapses. Therefore, in order to improve the non-von Neumann architecture, it is necessary to develop a reading circuit that can utilize the resistive memory element even if the resistive memory element has overlapping memory state distributions.

The disclosed memory devices, circuits, and methods are related to alleviating or overcoming one or more of the above problems and other problems in the prior art.

An embodiment of the present disclosure relates to a memory device. The memory device includes: a plurality of memory units; at least one geometric average operator, coupled to at least two of the plurality of memory units; and a memory state reader, coupled to at least one geometric average operator Read the memory status of multiple memory cells.

Another aspect of the present disclosure relates to a memory device. The memory device includes a plurality of non-volatile memory cells; a means for generating a first product by multiplying a memory reading current associated with the memory cell; A product that performs a square root operation to generate a first square root; and a member for determining the memory state of the plurality of memory cells based on the memory current corresponding to the first square root.

Another aspect of the present disclosure relates to a method for determining the state of memory. The method includes obtaining a plurality of memory read currents of a plurality of memory cells; determining a product based on the plurality of memory read currents; determining a square root based on the product; and determining the memory based on the square root Body status.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

The present disclosure generally relates to a memory device and a memory circuit that aggregate outputs of a plurality of memory cells to narrow a memory state distribution. Although individual memory elements may have a wider and overlapping memory state distribution, the total output of multiple memory cells may be processed to produce a finer distribution. The disclosed memory device can accurately determine the overall memory state by processing groups of memory cells, even when it may be difficult to distinguish the memory states of individual memory cells. In addition, the processing circuit in the memory device can generate a distribution with no overlap by reducing the distribution spread and filtering the output of the memory cell with a non-normal distribution.

The disclosed memory device and memory reading circuit can also quickly perform required data processing to narrow the data distribution. For example, by using an analog circuit or other dedicated hardware, the memory device may be able to quickly and seamlessly process signals from the memory element to provide data to the reading circuit that determines the state of the memory.

FIG. 1 is a schematic diagram of an exemplary electronic system 100 according to one embodiment. The electronic system 100 may include one of a central processing unit (CPU) 102, a graphic processing unit (GPU) 104, a digital signal processor (DSP) 106, and a multimedia processor 108. Multiple. In addition, the electronic system 100 may include one or more of a sensor 110, an image signal processor (ISP) 112, a display/LCD 114, a navigation module 116, and a connection module 118. As such, the electronic system 100 may include fewer components than all components illustrated in FIG. 1 and/or additional components not illustrated in FIG. 1. In addition, the electronic system 100 may include a neural processing unit (NPU) 120.

In some embodiments, each of the elements of the electronic system 100 and the elements of the electronic system 100 may be connected to each other and may be accommodated in a single device. For example, the CPU 102 can be independently connected to all other elements of the electronic system 100. However, in other embodiments, the electronic system 100 may have specific connections and distribute the elements among multiple devices. For example, in some embodiments, the display/LCD 114 may only be connected to the multimedia processor 108, or the navigation 116 may be located in another device and only connected to the connection module 118.

The CPU 102 may be assembled from electronic circuits configurable to execute instructions of a computer program. For example, the CPU 102 may be configured to perform arithmetic, logic, control, and input/output (I/O) operations specified by a set of instructions. In some embodiments, the CPU 102 may include: an arithmetic logic unit (ALU), which performs arithmetic and logical operations; a processor register, which provides an arithmetic unit to the ALU and stores the result of the ALU operation; and The control unit, by guiding the coordinated operation of the ALU, registers, and other components, combines instruction fetching (fetching from memory) and execution in a coordinated manner. Additionally or alternatively, the CPU 102 may also include one or more microprocessors and peripheral interfaces. In addition, in some embodiments, the CPU 102 may additionally include a multi-core processor, which may be configured to operate in parallel.

The GPU 104 may be designed with electronic circuits that are designed to quickly manipulate and change memory devices to speed up the creation of images in the frame buffer. For example, GPU 104 may include circuits for basic 2D acceleration and frame buffer circuits. In some embodiments, GPU 104 may be analogized to 2D acceleration. In other embodiments, GPU 104 may be configured for texture mapping and drawing polygons, speeding up geometric calculations (eg, rotation), and transforming vertices to different coordinate systems.

The GPU 104 can be installed as a plug-in card in the chipset on the motherboard or in the same chip as the CPU 102. In addition, the GPU 104 may be directly connected to the display/LCD 114.

The DSP 106 may be equipped with a dedicated microprocessor required for digital signal processing operations. For applications that require fast processing without significant delay, DSP 106 can be configured to process data in real time. The DSP 106 may also include circuits to receive digital signals and process them to improve the signals to provide clearer sound, faster data transmission, or sharper images. In some embodiments, the DSP 106 may, for example, receive digitized video, voice, audio, temperature, or position signals from the sensor 110 and perform mathematical functions on the signals. In the described embodiment, the DSP 106 may be designed to perform these mathematical functions quickly.

The multimedia processor 108 may include a microprocessor or system chip designed to provide a digital stream at an immediate rate. In some embodiments, the multimedia processor 108 may be configured to handle including uncompressed video, compressed digital video (eg MPEG-1, MPEG-2, MPEG-4, etc.) and digital audio (eg PCM, AAC, etc.) 'S profile. The microprocessor in the multimedia processor 108 can be optimized to adapt to different media data types, for example, by including a storage interface, a streaming media interface, or a dedicated functional unit to accommodate various digital media transcoders. For example, the multimedia processor 108 may include a vector processing function unit or a SIMD function unit to effectively adapt to these media data types and/or DSP-like features.

The sensor 110 may include a plurality of sensing units that convert external events and send the external events to a processing unit in the electronic system 100, such as the CPU 102 or the DSP 106. The sensor 110 may include one or more of an accelerometer, a gyroscope, a digital compass, a barometer, a fingerprint recognition sensor, an iris (eye) scanning sensor, and/or a facial recognition sensor. In addition, the sensor 110 may include a camera and a microphone. Additionally or alternatively, the sensor 110 may include a GPS unit, a magnetometer, a lux meter, and/or a proximity sensor.

The ISP 112 may include a dedicated processor for image processing. ISP 112 can use SIMD technology or MIMD technology to use parallel computing to increase speed and efficiency. The ISP 112 may be configured to perform image processing tasks, such as increasing system integration on embedded devices. In some embodiments, the ISP 112 may be provided on the same board as other components of the electronic system 100. For example, ISP 112 may be on the same board as CPU 102. However, in other embodiments, the ISP 112 may be a discrete unit. The ISP 112 may include a circuit for controlling a complementary metal-oxide semiconductor (CMOS) sensor. For example, the ISP 112 may include circuits for performing image processing operations such as demosaicing, auto focus, auto exposure, and white balance. In addition, ISP 112 may have noise reduction, filtering, and high-dynamic-range (HDR) capabilities.

The navigation module 116 may include hardware with radar and/or a GPS device to record location. For example, the navigation module 116 may be GPS-based, ground beacon-based, or Distance Measurement Instrument (DMI). The navigation module 116 may be configured to determine the current position of the electronic system 100. Additionally or alternatively, the navigation module 116 may include a data memory device for storing navigation map information. The navigation module 116 may also be integrated into specific components of the electronic system 100. For example, the navigation module 116 may be integrated in the CPU 102. In some embodiments, the navigation module 116 may be connected to the display/LCD 114, and may be connected to the geographic location service via the Internet through, for example, the connection module 118.

The connection module 118 may include an antenna, a microcontroller, and a data port for wireless or wired communication. For example, the connection module 118 may include antennas for 4G LTE, WIFI, and FM communications. Alternatively or additionally, the connection module 118 may include USB communication. In some embodiments, the connection module may include a processor connected via a standard peripheral interface. The standard peripheral interface may include an inter-integrated circuit (I2C) interface and a serial peripheral interface (Serial Peripheral Interface); SPI), Universal Asynchronous Receiver/Transmitter (UART) interface, High-Speed Inter-Chip (HSIC) interface or another suitable standard interface implemented by the processor or otherwise supported . In addition, the connection module 118 may provide a command agreement to provide services associated with the communication architecture required to connect the processing unit (eg, CPU 102 or GPU 104) to external IoT devices, cloud services, and so on.

The NPU 120 may include an electronic platform for brain-inspired computing (ie, neuromorphic computing). The NPU 120 may include an artificial intelligence acceleration chip and be associated with a software API to interact with the platform. In some embodiments, NPU 120 may be configured to execute machine learning algorithms, such as deep learning. In addition, the NPU 120 may be configured to perform image and sound processing operations, including speech recognition. In some embodiments, NPU 120 may be constructed with a microprocessor dedicated to speed up machine learning algorithms. For example, NPU 120 may be configured to operate according to predictive models such as artificial neural networks or random forests.

FIG. 2 is a schematic diagram of an exemplary memory device 200. In some embodiments, the memory device 200 may be part of the electronic system 100. For example, the memory device 200 may constitute the NPU 120. However, in other embodiments, the memory device 200 may be an independent unit. The memory device 200 may include multiple neurons 202, multiple synapses 204, and multiple communication channels 206.

The exemplary memory device 200 in FIG. 2 includes nine neurons 202, including neuron 202(a), neuron 202(b), neuron 202(c)..., neuron 202(g). However, other embodiments with more neurons 202 or fewer neurons 202 are also possible. The neuron 202 may be designed with a digital or analog circuit for analog neural operation. In some embodiments, the neuron 202 may include a CMOS digital circuit configured to perform logical operations of the neuron state and start function. Alternatively, the neuron 202 may include an analog circuit including a MOS transistor or a BJT transistor, which is configured to operate in a sub-threshold state for nonlinear voltage-controlled conductance.

Synapse 204 includes synapse 204(a), synapse 204(b), ..., synapse 204(f), and may include electronic components with variable resistance. However, other embodiments with more synapses 204 or fewer synapses 204 are also possible. Synapse 204 may be coupled with neuron 202, and the synapse itself is coupled. In some embodiments, the synapse 204 may include a resistive random-access memory (ReRAM) memory grid or array as further described with respect to FIGS. 3A-3C. In other embodiments, the synapse 204 may include a flash memory grid, where the transistors in the flash memory cell are controlled by the gate voltage to act as a resistance. In the described embodiment, the transistor channel may be configured to act as a gate-controllable resistor.

The communication channel 206 includes a channel 206(a), a channel 206(b), ..., and a channel 206(d), and may include parallel and/or serial data buses. However, other embodiments with more communication channels 206 or fewer communication channels 206 are also possible. In some embodiments, the communication channel 206 may include a dedicated bus between the elements of the memory device 200. For example, the communication channel 206(a) may include a dedicated communication line between the neuron 202(a) and the neuron 202(b).

In some embodiments, each of the neurons 202 may be coupled to multiple synapses 204. For example, although FIG. 2 shows that each of the neurons 202 is coupled to four synapses 204, each of the neurons 202 may be coupled to one hundred or more synapses 204. In these embodiments, synapse 204 may be directly or indirectly coupled to neuron 202. For example, the synapse 204(a) may be directly connected to the neuron 202(a) using on-chip interconnects. However, in other embodiments, synapse 204(a) may be coupled to neuron 202(a) via a buffer circuit, other synapse, or filter circuit.

Since the neuron 202 may have more electronic components than the synapse 204, the area occupied by the neuron 202 may be larger than the area occupied by the synapse. For example, in some embodiments, the neuron 202 may occupy an area that is at least one hundred times larger than the synapse. Each synapse 204 may be a single electronic element, such as a ReRAM cell or flash memory cell, and each of the neurons 202 may include several transistors, current sources, and capacitors. For example, each of the neurons 202 can occupy an area of 8000 F ² or more, and each of the synapses 204 can occupy an area of 30 F ² or less, where F ² is the minimum representing the technology node Resolvable feature's relative area unit.

As depicted in FIG. 2, the memory device 200 may place neurons 202 and associated synapses 204 close to each other, such that between the memory unit (eg, synapse 204) and the processing unit (eg, neuron 202) The length of any communication line is minimized. However, the communication channel 206 may additionally use a longer communication line to connect the processing unit.

FIG. 3A is a schematic diagram of the first exemplary memory circuit 310. The memory circuit 310 includes a row decoder 312, a ReRAM register 316, a data register 318, and a column decoder 320 connected to the ReRAM array 314. In addition, the memory circuit 310 includes an amplifier 324 and a data bus 322 both connected to the column decoder 320.

The ReRAM array 314 contains non-volatile random access memory cells that work by changing the resistance on solid materials. For example, the ReRAM array 314 may be assembled with multiple memristors. Alternatively, the ReRAM array may include a grid or crossbar with resistive elements with controllable resistance. For example, the ReRAM array may include a 3D Xpoint array. Alternatively or additionally, the ReRAM array 314 may be designed with dedicated MOSFET transistors in a 1T1R structure, where the transistors provide exclusive access to ReRAM cells.

The row decoder 312 includes switches and/or multiplexers to establish electrical communication with multiple bit lines to read data from and write data to memory cells in the ReRAM array 314. The row decoder 312 also includes an amplifier to drive voltage or current during read and write operations. For example, the row decoder 312 may include a sense amplifier and a write amplifier.

The ReRAM register 316 contains hardware configured to store information about the state of the ReRAM array 314. Individual bits in the ReRAM register 316 may be implicitly or explicitly read and/or written by machine code instructions executing on the ReRAM array 314. For example, in some embodiments, the ReRAM register may store a set of processor status flag bits.

The data register 318 includes a storage buffer that stores data transferred to and from the ReRAM array 314. The data register 318 allows immediate access to reusable information. For example, the data register 318 may contain a copy of the specified memory cell in the ReRAM array 314 as specified by the row decoder 312. In some embodiments, using the data register 318 as part of the memory circuit 310 may allow the neuron 202 to access frequently needed information faster by avoiding the required configuration of the decoder.

The column decoder 320 includes a circuit for establishing an electrical connection between the memory cell in the ReRAM array 314 and other reading elements, such as an amplifier 324 or a data bus 322. The column decoder 320 may operate using an analog method or a digital method or a partial analog and partial digital method. The column decoder 320 may include one or more multiplexers, and is directly connected to the data register 318.

In order to read the data and send the data to, for example, the neuron 202, the memory circuit 310 may include an amplifier 324 and a data bus 322. In the exemplary memory circuit 310, the amplifier 324 includes an operational amplifier configured as a driver and a data bus 322 coupled to the processing unit.

FIG. 3B is a schematic diagram of the second exemplary memory circuit 330. The memory circuit 330 includes elements similar to the memory circuit 310, including a row decoder 312, a ReRAM register 316, a data register 318, and a column decoder 320 connected to the ReRAM array 314. However, the memory circuit 330 implements different memory control using the address counter 344, the control circuit 348, and the parallel-series converter 332 and the parallel-series converter 346. In addition, in the memory circuit 330, the elements may have different arrangements. As shown in FIG. 3B, the data register 318 in the memory circuit 330 is connected to the row decoder 312 instead of the ReRAM array 314 and the column decoder 320.

The address counter 344 includes hardware that calculates the required row and column addresses based on instructions from the control circuit 348. In some embodiments, the address counter 344 includes programmable and/or fixed offset registers for column addresses and/or row addresses that exist respectively. For example, as shown in FIG. 3B, the address counter 344 may be connected to the column decoder 320 and the row decoder 312. The address counter 344 may include a multiplexer that generates a high frequency control signal based on the low frequency input signal provided by the control circuit 348.

The parallel-series converter 332 and the parallel-series converter 346 may include flip-flops, latches, and/or temporary registers that transmit bits from the input terminal in parallel or in series according to a clock signal. For example, if there is a high signal (logic 1) at the input of the flip-flop of the parallel-to-serial converter 332 or the parallel-to-serial converter 346, then when the clock edge transitions from low to high, the Logic 1 is transmitted to the parallel terminal. In addition, the parallel-series converter 332 and the parallel-series converter 346 may be coupled with a serial input (SI) or a serial output (SO) to convert data that can then be transmitted to the processing unit.

The control circuit 348 is a digital circuit that manages the flow of data to and from the ReRAM array 314. In some embodiments, the control circuit 348 may be equipped with a microcontroller or a processing unit. In addition, the control circuit 348 may provide means for determining the state of the memory based on the measured memory current. In addition, the control circuit 348 can communicate with other components via data pins, such as chip select (CS) pins, clock signal (SCK) pins, interrupt (HOLD) pins, and write protection (Write protect; WP) pin.

FIG. 3C is a schematic diagram of a third exemplary memory circuit 360. FIG. The memory circuit 360 represents a possible implementation of the ReRAM memory cells in the ReRAM array 314. Although not shown in FIG. 3C, similar to the memory circuit 310, the memory circuit 360 may further include an amplifier 324, a column decoder 320, and a row decoder 312, and other electronic devices for reading the ReRAM array 314. The memory circuit 360 may also include a selection transistor 348 used by the decoder to arrange the connections between the memory cells.

In some embodiments, the memory cells in the ReRAM array 314 in the memory circuit 360 are designed with a cross-over network. For example, ReRAM array 314 may include nanowire crossbar switches connected to CMOS lines for reading and writing. Nanowire crossbar switches have controllable resistivity. However, as shown in FIG. 3C, the memory cells in the ReRAM array 314 may also be assembled with a resistance switch (A), a vertical transistor (B), a series-resistance switch (C), or a complementary resistance switch (D) . Alternative implementations using different types of electronic components with adjustable resistivity can also be used to construct ReRAM array 314.

4 is a schematic diagram of a first exemplary memory reading configuration 500. The memory read configuration 500 is used to process readings from multiple memory cells and to determine the overall state of the memory cells. Grouping or clustering the memory readings in the memory reading configuration 500 facilitates the determination of the memory state, because the deviation of the memory state distribution and the maximum/minimum (max/min) ratio are reduced. That is, summing the currents from multiple memory cells produces a finer distribution of memory states, which facilitates the determination of the memory state by the reading circuit. The memory read configuration 500 enables clustering and processing of multiple memory units in a series of stages. In each stage of the memory reading configuration 500, the current of the memory cell is processed to obtain a composite reading with less variation and easily discernable state. The current distribution generated using the memory read configuration 500 will be discussed in more detail with respect to FIGS. 7A-7C.

The memory reading configuration 500 includes: a memory unit 502(a), ..., a memory unit 502(z), collectively referred to herein as a memory unit 502; a filter circuit 505(a), ..., a filter circuit 505(z) In this document, they are collectively referred to as the filter circuit 505; and the first-stage geometric average operator 511(a), ..., the first-stage geometric average operator 511(y), which are collectively referred to herein as the geometric average operator 511. In addition, the memory reading configuration 500 includes: a second-level geometric average operator 517(a), ..., a second-level geometric average operator 517(x), collectively referred to herein as a geometric average operator 517; and a third-level Geometric average operand 523. As shown in FIG. 4, the geometric average operator may have a first-level geometric average operator 511, a second-level geometric average operator 517 and a third-level geometric average operator 523 in a cascaded manner. Although only three levels are shown in FIG. 4, the memory read configuration 500 may include more levels. In the described embodiment, the last stage may be directly or indirectly coupled to the reading circuit. In addition, the memory read configuration 500 includes: a first-stage buffer circuit 512(a), ..., a first-stage buffer circuit 512(y), collectively referred to herein as a first-stage buffer circuit 512; a second-stage buffer The second-stage buffer circuit 518(a),..., The second-stage buffer circuit 518(x) are collectively referred to herein as the second-stage buffer circuit 518; and the third-stage buffer circuit 524. The buffer circuits can be organized in a similar manner. In addition, the memory reading configuration 500 includes a data bus 530 and a reading circuit 540.

The text used to refer to individual elements in FIG. 4 (such as (x), (y), or (z)) does not specify the number of elements in the memory read configuration 500 or the total number of elements. Alternatively, it is a variable marker indicating the variable element number and the variable total element number. For example, the text (z) used to refer to the memory unit 502(z) does not indicate that the memory unit 502(z) is the 26th memory unit. Alternatively, (z) is a variable flag that can indicate any integer value. Therefore, the memory unit 502(z) is any one of the memory units 502, and the number of the memory units 502 in the memory reading configuration 500 is any integer. Similarly, the words (y) and (x) used to refer to, for example, the first-level geometric averaging operator 511(y) or the second-level geometric averaging operator 517(x) are also variable marks, which do not indicate or limit The number of components or the total number of components.

However, in some embodiments, text used as variable markers may have an algebraic relationship. For example, in some embodiments, the variable label satisfies the relationship (z)>(y)>(x). In other embodiments, the variable label satisfies the relationship z = 2(y) = 4(x). In other embodiments, the variable label satisfies the relationship (z)>(y)+1>(x)+1.

In addition, in some embodiments, different computing stages may be pooled in a single stage performing equivalent functions. Although FIG. 4 illustrates the discrete first-level geometric average operator 511, the second-level geometric average operator 517, and the third-level geometric average operator 523, these stages may be implemented in a single stage. For example, the aggregation stage 519 can perform the same functions as the first-level geometric average operator 511 and the second-level geometric average operator 517. In the described embodiment, the aggregation stage 519 may include circuitry to perform aggregation operations. For example, in some embodiments, the aggregation stage 519 includes a CMOS square root circuit configured in a loop, where the output of the CMOS square root circuit is routed back to an input of the CMOS square root circuit to perform the square root calculation of the product of at least two Times. Alternatively, the aggregation stage 519 includes logic circuits to perform the equivalent operations of the first-stage geometric average operator 511 and the second-stage geometric average operator 517 in a single stage. In addition, the aggregation stage 519 may include a processor configured to calculate cascaded geometric averages to effectively perform the functions of the first-level geometric average operator and the second-level geometric average operator.

The memory unit 502 may include different types of memory. For example, the memory unit 502 may include a ReRAM memory unit, such as the ReRAM memory unit previously described with respect to FIG. 3C. In addition, the memory cell 502 may be part of the ReRAM array 314. However, in other embodiments, the memory unit 502 may be a flash memory, PCM, MRAM, or FeRAM memory unit. For example, the memory cell 502 may include a flash memory cell in which the transistor is controlled by the gate voltage to act as a resistance.

In some embodiments, the memory unit 502 is coupled with the filter circuit 505. The filter circuit 505 includes hardware for processing the analog signal received from the memory unit 502. Filtering circuits may be needed when readings from memory cells are subject to noise sources (such as clock signals) that can confuse readings, or when preprocessing data will facilitate subsequent clustering of data. Various filtering techniques may be included in the memory reading configuration 500.

As shown in FIG. 4, the filter circuit 505 includes a band-pass filter (collectively referred to as a band-pass filter 504) and a min/max filter (min/max filter (referred to collectively as a min/max filter 506 )). These circuits may be configured to filter noise from undesired frequencies or cut off from the outlier memory unit 502. For example, the band-pass filter 504 may be configured to filter out high frequencies that are not characteristic of reading memory cells. In addition, when the output of the memory unit 502 is expected to be within a range (for example, 1 uA to 10 uA), if one of the memory units 502 outputs a current that exceeds the range (for example, 100 uA), it indicates that The memory unit has failed. To avoid outlier readings from compromising the accuracy of memory state determination, min/max filter 506 may truncate or remove any unexpected values. In this example, the unexpected current of 100 uA can be truncated to a maximum expected current of 10 uA. Alternatively, the min/max filter 506 may completely remove the unexpected current.

The first-stage geometric averaging operator 511 includes hardware for processing signals from the memory unit 502. As shown in FIG. 4, the first-stage geometric averaging operator 511 is coupled to the memory unit 502 via the filter circuit 505. However, in other embodiments, the first-level geometric averaging operator 511 may be directly connected to the memory unit 502. In addition, in some embodiments, the first-level geometric averaging operator 511 may be directly or indirectly coupled to the reading circuit 540 so that the memory reading configuration 500 includes only a single-level geometric reading operator.

In some embodiments, geometric averaging operators 511 are organized in subsets, each subset being coupled to a specific group of memory cells 502. For example, referring to FIG. 4, the first subset of geometric averaging operators 511 includes the two top geometric averaging operators 511(a) and geometric averaging operators 511(a+1). Therefore, the first subset of geometric mean operator 511 will be coupled to include memory unit 502(a), memory unit 502(a+1), memory unit 502(a+2), and memory unit 502(a +3) A memory cell group and is configured to process readings from the memory cell group. Similarly, the second subset of geometric averaging operators 511 contains the bottom two geometric averaging operators 511(y) and geometric averaging operators 511(y-1). Thus, the second subset of geometric mean operator 511 is coupled to include memory unit 502(z), memory unit 502(z-1), memory unit 502(z-2), and memory unit 502(z -3) a memory cell group, and is configured to process readings from the memory cell group. Depending on the number of memory cells 502 to be processed, an additional subset of geometric averaging operators 511 may be added to the memory read configuration 500.

By organizing the geometric mean operator 511 in a subset manner, the memory reading configuration 500 can identify areas in the memory having poor characteristics, and disconnect the area by disabling a subset of the geometric mean operator 511. For example, in some storage chips, poorly performing memory cells 502 are concentrated in a specific area of the chip. The described organization of the subset of geometric averaging operators 511 will allow isolation of defective areas and improve memory reading accuracy.

。可替代地，每個第一級幾何平均運算元511可接收來自多個記憶體單元502的電流，且在單次計算操作中將所述電流合併在一起。舉例來說，每個第一級幾何平均運算元511可接收來自四個記憶體單元502的電流，且執行運算

。即，一般來說，每個第一級幾何平均運算元511可被配置成確定來自記憶體單元502的多個電流的幾何平均值，其中所述幾何平均值通過下式得出：幾何平均值=

=

。由此，如果每個第一級幾何平均運算元511耦合到兩個記憶體單元502 （n = 2），那麼幾何平均值等於對分別與所述兩個記憶體單元相關聯的兩個讀取電流的乘積開平方根。The first-stage geometric averaging operator 511 can receive signals from multiple memory cells 502 and process the signals to output a single signal. In some embodiments, the first-stage geometric averaging operator 511 can multiply the current of the memory cell 502 and then perform pre-square. For example, if each first-level geometric average operator 511 is coupled to two memory cells 502, then each first-level geometric average operator 511 generates an output current having the following relationship:

. Alternatively, each first-level geometric averaging operator 511 may receive current from multiple memory cells 502 and combine the currents in a single calculation operation. For example, each first-stage geometric average operator 511 can receive current from four memory cells 502 and perform operations

. That is, in general, each first-level geometric average operator 511 may be configured to determine a geometric average value of multiple currents from the memory unit 502, wherein the geometric average value is obtained by the following formula: =

=

. Thus, if each first-level geometric mean operator 511 is coupled to two memory cells 502 (n = 2), then the geometric mean is equal to two reads associated with the two memory cells, respectively The square root of the product of currents.

In other embodiments, the first-level geometric averaging operator 511 can be replaced or reconfigured to apply other averaging operations. For example, the first-level geometric averaging operator 511 can be replaced by the first-level averaging operator or reconfigured as the first-level averaging operator, which is configured as a computing and memory unit 502 The arithmetic mean value of the associated read current. Alternatively, the first-stage geometric average operator 511 may be replaced by a first-stage multiplication circuit or a first-stage adder, or reconfigured as a first-stage multiplication circuit or a first-stage adder, the first-stage multiplication circuit or The first-stage adder uses different operations to combine the current of the memory cell 502.

In some embodiments, as shown in FIG. 4, the first-stage geometric averaging operator 511 may be constructed with an independent first-stage multiplication circuit (collectively referred to as first-stage multiplication circuit 508), which is connected to the first-stage square The root circuit (collectively referred to as the first-stage square root circuit 510). However, in other embodiments, a single circuit such as a CMOS square root circuit can separately process the current from the memory cell 502.

For a memory read configuration 500 with multiple levels, the original signal from the memory unit 502 may deteriorate as it passes through different processing levels. For example, conductor loss or noise from electronic components can damage the signal being processed. In addition, in the case of multiple levels, the apparent impedance of certain elements in the memory read configuration 500 may cause malfunctions. For example, the operation of the first stage geometric averaging operator 511 may be impaired when connected to multiple stages that produce high output impedance. Therefore, in some embodiments, the memory read configuration 500 may include a first stage buffer circuit 512 that is used to restore the quality of the signal and/or circuit decoupling portion to avoid such problems.

As previously discussed, the memory read configuration 500 may include multiple data processing stages. 4 shows three data processing stages, including a second-stage geometric average operation unit 517, a second-stage buffer circuit 518, a third-stage geometric average operation unit 523, and a third-stage buffer circuit 524. In some embodiments, higher levels can be reused for lower level hardware. For example, the second-level geometric average operator 517 and the third-level geometric average operator 523 may repeat the first-level geometric average operator 511. However, in other embodiments, there may be differences between the elements of each level. For example, the first stage geometric average operator 511 can be configured to handle two currents, while the second stage geometric average operator 517 can be configured to handle four or more currents simultaneously. Additionally or alternatively, the first-level geometric average operator 511 may be an analog circuit, and the third-level geometric average operator 523 may be a digital circuit.

The second-stage geometric average operator 517 includes a second-stage multiplication circuit (collectively referred to as second-stage multiplication circuit 514) and a second-stage square root circuit (collectively referred to as second-stage square root circuit 516). Similarly, the third stage geometric averaging operator 523 includes a third stage multiplication circuit 520 and a third stage square root circuit 522.

The memory reading configuration 500 may include more than three levels shown in FIG. 4. For example, the memory read configuration 500 may have "K" levels, where K is any positive integer. In the described embodiment, the relationship between the number of memory cells 502 and the number of geometric average operands can be defined by the number of levels selected. For example, in some embodiments, in the case of K levels, the total number of memory cells is 2 ^K and the total number of geometric average operators is 2 ^K -1. Therefore, if the memory read configuration 500 has 10 levels (K=10), the total number of memory cells that will be grouped to determine the overall memory state is 2 ¹⁰ , and the total number of geometric average operands will be 2 ¹⁰ -1. This relationship results from having square root-level operands that are repeated and each level of operands processing two currents or signals. However, when the geometric mean operands are different or more than two currents can be handled, other relationships are possible.

After processing the signals from the plurality of memory cells 502 in the processing stage, the resulting current is sent to the reading circuit 540. For example, the last geometric average operator stage can output a processed current, which is sent to the reading circuit 540 via the data connection 530. Alternatively, the coupling between the memory unit 502 and the reading circuit 540 may be indirect through additional electronic components such as filters or amplifiers. In some embodiments, the reading circuit 540 may include hardware and software to determine the state of the memory according to the reading current. For example, the reading circuit 540 may include hardware that determines one of the low resistance state or the high resistance state according to the reading current. In other embodiments, the reading circuit 540 may include a processing unit that operates based on the current received from the memory unit 502. For example, the reading circuit 540 may be coupled to one or more of the neurons 202.

The reading circuit 540 provides means for determining the memory state of the plurality of memory cells based on the memory current. In some embodiments, the reading circuit 540 may include a computer processor that correlates the reading current with the state of the memory. For example, the reading circuit 540 may correlate the reading current with a low-resistance memory state, an intermediate-resistance memory state, or a high-resistance memory state. Alternatively or additionally, the reading circuit 540 may be coupled with one or more of the neurons 202. However, in other embodiments, the reading circuit 540 may include a CPU or a GPU. In addition, the means for determining the state of the memory based on the memory current may include a microprocessor, microcontroller or other equivalent processing unit for correlating the current with the state of the memory.

FIG. 5 is a schematic diagram of a second exemplary memory reading configuration 600. Similar to the memory read configuration 500, the memory read configuration 600 is configured to cluster the outputs of a plurality of memory cells to reduce deviations in the state distribution of each memory. In the memory reading configuration 600, combining multiple memory readings produces a distribution of memory states with a lower max/min ratio per state, thereby facilitating the determination of memory states.

The memory reading configuration 600 includes a memory unit 502 and a filter circuit 505. However, instead of several levels of geometric average operands and buffers with the memory read configuration 500, the memory read configuration 600 includes an analog-to-digital converter (ADC) 610, a processor 612, and digital /Analog converter (digital-to-analog converter; DAC) 614. The configuration of the memory reading configuration 600 can perform digital processing on the reading current from the memory unit 502.

As shown in FIG. 5, the memory unit 502 is coupled to the ADC 610, the processor 612 and the DAC 614. The ADC 610 converts the analog signal from the memory unit 502 into digital data. In some embodiments, ADC 610 may be configured with a high-speed converter operating at a GHz input bandwidth. In some embodiments, the number of input pins to ADC 610 may be equal to the number of memory cells that are clustered. However, in other embodiments, the ADC 610 may include a parallel-to-serial converter and have a smaller number of input pins.

The digitized data from ADC 610 is sent to processor 612, which can calculate the output value. The processor 612 may include any computing unit, such as a CPU or GPU. The processor 612 receives all the digitized data to calculate the output. For example, the processor 612 may operate on the digitized current value to calculate the geometric mean value of the current. Thus, the processor 612 can multiply the current value and then square the product. Alternatively, the processor 612 may calculate the arithmetic mean, sum and/or product of the digitized current values. The processor 612 may also calculate other values based on the digitized current. For example, the processor 612 may calculate the mode and/or median of the current.

The processor 612 sends the calculated value to the DAC 614. DAC 614 may include any digital/analog converter. However, the DAC 614 may be selected based on quality factors including resolution, maximum sampling frequency, and the like. The DAC 614 converts the calculated digital signal into an analog signal, which is then sent to the reading circuit 540.

Although FIG. 5 illustrates ADC 610, processor 612, and DAC 614 as separate units connected via bus 620 and bus 622, in some embodiments, all functions of these three elements may be performed in a single unit. For example, ADC operations, processing operations, and DAC operations may be performed by a single element, such as a CPU or GPU.

FIG. 6 is a flowchart illustrating an exemplary memory state determination method 1200. In some embodiments, the method 1200 may be performed by a series of processing stages presented in the memory reading configuration 500. However, in other embodiments, the method 1200 may be implemented by a single element. For example, the method 1200 may be implemented by the processor 612.

In step 1202, a request to determine the state of the memory is received. For example, one of the neurons 202 may require memory state to perform calculations and send a request for memory state. The request may specify a group of memory units that should be queried.

In step 1204, multiple memory read currents are obtained from the memory unit. In some embodiments, multiple memory read currents are obtained from the memory unit 502. The memory read current can be filtered to eliminate noise from unwanted frequencies or truncate outliers. To further explain the method 1200 with an algebraic example, the exemplary multiple memory read currents obtained in step 1204 are referred to as current A, current B, current C, and current D.

In step 1206, multiple memory read currents are divided into different groups. In some embodiments, the memory read current may be divided into two groups of memory read currents. Alternatively, a divided group of more than two memory read currents may be defined in step 1206. For example, continuing the examples of current A, current B, current C, and current D, the divided groups may be group 1 {A, B} and group 2 {C, D}.

In step 1208, the elements in each of the divided groups are multiplied to calculate the product associated with each of the divided groups. For example, if each group has two memory read currents, then calculate the product of the two memory read currents. Thus, for example, in step 1208, the product of {A*B} and {C*D} is calculated.

In step 1210, the square root of the product is calculated. For example, each of the products calculated in step 1208 is calculated to produce a geometric mean. Therefore, for example, in step 1210, the following square roots are calculated: {A*B} ^1/2 and {C*D} ^1/2 .

In step 1212, it is determined whether all processing stages have been completed. For example, in the case where there are K levels, if K levels have not been completed (step 1212: No), then the method 1200 returns to step 1208 to calculate the additional product. However, if K levels have been completed (step 1212: Yes), then the method 1200 continues to step 1214. The algebraic examples of current A, current B, current C, and current D have 2 levels (K=2). Therefore, in the example, the method will return to step 1208 to calculate the new product [{A*B} ^1/2 *{C*D} ^1/2 ], and then calculate the second level in step 1210 The square root of the product [{A*B} ^1/2 *{C*D} ^1/2 ] ^1/2 . If there are more levels, then the loop between step 1208 and step 1212 continues until a single current represents all clustered memory cells.

In step 1214, the memory state is determined based on the single representative current determined in the step loop of step 1208 to step 1212. For example, in some embodiments, when the memory current is lower than the first reference current, it can be determined that the memory state is high resistance; when the memory current is between the first reference current and the second reference current, Determine that the memory state is the first intermediate state, and the second reference current is greater than the first reference current; when the memory current is between the second reference current and the third reference current, the state can be determined to be the second intermediate state, the third reference The current is greater than the second reference current; and when the memory current exceeds the third reference current, it can be determined that the memory state is a high resistance state. In the described embodiment, the memory reader (eg, reading circuit 540) may select the first reference current to be higher than the maximum current in the memory current distribution associated with the low resistance state; and the third reference The current is selected to be lower than the minimum current in the memory current distribution associated with the high resistance state. Therefore, the memory reader will be able to correlate the memory current with the memory state by comparing the memory reading from the clustered memory unit 502 with the reference current.

In order to determine the state of the memory, the processing circuit may correlate the memory output with the state of the memory. For example, in step 1214, an analog/digital converter (ADC) may determine one of the states based on the current input. The ADC may determine that any current lower than the first reference number corresponds to a low memory state, and a current exceeding the third reference number corresponds to a high memory state. Therefore, the means for determining the memory state of the plurality of memory cells may include an ADC that correlates the analog signal with the memory state. Alternatively, the memory state can be identified using a processing unit, such as a microprocessor, which correlates the received analog input with the memory state.

In step 1216, the determined memory state is sent to a directly or indirectly coupled processing unit. For example, the determined memory state may be sent to one of the neurons 202 for processing tasks or calculations. Although the method 1200 has been described for a set of four memory currents processed in two levels, the method 1200 can also be used to handle more than two memory read currents per state. Next, a numerical example of an application method 1200 with multiple memory read currents per level will be described.

According to the numerical example, in step 1204, the reading operation starts with eight memory cells 502 outputting the following values: 8 uA, 10 uA, 9 uA, 12 uA, 7 uA, 8 uA, 9 uA, and 10 uA. These initial values can be obtained through the processing circuit or the network illustrated in FIG. 4. Subsequently, these values are divided into two groups of four values each (step 1206), and these values are then processed to obtain a geometric mean. For example, the following operations are performed according to step 1208 and step 1210 of method 1200: (8*10*9*12) ^1/4 = 9.6 uA and (7*8*9*10) ^1/4 = 8.4 uA. The numerical examples show ways in which the disclosed processing techniques can be used to reduce the max/min ratio. The initial value has a wide distribution in the range of 7 uA to 12 uA, the difference is 5 uA, while the processed data has a max/min ratio of only 8.4 uA to 9.6 uA, and the difference is 1.2 uA. Therefore, the max/min ratio is reduced, and it will be easier to recognize the memory state associated with the distribution.

7A to 7C are graphs showing exemplary relationships between cumulative distribution functions (CDF) of different memory states of multiple memory cells and read currents.

Referring to FIG. 7A, a graph 1310 shows a low resistance state (LRS), a first intermediate state (IR1), a second intermediate state (IR2), and a high resistance state ; HRS) the relationship between the reading current and the cumulative distribution function. Graph 1310 shows the significant overlap between the four states. For example, a reading current of 10 uA can represent all states. This overlap between the distributions complicates the read operation because it creates uncertainty about the corresponding state of the memory cell.

Referring to FIG. 7B, graph 1320 presents a second relationship between the read current and the cumulative distribution function after some processing and amplification or using different read operations. Although the overlap between the distributions is reduced, determining the memory state is still challenging because the distributions overlap, and there is no clear boundary between the upper and lower boundaries of adjacent memory states. As shown in graph 1320, there is overlap between different memory states. Therefore, at a given reading current (for example, 5 uA), it is impossible to distinguish between different states. The memory reading method that provides the results of graph 1320 can be reliably used in only two states of low resistance and high resistance. However, using only two states reduces the storage capacity exponentially.

Referring to FIG. 7C, graph 1330 presents a third relationship between the read current and the cumulative distribution function. After processing the memory state with method 1200 and/or using memory read configuration 500 or memory read configuration 600, the relationship shown in graph 1330 may be obtained. To obtain the graph 1330, a plurality of memory cells are clustered before performing memory reading. For example, data processing techniques such as determining the geometric mean have been applied to obtain the relationship represented in graph 1330.

Graph 1330 shows that each memory state has clearly defined upper and lower boundaries. For example, it is obvious that any current below 3 uA should be associated with HSR, and any current above 9 uA should be associated with LSR. Subsequently, the clustering of the memory cells produces a clear distribution with easily recognizable memory states. As presented in graph 1330, using the disclosed clustering method, the cumulative distribution functions between different states do not overlap, and the min/max ratio is significantly reduced. Therefore, different read currents can easily be related to a specific memory state.

The clustering method used to generate the third relationship in graph 1330 improves memory reading distribution and facilitates the use of memory cells for applications such as neuromorphic calculations. With the disclosed processing method, there is no tail overlap between the states, thereby forming a clear distinction between the states of the memory cells.

After processing the memory current, the memory state in the graph 1330 can be identified by means for determining the memory state. For example, the microcontroller may provide means for correlating memory current with memory state. The microcontroller may include a relationship table or other related methods to generate an output of the memory state based on the memory current.

FIG. 8 is a graph 1400 showing an exemplary relationship between current distribution and current ratio for different memory reading configurations. The distribution of the max/min ratio is a measure of the standard deviation of the distribution. A higher max/min ratio is associated with a higher standard deviation because the maximum number is far from the minimum number. In contrast, a lower max/min ratio is associated with a tight distribution, where the maximum and minimum are close to each other. For memory read operations, a lower max/min ratio is expected. At lower max/min ratios, the distribution of different memory states is narrower and does not include overlap between different memory states. For example, a memory cell with a lower distribution max/min ratio will be associated with the memory state presented in graph 1330.

Graph 1400 shows the max/min ratio for different cluster operations. The graph 1400 shows the results of the memory reading configuration of adding, multiplying, calculating arithmetic mean or calculating geometric mean through clustered memory cells. Graph 1400 shows that adding or multiplying memory currents and normalizing them with the minimum current results in a larger max/min ratio. For example, in graph 1400, sum/Imin 1402 and prod/Imin^2 1404 produce a larger max/min ratio. These larger max/min ratios are undesirable because they lead to overlapping memory states. The graph 1400 also shows the result of calculating the arithmetic average of multiple memory cells with avg/Imin 1408. Using the averaging operation, max/min decreases, indicating that the memory state distribution becomes narrower. For example, avg/Imin 1408 produces a smaller max/min ratio compared to sum/Imin 1402 and prod/Imin^2 1404. However, the geometric mean calculation desirably achieves even smaller max/min ratios. As shown in the graph 1400 with sqrt(prod)/Imin 1406, the operation of taking the square root of the product of the read current produces the smallest max/min ratio. In the case of the square root operation of the product, the min/max ratio is reduced, thereby allowing a simpler resolution of the memory state. For example, in all cluster operations, sqrt(prod)/Imin 1406 has the smallest min/max ratio.

Operations other than those presented in graph 1400 are also possible. The graph 1400 only shows the effect on the standard deviation of the distribution produced by different operations intended to reduce the diffusion of the reading current value. Other operations can also be performed on the read current through the cluster, such as determining an average or mode to reduce the min/max ratio and facilitate memory read operations. Alternatively, multiple operations can be combined in a memory read configuration. For example, averaging operations can be performed in some stages of the memory read configuration, while geometric average operations can be performed in other stages of the configuration.

It can be understood by those skilled in the art that various modifications and changes can be made to the disclosed system and related methods. For those skilled in the art, other embodiments will be understood by considering this specification and practicing the disclosed system and related methods. It is hoped that this specification and examples are to be regarded as exemplary only, in which the true scope is indicated by the following patent applications and their equivalents.

Furthermore, although illustrative embodiments have been described herein, the scope includes equivalent elements, modifications, omissions, combinations (such as combinations of aspects of various embodiments), adaptations as will be appreciated by those skilled in the art based on the present disclosure And/or changed any and all embodiments. For example, the number and arrangement of elements shown in the exemplary system can be modified. In addition, with regard to the exemplary method shown in the drawings, the order and sequence of steps may be modified, and steps may be added or deleted.

Therefore, the above description has been presented only for illustrative purposes. The description is not exhaustive and is not limited to the precise forms or embodiments disclosed. For those skilled in the art, modifications and adaptations will be understandable by considering this specification and practicing the disclosed embodiments.

The scope of patent application should be interpreted broadly based on the words used in the scope of patent application, and is not limited to the examples described in the present invention, which should be understood as non-exclusive. In addition, the steps of the disclosed method can be modified in any way, including by reordering the steps and/or inserting or deleting steps.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100: Electronic system 102: Central processing unit 104: Graphics processing unit 106: Digital signal processor 108: Multimedia processor 110: Sensor 112: Image signal processor 114: Display/LCD 116: Navigation module 118: Connection module Group 120: neural processing unit 200: memory devices 202, 202(a), 202(b), 202(c), 202(d), 202(e), 202(f), 202(g): neurons 204, 204(a), 204(b), 204(c), 204(d), 204(e), 204(f): synapse 206, 206(a), 206(b), 206(c) 206 (d): communication channels 310, 330, 360: memory circuit 312: row decoder 314: ReRAM array 316: ReRAM register 318: data register 320: column decoder 322, 530, 620, 622 : Data bus/data connection 324: amplifier 332, 346: parallel-serial converter 344: address counter 348: control circuit/select transistor 500, 600: memory read configuration 502, 502(a), ..., 502 (z): memory unit 504: band-pass filters 505, 505(a), ..., 505(z): filter circuit 506: min/max filter 508: first-stage multiplication circuit 510: first-stage square root Circuits 511, 511(a), ..., 511(y): first-stage geometric averaging operands 512, 512(a), ..., 512(y): first-stage buffer circuit 514: second-stage multiplication circuit 516 : Second-stage square root circuit 517, 517(a), ..., 517(x): second-stage geometric average operator 518, 518(a), ..., 518(x): second-stage buffer circuit 519: Aggregation stage 520: third stage geometric average operator 522: third stage square root circuit 523: third stage geometric average operator 524: third stage buffer circuit 540: read circuit 610: analog/digital converter 612: Processor 614: digital-to-analog converter 1200: flowcharts 1202, 1204, 1206, 1208, 1210, 1212, 1214, 1216: steps 1310, 1320, 1330, 1400: graphs

FIG. 1 is a schematic diagram of an exemplary electronic system according to one embodiment. 2 is a schematic diagram of an exemplary memory device. FIG. 3A is a schematic diagram of a first exemplary memory circuit. 3B is a schematic diagram of a second exemplary memory circuit. 3C is a schematic diagram of a third exemplary memory circuit. 4 is a schematic diagram of a first exemplary memory reading configuration. 5 is a schematic diagram of a second exemplary memory reading configuration. 6 is a flowchart illustrating an exemplary memory state determination method according to the disclosed embodiment. 7A is a graph of a first exemplary relationship between the cumulative distribution function of different memory states and read current. 7B is a graph of a second exemplary relationship between the cumulative distribution function of different memory states and the reading current. 7C is a graph of a third exemplary relationship between the cumulative distribution function of different memory states and the reading current. 8 is a graph of an exemplary relationship between current distribution and current ratio for different memory reading configurations.

500: memory read configuration

502(a), 502(z): memory unit

504(a), 504(z): band-pass filter

505(a), 505(z): filter circuit

506(a), 506(z): min/max filter

508(a), 508(y), 514(a), 514(x), 520: multiplication circuit

510(a), 510(y), 516(a), 516(x), 522: square root circuit

511(a), 511(y), 517(a), 517(x): geometric average operator

512(a), 512(y), 518(a), 518(x), 524: buffer circuit

519: Collection level

523: The third level geometric average operand

530: Data bus

540: Reading circuit

Claims (20)

A memory device, including: a plurality of memory cells; at least one geometric average operator, coupled to at least two of the plurality of memory cells; and a memory state reader, coupled to the at least one geometry The arithmetic unit is averaged to read the memory states of the plurality of memory cells. The memory device according to item 1 of the patent application scope, wherein the at least one geometric average operator is a first-level geometric average operator, and the memory device further includes: a plurality of first-level geometric average operators , Each of the plurality of first-level geometric average operators is coupled to at least two of the plurality of memory cells; and at least one second-level geometric average operator is coupled to the plurality of first At least two of the level geometric averaging operands, the at least one second level geometric averaging operand is coupled to the memory state reader. The memory device according to item 1 of the patent application range, wherein the plurality of memory cells include a variable resistance memory cell. The memory device as described in item 2 of the patent application range, wherein each of the plurality of first-level geometric average operators and the at least one second-level geometric average operator includes a complementary metal oxide semiconductor square root Circuit. The memory device as described in item 2 of the patent application range, wherein each of the plurality of first-level geometric average operators includes: a first-stage multiplication circuit coupled to at least one of the plurality of memory cells Two; and the first-stage square root circuit, coupled to the first-stage multiplication circuit. The memory device as recited in item 5 of the patent application range, wherein the at least one second-level geometric average operator includes: a second-level multiplication circuit coupled to at least one of the plurality of first-level geometric average operators Two; and a second-stage square root circuit, coupled to the second-stage multiplication circuit. The memory device according to item 1 of the patent application scope, further comprising an artificial neuron coupled to the memory state reader. The memory device as described in item 7 of the patent application range, wherein the area occupied by the artificial neuron is at least one hundred times larger than each of the plurality of memory cells. The memory device according to item 7 of the patent application range, wherein the artificial neuron occupies an area of 8000 F ² or more; and each of the plurality of memory cells occupies 30 F ² or less Area, where F ² is the relative area unit representing the smallest resolvable feature of the technology node. The memory device according to item 1 of the patent application scope, wherein the memory state reader is configured to: receive a memory current corresponding to the memory state based on the output of the second-level geometric average operator When the memory current is lower than the first reference current, it is determined that the memory state of the plurality of memory cells is in a high resistance state; When the memory current is between the first reference current and the second reference current When the second reference current is greater than the first reference current, it is determined that the plurality of memory cells are in the first intermediate state; when the memory current is between the second reference current and the third reference current When the third reference current is greater than the second reference current, it is determined that the plurality of memory cells are in the second intermediate state; and when the memory current exceeds the third reference current, the first When the third reference current is higher than the first reference current, it is determined that the plurality of memory cells are in a low resistance state. The memory device of claim 10, wherein the memory state reader is further configured to: select the first reference current to be higher than the memory associated with the high resistance state The maximum current in the current distribution; and The third reference current is selected to be lower than the minimum current in the memory current distribution associated with the low resistance state. The memory device according to item 2 of the patent application scope, wherein the at least one second-level geometric average operator includes two second-level geometric average operators; and the memory state reader passes the third level The geometric average operator is coupled to the two second-level geometric average operators. The memory device as described in item 2 of the patent application scope further includes a plurality of filter circuits, wherein each of the plurality of first-level geometric average operators is coupled to at least one of the plurality of filter circuits At least two of the plurality of memory cells; and the filter circuit includes a band pass filter and a min/max filter. The memory device as described in item 2 of the patent application scope further includes a plurality of buffer circuits, wherein the at least one second-level geometric averaging operand is coupled to the buffer via at least one of the plurality of buffer circuits At least two of the multiple first-level geometric averaging operands. The memory device as described in item 2 of the patent application scope further includes an additional geometric average operator, wherein the plurality of memory cells includes 2 ^K memory cells, where K is any positive integer; and the plurality The number of first-level geometric average operators plus the number of the at least one second-level geometric average operand plus the number of additional geometric average operators are at least 2 ^K -1. A memory device, including: a plurality of non-volatile memory cells; a component for generating a first product by multiplying a memory reading current associated with the memory cell; a device for generating a first product; The first product performs a square root operation to generate a first square root; and means for determining the memory state of the plurality of memory cells based on the memory current corresponding to the first square root. The memory device according to item 16 of the patent application scope, further wherein the means for generating the first product includes a means for generating a plurality of first products; the means for generating the first square root includes Means for generating a plurality of first square roots; the memory device further includes: means for generating a second product by multiplying the first subset of the plurality of first square roots, the first A subset includes at least two of the plurality of first square roots; means for generating a second square root by performing a square root operation on the second product; and the memory current is further based on the Second party root. The memory device as described in item 17 of the patent application scope further includes: means for generating a third product by multiplying the second subsets of the plurality of first square roots, the second subsets Including at least two of the plurality of first-party roots, the second subset is different from the first subset; means for generating the third-party root by performing a square root operation on a third product A means for generating the fourth product by multiplying the second square root and a third-party root; and a means for generating a fourth square root by performing a square root operation on the at least one fourth product Component; wherein the memory current is further based on the fourth square root. A method for determining the state of a memory, the method comprising: obtaining a plurality of memory read currents of a plurality of memory units; determining a product based on the plurality of memory read currents; determining a square root based on the product ; And determining the state of the memory based on the square root. The method according to item 19 of the patent application scope, wherein the plurality of memory reading currents include two memory reading currents; and determining the square root includes determining the square root of the product of the two memory reading currents .

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