TW202018500A - Saving and restoring machine state between multiple executions of an instruction - Google Patents

Abstract

Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Description

Save and restore machine state between multiple executions

One or more aspects are generally related to facilitating processing within a computing environment, and in particular, are related to facilitating instruction processing.

Instructions executed within the computing environment may require a large number of execution loops to complete the operation. When an instruction requires a large number of execution cycles to complete, the instruction can be defined as interruptible. Therefore, in order to finally complete the instruction, additional processing is implemented.

Overcoming the shortcomings of the prior art and providing additional advantages by providing computer program products for facilitating processing in computing environments. The computer program product includes a computer-readable storage medium that can be read by a processor and stores instructions for performing a method. The method includes determining that the processing of the operation of the instruction executed on the processor has been interrupted before completion. The processing based on the judgment operation has been interrupted, and the post-processor information is obtained. The meta data is the current meta data of the processor. The meta data is stored in the location associated with the instruction, and is used when the instruction is re-executed to resume the forward processing of the instruction from where it was interrupted.

By obtaining the configuration data and saving the other data after interrupting the operation, when the command is re-executed, the saved configuration data can be loaded and used instead of repeating the task to regenerate the configuration data. This saves time and thus improves the performance within the processor.

In one example, the command is a sorting command, and the meta data includes information about one or more input lists of the sorting command. For example, the meta data includes information about previous comparisons made to the record of one or more input lists to indicate subsequent comparisons to be made. For example, without repeating the previous comparison, indicating the subsequent comparison to be made.

In one example, the determination includes checking the condition code set based on the termination of the instruction, and the condition code set to the selected value indicates partial completion of the instruction.

As an example, the location where the meta data is stored is the parameter block specified by the instruction in the memory. The location of the parameter block in the memory is indicated by the contents of the implied register such as the command. In a particular example, the parameter block includes a connection status buffer for storing metadata, which includes internal status data of the processor. In addition, in one example, the parameter block includes a connection indicator to indicate the partial completion of the operation.

In one aspect, using the meta data when the command is re-executed further includes re-executing the command to resume processing again; acquiring the meta data from the location; and loading the meta data from the location into one of the processors or In multiple selection locations, the metadata is provided to the processor without repeating one or more tasks to generate metadata.

This article also describes and advocates computer-implemented methods and systems related to one or more aspects. In addition, this article also describes and may claim services related to one or more aspects.

Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein and considered as part of the claimed aspect.

According to the aspect of the present invention, an ability to facilitate processing within a computing environment is provided. As an example, a single instruction (eg, a single structured hardware machine instruction at a hardware/software interface) is provided to perform operations to sort and/or merge data records. For example, instructions are executed on a general-purpose processor.

When executing instructions, a large number of execution cycles may be required to complete the operation. Therefore, in one aspect, the instruction system is defined as interruptible. When the instruction is interrupted, the operation (eg, sorting and/or merging) is only partially completed. Command execution ends by setting the condition code to notify the program (for example, the program that issued the command) of the partially completed value of the operation. The program can then re-execute the instruction to resume processing.

In one embodiment, the instruction uses several (e.g., a large number) execution loops to start the processor with post data before generating the results. Whenever a command is executed or re-executed, the processor is started with the post data. Therefore, according to the aspect of the present invention, the previously generated meta data is stored and used so that it is not necessary to regenerate the previously generated meta data when the command is re-executed.

In one example, the instruction is a sorting instruction that sorts and/or merges records entered into one or more input lists of the instruction. For this example, the post data includes the internal state of the processor, including, for example, information about the input list, such as information about previous comparisons of the records of the input list, in order to determine subsequent comparisons to be made.

The processor obtains the meta data and stores it in the location provided by the program. Then, when the instruction is re-executed after the interruption, the meta data is obtained from the location and loaded into the processor without using the task to regenerate the meta data. This saving generates the time it will take to set up the data after the operation.

Referring to FIG. 1A, an embodiment of a computing environment in which one or more aspects of the present invention are described and used. For example, the computing environment 100 includes a processor 102 (eg, central processing unit), memory 104 (eg, main memory; also known as system memory, main storage, central storage, storage), and one or Multiple input/output (I/O) devices and/or interfaces 106, each of which is coupled to each other via, for example, one or more bus bars 108 and/or other connectors.

In one example, the processor 102 is based on Armonk, New York City, z supplied by the International Business Machines Corporation / Architecture ^® architectures, and is part of a server, such as an IBM Z ^® servers, which increased from International Business The machine company supplies and implements the z/Architecture (z/architecture) hardware architecture. An example of the z/Architecture hardware architecture is described in the public case entitled "z/Architecture Principles of Operation" (IBM Publication No. SA22-7832-11, 12th edition, 2017 In September), this publication is hereby incorporated by reference in its entirety. However, the z/Architecture hardware architecture is only an example architecture; other architectures and/or other types of computing environments may include and/or use one or more aspects of the present invention. In one example, the processor executes an operating system also supplied by International Business Machines Corporation, such as the z/OS ^® operating system.

The processor 102 includes a plurality of functional components for executing instructions. As depicted in FIG. 1B, these functional components include, for example, an instruction fetch component 120, which is used to fetch instructions to be executed, and an instruction decoding unit 122, which is used to decode the fetched instructions and obtain operands of the decoded instructions ; Instruction execution component 124, which is used to execute decoded instructions; memory access component 126, which is used to access memory for instruction execution when necessary; and write-back component 130, which is used to provide the result of the executed instruction . According to one or more aspects of the invention, one or more of these components may include one or more other that provide sorting/merging processing (or other processing that may use one or more aspects of the invention) At least a part of the component may be able to access the one or more other components. The one or more other components include, for example, sorting/merging components (or other components) 136. The functionality provided by component 136 is described in further detail below.

Refer to FIG. 2 for another example of a computing environment in which one or more aspects of the present invention are described and used. In one example, the computing environment is based on the z/Architecture hardware architecture; however, the computing environment may be based on other architectures supplied by International Business Machines Corporation or other companies.

Referring to FIG. 2, in one example, the computing environment includes a central electronic device complex (CEC) 200. CEC 200 includes a plurality of components, such as memory 202 (also known as system memory, main memory, main storage, central storage, storage), which is coupled to one or more processors (also known as central Processing unit (CPU) 204 and input/output subsystem 206.

The memory 202 includes, for example, one or more logical partitions 208, a hypervisor 210 that manages the logical partitions, and processor firmware 212. An example of the hyper-manager 210 is the processor resource/system manager (PR/SM™) hyper-manager supplied by International Business Machines Corporation of Armonk, New York. As used herein, firmware includes microcode such as a processor. It includes, for example, hardware-level instructions and/or data structures for implementing higher-level machine code. In one embodiment, it includes, for example, proprietary code, which is typically delivered as microcode that includes trusted software or microcode that is specific to the underlying hardware, and controls access to the system hardware by the operating system.

Each logical partition 208 can act as a separate system. That is, each logical partition can be independently reset, run a guest operating system 220 such as a z/OS operating system or another operating system, and operate with different programs 222. The operating system or application running in the logical partition appears to be able to access the complete system, but in reality, only part of it is available.

The memory 202 is coupled to a processor (eg, CPU) 204, which is a physical processor resource that can be allocated to a logical partition. For example, logical partition 208 includes one or more logical processors, each of which represents all or a portion of physical processor resources 204 that can be dynamically allocated to the logical partition.

In addition, the memory 202 is coupled to the I/O subsystem 206. I/O subsystem 206 may be part of or separate from the central electronic device complex. It guides the information flow between the main storage 202 and the input/output control unit 230 and the input/output (I/O) device 240 coupled to the central electronic device complex.

Many types of I/O devices can be used. One particular type is the data storage device 250. The data storage device 250 may store one or more programs 252, one or more computer readable program instructions 254 and/or data, and so on. Computer readable program instructions can be configured to perform the functions of the embodiments of the present invention.

In one example, the processor 204 includes a sorting/merging component (or other component) 260 to perform one or more of sorting and/or merging (or other operations that may use one or more aspects of the invention). In various examples, there may be one or more components that perform such tasks. Many changes are possible.

The central electronic device complex 200 may include and/or be coupled to a removable/non-removable, volatile/non-volatile computer system storage medium. For example, the central electronic device complex may include and/or be coupled to non-removable non-volatile magnetic media (commonly referred to as "hard drives"), for self-removable non-volatile magnetic disks (eg, "Floppy Disk") A drive that reads and writes to removable non-volatile disks, and/or is used to read from non-volatile optical disks such as CD-ROM, DVD-ROM or other optical media Or write to a disc drive with removable non-volatile discs. It should be understood that other hardware and/or software components may be used in conjunction with the central electronic device complex 200. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archiving and storage systems.

In addition, the central electronic device complex 200 can operate with many other general or special computing system environments or configurations. Examples of well-known computing systems, environments, and/or configurations suitable for use with central electronic device complex 200 include, but are not limited to: personal computer (PC) systems, server computer systems, thin clients, complex clients , Handheld or laptop computer devices, multi-processor systems, microprocessor-based systems, set-top boxes, programmable consumer electronic devices, network PCs, small computer systems, large computer systems, and systems that include the above A distributed cloud computing environment for any of the devices, and the like.

Although various examples of computing environments are described herein, one or more aspects of the invention can be used with many types of environments. The computing environment provided in this article is only an example. In addition, although one or more aspects of the invention are described with reference to sorting instructions, one or more of these aspects are applicable to other processes and/or instructions that use a large number of execution loops and that can be interrupted. The sort instruction is only an example.

According to one aspect of the invention, a processor such as processor 102 or 204 uses an enhanced sorting facility that provides a mechanism for sorting multiple lists of unsorted input data into one or more lists of sorted output data. In one example, when the facility indicator is set to, for example, one, the enhanced sequencing facility is installed in the system. As a specific example of the z/Architecture hardware architecture, when the enhanced sequencing facility is installed in the z/Architecture architecture mode, the facility bit 150 is set to, for example, one. In one embodiment, the facility also provides a mechanism to merge multiple lists of sorted input data into a single list of sorted output data. For example, the facility includes a sorted list instruction, and an embodiment of the instruction is described below.

3A to 3K describe an embodiment of the details related to the sort list instruction. In one example, this instruction is executed on a general-purpose processor (eg, processor 102 or 204). In the description herein, specific locations, specific fields, and/or specific sizes of fields (eg, specific bytes and/or bits) are indicated. However, other locations, fields and/or sizes may be provided. In addition, although it is specified that the bit is set to a specific value such as one or zero, this is only an example. In other examples, the bits may be set to different values, such as opposite values or another value. Many changes are possible.

Referring to FIG. 3A, in one example, the format of the sorted list (SORTL) instruction 300 is an RRE format that indicates the operation of the register and the register by an extended operation code (operation code). As an example, the instruction comprises: an opcode field 302 (e.g., bits 0-15), and having an indicating sort / merge operation or the operation code; a first register field (R ₁₎ 304 (e.g. , Bits 24 to 27), which specifies the first pair of general-purpose registers; and the second register field (R ₂ ) 306 (for example, bits 28 to 31), which specifies the second pair of general-purpose registers . The content of the register specified by the R ₁ field 304 specifies the location of the first operand (in the memory), and the content of the register specified by the R ₂ field 306 specifies the location of the second operand (in Memory). The content of R ₁ +1 specifies the length of the first operand, and the content of R ₂ +1 specifies the length of the second operand. In one example, bits 16 to 23 of the instruction are reserved and should contain zeros; otherwise, the program may not be compatible in the future. As used in this article, the program is a program that issues a sorted list command. The program can be a user program, operating system, or another type of program.

In one embodiment, instruction execution includes the use of one or more implied general purpose registers (ie, registers not explicitly specified by the instruction). For example, the general-purpose registers 0 and 1 are used when executing the sorted list instruction, as described herein. In one example, the general-purpose register 0 is used to specify whether to execute the combination and the sorting function executed by the instruction, and the general-purpose register 1 is used to provide the location of the parameter block used by the instruction. In another example, the general purpose register 0 is not used to specify whether to perform the merge; the fact is that the merge is set/not set by the machine (eg, processor) and cannot be changed by the mode indicator. Other changes are possible.

As an example, referring to FIG. 3B, the general register 0 (308) includes a merge mode field 310 (described below) and a function code field 312. In a specific example, the bit positions 57 to 63 of the general register 0 contain the function code; but in other embodiments, other bits can be used to contain the function code. In one example, when bits 57 to 63 of general register 0 indicate unassigned or uninstalled function codes, a specification exception is recognized.

The assigned function codes for the example of the sort list command are shown in FIG. 3C and include, for example: function code 0 (313), which indicates the SORTL-QAF (query available function) function; function code 1 (315) , Which indicates the SORTL-SFLR (sort fixed-length records) function; and function code 2 (317), which indicates the SORTL-SVLR (sort variable-length records) function. In one example, each code uses a parameter block and the size of the parameter block depends on the function. For example, for the SORTL-QAF function, the parameter block is 32 bytes; and for SORTL-SFLR and SORTL-SVLR, the parameter block is 576+16×N _IS , where N _IS is the number of input lists , As specified by the interface size. In this example, no other function codes are assigned. Although example functions and function codes are described, other functions and/or function codes may be used.

As previously indicated, the general purpose register 0 also includes a merge mode field 310. In one example, bit 56 of general purpose register 0 specifies the operation mode (merging mode) applied to functions such as SORTL-SFLR and SORLT-SVLR functions. In one example, when the designated function is SORTL-QAF, bit 56 of general purpose register 0 is ignored. In addition, in one example, bit positions 0 to 55 of general purpose register 0 are ignored.

Referring to FIG. 3D, other details regarding another implicit register (general register 1) used by the sort list instruction are described. For example, the contents of general purpose register 1 (314) specify the logical address 316 of the leftmost byte of the parameter block in the memory. In one example, the parameter block will be indicated on a double-word boundary; otherwise, a specification exception is recognized. Further details regarding parameter blocks are described further below.

For specified functions (for example, SORTL-QAF, SORTL-SFLR, SORTL-SVLR), the contents of general purpose registers 0 and 1 are not modified. In addition, in one example, the R ₁ field 304 indicates a pair of parity general registers. It will indicate the even-numbered register and not the general-purpose register 0; otherwise, the specification exception is recognized. When the specified function is SORTL-SFLR or SORTL-SVLR, as shown in FIGS. 3E to 3F, the content of the general register R ₁ 318 specifies, for example, the logical address 320 of the leftmost byte of the first operand , And the content of the general register R ₁ +1 (322) specifies the length 324 of the first operand in bytes, for example. When the specified function is SORTL-SFLR or SORTL-SVLR, the first operand will be indicated on a double-word boundary, for example; otherwise, a specification exception is recognized. The data in the form of records is selected from a set of input lists and stored at the first operand location (for example, starting at the address specified using R ₁ ). When the SORTL-QAF function is specified, the contents of the general purpose registers R ₁ and R ₁ +1 are ignored.

In addition, for specified functions (eg, SORTL-QAF, SORTL-SFLR, SORTL-SVLR), in one example, the R ₂ field 306 specifies a pair of parity general registers. It will indicate the even-numbered register and not the general-purpose register 0; otherwise, the specification exception is recognized. When the specified function is SORTL-SFLR or SORTL-SVLR and the merge mode (MM) is zero, as shown in FIGS. 3G to 3H, the content of the general register R ₂ 326 specifies, for example, the leftmost of the second operand The logical address of the byte is 328, and the content of the general register R ₂ +1 (330) specifies the length 332 of the second operand in bytes, for example. In one example, when the specified function is SORTL-SFLR or SORTL-SVLR and the merge mode (MM) is zero, the second operand will be indicated on a double-word boundary; otherwise, a specification exception is recognized. When MM is zero, the starting address and length of each output list (called output list rendering (OLD)) is stored at the second operand location (for example, starting at the address specified using R ₂ ). When the SORTL-QAF function or MM is specified as one, the contents of the general purpose registers R ₂ and R ₂ +1 are ignored.

In execution, in one embodiment, the function specified by the function code in the general register 0 is implemented. In one embodiment, when the specified function is SORTL-SFLR or SORTL-SVLR, as part of the operation, the following occurs:

* The address in the general register R ₁ increases the number of bytes stored at the position of the first operand, and the length in the general register R ₁ +1 decreases by the same number.

* When MM is zero, the address in the general register R ₂ increases by the number of bytes stored at the second operand position, and the length in the general register R ₂ +1 decreases by the same number.

In one example, the formation and update of the address and length depend on the addressing mode.

In one embodiment, in the 24-bit addressing mode, the following applies:

* The contents of bit positions 40 to 63 of general register 1, R ₁ and R ₂ constitute the address of the parameter block, the first operand and the second operand, respectively, and the contents of bit positions 0 to 39 are ignored .

* Bits 40 to 63 of the updated first operand address and second operand address replace the corresponding bits in the general purpose registers R ₁ and R ₂ respectively. The carry output of the bit position 40 of the updated address is ignored, and the contents of the bit positions 32 to 39 of the general-purpose registers R ₁ and R _{2 are} set to zero. The contents of bit positions 0 to 31 of the general purpose registers R ₁ and R ₂ remain unchanged.

* The contents of the bit positions 32 to 63 of the general-purpose registers R ₁ +1 and R ₂ +1 form a 32-bit unsigned binary integer, which specifies the bits in the first operand and the second operand, respectively The number of groups. The contents of bit positions 0 to 31 of the general purpose registers R ₁ +1 and R ₂ +1 are ignored.

* The updated bits 32 to 63 of the first operand length and the second operand length replace the corresponding bits in the general-purpose registers R ₁ +1 and R ₂ +1, respectively. The contents of bit positions 0 to 31 of the general purpose registers R ₁ +1 and R ₂ +1 remain unchanged.

In one embodiment, in the 31-bit addressing mode, the following applies:

* The contents of bit positions 33 to 63 of general register 1, R ₁ and R ₂ constitute the address of the parameter block, the first operand and the second operand, respectively, and the contents of bit positions 0 to 32 are ignored .

* Bits 33 to 63 of the updated first operand address and second operand address replace the corresponding bits in the general-purpose registers R ₁ and R ₂ respectively. The carry output of the bit position 33 of the updated address is ignored, and the contents of the bit position 32 of the general registers R ₁ and R ₂ are set to zero. The contents of bit positions 0 to 31 of the general purpose registers R ₁ and R ₂ remain unchanged.

* The contents of the bit positions 32 to 63 of the general-purpose registers R ₁ +1 and R ₂ +1 form a 32-bit unsigned binary integer, which specifies the bits in the first operand and the second operand, respectively The number of groups. The contents of bit positions 0 to 31 of the general purpose registers R ₁ +1 and R ₂ +1 are ignored.

* The updated bits 32 to 63 of the first operand length and the second operand length replace the corresponding bits in the general-purpose registers R ₁ +1 and R ₂ +1, respectively. The contents of bit positions 0 to 31 of the general purpose registers R ₁ +1 and R ₂ +1 remain unchanged.

In one embodiment, in 64-bit addressing mode, the following applies:

* The contents of bit positions 0 to 63 of general register 1, R ₁ and R ₂ respectively constitute the address of the parameter block, the first operand and the second operand.

* Bits 0 to 63 of the updated first operand address and second operand address replace the corresponding bits in the general purpose registers R ₁ and R ₂ respectively. The carry output of bit position 0 of the updated address is ignored.

* The contents of bit positions 0 to 63 of the general purpose registers R ₁ +1 and R ₂ +1 form 64-bit unsigned binary integers, which specify the bits in the first and second operands, respectively The number of groups.

* Bits 0 to 63 of the updated first operand length and second operand length replace the corresponding bits in the general purpose registers R ₁ +1 and R ₂ +1, respectively.

In the access register mode, the access registers 1, R ₁ and R ₂ specify the address space containing the parameter block, the first operand and the second operand, respectively.

Other details about various functions are described below.

Function code 0 : SORTL-QAF ( Query available functions )

The SORTL-QAF (query) function provides a mechanism to indicate the availability of all installed functions, the format of installed parameter blocks, and the size of available interfaces. The interface size is the number of input lists available for the program. The size of the parameter block used in the SORT-SFLR and SORT-SVLR functions is proportional to the size of the interface specified by the program.

An example format of the parameter block used in the SORTL-QAF function is described with reference to FIG. 3I. In one example, the parameter block 340 for the SORTL-QAF function (eg, function code 0) includes an installed function vector 342, an installed interface size vector 344, and an installed parameter block format vector 346. In a specific example, these vectors are stored in byte 0 to 15, byte 16 and byte 24 to 25 of the parameter block, respectively. Each of these vectors is further described below.

As an example, bits 0 to 127 of the installed function vector 342 correspond to function codes 0 to 127 of the sorted list command, respectively. When the bit is one, for example, the corresponding function is installed; otherwise, the function is not installed.

In addition, in one example, bits 0 to 7 of the installed interface size vector 344 indicate the interface sizes available for the program. The interface size is the number of input lists to be designated by the program for the SORT-SFLR and SORTL-SVLR functions. In one example, bits 0 to 7 of the installed interface size vector 344 correspond to the following interface sizes: bits 0, 1, 5 to 7 are reserved; bit 2-32 input lists; bit 3-64 Input list; and 4-128 input list. Other examples are also possible.

When the bit of the installed interface size vector 344 is, for example, one, the corresponding interface size can be used in the program. One or more bits can be stored as one. For example, a binary value of 00101000 indicates that the interface sizes of 32 and 128 input lists are available. In one example, bits 0 to 1 and 5 to 7 are reserved and stored as zero. In addition, in one example, when the enhanced sorting facility is installed, the interface size of 32 input lists is available. Therefore, bit 2 is stored as one. Other examples are also possible.

In addition to the above, in one example, bits 0 to 15 of the installed parameter block format vector 346 correspond to parameter block formats 0 to 15, respectively. When the bit is one, for example, the corresponding parameter block format is installed; otherwise, the parameter block format is not installed. In one example, zeros are stored in reserved bytes 17 to 23 and 26 to 31 of the parameter block.

The SORT-QAF function ignores the contents of the general purpose registers R ₁ , R ₂ , R ₁ +1 and R ₂ +1.

Where applicable, program event record (PER) memory change events are identified for parameter blocks. When applicable, PER zero address detection events are identified for parameter blocks.

In one example, when the execution of the SORTL-QAF function is completed, condition code 0 is set; condition codes 1, 2, and 3 are not applicable to the query function.

Function code 1 : SORTL-SFLR ( Sort fixed length records )

In one example, a set of input lists is sorted and stored as a set of output lists at the first operand location. Each list is a set of records, and referring to FIG. 3J, each record 350 includes a key 352 (for example, a fixed-length key) and a payload 354 (for example, a fixed-length payload).

Sort records from the input list based on the value of the key. The records may be sorted in ascending or descending order specified in the sort order (SO) field of the parameter block associated with function code 1 as described below. The records entered in the list may or may not be listed in sorted order.

The records of the output list can be derived from multiple input lists and stored in sorted order. The number of output lists stored at the first operand position depends on the input data. In one example, when each active input list contains records listed in the same order as specified in the SO field, only one output list is generated.

As indicated above, bit 56 of general purpose register 0 specifies the mode of operation applied to the SORTL-SFLR function, which is called the merge mode (MM). When the merge mode is, for example, zero, for each output list stored at the first operand position, the corresponding output list drawing (OLD) is stored at the second operand position. Each OLD includes, for example, an 8-byte OLD address, which indicates the position of the first record in the corresponding output list; and an 8-byte OLD length, which specifies the length of the corresponding output list in bytes, for example. When the merge mode is one, the input list is considered pre-sorted. That is, each active input list is considered to contain records in the same order as specified by the SO field of the parameter block.

When MM is one and each input list is pre-sorted, the result stored at the first operand position is a single output list of records in sorted order. When MM is one and each input list is not pre-sorted, the result is unpredictable.

When MM is, for example, one, the contents of the general registers R ₂ and R ₂ +1 are ignored and no information is stored at the second operand location. When MM is one, the procedure to distinguish the separation between the output lists may not be implemented, thereby potentially improving the performance of the operation. When MM is one, the data is not saved to the connection record re-call buffer described below.

In one example, to generate a single list of records in sorted order from a set of records in random order, the program may implement the following procedure:

1. Split the set of records evenly among a set of initial lists, where each list contains records in random order. When the initial list is used as the input list and the merge mode is equal to zero, the sort list command is executed to generate a set of intermediate lists (each of which contains records in sorted order), and each of the set of intermediate lists The storage location and length of the list.

2. When the set of intermediate lists is used as the input list and the merge mode is equal to one, execute the sort list command to generate a final and single list, which contains records in sorted order.

An example of SORTL-SFLR with merge mode equal to zero is illustrated in FIG. 4A. The input and the resulting output are included in this example. As shown, there are three input lists 400: input list0, input list1, and input list2. In addition, examples of the obtained first operand 402 and second operand 404 are depicted. In one example, there are three lists in the first operand 402 (FIG. 4A), and as shown in the second operand 404, one list starts at address 1000 and has a length of 18; the other list starts at bit The address 1018 has a length of 28; and the third list starts at the address 1040 and has a length of 20.

In one example, when two operations implement the same SORTL-SFLR function with the merge mode equal to zero on the same set of unsorted input records and the only difference between the two operations is the number of input lists used to specify the input data, Operations with a larger number of input lists produce a smaller number of output lists. FIG. 4B illustrates an example of using six input lists 450 to operate on the same input data as in the example of using three input lists in FIG. 4A. Also depicted is a resulting first operand 452 with two instead of three output lists and a depicted second operand 454 that provides two output lists.

As indicated, the SORTL-SFLR function uses a parameter block, and an example of the parameter block is described with reference to FIG. 3K. In the example parameter block described herein, a specific location and a specific size of the field (eg, a specific byte and/or bit) for a specific field within the parameter block are indicated. However, other positions and/or sizes may be provided for one or more of these fields. In addition, although it is specified that the bit is set to a specific value such as one or zero, this is only an example. In other examples, the bits may be set to different values, such as opposite values or another value. Many changes are possible.

In one example, the parameter block 360 for the SORTL-SFLR function includes the following:

Parameter block version number (PBVN) 362: Bytes 0 to 1 of the parameter block specify the version and size of the parameter block. Bits 0 to 7 of PBVN have the same format and definition as bits 0 to 7 of the installed interface size list vector (byte 16) used in the parameter block of the SORTL-QAF (query) function. Bits 0 through 7 specify the number of input lists N _IS described in the parameter block. The size of the parameter block in bytes is determined by the evaluation formula (576+16×N _IS ). One of the bits 0 to 7 will have a value of one; otherwise, the general operator data exception is recognized. Bits 8 to 11 of PBVN are reserved and should contain zero; otherwise, the program may not be compatible in the future. Bits 12 to 15 of PBVN contain unsigned binary integers that specify the format of the parameter block. The SORTL-QAF function provides a mechanism to indicate the available parameter block format. When the model does not support the specified size or format of the parameter block, an exception to the general operation metadata is recognized. PBVN is specified by the program and will not be modified during the execution of the command.

Model Version Number (MVN) 364: Byte 2 of the parameter block is an unsigned binary integer that identifies the model that executes the instruction. The MVN is updated by, for example, the processor during execution of the instruction. The values stored in MVN are model dependent.

When the continuous flag (CF) 368 described below is one, the MVN is the input for the operation. When the CF is one and the MVN recognizes the same model as the currently executing instruction, the data from the connection state buffer (CSB) 390 described below can be used to resume the operation. When CF is one and MVN recognizes a model that is different from the currently executing instruction model, part or all of the CSB field can be ignored.

In one example, the program initializes MVN to zero. I anticipate that the program will not modify the MVN if the instruction is re-executed for the purpose of resuming operation; otherwise, the result is unpredictable.

Sort Order (SO) 366: Bit 56 of the parameter block, which specifies ascending sort order when it is zero and descending sort order when it is one. When ascending sort order is specified, each record in the output list contains a key that is greater than or equal to the adjacent record (for example, on the left) in the same output list. When a descending sort order is specified, each record in the output list contains a key that is less than or equal to the adjacent record (for example, on the left) in the same output list. SO is not updated during instruction execution.

Connection flag (CF) 368: Bit 63 of the parameter block, which indicates that the operation is partially completed and the content of the connection status buffer 390 when it is one, and when the merge mode (MM) is zero, the connection record is called again The contents of the buffer can be used to resume operation. The program initializes the continuation flag (CF) to zero and does not modify the CF if the instruction is re-executed for the purpose of resuming the operation; otherwise, the result is unpredictable. In one example, the processor modifies the CF if it will re-execute the instruction.

Record key length 370: Bytes 10 to 11 of the parameter block contain unsigned binary integers that specify the size in bytes of the key in the record processed during the operation. In one example, for any of the following conditions, a general operator metadata exception is recognized:

* Specify the key size of zero bytes.

*Specify the key size that is not a multiple of 8.

* Specify the key size larger than 4096 bytes.

The record key length is not updated during command execution.

Record payload length 372: When the SORTL-SFLR function is specified, the bytes 14 to 15 of the parameter block contain the unsigned sign two that specifies the size in bytes of the payload in the record processed during the operation Rounded integer. In one example, for any of the following conditions, a general operator metadata exception is recognized:

* Specify a payload size that is not a multiple of 8.

* The sum of the specified key size and payload size is greater than 4096 bytes.

Zero payload size is valid.

When the SORTL-SVLR function is specified, the record payload length field of the parameter block is ignored. The record payload length is not updated during instruction execution.

Operand Access Intent (OAI) 374: Bits 0 to 1 of byte 32 of the parameter block send to the CPU a future access intention for the input list and the first operand. The provided access intent can be used to modify cache line installation and replacement strategies for corresponding storage locations at various levels of cache memory in the storage hierarchy.

When bit 0 of the OAI field is one, the storage location specified to contain any active input list data will be referred to as one or more operands of the subsequent command. When bit 0 of the OAI field is zero, the storage location specified to contain any active input list data will not be referenced as one or more operands of the subsequent command.

When bit 1 of the OAI field is one, the storage location specified to contain the first operand will be referred to as one or more operands of the subsequent instruction. When bit 1 of the OAI field is zero, the storage location specified to contain the first operand will not be referenced as one or more operands of the subsequent instruction.

The CPU is not guaranteed to use this information. The duration for which this information can be used is not defined, but it is limited.

When the next sequential instruction after the next instruction access intention (NIAI) is a sorted list (SORTL), the execution of SORTL is not affected by NIAI.

OAI is not updated during instruction execution.

Active input list count code (AILCC) 376: Bits 1 to 7 of byte 33 of the parameter block are 7-bit unsigned integers, which specify the boundary between the active input list and the non-active input list The number of the input list. The input list with the list number that is less than or equal to the value of the AILCC field, for example, is in the active state. The input list with a list number greater than the value of the AILCC field, for example, is in an inactive state. The number of input lists in the active state is one greater than the value in the AILCC field.

The input list in the active state participates in the operation. The input list in the non-active state does not participate in the operation.

Bit 0 of byte 33 of the parameter block is reserved and should contain zero; otherwise, the program may not be compatible in the future.

In one example, when the value of the AILCC field plus a number greater than the number of input lists described in the parameter block (as specified by bits 0 to 7 of the PBVN field), an exception is recognized for general arithmetic data situation.

The value specified in the AILCC field does not affect the size of the parameter block. The access exception is applicable to specify the field of the reference parameter block corresponding to the input list address or length of the input list in the inactive state.

AILCC is not updated during instruction execution.

Empty input list control item (EILCL) 378: When bit 0 of byte 40 of the parameter block is one, when the length of input list0 becomes zero during the operation, the operation ends. When bit 0 of byte 40 of the parameter block is zero, when the length of input list0 becomes zero during the operation, the operation continues. When bit 1 of byte 40 of the parameter block is one, when the length of the input list becomes zero during the operation except for input list0, the operation ends. When bit 1 of byte 40 of the parameter block is zero, when the length of the input list becomes zero during the operation other than input list0, the operation continues.

When the length of the active input list is initially zero before the instruction is executed, the corresponding bit of EILCL is not applied.

EILCL is not updated during instruction execution.

I anticipate that the program will not modify EILCL if the instruction is re-executed for the purpose of resuming operation; otherwise, the result is unpredictable.

Empty input list flag (EILF) 380: When EILCL is 11 binary and the operation ends because the updated length of the active input list is equal to zero and condition code 2 is set, for example, the value 1 is stored in the parameter block by the processor Bit 2 of byte 40; otherwise, the value zero is stored in bit 2 of byte 40 of the parameter block. When EILF contains the value one, the input list number of the input list that becomes empty during the operation is placed in the EILN field of the parameter block. In one example, the program initializes EILF to zero.

When resuming operation, refer to EILF at the beginning of instruction execution. We expect that the program will not modify the EILF if the instruction is re-executed for the purpose of resuming the operation; otherwise, the result is unpredictable.

Empty input list number (EILN) 382: When the condition is such that the value one is stored in the EILF field, for example by the processor storing the input list number of the input list that became empty during operation in the bit of the parameter block Group 41; otherwise, store the value zero in byte 41 of the parameter block.

EILN is ignored at the beginning of the operation. In one example, the program initializes EILN to zero.

Incomplete input list flag (IILF) 384: When the operation ends due to an attempt to process an incomplete input list, for example, the processor stores the value one to bit 0 of byte 46 of the parameter block; otherwise, it will The value zero is stored in bit 0 of byte 46 of the parameter block. When the length of the corresponding input list is greater than zero and less than the number of bytes of the record specified by the input list address, the active input list is considered to be incomplete. This condition may exist at the beginning of the operation, or it may be encountered during the operation. When the IILF contains the value one, the input list number of the incomplete input list encountered is placed in the IILN field of the parameter block. In one example, the program initializes IILF to zero.

When the operation ends with the set condition code 2 and the resulting value in the IILF field is zero, the operation ends because of an empty input list. When the operation ends with the set condition code 2 and the resulting value in the IILF field is one, the operation ends because of an incomplete input list.

When resuming operation, refer to IILF at the beginning of instruction execution. We expect that the program will not modify the IILF if the instruction is re-executed for the purpose of resuming the operation; otherwise, the result is unpredictable.

Incomplete input list number (IILN) 386: When the condition is such that the value one is stored in the IILF field, for example, the processor stores the input list number of the incomplete input list encountered in the byte of the parameter block 47; otherwise, store the value zero in byte 47 of the parameter block. When multiple input lists are incomplete, they are model dependent, where the incomplete input list number is stored in the IILN field. In one example, the program initializes IILN to zero.

IILN is ignored at the beginning of the operation.

Connection record re-call buffer starting point 388: Under the condition that the operation ends and can be resumed later, the program provides the CPU with a 4K byte buffer in the memory (referred to as the connection record re-call buffer), to Store and refer to the data between two executions of the same sorted list command. Fifty-two bits of the parameter block (starting from bit 0 of byte 56 to bit 3 of byte 62) contain unsigned binary integers used in the formation of the connection record to recall the address, The connection record recall address is aligned on the 4K byte boundary. The connection record recall address is, for example, the logical address of the leftmost byte of the connection record recall buffer.

In the 24-bit addressing mode, bits 40 to 51 at the beginning of the connection record recall buffer with 12 zeros added to the right form the connection record recall address. In the 31-bit addressing mode, bits 33 to 51 at the beginning of the connection record recall buffer with 12 zeros added to the right form the connection record recall address. In the 64-bit addressing mode, bits 0 to 51 at the beginning of the connection record recall buffer at the right are appended with 12 zeros to form the connection record recall address.

In the access register mode, the access register 1 specifies the address space containing the recall buffer of the continuous record in the memory.

When the merge mode (MM) is zero, the operation ends after one or more records are stored and normal completion does not occur. The key of the last record stored in the first operand is also stored in the subsequent record recall buffer. When MM is one, the starting point of the buffer is called again, ignoring the connection record.

Recall the starting point of the buffer without modifying the connection record during the execution of the instruction.

We expect that in the case of re-executing the command for the purpose of resuming the operation, the program will not modify the connection record and call the starting point of the buffer again; otherwise, the result is unpredictable.

Connection Status Buffer (CSB) 390: When the condition is such that the value one is stored in the CF field, for example, the processor stores the internal state data in bytes 64 to 575 of the parameter block; otherwise, the parameter block Bytes 64 to 575 are undefined and can be modified. The stored internal state data is model dependent, and can be used later when the command is re-executed to resume the operation. In one example, the program initializes the connection status buffer to zero. We expect that the program will not modify the connection status buffer if the command is re-executed for the purpose of resuming operation; otherwise, the result is unpredictable.

As an example, the internal status data includes information related to the input list, such as information about previous comparisons of records of the input list, to determine the subsequent comparison to be made. The internal state data is model dependent, because it can be stored or presented in different ways depending on the processor model. Other changes are possible.

In one embodiment, the command may be partially completed by one model in a configuration, and execution may be resumed on different models in the configuration. Although in one embodiment, different models may maintain different internal states, in one example, each model will be able to interpret the content of the CSB (if any) to resume operation. When the operation resumes, the MVN indicates to the machine which contents of the CSB (if any) can be interpreted.

Input ListN address 392, 394, 396: The parameter block defines multiple input lists. The number N _IS of the input list defined in the parameter block is specified by bits 0 to 7 of PBVN 362. Number the input list from zero to (N _IS -1). For each input list, the parameter block specifies, for example, an 8-byte input list address. For input list number N, the content of bytes 576+16×N to 583+16×N of the parameter block specifies, for example, the logical address of the leftmost byte of input list number N in the memory.

If specified by the AILCC field, each input list address corresponding to the input list in the active state is the input of the operation and is updated by the operation. If specified by the AILCC field, each input list address corresponding to the input list in the inactive state is ignored by the operation.

In one embodiment, when the input list address is an operation input, the following situations apply:

* In the 24-bit addressing mode, bits 40 to 63 of the input list address indicate the position of the leftmost byte of the input list in the memory, and the contents of bits 0 to 39 of the input list address are viewed Is zero.

* In the 31-bit addressing mode, bits 33 to 63 of the input list address indicate the position of the leftmost byte of the input list in the memory, and the contents of bits 0 to 32 of the input list address are viewed Is zero.

* In the 64-bit addressing mode, bits 0 to 63 of the input list address indicate the position of the leftmost byte of the input list in the memory.

In the access register mode, the access register 1 specifies the address space in the memory that contains the active input list.

For the input list in the active state, the address of the corresponding input list will be indicated on the double-word boundary; otherwise, in one example, the exception of general operational metadata is recognized.

In one embodiment, when the input list address is updated by the operation, the following situations apply:

* When one or more records of the processed input list are processed as part of the operation, the corresponding input list address is incremented by the number of bytes occupied by the processed record in the memory. The formation and update of the input list address depends on the addressing mode.

* In the 24-bit addressing mode, the updated input list address bits 40 to 63 replace the corresponding bits in the input list address field of the parameter block, ignoring the updated input list address bit Carry output at position 40, and set the content of bit positions 0 to 39 of the input list address field of the parameter block to zero.

* In the 31-bit addressing mode, bits 33 to 63 of the updated input list address replace the corresponding bits in the input list address field of the parameter block, ignoring the bits of the updated input list address Carry output at position 33, and set the contents of bit positions 0 to 32 of the address field of the input list of the parameter block to zero.

* In the 64-bit addressing mode, the updated input list address bits 0 to 63 replace the corresponding bit in the input list address field of the parameter block, and ignore the updated input list address bit The carry output of the meta position 0.

In the 24-bit addressing mode and the 31-bit addressing mode, when the command execution ends and the command is not suppressed, set to null (nullify), or terminated, each 64-bit input list corresponding to the active input list is updated Address, even when the address is not incremented.

Input ListN lengths 393, 395, 397: For each input list, the parameter block specifies the 8-byte input list length. For input list number N, the bytes 584+16×N to 591+16×N of the parameter block contain unsigned integers that specify the number of bytes in input list number N.

If specified by the AILCC field, the length of each input list corresponding to the active input list is the input of the operation and is updated by the operation. If specified by the AILCC field, the length of each input list corresponding to the input list in the inactive state is ignored by the operation.

In various addressing modes, the contents of bit positions 0 to 63 of the input list length field specify the length of the corresponding input list.

When one or more records of the processed input list are processed as part of the operation, the length of the corresponding input list is decremented by the number of bytes occupied by the processed record in the memory. In various addressing modes, bits 0 to 63 of the updated input list length replace bits 0 to 63 in the corresponding input list length field of the parameter block.

Reserved: There are several reserved fields in the parameter block (for example, fields that do not include other information). As input to the operation, the reserved field should contain zero; otherwise, the program may not be able to operate in a compatible manner in the future. When the operation ends, the reserved field can be stored as zero or can remain unchanged.

5A to 5B summarize an example of the original value and final value of the input (including the field in the parameter block) of the SORTL-SFLR function.

In one embodiment, for the purpose of resuming the operation, it is unnecessary and undesirable for the program to modify the parameter block between ending the operation with the set condition code 3 and branching back to the instruction to re-execute the instruction.

In one embodiment, the SORTL-SFLR function includes multiple comparisons between recorded keys from different input lists. In one example, when comparing keys, the following applies:

* The key is regarded as a binary integer without sign, also known as unstructured data.

* When determining which key contains the lowest or highest value, it may not be necessary to access all the bytes of each key being compared. The number of bytes of each key in a comparison (called the key comparison unit) is model dependent. The number of bytes of the accessed key is an integer number of key comparison units.

* When comparing keys with equal values, in one example, the key from the input list with the highest input list number is selected to be before other keys with the same value in sort order. In this case, the corresponding record from the input list with the highest input list number is stored in the first operand before other records with the same key value. This applies to ascending and descending sort order.

One embodiment may maintain a history of previous comparisons between records from the active input list. When history is available and applicable, instead of accessing and comparing previously compared records, you can refer to history. Reference history reduces the execution time required to produce results, thereby improving processing within the computing environment.

The SORTL-SFLR function includes selecting records from a set of input lists in a specified sort order and placing the selected records at the first operand position. As the operation continues, the current value of the first operand address and the address of the active input list is maintained. The function continues with the operating unit. During each operation unit, for each active input list, the key indicated by the corresponding current input list address is checked and a record is placed at the first operand position.

When the merge mode (MM) is zero, the active input list indicates that each is regarded as a list containing records in a random order from left to right, for example. When MM is zero, the record stored in the first operand position constitutes one or more output lists, and the start address and length of each output list are stored in the second operand position. When MM is zero, as an example, each operation unit includes the following steps in the specified order:

1. Determine whether a record to be stored under the first operand position can be included in the most recent output list (including the output list of the record most recently stored in the first operand position), as follows:

* When the connection flag (CF) is zero and the first operating unit is being processed, no record has been stored in the first operand location, and the next record to be stored will be the first record in the output list.

* When CF is one, the previous execution of the instruction ends with condition code 1 and the first operation unit is being processed for the current execution of the instruction, the next record to be stored will be the first record of the output list.

* When CF is one, IILF is zero, and EILF is zero, the previous execution of the instruction ends with condition code 2 and the first operation unit is being processed for the current execution of the instruction, the next record to be stored will be the first of the output list recording.

* When CF is one, IILF or EILF is one, the previous execution of the instruction ends with condition code 2 and the first operation unit is being processed for the current execution of the instruction, the next record to be stored can be included in the recent output list.

* When CF is one, the previous execution of the instruction ends with condition code 3 and the first operation unit is being processed for the current execution of the instruction, the next record to be stored may be included in the most recent output list.

* When the operation unit being processed is not the first operation unit currently used for the instruction, the next record to be stored can be included in the most recent output list.

2. When the next record to be stored can be included in the recent output list, the determination is limited to a set of records included in the recent output list. For each input list that is active, not empty, and not incomplete, compare the key of the record specified by the address of the current input list (the current input key) with the key of the record most recently stored to the first operand position ( Save the key previously). For this purpose, the reference to the previously stored key is not a reference to the position of the first operand. The fact is that it is a reference to the input list for the selection key, or it is a reference to the recall buffer for the connection record. When the operation is being resumed and the current execution of the instruction has not placed any record at the position of the first operand, the reference is a reference to re-call the buffer for the continued record.

When the sort order is ascending and the value of the current input key is greater than or equal to the value of the previously stored key, the current input key is considered to belong to a set of keys limited to be included in the most recent output list. When the sorting order is descending and the value of the current input key is less than or equal to the value of the previously stored key, the current input key is regarded as belonging to a group of keys restricted to be included in the most recent output list. When the number of keys in the set of keys included in the most recent output list is zero, the next record to be stored will be the first record in the output list. When the number of keys defined in the set of keys included in the most recent output list is non-zero, the next record to be stored will be included in the most recent output list.

3. When the next record to be stored will be included in the recent output list, the comparison is limited to the keys in the set of keys included in the recent output list. When the sort order is ascending, select the minimum key value and corresponding record. When the sort order is descending, select the maximum key value and corresponding record.

4. When the next record to be stored will be the first record of the output list, compare the key of the record specified by the current input list address corresponding to the active, non-empty and not incomplete input list. When the sort order is ascending, select the minimum key value and corresponding record. When the sort order is descending, select the maximum key value and corresponding record.

5. Place the selected record at the current first operand position.

6. The current first operand address increments by the number of bytes equal to the length of the selected record.

7. The address of the current input list corresponding to the input list containing the selected record is incremented by the number of bytes equal to the length of the selected record.

When the merge mode is zero, as part of the operation, for each output list stored at the first operand location, the corresponding output list drawing (OLD) is stored at the second operand location. Each OLD includes, for example, an 8-byte OLD address, which indicates the position of the first record in the corresponding output list; and, for example, an 8-byte OLD length, which specifies the length in bytes corresponding to the output list. When the operation ends with condition code 3 and condition code 2 and EILF are equal to one or condition code 2 and IILF are equal to one, the most recent output list being processed at the end of the operation may be partially processed and not fully processed. That is, the number of records in the partially processed output list is an intermediate value and can be increased when the operation resumes. In this case, the output list drawing (OLD) corresponding to the partially processed output list is not placed at the second operand position until the operation is resumed and the output list is completely processed.

When the merge mode is zero and the operation ends after storing one or more records and normal completion does not occur, the key of the last record stored in the first operand position is also stored in the subsequent record recall buffer.

When the merge mode is zero and the operation ends due to normal completion, one or more output lists have been placed at the first operand position and the output list depiction has been placed at the second operand position. The program can use the output list to describe the address and length values of the input list in the parameter block for subsequent SORTL operations.

6A to 6D illustrate the first operand and the second operand before or after the SORTL-SFLR in which the merge mode is equal to zero. 6A to 6B, FOSA 600 is the first operand start address: the location specified by R ₁ ; FOEA 602 is the first operand end address: specified by R ₁ +(R ₁ +1)-1 Location; and OL 604 is an output list (eg, output list 1...output list N). In addition, referring to FIGS. 6C to 6D, SOSA 610 is the start address of the second operand: the position specified by R ₂ ; SOEA 612 is the end address of the second operand: from R ₂ +(R ₂ +1)-1 The specified location; and OLD 614 is the output list specification (for example, the output list specification 1...the output list specification N).

When the merge mode (MM) is one, the active input list indicates that each is considered to contain a list of records that are sorted from left to right as specified by the SO field of the parameter block. When MM is one, the record stored in the first operand position constitutes a single output list. As an example, when MM is one, each operation unit includes, for example, the following steps in a specified order:

1. Compare the keys of the records specified by the current input list address corresponding to the active, non-empty and not incomplete input list. When the sort order is ascending, select the minimum key value and corresponding record. When the sort order is descending, select the maximum key value and corresponding record.

2. Place the selected record at the current first operand position.

3. The current first operand address increments by the number of bytes equal to the length of the selected record.

4. The address of the current input list corresponding to the input list containing the selected record is incremented by the number of bytes equal to the length of the selected record.

7A to 7B illustrate the first operand before or after performing the SORTL-SFLR with the merge mode equal to one. 7A to 7B, FOSA 700 is the start address of the first operand: the position specified by R ₁ ; FOEA 702 is the end address of the first operand: specified by R ₁ +(R ₁ +1)-1 Location; and OL 704 is an output list (eg, output list 1).

When the merge mode is zero or one, as part of the operation, the input list address and length of the input list in the active state are updated. For each input list in the active state, the input list address is incremented by the number of bytes from the input list's records selected during the operation and placed at the first operand position, and the input list length is decremented by the same number. The formation and update of the input list address depends on the addressing mode.

As the operation continues, an incomplete input list may be encountered. During an operation unit attempting to refer to a record from an incomplete input list, an incomplete input list was identified. Multiple operating units can be completed before an incomplete input list is recognized. This applies when the merge mode is zero or one.

As the operation continues, access exceptions to the access input list, the first operand, or the second operand (where applicable) may be encountered. An access exception was recognized during the operation unit attempting to access the storage location, and there was an access exception for that location. Multiple operating units can be completed before an access exception is recognized. This applies when the merge mode is zero or one.

When the operation ends with partial completion, the internal state data, which can include the history of the previous comparison between the records, is stored in the CSB field of the parameter block. Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB can be loaded into the implementation and the history can be referred to when the operation resumes. This applies when the merge mode is zero or one.

When the records from the active input list are sorted and stored in the first operand, normal completion occurs.

In one embodiment, when the operation ends due to normal completion, the following occurs:

* Respectively update the address and length in the general registers R ₁ and R ₁ +1.

* When MM is zero, update the address and length in the general registers R ₂ and R ₂ +1 respectively.

* For the input list in the active state, update the input listN address field and input listN length field.

* Set the model version number.

* Set the connection flag to zero.

* Set the empty input list flag to zero.

* Set the empty input list number to zero.

* Set the incomplete input list flag to zero.

* Set the incomplete input list number to zero.

* Set condition code 0.

The formation and update of the address and length depend on the addressing mode.

When normal completion occurs, the CSB field of the parameter block is undefined after the operation is completed.

In one embodiment, when the processed CPU determines the number of bytes, the operation ends and the following occurs:

* Respectively update the address and length in the general registers R ₁ and R ₁ +1.

* When MM is zero, update the address and length in the general registers R ₂ and R ₂ +1 respectively.

* For the input list in the active state, update the input listN address field and input listN length field.

* Set the model version number.

* Set the connection flag to one.

* When MM is zero and one or more records have been placed at the position of the first operand during the execution of the command, store the key value in the connection record and call the buffer again.

* Update the connection status buffer.

* Set the empty input list flag to zero.

* Set the empty input list number to zero.

* Set the incomplete input list flag to zero.

* Set the incomplete input list number to zero.

* Set condition code 3.

The formation and update of the address and length depend on the addressing mode.

The number of CPU decisions for bytes depends on the model, and can be a different number each time an instruction is executed. The CPU determination number of bytes is usually non-zero. Although this number may be zero and appear as a non-progressive condition, the CPU prevents the infinite recurrence of this non-progressive condition.

After the instruction ends with, for example, setting condition code 3, we expect that the program does not modify any input or output specifications of the instruction and branches back to re-execute the instruction to resume the operation.

In one embodiment, when bit 0 of the empty input list control (EILCL) is one and the length of the input list0 becomes zero during the operation and normal completion is not applicable, the operation ends and the following occurs:

* Respectively update the address and length in the general registers R ₁ and R ₁ +1.

* When MM is zero, update the address and length in the general registers R ₂ and R ₂ +1 respectively.

* For the input list in the active state, update the input listN address field and input listN length field.

* Set the model version number.

* Set the connection flag to one.

* When EILCL is 10 binary and MM is zero, the key value can be stored in the connection record to re-call the buffer. When EILCL is 11 binary and MM is zero, the key value can be stored in the connection record to recall the buffer. In either case, one or more records have been placed at the first operand location during execution of the instruction.

* Update the connection status buffer.

* Set an empty input list flag (see Figure 8 which depicts various parameter block fields at the end of the operation).

* Set an empty input list number (see Figure 8).

* Set the incomplete input list flag to zero.

* Set the incomplete input list number to zero.

* Set condition code 2.

The formation and update of the address and length depend on the addressing mode.

In one embodiment, when bit 1 of the empty input list control (EILCL) is one and the length of the input list during the operation other than input list0 becomes zero during the operation and normal completion is not applicable, the operation ends and the following conditions occur:

* Respectively update the address and length in the general registers R ₁ and R ₁ +1.

* When MM is zero, update the address and length in the general registers R ₂ and R ₂ +1 respectively.

* For the input list in the active state, update the input listN address field and input listN length field.

* Set the model version number.

* Set the connection flag to one.

* When EILCL is 01 binary and MM is zero, the key value can be stored in the connection record to re-call the buffer. When EILCL is 11 binary and MM is zero, the key value can be stored in the connection record to recall the buffer. In either case, one or more records have been placed at the first operand location during execution of the instruction.

* Update the connection status buffer.

* Set the empty input list flag (see Figure 8).

* Set an empty input list number (see Figure 8).

* Set the incomplete input list flag to zero.

* Set the incomplete input list number to zero.

* Set condition code 2.

The formation and update of the address and length depend on the addressing mode.

In one embodiment, when an incomplete input list is encountered in the active state, the operation ends and the following occurs:

* Respectively update the address and length in the general registers R ₁ and R ₁ +1.

* When MM is zero, update the address and length in the general registers R ₂ and R ₂ +1 respectively.

* For the input list in the active state, update the input listN address field and input listN length field.

* Set the model version number.

* Set the connection flag to one.

* When MM is zero and one or more records have been placed at the position of the first operand during the execution of the command, store the key value in the connection record and call the buffer again.

* Update the connection status buffer.

* Set the empty input list flag to zero.

* Set the empty input list number to zero.

* Set the Incomplete Input List Flag (IILF) to one.

* Place the input list number of the incomplete input list encountered in the IILN field of the parameter block.

* Set condition code 2.

The formation and update of the address and length depend on the addressing mode.

In one embodiment, when the length of the first operand is insufficient to store another record, the operation ends and the following occurs:

* Respectively update the address and length in the general registers R ₁ and R ₁ +1.

* When MM is zero, update the address and length in the general registers R ₂ and R ₂ +1 respectively.

* For the input list in the active state, update the input listN address field and input listN length field.

* Set the model version number.

* Set the connection flag to one.

* When MM is zero and one or more records have been placed at the position of the first operand during the execution of the command, the key value can be stored in the connection record to recall the buffer.

* Update the connection status buffer.

* Set the empty input list flag to zero.

* Set the empty input list number to zero.

* Set the incomplete input list flag to zero.

* Set the incomplete input list number to zero.

* Set condition code 1.

The formation and update of the address and length depend on the addressing mode.

In one embodiment, when the merge mode (MM) is zero and the length of the second operand is less than 16, the operation ends and the following occurs:

* Respectively update the address and length in the general registers R ₁ and R ₁ +1.

* Update the address and length in the general registers R ₂ and R ₂ +1 respectively.

* For the input list in the active state, update the input listN address field and input listN length field.

* Set the model version number.

* Set the connection flag to one.

* When one or more records have been placed at the position of the first operand during the execution of the command, the key value can be stored in the connection record to re-call the buffer.

* Update the connection status buffer.

* Set the empty input list flag to zero.

* Set the empty input list number to zero.

* Set the incomplete input list flag to zero.

* Set the incomplete input list number to zero.

* Set condition code 1.

The formation and update of the address and length depend on the addressing mode.

When the instruction execution ends with completion (not with suppression, set to null, or with termination) and normal completion does not occur, the operation end condition is called partial completion.

When applicable, for the part of the first operand position, the second operand position, the connection record recall buffer and the stored parameter block, the PER memory change event is recognized. When a PER memory change event is recognized, before reporting the event, less than 4K extra bytes are stored to the operand position that intersects the specified PER memory area.

When applicable, PER zero address detection events are identified for the parameter block, the first operand position, and the second operand position. Zero address detection does not apply to the input list address and connection record specified in the parameter block to call the buffer starting point again.

For a description of examples of other conditions applicable to the SORTL-SFLR function, please refer to the other conditions below.

When the command ends with condition code 1, the program can modify the first operand address, the first operand length, the second operand address, the second operand length, any active input list address and any when appropriate Enter the length of the list while it is active, and then resume the operation again.

When the instruction ends with condition code 2, IILF is equal to zero and EILF is equal to zero, the program can modify the first operand address, first operand length, second operand address, second operand length, any action as appropriate Enter the list address and any active input list length, and then resume the operation again.

When the command ends with condition code 2 and EILF is equal to one, the program can modify the input list address and length of the input list specified by EILN as appropriate, and then resume the operation again. In this case, the program can also modify the first operand address and the first operand length when the merge mode (MM) is one.

When the command ends with condition code 2 and IILF is equal to one, the program can modify the input list address and length of the input list specified by IILN as appropriate, and then resume the operation again. In this case, the program can also modify the first operand address and the first operand length when the merge mode (MM) is one.

When the command ends with condition code 3 and before re-executing the command to resume the operation, the program modifies any active input list address or length, first operand address or length or second operand address or length, the result As unpredictable.

Function code 2 : SORTL-SVLR ( Sort variable length records )

The SORTL-SVLR function operates the same as the SORTL-SFLR function, except for the following cases:

* For example, as shown in FIG. 9, the record includes a fixed-length key 900, an 8-byte payload length (PL) 902, and a variable-length payload 904. Therefore, the record has a variable length.

* Ignore bytes 14 to 15 of the parameter block used in the SORTL-SVLR function.

* The least significant, for example, 2 bytes in the payload length field of each record contains unsigned integers that specify the length in bytes of the payload in the same record. The payload length of zero is valid. In one example, the payload length will be, for example, a multiple of 8; otherwise, a general arithmetic metadata exception is recognized. The most significant 6 bytes of the payload length field (as an example) are reserved and should contain zero; otherwise, the program may not be compatible in the future. In one example, the sum of the key length eight and the payload length is not greater than, for example, 4096; otherwise, an exception to the general operation metadata is recognized. When an exception condition of a general operand data is recognized due to an inappropriate payload length, the input list address corresponding to the input list in which the exception condition is encountered specifies the logical address of the leftmost byte of the error record. When storing variable-length records to the first operand position, the reserved bytes of the payload length field are not modified.

* During the operation unit that only attempts to refer to the key of the record from the input list whose input list length is greater than the key size and smaller than the record size, the incomplete input list may not be recognized. In this situation, the incomplete input list will be recognized when attempting to save the record from the incomplete input list to the first operand location.

The parameter block used in the SORTL-SVLR function is the same as the parameter block used in the SORTL-SFLR function, except for bytes 14 to 15, as indicated above.

For the description of other conditions applicable to the SORTL-SVLR function, please refer to the other conditions below.

Special conditions

In one embodiment, when attempting to perform a sorted list, specification exceptions are identified, and any of the following applies:

* Bits 57 to 63 of general register 0 indicate that the function code is not assigned or installed.

* The R ₁ column indicates the odd-numbered register or general-purpose register 0.

* The R ₂ column indicates the odd-numbered register or general-purpose register 0. This applies when the merge mode (MM) is zero or one.

* The parameter block is not indicated on the double-word boundary.

* Specify SORTL-SFLR function or SORTL-SVLR function, and the first operand is not specified on the double word boundary.

* Specify the SORTL-SFLR function or SORTL-SVLR function, and when MM is zero, the second operand is not specified on the double word boundary.

In one embodiment, when an attempt is made to perform a sorted list, an exception to the general operand data is recognized, and any of the following applies:

* Specify the SORTL-SFLR or SORT-SVLR function, and no bit or multiple bits in the bit number 0 to 7 of the parameter block version number contain the value one. In this case, the operation is suppressed.

* The SORTL-SFLR or SORTL-SVLR function is specified, and the model does not support the size or format of the parameter block as specified by the parameter block version number. In this case, the operation is suppressed.

* Specify the SORTL-SFLR or SORTL-SVLR function, and the record key length specifies a key size of zero, a key size that is not a multiple of 8, or a key size greater than 4096. In this case, the operation is suppressed.

* Specify the SORTL-SFLR function, and the record payload length specifies a payload size that is not a multiple of 8 or a payload size greater than 4096 when added to the key size. In this case, the operation is suppressed.

* Specify the SORTL-SVLR function, and the record payload length specifies a payload size that is not a multiple of 8, or a payload size greater than 4088 when added to the key size. In this case, whether the operation is suppressed or terminated , Which are all model dependent.

* Specify the SORTL-SFLR or SORTL-SVLR function, and the value of the input input list count code (AILCC) plus one greater than the number of input lists described by the parameter block. In this case, the operation is suppressed.

* Specify the SORTL-SFLR or SORTL-SVLR function, and the address of the input list corresponding to the active input list is not specified on the double-word boundary. In this case, the operation is suppressed.

Other conditions

In one embodiment, the following conditions apply:

Instruction execution is interruptible. When an interrupt occurs, update the general register R ₁ and R ₂ in the addresses, the specified _{field. 1} general register R + 1 + 1 and R ₂ in the length of the block and a parameter, such that the instructions in the re The execution resumes at the break point.

For positions greater than 4K bytes to the right of the position indicated by the first operand address, no access exception is recognized. For positions greater than 4K bytes to the right of the position indicated by the input list address, no access exception is recognized.

If the access exception is recognized due to the first operand, the second operand, or any input list, the result is that the exception is recognized or the condition code 3 is set. If condition code 3 is set, it is assumed that the exception condition still exists, and the exception condition will be recognized when the instruction is executed again to continue processing the same operand.

When the recorded key crosses the page boundary and there are access exception conditions for both pages, any access exception can be identified.

When there are access exception conditions for multiple keys being processed during a single operating unit, any of these conditions can be identified.

When the parameter block crosses the page boundary and there are access exception conditions for both pages, the access exception of the leftmost page can be identified.

When the operation ends with partial completion, up to 4K bytes of data may have been stored at the location in the first operand, which is at or at the location specified by the updated first operand address To its right. Such storage causes the setting to change bits when applicable, and recognizes the PER memory change event when applicable. When the instruction is executed again to continue processing the same operand, it will be repeated to the storage of these locations.

As observed by this CPU, other CPUs, and channel programs, the reference to the parameter block, the first operand, the output list drawing buffer, and the active input list can be multiple access references, which are stored The access to locations is not necessarily block-parallel, and the order of these accesses or references is not defined.

In one embodiment, when the specified function is SORTL-SFLR or SORTL-SVLR, the result is unpredictable and any of the following situations apply:

* The parameter block overlaps with any active input list or first operand.

* The input list overlaps the first operand in any function.

* The merge mode is zero and the parameter block overlaps with the second operand or the call record buffer.

* The merge mode is zero and any active input list overlaps with the second operand or connection record re-call buffer.

* The merge mode is zero and the first operand overlaps with the second operand or the connection record re-call buffer.

* The merge mode is zero and the second operand overlaps with the re-call buffer of the connection record.

* Another CPU or channel program stores the recorded key in the input list or the connection record and recalls the buffer.

Condition code obtained by example:

0 Normal completion

1 The length of the first operand is less than the size of the record, or the merge mode is zero and the length of the second operand is less than 16 (that is, the length of the first operand or the length of the second operand is insufficient to continue)

2 An incomplete input list is encountered (IILF=1), or EILCL is non-zero, and the length of the input list becomes equal to zero during the operation (that is, an incomplete or empty input list is encountered).

3 The CPU judgment data has been processed (that is, the CPU judgment is completed).

Program exceptions:

* Access (extract input list; extract and store parameter blocks and connection records to call buffer again; store operands 1 and 2)

* Data with data exception status code (DXC) 0 (general operand)

* Operation (if enhanced sorting facilities are not installed)

* Specifications

* Transactional constraints

The following shows the priority order of the execution of sorted list instructions. When there are multiple conditions with a priority value starting at 13, the recognized condition is the first encountered when the operation continues. When the operation is resumed (the continuation flag is one at the beginning of the execution of the command), the history of previous comparisons between the keys can be used to replace the initial access to the active and not empty input list. As a result, access exceptions for accessing specific input lists may not be encountered at the same processing point compared to when the history of previous comparisons is not used. When processing variable length records, the conditions that vary with the record length can be partially evaluated before the payload length is determined, and these conditions are fully evaluated after the payload length is determined. As a result, when the judgment condition exists after only partially evaluating the requirements rather than after completely evaluating all the requirements, the order of priority observed among such conditions may be different.

Execution Priority (SORTL)

1.-6. Exceptions that have the same priority order as the program interruption conditions of the general condition.

7.A Access exception for second instruction halfword.

7.B Operational exceptions.

7.C Transaction constraints.

8.A Due to the exception of invalid function code or invalid register number specification.

8.B Due to the exception of the specification of the first operand not specified on the double word boundary.

8.C Exception due to the specification that the first operand is not specified on the double word boundary.

8.D Because the second operand does not specify an exception on the double word boundary and the merge mode is zero.

9. Access exceptions for bytes 0 to 7 of the access parameter block.

10. The exception for general operand data due to unsupported values in the PBVN field in the parameter block.

11. Access exceptions for bytes other than bytes 0 to 7 in the access parameter block.

12. Due to the exception of general operand data for invalid values in fields other than PBVN in the parameter block.

13.A Access exceptions to the input list in the access role.

13.B When the merge mode is zero, access to the connection record re-call buffer access exception.

13.C Access exception for access to the first operand.

13.D The access exception for accessing the second operand when the merge mode is zero.

13.E The condition code 2 for the incomplete input list.

13.F Condition code 1 due to the insufficient length of the first operand.

13.G When the merge mode is zero, the condition code 1 due to the insufficient length of the second operand.

13.H An exception to the general operand data of invalid payload length for variable length records.

13.I The condition code 2 for the empty input list.

14. Condition code 3.

Stylized notes. In one embodiment:

1. The expected use of the empty input list control item (EILCL) is as follows:

EILCL(0:1)

(Binary) description

00 Stop after the records from the active input list are sorted (for example, all records from all active input lists).

10 Stop after input list0 (always active) becomes empty.

11 In any role, the input list becomes empty and stops.

2. When the active input list count code (AILCC) is zero, there is only one active input list and the result stored in the first operand position is the same as the data extracted from the input list0.

3. Implement the model of separate instruction and data cache memory. You can use the instruction cache memory to implement the reference extraction of the memory operator of the data in the active input list.

4. When the program expects to call the sorted list with merge mode equal to zero multiple times, as part of processing a large data set, the program will use the available input list in one instance and divide the records evenly among the input lists. This reduces the number of times data is accessed when sorting the entire data set.

5. After the sorting list with merge mode equal to zero ends with the set condition code 0 and multiple output list depictions (OLD) are in the second operand, the program that wants to generate a single list of records in sorting order will call another sorting list operation , Where the input list is specified as the OLD derived from the previous sort list call. In this case, in one instance, the second call to the sorted list specifies a merge mode equal to one.

Similarly, in one embodiment, after calling a sorted list with merge mode equal to zero as many times as needed or required to generate a complete set of sorted lists from a large number of arbitrary order records, in one instance, as many as needed or needed The sorted list whose merge mode is equal to one is called twice to generate a single sorted list.

6. In one embodiment, to reduce the number of times each record is accessed when merging multiple sorted lists in ascending sort order (for example) into a single list, the program implements the following processing procedure:

* Determine the maximum number N of input lists that can be used for sorting lists.

* Compare the keys of the first record of the sorted list that has not been merged into a single list. Select the N lists with the lowest first key value.

* Execute the sorted list, the merge mode (MM) is equal to one, the empty input list control item (EILCL) is equal to 10 binary, input list0 only specifies the first record of the list with the highest first key value of the selected N lists, And the remaining input list specifies other N-1 selected lists.

* After the sorting list ends with condition code 2, IILF is equal to zero and EILF is equal to zero, the process is repeated.

7. After the sorting list ends with the setting condition code 1, the program performs the following actions. In one example, before calling the sorting list again, the operation is resumed:

* If the length of the first operand is less than the maximum record length of the record being processed, the length of the first operand or the address and length of the first operand should be updated as appropriate.

* If the merge mode (MM) is zero and the length of the second operand is less than 16, the length of the second operand or the address and length of the second operand should be updated as appropriate.

* If the length of any active input list is equal to zero, the address and length of the corresponding input list can be updated to indicate another list of records to be included in the sorting operation.

8. After the sorting list ends with the set condition code 2, the program performs the following actions. In one example, before calling the sorting list again, the operation is resumed:

* If the incomplete input list flag (IILF) is one, the input list length or input list address and length of the input list identified by the incomplete input list number (IILN) should be updated as appropriate.

* If the empty input list flag (EILF) is one, the input list length or input list address and length of the input list identified by the empty input list number (EILN) should be updated as appropriate.

* If IILF is zero, EILF is zero and the length of input list0 is zero, the length of input list0 or the address and length of list0 should be updated as appropriate. In addition, the input list address and length of the active input list can be updated. If there is only one record initially specified by input list0 and the empty input list control item (EILCL) is 10 binary, the update can be an appropriate action.

* If the merge mode (MM) is one and the length of the first operand is less than the maximum record length of the record being processed, the length of the first operand or the address and length of the first operand should be updated as appropriate.

* If MM is zero and any IILF is one, or EILF is one, then the address and length of the first operand and the address and length of the second operand should not be updated.

* If MM is zero, IILF is zero, EILF is zero and the length of the first operand is less than the maximum record length of the record being processed, the length of the first operand or the address and length of the first operand should be updated as appropriate.

* If MM is zero, IILF is zero, EILF is zero and the length of the second operand is less than 16, the length of the second operand or the address and length of the second operand should be updated as appropriate.

As described herein, in one aspect, a single instruction (eg, a single architected machine instruction, sorting list) is provided to perform sorting and/or merging operations on a general-purpose processor. In one example, a program that performs sorting and/or merging operations on a database and executes on a general-purpose processor can replace a valid subset of primitive instructions with a single instruction to implement the operation. This instruction is, for example, a hardware instruction defined in an instruction set architecture (ISA). As a result, the complexity of programs related to sorting and/or merging operations is reduced. In addition, the operation and therefore the performance of the processor are improved.

Advantageously, the sorted list instructions are on a general purpose processor (eg, a central processing unit, referred to herein as a processor) rather than a dedicated processor such as a graphics processing unit (GPU), database engine (DBE), or other types of dedicated processors Execution on a dedicated processor.

Although various fields and registers are described, one, or more aspects of the invention may use other, additional or fewer fields or registers, or other sizes of fields or registers, etc. Many changes are possible. For example, implicit registers may be used instead of explicitly specified registers or fields of commands, and/or explicitly specified registers or fields may be used instead of implicit registers or fields. Other changes are also possible.

In one example, the sorted list command works on a large amount of data (such as megabyte or terabyte data) in a database (eg, a commercial database). Therefore, the instruction is interruptible and processing can resume where it was interrupted.

When the instruction is interrupted, the operation (eg, sorting and/or merging) is only partially completed. Command execution ends by setting the condition code to notify the program (for example, the program that issued the command) of the partially completed value of the operation. The program can then re-execute the instruction to resume processing.

In one embodiment, the instruction uses several (e.g., a large number) execution loops to start the processor with post data before generating the results. Whenever a command is executed or re-executed, the processor is started with the post data. Therefore, according to the aspect of the present invention, the previously generated meta data is stored and used so that it is not necessary to regenerate the previously generated meta data when the command is re-executed.

In one example, the post data includes the internal state of the processor, including, for example, information about the input list, such as information about previous comparisons of the records of the input list, in order to determine subsequent comparisons to be made.

The processor obtains the meta data and stores it in the location provided by the program. Then, when the instruction is re-executed after the interruption, the meta data is obtained from the location and loaded into the processor without using the task to regenerate the meta data. This saving generates the time it will take to set up the data after the operation.

Other details of one embodiment of the execution of the resume operation will be described with reference to FIGS. 10A to 10B. For example, FIG. 10A depicts processing associated with partially completed instructions; and FIG. 10B depicts processing associated with resuming execution of partially completed instructions. In this example, the instruction is an instruction to perform sorting and/or merging, such as a sorting list instruction; however, in other examples, it may be other instructions that can be interrupted. The processing of FIGS. 10A to 10B is executed by a processor (for example, the processor 102 or 204).

Referring initially to FIG. 10A, instructions executed on the processor and performing operations such as sorting and/or merging terminate before completing the operation (step 1000). Based on the partial completion, the connection indicator (eg, the connection flag 368 of the parameter block 360) is set to, for example, one to indicate partial completion (step 1002). In addition, the internal state of the processor (such as, for sorting or merging operations, previously compared information about the records of the input list) is stored in the parameter block, for example, in the connection state buffer 390 (step 1004).

Thereafter, referring to FIG. 10B, an instruction (e.g., sort/merge instruction) is executed (step 1050). A determination is made as to whether to set a connection indicator to indicate that this is a re-execution of the instruction (inquiry 1052). If the connection indicator is set to instruct to resume the operation (step 1053), the internal state of the processor stored in the connection state buffer 390 is obtained (step 1054) and loaded into one or more of the processors Select the location (step 1056). Then use the acquired and loaded internal state data when re-executing the command (step 1058). For example, instead of repeating the previously performed comparison, the internal state data is used to determine the subsequent comparison to be performed, thereby reducing execution time and improving performance.

Returning to query 1052, if the connection indicator is not set to indicate re-execution, in one example, the operation starts instead of resuming (step 1060). Therefore, in one example, the operation continues without using internal state data such as a connection state buffer (CSB) 390 from a parameter block (eg, parameter block 360) in memory.

One or more aspects of the invention are inevitably related to computer technology and facilitate processing within the computer, thereby improving its performance. When re-executing the command after the interruption, the acquired and saved post-configuration data is used instead of post-regeneration post-configuration data, which saves time and improves performance in the computing environment.

In a specific example, the re-executed instruction is a sorted list instruction, which is a single structured machine instruction used to perform sorting and/or merging of a large number of database records of a database, which replaces many software instructions to improve the computing environment Within the effectiveness. These sorted and/or merged records can be used in many technical fields for managing and/or using large amounts of data, such as computer processing, medical processing, security, etc. By providing optimization of sorting/merging, these technical fields are improved by reducing the execution time of obtaining and using information and reducing storage requirements.

11A to 11B describe other details of an embodiment that facilitates processing within a computing environment because the computing environment is related to one or more aspects of the invention.

Referring to FIG. 11A, in one embodiment, it is determined that the processing of the operation of the instruction executed on the processor has been interrupted before completion (1100). Based on the determination that the processing of the operation has been interrupted, the processor meta data is obtained (1102). The metadata is, for example, the current metadata of the processor (1104). The meta data is stored in the location associated with the instruction (1106), and is used to re-execute the instruction to resume the forward processing of the instruction from where it was interrupted (1108).

In one example, the instruction is a sort instruction (1110), and the meta data includes information about one or more input lists of the sort instruction (1112). For example, the meta data includes information about previous comparisons made to the records of one or more input lists to indicate subsequent comparisons to be made (1114). For example, without repeating the previous comparison, the subsequent comparison to be made is indicated (1116).

In one example, the determination includes checking the condition code set based on the termination of the instruction, and the condition code set to the selected value indicates partial completion of the instruction (1118).

As an example, referring to FIG. 11B, the location where the meta data is stored is the parameter block (1120) specified by the instruction in the memory. The location of the parameter block in the memory is indicated by the contents of the implied register of the instruction, for example (1122). In a specific example, the parameter block includes a connection status buffer (1124) for storing metadata, which includes internal status data of the processor (1126). In addition, in one example, the parameter block includes a connection indicator (1128) to indicate the partial completion of the operation.

In one aspect, using the meta data when the command is re-executed further includes re-executing the command to resume processing (1132); acquiring the meta data from the location (1134); and loading the meta data from the location To one or more selected locations of the processor, where the metadata is provided to the processor without repeating one or more tasks to generate metadata (1136).

Other changes and embodiments are possible.

The aspect of the present invention can be used in many types of computing environments. Referring to FIG. 12A, another embodiment of a computing environment in which one or more aspects of the present invention are described and used. In this example, the computing environment 10 includes, for example, a native central processing unit (CPU) 12, memory 14, and one or more input/output devices and/or interfaces 16, each of which is via, for example, one or more bus bars 18 and And/or other connectors are coupled to each other. As an example, the computing environment 10 may include: PowerPC ^® processor supplied by International Business Machines Corporation of Armonk, New York; HP Superdome with Intel Ando II processor supplied by Hewlett-Packard Company of Palo Alto, California; And/or other machines based on architectures supplied by International Business Machines Corporation, Hewlett-Packard Company, Intel Corporation, Oracle Corporation or others. IBM, z/Architecture, IBM Z, z/OS, PR/SM and PowerPC are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction. Intel and Ando are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

The native central processing unit 12 includes one or more native registers 20, such as one or more general-purpose registers and/or one or more dedicated registers used during processing within the environment. These registers include information indicating the state of the environment at any particular point in time.

In addition, the native central processing unit 12 executes instructions and code stored in the memory 14. In a specific example, the central processing unit executes the emulator code 22 stored in the memory 14. This code enables the computing environment configured in one architecture to simulate another architecture. For example, the emulator code 22 allows machines based on architectures other than the z/Architecture hardware architecture (such as PowerPC processors, HP Superdome servers, or others) to emulate the z/Architecture hardware architecture and execute z/Architecture-based hardware architectures. Architecture hardware development software and instructions.

12B describes other details related to the emulator code 22. The guest instructions 30 stored in the memory 14 include software instructions (eg, related to machine instructions) that have been developed to execute in an architecture other than the architecture of the native CPU 12. For example, the guest instructions 30 may have been designed to execute on a processor based on the z/Architecture hardware architecture, but instead, be emulated on a native CPU 12 that may be an Intel Ando II processor, for example. In one example, the emulator code 22 includes an instruction fetch routine 32 to obtain one or more guest instructions 30 from the memory 14 and optionally provide local buffering of the obtained instructions. The emulator code also includes a command translation routine 34 to determine the type of object command that has been obtained and translate the object command into one or more corresponding native commands 36. This translation includes, for example, identifying the function to be executed by the object command and selecting the native command to execute the function.

In addition, the emulator code 22 includes an emulation control routine 40 so that native instructions are executed. The emulation control routine 40 enables the native CPU 12 to execute the emulation routine of the native instruction emulating one or more previously obtained object instructions and at the end of this execution, returns control to the instruction extraction routine to emulate the next object Instructions or a set of object instructions. The execution of the native command 36 may include loading data from the memory 14 into the register; storing the data from the register back to the memory; or performing a certain type of arithmetic or logical operation, as determined by the translation routine .

Each routine is implemented in software, for example, which is stored in memory and executed by the native central processing unit 12. In other examples, one or more routines or operations are implemented in firmware, hardware, software, or some combination thereof. The register 20 of the native CPU can be used or the register of the emulated processor can be emulated by using the location in the memory 14. In an embodiment, the guest instruction 30, the native instruction 36, and the emulator code 22 may reside in the same memory or may be allocated in different memory devices.

The computing environment described above is only an example of a usable computing environment. Other environments may be used, including but not limited to other undivided environments, other divided environments, and/or other simulation environments; embodiments are not limited to any one environment.

Each computing environment can be configured to include one or more aspects of the invention. For example, according to one or more aspects of the invention, each computing environment is configured to provide ordering and/or merging.

One or more aspects may be related to cloud computing.

It should be understood that although the present invention includes a detailed description of cloud computing, embodiments of the teachings described herein are not limited to cloud computing environments. Rather, embodiments of the present invention can be implemented in conjunction with any other type of computing environment now known or later developed.

Cloud computing is used to facilitate a shared pool of configurable computing resources (e.g., network, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) On-demand network access service delivery model, configurable computing resources can be quickly deployed and released with minimal management or interaction with service providers. This cloud model may include at least five features, at least three service models, and at least four deployment models.

The characteristics are as follows:

On-demand self-service: Cloud consumers can automatically provision computing capabilities in one direction (such as server time and network storage) as needed, without human interaction with service providers.

Broadband network access: Capability is available through the network and access is provided through standard mechanisms that are facilitated by heterogeneous thin or complex client platforms (eg, mobile phones, laptops, and PDAs) .

Resource collection: The computing resources of the provider are used to serve multiple consumers using a multi-tenant model, where different entities and virtual resources are dynamically assigned and reassigned as needed. The meaning of location independence exists because consumers generally do not have control or knowledge about the exact location of the resources provided, but may be able to specify the location at a higher level of abstraction (eg, country, state, or data center).

Rapid elasticity: Ability can be quickly and elastically deployed (in some cases, automatically) to quickly extend outward, and the ability can be quickly released to quickly extend inward. From the consumer's perspective, the capabilities available for provisioning often appear to be unlimited and can be purchased in any amount at any time.

Measured services: Cloud systems automatically control and optimize resource usage by fully utilizing metering capabilities at an abstract level suitable for the type of service (eg, storage, processing, bandwidth, and active user account). You can monitor, control, and report on resource usage to provide transparency for both providers and consumers of the services used.

The service model is as follows:

Software-as-a-Service (SaaS): The ability to provide consumers with applications that use providers running on cloud infrastructure. Applications can be accessed from various client devices via a thin client interface such as a web browser (eg, web-based email). Consumers do not manage or control the underlying cloud infrastructure that includes network, server, operating system, storage, or even individual application capabilities. The possible exceptions are limited user-specific application configuration settings.

Platform-as-a-Service (PaaS): The ability to provide consumers deploys applications created or acquired by consumers using programming languages and tools supported by the provider to the cloud infrastructure. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but control the applications that are deployed and the applications that may be configured in the hosted environment.

Infrastructure as a service (IaaS): The ability to provide consumers with the ability to provision processing, storage, networking, and other basic computing resources, where consumers can deploy and run any software that can include operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but control the operating system, storage, deployed applications, and may have limited control over the choice of network connection components (eg, host firewall).

The deployment model is as follows:

Private cloud: Operate the cloud infrastructure only for organizations. The private cloud can be managed by an organization or a third party and can exist on-premises or externally.

Community Cloud: The cloud infrastructure is shared by several organizations and supports specific communities with shared concerns (eg, tasks, security requirements, policies, and compliance considerations). The private cloud can be managed by an organization or a third party and can exist on-premises or externally.

Public cloud: The cloud infrastructure can be used by the public or large industrial groups and is owned by organizations that sell cloud services.

Hybrid cloud: The cloud infrastructure is a combination of two or more clouds (private, community, or public), which maintain unique entities but achieve data and application portability (for example, for Cloud bursts that achieve load balancing between clouds are standardized or proprietary technologies tied together.

Service-oriented cloud computing environment by focusing on borderless, low coupling, modularization and semantic interoperability. The key to cloud computing is the infrastructure of the network including interconnected nodes.

Referring now to FIG. 13, an illustrative cloud computing environment 50 is depicted. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 52 that are used by cloud consumers such as personal digital assistants (PDAs) or cellular phones 54A, desktop computers 54B, laptop computers 54C and/or Or the local computing device of the automotive computer system 54N can communicate with the one or more cloud computing nodes. The nodes 52 can communicate with each other. These nodes can be physically or virtually grouped (not shown) in one or more networks, such as private, community, public or hybrid clouds or combinations thereof as described above. This situation allows the cloud computing environment 50 to provide infrastructure, platforms, and/or software as services. For these services, cloud consumers do not need to maintain resources on the local computing device. It should be understood that the types of computing devices 54A to 54N shown in FIG. 13 are intended to be illustrative only, and the computing node 52 and cloud computing environment 50 may be connected via any type of network and/or network addressable (e.g., Use a web browser) to communicate with any type of computerized device.

Referring now to Figure 14, a collection of functional abstraction layers provided by the cloud computing environment 50 (Figure 13) is shown. It should be understood in advance that the components, layers, and functions shown in FIG. 14 are intended to be illustrative only and embodiments of the present invention are not limited thereto. As depicted, the following layers and corresponding functions are provided.

The hardware and software layer 60 includes hardware and software components. Examples of hardware components include: a large computer 61; a server 62 based on a reduced instruction set computer (RISC) architecture; a server 63; a blade server 64; a storage device 65; and a network and network connection component 66. In some embodiments, the software components include network application server software 67 and database software 68.

The virtualization layer 70 provides an abstraction layer from which the following instances of virtual entities can be provided: virtual server 71; virtual storage 72; virtual network 73, including virtual private network; virtual applications and operating system 74; And virtual client 75.

In one example, management layer 80 may provide the functions described below. Resource provisioning 81 provides dynamic procurement of computing resources and other resources used for tasks within the cloud computing environment. When resources are used in the cloud computing environment, metering and pricing 82 provides cost tracking, as well as accounting processing and invoice issuance of the consumption of these resources. In one example, such resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection of data and other resources. The user portal 83 provides consumers and system administrators with access to the cloud computing environment. Service level management 84 provides cloud computing resource allocation and management to meet the required service level. Service Level Agreement (SLA) Planning and Implementation 85 Provides pre-configuration and procurement of cloud computing resources. Future requirements for cloud computing resources are expected based on SLA.

The workload layer 90 provides an example of functionality for which a cloud computing environment can be utilized. Examples of workloads and functions available from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analysis processing 94; transaction processing 95; and sequencing and/or merge processing 96.

The aspect of the present invention may be a system, method, and/or computer program product at any possible technical detail integration level. The computer program product may include one (or more) computer-readable storage media with computer-readable program instructions on it to enable the processor to perform the aspect of the present invention.

The computer-readable storage medium may be a tangible device that can retain and store instructions for use by the instruction execution device. The computer-readable storage medium may be, for example but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard drives, random access memory (RAM), read-only memory (ROM), erasable and programmable Read-only memory (EPROM or flash memory), static random access memory (SRAM), portable disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk , Any suitable combination of mechanical coding devices (such as punched cards or raised structures in grooves with instructions recorded on them) and the foregoing. As used herein, computer-readable storage media should not be interpreted as temporary signals, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (eg, light transmitted through fiber optic cables Pulse), or electrical signals transmitted through wires.

The computer-readable program instructions described in this article can be downloaded from a computer-readable storage medium to various computing/processing devices or via a network (e.g., Internet, local area network, wide area network, and/or wireless network) To an external computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for computer-readable storage in each computing/processing device Storage media.

The computer readable program instructions for performing the operations of the present invention may be grouped program instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, written in any combination of one or more programming languages Firmware commands, state setting data, configuration data for integrated circuits, or source code or target code, the one or more programming languages include object-oriented programming such as Smalltalk, C++, or the like Languages, and procedural programming languages, such as "C" programming languages or similar programming languages. Computer readable program instructions can be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or Run completely on a remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer via any type of network including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, by using the Internet Internet service providers). In some embodiments, electronic circuitry including, for example, a programmable logic circuit system, a field programmable gate array (FPGA), or a programmable logic array (PLA) can be obtained by using computer-readable program command status information The electronic circuit system is personalized to execute computer-readable program instructions in order to implement the aspect of the present invention.

The present invention is described herein with reference to flowchart illustrations and/or block diagrams of methods, devices (systems) and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustration and/or block diagram may be implemented by computer-readable program instructions, and a combination of blocks in the flowchart illustration and/or block diagram.

These computer-readable program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device can be created A component used to implement one or more of the functions/actions specified in the flowchart and/or block diagram blocks. These computer-readable program instructions can also be stored in a computer-readable storage medium. These instructions can guide the computer, programmable data processing equipment, and/or other devices to function in a specific manner, so that the computer with the stored instructions can The read storage medium includes an artifact that includes instructions to implement one or more of the functions/actions specified in the flowchart and/or block diagram blocks.

Computer readable program instructions can also be loaded onto computers, other programmable data processing equipment or other devices to enable a series of operating steps to be executed on computers, other programmable equipment or other devices to generate computer-implemented processing procedures , So that the instructions executed on the computer, other programmable equipment, or other devices implement one or more functions/actions specified in the flowchart and/or block diagram blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, section, or portion of instructions, which includes one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions mentioned in the blocks may occur out of the order noted in the figures. For example, depending on the functionality involved, two blocks shown in succession may actually be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order. It will also be noted that each block described in the block diagram and/or flowchart may be implemented by a dedicated hardware-based system that performs specified functions or actions or performs a combination of dedicated hardware and computer instructions, and the block diagram and/or Or a combination of blocks in the flow chart description.

In addition to the above situations, one or more aspects of providing, supplying, deploying, managing, and serving (such as) service providers who provide management of the consumer environment. For example, a service provider may create, maintain, support (etc.) computer code and/or execute a computer infrastructure for one or more aspects of one or more consumers. In return, the service provider may receive payment from consumers according to a subscription and/or charging agreement (as an example). Additionally or alternatively, the service provider may receive payment from the sale of advertising content to one or more third parties.

In one aspect, an application can be deployed to execute one or more embodiments. As an example, the deployment of an application program includes providing a computer infrastructure that can be used to execute one or more embodiments.

As another aspect, a computing infrastructure may be deployed, including the integration of computer-readable program code into a computing system, where the program code in conjunction with the computing system can execute one or more embodiments.

As yet another aspect, a processing procedure for integrating computing infrastructure may be provided, including integrating computer-readable code into a computer system. The computer system includes computer-readable media, where the computer media includes one or more embodiments. The code combined with the computer system can execute one or more embodiments.

Although various embodiments are described above, these embodiments are merely examples. For example, computing environments of other architectures can be used in conjunction with and use one or more embodiments. In addition, different instructions or operations can be used. In addition, different registers can be used and/or other types of instructions can be specified (other than the register number). Many changes are possible.

In addition, other types of computing environments can be beneficial and can be used. As an example, a data processing system suitable for storing and/or executing program code may be used, which includes at least two processors coupled directly or indirectly to memory elements through a system bus. Memory components include, for example, local memory used during the actual execution of the code, mass storage, and provision of temporary storage of at least one code to reduce the number of times code must be retrieved from the mass storage during execution Cache memory.

Input/output or I/O devices (including but not limited to keyboards, monitors, pointing devices, DASD, tapes, CDs, DVDs, thumb drives, and other memory media, etc.) can directly or through intervening I/O The controller is coupled to the system. The network adapter can also be coupled to the system so that the data processing system can become coupled to other data processing systems or remote printers or storage devices through the intervening private network or public network. Modems, cable modems and Ethernet cards are just a few available types of network adapters.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "the" are intended to include the plural forms as well. It should be further understood that the term "comprises and/or comprising" when used in this specification specifies the presence of stated features, wholes, steps, operations, elements and/or components, but does not exclude one or more other features , Whole, steps, operations, elements, components and/or their existence or addition.

The corresponding structures, materials, actions and equivalents (if any) of all components or steps plus functional elements within the scope of the following patent applications are intended to include any structure, material or function used to perform functions in combination with other claimed elements as specifically claimed action. The description of one or more embodiments has been presented for purposes of illustration and description, but it is not intended to be exhaustive or limited to the disclosed form. For those who are familiar with this technology in general, many modifications and changes will be obvious. The embodiments are selected and described in order to best explain the various aspects and practical applications, and to enable those of ordinary skill in the art to understand various embodiments with various modifications as appropriate for the specific uses anticipated.

10: computing environment 12: native central processing unit (CPU) 14: memory 16: input/output device and/or interface 18: bus 20: native register 22: emulator code 30: object instruction 32: instruction Extraction routine 34: command translation routine 36: native command 40: simulation control routine 50: cloud computing environment 52: cloud computing node 54A: cellular telephone 54B: desktop computer 54C: laptop computer 54N: car computer System 60: hardware and software layer 61: mainframe computer 62: server based on reduced instruction set computer (RISC) architecture 63: server 64: blade server 65: storage device 66: network and network connection components 67: Web application server software 68: database software 70: virtualization layer 71: virtual server 72: virtual storage 73: virtual network 74: virtual application and operating system 75: virtual client 80: management layer 81 : Resource provisioning 82: Measurement and pricing 83: User portal 84: Service level management 85: Service level agreement (SLA) planning and implementation 90: Workload layer 91: Map surveying and navigation 92: Software development and life cycle management 93: virtual classroom education delivery 94: data analysis processing 95: transaction processing 96: sorting and/or merge processing 100: computing environment 102: processor 104: memory 106: input/output (I/O) device and/or interface 108: bus 120: instruction extraction component 122: instruction decoding unit 124: instruction execution component 126: memory access component 130: write-back component 136: sorting/merging component 200: central electronic device complex (CEC) 202: memory Body/main storage 204: central processing unit (CPU)/physical processor resources/processor 206: input/output subsystem 208: logical partition 210: hypervisor 212: processor firmware 220: guest operating system 222 : Program 230: input/output control unit 240: input/output (I/O) device 250: data storage device 252: program 254: computer-readable program command 260: sorting/merging components (or other components) 300: sorting list (SORTL) instruction 302: opcode field 304: first register field (R ₁ ) 306: second register field (R ₂ ) 308: general register 0 310: merge mode field 312 : Function code field 313: function code 0 315: function code 1 316: logical address 317: function code 2 318: general-purpose register R ₁ 320: logical address 322: general-purpose register R ₁ +1 324: length 326: general-purpose register R ₂ 328: logical address 330: general-purpose register R ₂ +1 332: length 340: parameter block 342: installed function vector 344: installed interface size vector 346: Installed parameter block format vector 3 50: record 352: key 354: payload 360: parameter block 362: parameter block version number (PBVN) 364: model version number (MVN) 366: sort order (SO) 368: connection flag (CF) 370 : Record key length 372: record payload length 374: operand access intention (OAI) 376: active input list count code (AILCC) 378: empty input list control (EILCL) 380: empty input list flag (EILCL) (EILF) 382: empty input list number (EILN) 384: incomplete input list flag (IILF) 386: incomplete input list number (IILN) 388: connection record re-call buffer starting point 390: connection status buffer (CSB) 392: Enter ListN address 393: Enter ListN length 394: Enter ListN address 395: Enter ListN length 396: Enter ListN address 397: Enter ListN length 400: Enter list 402: First operand 404: Second operand 450 : Input list 452: First operand 454: Second operand 600: FOSA 602: FOEA 604: OL 610: SOSA 612: SOEA 614: OLD 700: FOSA 702: FOEA 704: OL 900: fixed-length key 902: 8-byte payload length (PL) 904: variable-length payload 1000: step 1002: step 1004: step 1050: step 1052: query 1053: step 1054: step 1056: step 1058: step 1060: step 1062: step 1100: Step 1102: Step 1104: Step 1106: Step 1108: Step 1110: Step 1112: Step 1114: Step 1116: Step 1118: Step 1120: Step 1122: Step 1124: Step 1126: Step 1128: Step 1132: Step 1134: Step 1136: Step

One or more aspects are specifically pointed out and clearly claimed as examples in the patent application scope at the end of this specification. The foregoing content and objectives, features, and advantages of one or more aspects are apparent from the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1A depicts and utilizes one or more aspects of the computing environment of the present invention An example; FIG. 1B depicts other details of the processor of FIG. 1A according to one or more aspects of the present invention; FIG. 2 depicts another example of a computing environment incorporating and using one or more aspects of the present invention; FIG. 3A depicts a format of a sorted list instruction according to the aspect of the present invention; FIG. 3B depicts one of the fields of the hidden register (general register 0) used by the sorted list instruction according to the aspect of the present invention Example; FIG. 3C depicts an example of function code for sorting list instructions according to the aspect of the present invention; FIG. 3D depicts an implicit register (general temporary storage) used by the sorting list instruction according to the aspect of the present invention An example of the field of the device 1); FIG. 3E depicts an example of the contents of the register R ₁ specified by the sorting list instruction according to the aspect of the present invention; FIG. 3F depicts the sorting list according to the aspect of the present invention An example of the contents of the register R ₁ +1 used by the instruction; FIG. 3G depicts an example of the contents of the register R ₂ specified by the sorted list instruction according to the aspect of the invention; FIG. 3H depicts the contents of the register R ₂ according to the invention An example of the contents of the register R ₂ +1 used by the sorted list command according to the aspect; FIG. 3I depicts the contents of the parameter block used by the SORTL-QAF function of the sorted list command according to the aspect of the present invention An example; FIG. 3J depicts an example of a fixed-length record format used by the sort list instruction according to the aspect of the invention; FIG. 3K depicts parameters used by the SORTL-SFLR function of the sort list instruction according to the aspect of the invention An example of the content of a block; FIGS. 4A to 4B depict an example of SORTL-SFLR according to one or more aspects of the invention; FIG. 5A depicts an input for a SORTL-SFLR function according to aspects of the invention An example of a summary of values; FIG. 5B depicts an example of restrictions on the modification of the input list address and length field of the SORTL-SFLR function according to the aspect of the invention; FIG. 6A depicts an aspect of the aspect according to the invention An example of the first operand position/first operand before executing the SORTL with the merge mode indication set to zero; FIG. 6B depicts the first after performing the SORTL with the merge mode indication set to zero according to the aspect of the invention An example of the operand position/first operand; FIG. 6C depicts an example of the second operand position/second operand before performing the SORTL with the merge mode indication set to zero according to the aspect of the present invention; FIG. 6D An example of the second operand position/second operand after performing the SORTL with the merge mode indication set to zero according to the aspect of the present invention; FIG. 7A depicts the setting of the merge mode indication according to the aspect of the invention Is the first operand position before SORTL/ An example of the first operand; FIG. 7B depicts an example of the first operand position/first operand after performing the SORTL with the merge mode indication set to one according to the aspect of the invention; FIG. 8 depicts the invention according to the invention An example of certain fields of the parameter block used by the aspect; FIG. 9 depicts an example of a variable-length record format used by the sort list instruction according to the aspect of the present invention; FIGS. 10A to 10B depict the The aspect of the invention relates to the processing associated with the interruption of the operation of the instruction and the re-execution of the instruction; FIGS. 11A to 11B depict an example of facilitating processing within the computing environment according to the aspect of the invention; FIG. 12A depicts the presence and use Another example of one or more aspects of the computing environment of the present invention; FIG. 12B depicts other details of the memory of FIG. 12A; FIG. 13 depicts an embodiment of a cloud computing environment; and FIG. 14 depicts an example of an abstract model layer .

200: Central Electronic Device Complex (CEC)

202: memory/main memory

204: central processing unit (CPU)/physical processor resources/processor

206: input/output subsystem

208: logical partition

210: Super Manager

212: Processor firmware

220: guest operating system

222: Program

230: input/output control unit

240: input/output (I/O) device

250: data storage device

252: Program

254: Computer readable program instructions

260: Sort/Merge components (or other components)

Claims (20)

A computer program product for facilitating processing in a computing environment. The computer program product includes: A computer-readable storage medium, which can be read by a processor and stores instructions for executing a method, the method including: Determine that the process of executing one of the instructions on the processor has been interrupted before completion; Based on the determination that the processing of the operation has been interrupted, the meta data of the processor is obtained, and the meta data is the current meta data of the processor; Store the meta data in a location associated with the instruction; and When the instruction is re-executed, the metadata stored in the location is used to resume the forward processing of the instruction from where it was interrupted. For example, the computer program product of claim 1, wherein the instruction is a sorting instruction, and the meta data includes information about one or more input lists of the sorting instruction. For example, the computer program product of claim 2, wherein the meta data includes information about previous comparisons made to the record of one or more input lists to indicate subsequent comparisons to be made. The computer program product of claim 3, in which the subsequent comparisons to be made are instructed without repeating the previous comparisons. The computer program product of claim 1, wherein the determination includes checking a condition code set based on the termination of the instruction, the condition code being set to a selection value indicating the partial completion of the instruction. For example, the computer program product of claim 1, wherein the location is a parameter block specified by the instruction in the memory. For example, in the computer program product of claim 6, the position of the parameter block in the memory is indicated by the content of an implicit register in one of the instructions. As in the computer program product of claim 6, wherein the parameter block includes a connection status buffer for storing the metadata, the metadata includes internal state data of the processor. As in the computer program product of claim 8, wherein the parameter block further includes a connection indicator used to indicate the partial completion of the operation. For example, the computer program product of claim 1, wherein the use of the metadata when re-executing the instruction further includes: Re-execute the instruction to resume processing; Obtain the meta data from that location; and Loading the meta data obtained from the location into one or more selected locations of the processor, wherein the meta data is provided to the processor without repeating one or more tasks to generate the meta data data. A computer system for facilitating processing in a computing environment. The computer system includes: A memory; and A processor that communicates with the memory, wherein the computer system is configured to perform a method, the method includes: Determine that the process of executing one of the instructions on the processor has been interrupted before completion; Based on the determination that the processing of the operation has been interrupted, the meta data of the processor is obtained, and the meta data is the current meta data of the processor; Store the meta data in a location associated with the instruction; and When the instruction is re-executed, the metadata stored in the location is used to resume the forward processing of the instruction from where it was interrupted. The computer system of claim 11, wherein the instruction is a sorting instruction, and the meta data includes information about a previous comparison of records of one or more input lists of the sorting instruction to indicate a subsequent comparison to be made. As in the computer system of claim 11, wherein the location is a parameter block in the memory specified by the instruction, and wherein the parameter block includes a connection status buffer for storing the metadata, the metadata Contains the internal status data of the processor. The computer system of claim 13, wherein the parameter block further includes a connection indicator used to indicate that the operation is partially completed. For example, the computer system of claim 11, wherein the use of the metadata when re-executing the instruction further includes: Re-execute the instruction to resume processing; Obtain the meta data from that location; and Loading the meta data obtained from the location into one or more selected locations of the processor, wherein the meta data is provided to the processor without repeating one or more tasks to generate the meta data data. A computer-implemented method for facilitating processing in a computing environment. The computer-implemented method includes: Determine that the process of executing one of the instructions on a processor has been interrupted before completion; Based on the determination that the processing of the operation has been interrupted, the meta data of the processor is obtained, and the meta data is the current meta data of the processor; Store the meta data in a location associated with the instruction; and When the instruction is re-executed, the metadata stored in the location is used to resume the forward processing of the instruction from where it was interrupted. The computer-implemented method of claim 16, wherein the instruction is a sorting instruction, and the meta data includes information about a previous comparison of records of one or more input lists of the sorting instruction to indicate a subsequent comparison to be made . The computer-implemented method of claim 16, wherein the location is a parameter block in the memory specified by the instruction, and wherein the parameter block includes a connection status buffer for storing the metadata, the metadata The data contains the internal status data of the processor. The computer-implemented method of claim 18, wherein the parameter block further includes a connection indicator used to indicate that the operation is partially completed. The computer-implemented method of claim 16, wherein the use of the metadata when re-executing the instruction further includes: Re-execute the instruction to resume processing; Obtain the meta data from that location; and Loading the metadata obtained from the location into one or more selected locations of the processor, wherein the metadata is provided to the processor without repeating one or more tasks to generate the metadata data.

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