TW202017046A - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device formation method includes providing a dielectric layer; forming a metal line in the dielectric layer; forming an etch stop layer on the metal line, wherein the etch stop layer includes a metal atom bonded with a hydroxyl group; performing a treatment process to the etch stop layer to displace hydrogen in the hydroxyl group with an element other than hydrogen; partially etching the etch stop layer to expose the metal line; and forming a conductive feature above the etch stop layer and in physical contact with the metal line.

Description

Semiconductor device and its manufacturing method

The embodiments of the present invention relate to a semiconductor technology, and particularly to a semiconductor device and a method of manufacturing the same.

The semiconductor integrated circuit (IC) industry has experienced exponential growth. The technical progress of integrated circuit (IC) materials and design has produced several generations of integrated circuits (ICs), each of which has smaller and more complex circuits than the previous generation. In an integrated circuit (IC) evolution process, the functional density (ie, the number of interconnect devices per chip area) usually increases, while the geometric size (ie, the smallest component (or line) that can be produced using the manufacturing process) is Zoom out. This scaling process usually brings benefits by increasing production efficiency and reducing related costs. This scaling down also increases the complexity of processing and manufacturing integrated circuits (ICs).

As part of semiconductor manufacturing, conductive elements can be formed to provide electrical interconnection of various components in an integrated circuit (IC). For example, conductive lines and vias for interconnecting different metal layers can be formed by etching the openings in the intermetal dielectric (IMD) layer. The metal oxide compound can be used to form an etch stop layer as an endpoint control, thereby providing a high etch selectivity. However, hydroxyl groups (-OH) are often present in the metal oxide-containing film, which may lead to the oxidation of metal elements under the conductive features. Therefore, although the etch stop layer formation process is usually sufficient for its intended purpose, it is not completely satisfactory in every aspect.

A method for manufacturing a semiconductor device includes: providing a dielectric layer; forming a metal line in the dielectric layer; forming an etch stop layer on the metal line, wherein the etch stop layer includes metal atoms bonded to hydroxyl groups; The stop layer undergoes a process to replace hydrogen in the hydroxyl group with elements other than hydrogen; partially etch the etch stop layer to expose the metal line; and form a conductive feature on the etch stop layer and make physical contact with the metal line .

A method for manufacturing a semiconductor device includes: providing a substrate having a first dielectric layer and a conductive feature buried in the first dielectric layer; forming an etch stop layer on the first dielectric layer and the conductive feature Above, where the etch stop layer includes a metal oxide; a silicon-containing dopant is deposited onto the etch stop layer, wherein the silicon-containing dopant reacts with the metal oxide to generate MO-Si groups, and M represents the metal oxide Forming a second dielectric layer on the etch stop layer; and forming a conductive structure in the second dielectric layer, wherein the conductive structure is electrically connected to the conductive feature.

A semiconductor device includes: a first conductive element disposed in the first dielectric layer; an etch stop layer disposed on the first dielectric layer, wherein the etch stop layer includes a MOX group, M represents a metal element, and X represents An element other than hydrogen; a second dielectric layer, disposed on the etch stop layer; and a second conductive element, buried in the second dielectric layer, and passing through the etch stop layer, wherein the second conductive element and the second A conductive element is in physical contact.

The following disclosure provides many different embodiments or examples to implement different features of the present invention. The following disclosure content is a specific example describing the various components and their arrangement, in order to simplify the disclosure content. Of course, these are only examples and are not intended to limit the present invention. For example, if the following disclosure describes forming a first feature on or above a second feature, it means that it includes the formed first feature and the second feature directly The contact embodiment also includes an implementation in which additional feature parts can be formed between the first feature part and the second feature part, so that the first feature part and the second feature part may not be in direct contact example. In addition, the content of this disclosure will repeat the label and/or text in different examples. The repetition is for simplicity and clarity, rather than specifying the relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially related terms, such as "below", "below", "below", "above", "upper", etc. are used here to easily express the figures shown in this specification In the formula, the relationship between an element or a feature part and another element or a feature part. These spatially related terms not only cover the orientation shown in the drawings, but also cover different orientations of the device in use or operation. This device can have different orientations (rotate 90 degrees or other orientations) and the relevant spatial symbols used here also have corresponding interpretations. In addition, when using "about", "approximately", etc. to describe a number or a range of numbers, unless otherwise stated, this term is intended to include numbers within +/- 10% of the number. For example, the term "about 5 nm" includes a size range of 4.5 nm to 5.5 nm.

The embodiments of the present disclosure are generally related to integrated circuits, more systematically regarding the interconnection structure and formation method in the integrated circuit, and more specifically regarding the formation of an etch stop layer.

The integrated circuit includes a plurality of patterned metal lines separated by an inter-wiring spacing. Generally, the metal patterns of the vertically spaced metallization layers are electrically connected through the via electrode. The metal line formed in the trench-shaped opening generally extends substantially parallel to the semiconductor substrate. According to the prior art, this type of semiconductor device may include eight or more metallization layers to meet device geometry and miniaturization requirements.

A common process for forming metal wires or plugs is called "mosaic". Generally, the above process involves forming an opening in the dielectric inner layer, the opening separating the vertically spaced metallization layers. The openings are usually formed using traditional lithography and etching techniques. In some embodiments, after the opening is formed, the opening is filled with metal or metal alloy (eg, copper or copper alloy) to form a metal line and possibly a via electrode. Then the excess metal material above the surface of the dielectric inner layer is removed by chemical mechanical planarization (CMP).

In order to precisely control the formation of damascene openings, an etch stop layer is usually used. The etch stop layer stacked between the underlying conductive features (eg, metal lines) and the dielectric inner layer (eg, low-k dielectric layer) provides isolation as a barrier layer, and when the opening is formed in the dielectric inner layer It also provides end point control during the subsequent etching process.

Select the material composition of the etch stop layer so that there is an etch selectivity between the etch stop layer and the dielectric inner layer, so that the etching process through the dielectric inner layer will stop at the etch stop layer without causing the underlying conductive features to etch damage. The term "etch selectivity ratio" as used herein refers to the etching rate of the dielectric inner layer divided by the etching rate of the etching stop layer. For example, an etch selection ratio of about 10 will result in a dielectric inner layer removal rate that is about 10 times faster than the etch stop layer removal during the etching process.

Metal oxide-containing materials (also known as metal oxide composites) generally provide high etch selectivity for low-k dielectric materials. Therefore, in the modern technology generation, the etch stop layer may include a metal oxide compound, such as aluminum oxide or aluminum oxynitride. Nevertheless, the etch stop layer containing metal oxide still has disadvantages. Metal oxide-containing materials generally include a hydroxyl group (-OH), which contains hydrogen-bonded oxygen. The hydroxyl group diffuses throughout the metal oxide-containing material, but has the highest concentration on the top surface of the etch stop layer. Hydroxyl groups are formed through the dissociation chemisorption of H ₂ O molecules, and it is generally believed that hydration and hydroxylation occur on the lattice metal ions exposed on the surface because the lattice metal ions are strong Lewis acid. Most hydroxyl groups are in the form of surface hydroxyl groups, which stay on the surface of the etch stop layer. When the etch stop layer is thick, when the distance is far from the surface, the concentration of the hydroxyl group drops sharply. However, when the etch stop layer is thin, for example, less than about 100Å (Angstroms), the concentration of hydroxyl groups at the bottom of the etch stop layer may still be high enough to cause oxidation of the metal elements within the underlying conductive features. In addition, some surface hydroxyl groups are more likely to penetrate the interface between the underlying conductive features and oxidize the metal elements therein. This oxidation creates vacancies (sometimes on the order of nanometers) in the conductive features below, where the volume of the metal is consumed by oxidation. One way to reduce the formation of vacancies is to increase the thickness of the etch stop layer to increase the depth used to reduce the hydroxyl group concentration below a certain threshold. In some embodiments, the thickness of the etch stop layer is about 10 nm to about 20 nm to avoid oxidation. As semiconductor technology generations continue to scale down proportionally, thick etch stop layers increase parasitic capacitance and reduce the speed of semiconductor devices. Therefore, a solution is needed.

The preparation and use of embodiments of the present invention are discussed in detail below. One method significantly reduces or substantially eliminates the hydroxyl groups from the etch stop layer, and results in a new interconnect structure for integrated circuits that allows the thickness of the etch stop layer to be less than 50 Angstroms (eg, as thin as about 20 Angstroms). The following shows the intermediate stages of manufacturing the above-described embodiment and discusses changes of the embodiment. In the various views and illustrative embodiments herein, the same graphical notations are used to represent the same components. However, it is understandable that the embodiments provide many applicable inventive concepts that can be implemented in various specific occasions. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

FIGS. 1A, 1B, 1C, and 1D are flowcharts illustrating a method 100 of forming an integrated circuit according to some embodiments. Additional operation steps may be provided before, during, and after the method 100, and for other embodiments of the method 100, certain operation steps described may be replaced or excluded. The following method 100 is discussed in conjunction with Figures 2-14. Figures 2, 3, 5, 9, 10, 11, 12, and 13 are schematic cross-sectional views illustrating an exemplary integrated circuit 200 during various manufacturing stages of the method 100 according to some embodiments. Figures 4, 6, 7, 8 and 14 show exemplary chemical formulas of metal oxide composites and related physical properties.

Referring to FIG. 1A, the method 100 starts at operation 102, providing or receiving a device 200, which includes a substrate 202 as shown in FIG. In some embodiments, the substrate 202 includes silicon. Alternatively, according to some embodiments, the substrate 202 may include other element semiconductors, such as germanium. In some embodiments, the substrate 202 additionally or alternatively includes compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. In some embodiments, the substrate 202 includes alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, and gallium indium phosphide.

In some embodiments, the substrate 202 includes a semiconductor-on-insulator (SOI) structure. For example, the substrate 202 may include a buried oxide (BOX) layer formed by a process of separation by implanted oxygen (SIMOX). In various embodiments, the substrate 202 includes various p-type doped regions and/or n-type doped regions, for example, p-type well regions, n-type well regions, and p-type sources are formed through processes such as ion implantation and/or diffusion Pole/drain feature and/or n-type source/drain feature. The substrate 202 may include other functional features such as resistors, capacitors, diodes, and transistors (for example, field effect transistors (FETs)). The substrate 202 may include lateral isolation features configured to separate various devices formed on the substrate 202.

The substrate 202 may include a dielectric layer 204 formed on the upper surface. In some embodiments, the dielectric layer 204 is an inter-metal dielectric (IMD) layer with a dielectric constant value (k value) in the range of about 1 to about 5. For example, a low k value below about 3.5. The low-k dielectric layer may include commonly used low-k dielectric materials, such as carbon-containing dielectric materials, and may also include nitrogen, hydrogen, oxygen, and combinations thereof.

Referring again to FIGS. 1A and 2, the method 100 includes an operation step 104 to form a diffusion barrier layer 208 and one or more underlying conductive features 206 embedded in the dielectric layer 204. The diffusion barrier layer 208 may include titanium, titanium nitride, tantalum, tantalum nitride, or other alternatives. In the embodiment shown in FIG. 2, a lower conductive feature 206 is formed.

In some embodiments, the lower conductive features 206 are metal features, such as metal wires, metal via electrodes, or metal contact features. In some embodiments, the lower conductive features 206 include metal lines and metal via electrodes, which are formed by suitable processes, such as dual damascene processes or other suitable processes (including atomic layer deposition (ALD), Processes of chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless metal deposition (ELD) or electrochemical plating (ECP). Conductivity underneath The material of the feature part 206 may include copper (Cu) or copper alloy. Alternatively, it may be formed of other conductive materials or include other conductive materials, such as nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), Aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), osmium (Os), tungsten (W), etc. The steps of forming the underlying conductive features 206 may include forming a damascene Opening in the low-k dielectric layer 204, forming a diffusion barrier layer 208 in the damascene opening, depositing a thin seed layer of copper or copper alloy, and filling the damascene opening (for example, by electroplating). Then chemical mechanical planarization ( CMP) to smooth the surface to obtain the structure shown in Figure 2.

Alternatively, the lower conductive features 206 may be other conductive features. In some embodiments, the lower conductive features 206 are doped semiconductor features, such as source/drain features, and are not surrounded by the diffusion barrier layer 208. In a further embodiment, silicide is formed on the upper surface of the doped semiconductor feature. In some embodiments, the lower conductive feature 206 is a gate electrode, capacitor, or resistor. In a further embodiment, the metal is formed on the upper surface of the gate electrode (eg metal gate), capacitor (eg metal electrode of the capacitor) or resistor.

In the embodiment shown in FIG. 2, the lower conductive feature 206 is a metal line in a metal layer in a multilayer interconnection (MLI) structure. A multi-layer interconnection (MLI) structure includes metal lines in multiple metal layers. The metal wires in different metal layers can be connected through vertical conductive features, which are called via electrode features. The multi-layer interconnection structure also includes contact points configured to connect metal lines to the gate electrode and/or doped features on the substrate 202. The multi-layer interconnect (MLI) structure is designed to couple various device features (such as various p-type and n-type doped regions, gate electrodes, and/or passive devices) to form functional circuits. In a further embodiment, the dielectric layer 204 is the first dielectric material layer of the multilayer interconnection (MLI) structure, and the lower conductive feature 206 is a metal line in the bottom metal layer of the multilayer interconnection (MLI) structure.

Referring to FIGS. 1 and 3, the method 100 proceeds to operation step 106 to form an etch stop layer 210 on the dielectric layer 204 and the underlying conductive features 206. In some embodiments, the etch stop layer 210 includes a metal oxide compound. In the metal oxide composite, some metal atoms are bonded to oxygen atoms and some metal atoms are not bonded to oxygen atoms. Metal-oxygen bonding (M-O bonding, M stands for metal element) concentration is defined as the number of metal atoms bonded to oxygen divided by the total number of metal atoms in a given volume. The metal-oxygen (M-O) bonding concentration can be referred to simply as the oxygen concentration. When the metal oxide has a higher oxygen concentration, more metal atoms are bound to oxygen, and vice versa. In some examples, the metal oxide has a metal-oxygen (M-O) bonding concentration greater than 80%, such as about 90%. In other examples, the metal oxide has a metal-oxygen (M-O) bonding concentration of about 30% to about 60%, for example about 50%.

In some embodiments, the etch stop layer 210 includes metal oxide, nitride, oxynitride, or a combination thereof, including selected from hafnium (Hf), ruthenium (Ru), zirconium (Zr), aluminum (Al), titanium (Ti) or a combination of metals. The etch stop layer 210 may be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating process, or other suitable methods.

在此特定示例中，金屬氧化物組成還包含氮，其中金屬元素鍵結在氮與氧之間，並且氧進一步與氫鍵結，從而形成氫氧基（-OH）。 換句話說，金屬-氧（M-O）鍵為金屬-氫氧（M-OH）基（或N-M-OH基）的一部分。如以上所述，在一些實施例中，金屬可為鉿（Hf）、釕（Ru）、鋯（Zr）、鋁（Al）及鈦（Ti）或其組合中的一種。在進一步的實施例中，蝕刻停止層210中的金屬為鋁（Al），且金屬氧化物組成可表示為第4圖中所示的化學式。含有氧化鋁及富含氫氧基的蝕刻停止層的密度可能約為2.64g/cm³ 。This will be further described in conjunction with Figures 1B, 1C and 1D. Operation step 106 includes a special treatment that significantly reduces or substantially excludes the hydroxyl groups from the etch stop layer 210. Without the above special treatment, the etch stop layer will be rich in hydroxyl groups (especially for surface hydroxyl groups) and the metal-oxygen (MO) bond can be represented by the following chemical formula as part of the material composition:

In this particular example, the metal oxide composition also contains nitrogen, where the metal element is bonded between nitrogen and oxygen, and oxygen is further bonded with hydrogen, thereby forming a hydroxyl group (-OH). In other words, the metal-oxygen (MO) bond is part of a metal-oxygen (M-OH) group (or NM-OH group). As described above, in some embodiments, the metal may be one of hafnium (Hf), ruthenium (Ru), zirconium (Zr), aluminum (Al), and titanium (Ti), or a combination thereof. In a further embodiment, the metal in the etch stop layer 210 is aluminum (Al), and the metal oxide composition can be expressed as the chemical formula shown in FIG. 4. The density of the etch stop layer containing aluminum oxide and rich in hydroxyl groups may be about 2.64 g/cm ³ .

The hydroxyl group has the highest concentration on the upper surface of the etch stop layer. Even in the vicinity of the lower conductive feature 206, a small amount of hydroxyl groups are present under the upper surface. Because the hydroxyl groups are permeable to oxidize the underlying conductive features 206, a thick etch stop layer is usually required, such as about 10 nm to about 20 nm, to reduce the concentration of hydroxyl groups near its lower surface to prevent the metal from covering under the oxide . Various embodiments of the special processing in operation step 106 will be discussed below, which allows the etch stop layer 210 to be substantially free of hydroxyl groups, and in some specific examples to achieve a thickness of less than about 50Å, for example, a thickness of about 10Å to 30Å Range (for example, 20Å).

Please refer to FIG. 1B. In an embodiment, operation step 106 includes operation step 122 to form a metal oxide layer as the etch stop layer 210. The metal oxide layer includes metal-oxygen (M-OH) groups. In an exemplary embodiment, operation step 122 includes an atomic layer deposition (ALD) process. In a further embodiment, the formation of the etch stop layer 210 uses metal-containing chemicals and oxidizing chemicals in each cycle of the atomic layer deposition (ALD) process (eg, sequentially). For example, metal-containing chemicals include tetrakis (ethylmethylamino) hafnium (tetrakis (ethylmethylamino) hafnium, TEMA-Hf), tetrakis (ethylmethylamido) zirconium (TEMA -Zr), TEMA-Zr), trimethyl aluminum (TMA), tris(dimethylamido) aluminum (TDMAA) and their combinations. In various examples, hafnium (ethylmethylamino) hafnium (TEMA-Hf) is used to form hafnium oxide; haze (ethylmethylamino) zirconium (TEMA-Zr) is used to form zirconium oxide; and three Methyl aluminum (TMA) or ginseng (dimethylamide) aluminum (TDMAA) is used to form alumina. According to some embodiments, the oxidant-containing substance includes oxygen molecules (O ₂ ), ozone (O ₃ ), water (H ₂ O), or a combination thereof.

The etch stop layer 210 may be formed through an appropriate atomic layer deposition (ALD) process, such as a thermal atomic layer deposition (ALD) process with a temperature rise, a plasma-assisted plasma atomic layer deposition (ALD) process with plasma assist, or thermally-added plasma Atomic layer deposition (ALD) process. In some embodiments, the atomic layer deposition (ALD) process for forming the etch stop layer 210 includes a process temperature in the range of approximately 200°C to 400°C. In some embodiments, the atomic layer deposition (ALD) process for forming the etch stop layer 210 includes a process temperature for metal-containing chemicals of about 50°C to 100°C, and a vapor pressure of about 0.05 Torr to 0.5 Torr. In one example, the atomic layer deposition (ALD) process for forming the etch stop layer 210 includes zirconium (TEMA-Hf) or zirconium (ethylmethylamide) hafnium (ethylmethylamide) TEMA-Zr) process temperature is about 70ºC, and vapor pressure is about 0.05Torr to 0.2Torr. In another example, the atomic layer deposition (ALD) process for forming the etch stop layer 210 includes a process temperature for trimethyl aluminum (TMA) of about 70°C and a vapor pressure of about 0.1 Torr to 0.4 Torr. In yet another specific example, the atomic layer deposition (ALD) process for forming the etch stop layer 210 includes a process temperature for para-(dimethylamino) aluminum (TDMAA) at about 70ºC and a steam pressure at about 50 Torr to 200 Torr Scope.

Please refer to FIG. 1B again. In an embodiment, the operation step 106 further includes the operation step 124 to deposit a dopant 212 (FIG. 5) into the metal oxide-containing material. In the illustrated embodiment, the dopant includes a silicon-based monomer. Monomers are molecules that can, but do not crosslink with other monomers. The silicon-based monomer reacts with the hydroxyl group and replaces the metal-oxygen (M-OH) group with a metal-oxide-silicon (M-O-Si) group. The operation step 124 may be an in-situ doping process having the operation step 122, which means that the operation step 122 and the operation step 124 may be performed in the same process reaction chamber. In addition, no vacuum break may occur between operation step 122 and operation step 124. In some embodiments, the dopant source is introduced into the dopant bath at a temperature ranging from approximately 350 ºC to 400 ºC and a pressure ranging from approximately 500 mTorr to 800 mTorr, for example using rapid thermal chemical vapor deposition techniques. In some embodiments, the silicon-based monomer is implanted into the etch stop layer 210 by plasma immersion implantation technology. In some alternative embodiments, the etch stop layer 210 is rinsed with a solution containing a silicon-based monomer, and then subjected to a heat treatment to evaporate the solution, while the silicon-based monomer remains on the surface of the etch stop layer 210.

Figure 6 shows an exemplary chemical formula using silicon-based monomers as dopants. The silicon-based monomer 212 includes functional groups on all four sides of the silicon atom. Specifically, the four sides of the monomer 212 include functional groups R1, R2, R3, and R4, where each functional group may independently be the same as or different from one or other functional groups. In an example, the monomer 212 has four identical functional groups, such as four methyl groups. In another example, the monomer 212 has four different functional groups. Each functional group can independently represent multiple elements or molecules, including but not limited to hydrogen, methyl, or ethyl. In some further embodiments, the functional groups may not be directly bonded to silicon (Si) atoms, but are bonded through oxygen to form Si-O-R groups. In some embodiments, one or more functional groups may be able to provide cross-linking ability with another monomer.

In some embodiments, the monomer 212 may include a coordination of an alkyl group having 1 to 20 carbons (C ₁ -C ₂₀ ), which has an acyclic structure or a cyclic structure. For example, the ring structure may be an aromatic ring. In other examples, the alkyl group further includes functional groups, such as -I, -Br, -Cl, -NH ₂ , -COOH, -OH, -SH, -N ₃ , -S(=O)-, alkene, Alkynes, imines, ethers, esters, aldehydes, ketones, amides, ballast, acetic acid, cyanide, or combinations thereof. In some embodiments, the monomer 212 may include coordination that is an aromatic group or a heterocyclic group. The aromatic group may include a chromophore and include an alkyl group having 3 to 20 carbons (C3-C20). In some embodiments, the aromatic group may be phenyl, naphthyl, phenanthrenyl, anthracenyl, phenalenyl, or other aromatic derivatives containing one to five-membered rings. In this embodiment, each functional group is methyl, ethyl or phenyl.

The chemical reaction about the hydrogen in the M-OH group replaced by the silicon-based monomer (as shown in Figure 7) can be described as the formation of a self-assembled monolayer. In the formation of a self-assembled monolayer, the functional groups of the monomer (for example, R4) interact with the metal oxide surface through hydrogen bonding. Due to attractive forces such as van der Walls (van der Walls) interactions between alkyl chains and head groups (eg, dipole-dipole interactions), the order of monomers on the oxide surface occurs And the condensation of R4 with the metal oxide-OH group. In the example where R4 is -O-CH ₂ CH ₃ , condensation produces an ethanol molecule (CH ₃ CH ₂ -OH) and bonds Si to oxygen in the MO- group through a covalent bond to form a MO-Si group . The other three functional groups (R1-R3) can remain on the other three coordinations of the Si atom. In Figure 7, for simplicity, R1-R3 are shown only on one silicon atom. Therefore, the metal oxide composite can be expressed as MO _x Si _y C _z . By converting the M-OH group to the MO-Si group, the hydroxyl group is eliminated and the oxidation ability is lost.

Operation step 124 may further include plasma surface treatment, such as Ar plasma surface treatment or CO ₂ plasma surface treatment, to promote the reaction between hydroxyl groups and silicon-based monomers to replace M-OH groups with silicon Hydrogen (which can also be regarded as a displacement reaction). In some embodiments, at least 80% of the hydroxyl groups are eliminated. In some embodiments, more than 99% of the hydroxyl groups are eliminated. In some embodiments, operation step 124 may include a two-step heating process, which includes doping the monomer and generating a substitution reaction at a first temperature below a temperature threshold to trigger a cross-linking reaction, and then performing a baking process, which It causes a cross-linking reaction between monomers at a second temperature higher than the first temperature. During the baking process, the silicon-containing monomer becomes unstable, and the constituent -Si-R component may easily hydrolyze and become -Si-OH. Another R from the adjacent -Si-R further abstracts hydrogen from the Si-OH component. After the loss of hydrogen, Si-OH component into Si-O ^-, which is bonded to other monomers between the substituent groups R and Si aspect more active, resulting in Si-O-Si bonds two monomers. In particular, the MO-Si-O-Si-M group can be formed by crosslinking, as shown in Figure 8. In a further embodiment, operation step 124 may further include another heating process having a third temperature higher than the first and second temperatures to drive off (eg, evaporate) cross-linked by-products.

In the case of replacing hydrogen with silicon, the density of the etch stop layer 210 increases, for example, from about 15% to about 40%. Taking an alumina-containing material as an example, the density can be increased from about 2.64 g/cm ³ to about 3.3 g/cm ³ , an increase of about 25%. The benefits of eliminating hydroxyl groups can be illustrated in Figure 14. Figure 14 depicts the reflectance measurements of different sets of conductive features below. The oxidation of the metal reduces its reflectivity. Therefore, the reflectance measurement serves as a reference for the degree of oxidation of the underlying conductive features. Group I in Figure 14 shows the reflectivity of the conductive feature 206 below before the etch stop layer is deposited thereon, which marks the reference point as a metal that is substantially free of oxidation. In Group II, the reflectivity drops significantly, indicating that after a thin etch stop layer is deposited thereon, the underlying conductive features 206 are subject to oxidation. In Group III, for comparison, for another lower conductive feature 206 having an etch stop layer after the hydroxyl elimination process, the reflectivity is substantially the same as the reference point of Group I, which proves that this process can protect the lower conductive The feature 206 is protected from oxidation and even has a relatively thin etch stop layer.

Please refer to FIG. 1C. In another embodiment, operation step 106 includes operation step 132 (depositing a precursor to device 200) and operation step 134 (causing a reaction between the precursors) to form groups including MO-Si Etch stop layer. One difference between FIGS. 1B and 1C is that operation step 106 in FIG. 1C bypasses the operation step that produces the intermittent product M-OH (for example, operation step 122 in FIG. 1B), but directly forms MO-Si . As an example, operation step 132 may include providing trimethyl aluminum (TMA) precursor gas. The process pressure is approximately in the range of 2.2 torr to 2.4 torr, and the process temperature can be approximately in the range of 200ºC to 400ºC. Operation step 132 may further include providing a precursor gas containing a silicon-based monomer, such as the monomer discussed in FIG. 6 above. The oxidant gas may contain H ₂ O, H ₂ , O ₂ , O ₃ or a combination thereof. Operation step 134 may include plasma treatment, such as Ar plasma treatment or CO ₂ plasma treatment, to promote the formation of MO-Si groups. In one example, after immersion in trimethylaluminum (TMA) for about 4 seconds to 12 seconds, during the atomic layer deposition (ALD) process, the plasma treatment may last in the range of about 350ºC to 400ºC for about 2 seconds to 6 The duration in seconds. Operation step 134 may further include a baking process to trigger the cross-linking between monomers, such as discussed in Figure 8 above.

Please refer to FIG. 1D. In yet another embodiment, operation step 106 includes operation step 122 similar to that in FIG. 1B. A metal oxide layer containing M-OH groups is formed. Operation step 106 further includes operation step 154, which includes plasma treatment of the etch stop layer to eliminate hydroxyl groups. In some embodiments, the plasma treatment is a plasma treatment including N ₂ or a plasma treatment including NH ₃ . The plasma can be generated using mixed-frequency radio frequency (RF) energy. Radio frequency (RF) energy is used in frequency bands of approximately 13.56 MHz and approximately 350 kHz. Depending on the treatment time, the plasma treatment nitrides and densifies the surface of the metal oxide layer to a depth of about 10Å to 200Å. Nitrification replaces hydrogen in the hydroxyl group with nitrogen. In other words, the M-OH group is converted to the MON group, which also weakens the strong oxidation ability of the etch stop layer. In one example, the plasma treatment includes NH ₃ , the temperature is in the range of about 200°C to 400°C, and the pressure is in the range of about 2.2 torr to 2.4 torr for about 2 to 6 seconds.

After operation 106, in various embodiments, most of the oxygen present in the M-O bond bonds with elements other than hydrogen to form an M-O-X bond (X represents an element other than hydrogen, such as silicon or nitrogen). Therefore, the concentration of hydroxyl groups is greatly reduced. In addition, since the hydrogen before the displacement has the highest concentration on the upper surface of the etch stop layer, element X has the highest concentration on the upper surface of the etch stop layer and has a decreasing concentration gradient when the depth is far from the upper surface. In other words, the element X has a higher concentration in the upper part of the etch stop layer than in the lower part.

Referring to FIGS. 1A and 9, the method 100 proceeds to operation step 108, forming a cap layer 218 on the etch stop layer 210 having a composition different from that of the etch stop layer 210, and may be formed of a nitrogen-free material, such as SiC, doped Silicon oxycarbide (SiCO, also known as ODC) or other suitable materials. The cap layer 218 may be formed in situ with the formation of the etch stop layer 210, which means that the etch stop layer 210 and the cap layer 218 may be formed in the same process reaction chamber. In addition, no vacuum break occurs between the formation of the etch stop layer 210 and the formation of the cap layer 218. Both the deposition of the etch stop layer 210 and the cap layer 218 can be performed at an elevated temperature, for example, when formed in situ, the corresponding wafer (the wafer on which the device 200 is located) can be continuously heated, and there is no need to cool the wafer And, the wafer is heated again between the formation of the etch stop layer 210 and the formation of the cap layer 218, which results in less thermal budget.

The precursor used to form the cap layer 218 may include SiH ₄ , Si(CH ₃ ) ₄ (4MS), Si(CH ₃ ) ₃ H(3MS), methyldiethoxysilane (mDEOS), and combinations thereof . In one embodiment, the etch stop layer 210 and the cap layer 218 have a common precursor (for example, 3MS and/or 4MS as the silicon-based monomer used to form the etch stop layer 210). After forming the etch stop layer 210, if necessary, additional precursors may be added to continue forming the cap layer 218. In one embodiment, the cap layer 218 is formed of oxygen-doped silicon carbide (ODC), and the precursors may include CO ₂ , Si(CH ₃ ) ₄ , Si(CH ₃ ) ₃ H, He, O ₂ , N ₂ , Xe Wait. In some embodiments, the cap layer 218 is a nitrogen-free layer. The thickness of the cap layer 218 may be between about 20Å and 50Å. In a particular example, the cap layer 218 is an ODC layer about 30Å thick, and the etch stop layer 210 is less than about 30Å, such as about 20Å.

After the cap layer 218 is formed, a damascene process may be performed to form an upper structure, for example, a via electrode and a metal line (for example, a copper line) located above. As is known, the via electrode and the metal line located above can be formed through a single damascene process or a dual damascene process. Referring to FIGS. 1 and 10, the method 100 proceeds to operation step 110 to form a dielectric layer 220 on the cap layer 218. In some embodiments, the dielectric layer 220 is one of a plurality of inter-metal dielectric (IMD) layers. In a further embodiment, the dielectric layer 220 further includes a via hole metal interlayer dielectric (IMD) layer 222 and a trench metal interlayer dielectric (IMD) layer 224. First, a via metal interlayer dielectric (IMD) layer 222 is formed on the cap layer 218. The via metal interlayer dielectric (IMD) layer 222 may be a dielectric layer with a low-k value of less than about 3.5 or an ultra-low-k dielectric layer with a k value of less than about 2.7, and may include carbon-doped silicon oxide and fluorine-doped silicon oxide , Organic low-k materials and porous low-k materials. The forming method includes spin coating, chemical vapor deposition (CVD), or other known methods. Then, a trench metal interlayer dielectric (IMD) layer 224 is formed on the via metal interlayer dielectric (IMD) layer 222. A method and materials similar to those of the via metal interlayer dielectric (IMD) layer 222 may be used Trench metal interlayer dielectric (IMD) layer 224. In some embodiments, the trench metal interlayer dielectric (IMD) layer 224 and the via hole metal interlayer dielectric (IMD) layer 222 are made of a porous material.

Referring to FIGS. 1 and 11, the method 100 proceeds to operation step 112, and an opening 230 is formed in the dielectric layer 220 through one or more etching processes, wherein the opening 230 is at least partially aligned with the conductive features 206 below. In the illustrated embodiment, the opening 230 includes a via opening 232 and a trench opening 234. The formation of via openings 232 and trench openings 234 can be assisted by the photoresist used to define the pattern. FIG. 11 illustrates the photoresist 226 used to define the pattern of the trench opening 234. It should be noted that the cap layer 218 is nitrogen-free, thus substantially eliminating the adverse effect of nitrogen on the photoresist (called PR poisoning) because the cap layer 218 prevents the release of nitrogen from below to the photoresist 226. In particular, when the via opening 232 is formed, the cap layer 218 can also prevent nitrogen from poisoning the photoresist (not shown). Then the photoresist 226 is removed by a suitable process, such as photoresist stripping or oxygen ashing.

Referring to FIGS. 1 and 12, the method 100 proceeds to operation step 114, and the opening 230 is filled with a conductive material. The opening 230 includes partially removing the cap layer 218 and the etch stop layer 210 from the bottom of the via opening 232 in an etching process, and exposing the conductive features 206 below. In the subsequent operation steps, a diffusion barrier layer 242 is formed. The remaining via opening 234 and trench opening 234 are then filled with a conductive material such as copper or copper alloy. Then chemical mechanical polish (CMP) is performed to remove excess material. The remaining portion of the conductive material forms the via electrode 244 and the wire 246.

Please refer to FIG. 13. In an alternative embodiment, the method 100 may skip the formation of the cap layer 218 (ie, operation step 108) and form the dielectric layer 220 directly above the etch stop layer 210. In a particular embodiment, the thickness of the etch stop layer 210 without the cap layer 218 thereon is less than about 50Å, such as about 40Å. The method 100 may perform further subsequent operations to complete the manufacturing of the device 200. For example, the method 100 may include forming a higher film layer than a multi-layer interconnection (MLI) structure and forming a metal interconnection connecting the gate or source/drain features of the transistor to other parts of the device 200 to form a complete IC.

Although not limiting, one or more embodiments herein provide many benefits for semiconductor devices and methods of forming the same. For example, the embodiments of the present disclosure provide an etch stop layer with a thickness of only a few tens of Angstroms. The etch stop layer is substantially free of hydroxyl groups, which protects the underlying conductive features from oxidation, reduces parasitic capacitance, and further increases the operating speed of the integrated circuit. In addition, the etch stop layer formation method can be easily integrated into existing semiconductor manufacturing processes.

In an exemplary type, this embodiment provides a method of manufacturing a semiconductor device. The above method includes providing a dielectric layer; forming a metal line in the dielectric layer; forming an etch stop layer on the metal line, wherein the etch stop layer includes metal atoms bonded to hydroxyl groups; and performing a treatment on the etch stop layer In the process, elements other than hydrogen are used to replace hydrogen in the hydroxyl group; the etching stop layer is partially etched to expose the metal line; and a conductive feature is formed on the etching stop layer and is in physical contact with the metal line. In some embodiments, the treatment process includes plasma treatment with nitrogen, and the above element is nitrogen. In some embodiments, the processing process includes depositing a dopant, and the above element is silicon. In some embodiments, the dopant includes a silicon-based monomer. In some embodiments, the silicon-based monomer includes at least one functional group selected from methyl, ethyl, or phenyl. In some embodiments, after the processing process is performed, the etch stop layer includes M-O-Si groups, where M represents a metal atom. In some embodiments, after the processing process is performed, the etch stop layer includes Si—O—Si groups. In some embodiments, the Si-O-Si group is part of the M-O-Si-O-Si-M group, and M represents a metal atom. In some embodiments, the metal atom is selected from one of hafnium, zirconium and aluminum. In some embodiments, the processing process includes a two-step heating process having a first temperature followed by a second temperature higher than the first temperature. In some embodiments, the above elements have a higher concentration in the upper portion of the etch stop layer than in the lower portion of the etch stop layer. In some embodiments, the above method further includes forming a cap layer on the etch stop layer, wherein the formation of the cap layer and the processing process include using the same precursor.

In another exemplary type, this embodiment provides a method of manufacturing a semiconductor device. The above method includes providing a substrate having a first dielectric layer and a conductive feature buried in the first dielectric layer; forming an etch stop layer on the first dielectric layer and the conductive feature, wherein the etching stops The layer includes a metal oxide; a silicon-containing dopant is deposited to the etch stop layer, wherein the silicon-containing dopant reacts with the metal oxide to generate a MO-Si group, and M represents a metal atom in the metal oxide; forming A second dielectric layer on the etch stop layer; and forming a conductive structure in the second dielectric layer, wherein the conductive structure is electrically connected to the conductive feature. In some embodiments, the silicon-containing dopant is a monomer having four functional groups bonded to silicon atoms. In some embodiments, at least one of the four functional groups is selected from methyl, ethyl, or phenyl. In some embodiments, the above method further includes a plasma surface treatment after depositing the silicon-containing dopant. In some embodiments, after depositing the silicon-containing dopant, the etch stop layer is substantially free of hydroxyl groups.

In yet another exemplary type, the present embodiment provides a semiconductor device including a first conductive element disposed in the first dielectric layer; an etch stop layer disposed on the first dielectric layer, wherein The etch stop layer includes a MOX group, M represents a metal element, and X represents an element other than hydrogen; a second dielectric layer is disposed on the etch stop layer; and a second conductive element is buried in the second dielectric layer , And through the etch stop layer, where the second conductive element is in physical contact with the first conductive element. In some embodiments, elements other than hydrogen have a higher concentration in the upper portion of the etch stop layer than in the lower portion of the etch stop layer. In some embodiments, the thickness of the etch stop layer is less than 50 Angstroms.

The above outlines the features of several embodiments of the present invention, so that those skilled in the art can more easily understand the type of the present disclosure. Those of ordinary skill in the art should understand that the present disclosure can be easily used as a basis for changes or design of other processes or structures to perform the same purposes and/or obtain the same advantages as the embodiments described herein. Any person with ordinary knowledge in the technical field can also understand that the structure equivalent to the above does not deviate from the spirit and scope of this disclosure, and can be changed, replaced, and retouched without departing from the spirit and scope of this disclosure. .

100: Method 102, 104, 106, 108, 110, 112, 114, 122, 124, 132, 134, 154: operation steps 200: device 202: base 204, 220: dielectric layer 206: Lower conductive features 208, 242: diffusion barrier 210: Etching stop layer 212: monomer/dopant 218: Cover 222: via metal interlayer dielectric (IMD) layer 224: Trench metal interlayer dielectric (IMD) layer 226: Photoresist 230: opening 232: via opening 234: Groove opening 244: via electrode 246: Wire

FIGS. 1A, 1B, 1C, and 1D are flowcharts illustrating a method of manufacturing a semiconductor device having an etch stop layer according to some embodiments. FIGS. 2, 3, 5, 9, 10, 11, 12, and 13 are schematic cross-sectional views illustrating semiconductor structures during the manufacturing process according to the methods of FIGS. 1A, 1B, 1C, and 1D according to some embodiments. Figures 4, 6, 7, 8 and 14 illustrate exemplary chemical formulas of metal oxide composites and related physical properties.

no

100: Method

102, 104, 106, 108, 110, 112, 114: operation steps

Claims (20)

A method of manufacturing a semiconductor device, including: One provides a dielectric layer; Forming a metal line in the dielectric layer; Forming an etch stop layer on the metal line, wherein the etch stop layer includes a metal atom bonded to a hydroxyl group; Performing a treatment process on the etch stop layer to replace the hydrogen in the hydroxyl group with an element other than hydrogen; Partially etching the etch stop layer to expose the metal line; and A conductive feature is formed on the etch stop layer and is in physical contact with the metal line. The method for manufacturing a semiconductor device as described in item 1 of the patent application scope, wherein the processing process includes a plasma treatment containing nitrogen, and the element is nitrogen. The method for manufacturing a semiconductor device as described in item 1 of the patent application scope, wherein the processing process includes depositing a dopant and the element is silicon. The method for manufacturing a semiconductor device as described in item 3 of the patent application range, wherein the dopant includes a silicon-based monomer. The method for manufacturing a semiconductor device as described in item 4 of the patent application, wherein the silicon-based monomer includes at least one functional group selected from methyl, ethyl, or phenyl. The method for manufacturing a semiconductor device as described in item 1 of the patent application scope, wherein after the processing process is performed, the etch stop layer includes an M-O-Si group, and M represents the metal atom. The method for manufacturing a semiconductor device as described in item 1 of the patent application scope, wherein after the processing process is performed, the etch stop layer includes a Si—O—Si group. The method for manufacturing a semiconductor device as described in item 7 of the patent application scope, wherein the Si-O-Si group is a part of the M-O-Si-O-Si-M group, and M represents the metal atom. The method for manufacturing a semiconductor device as described in item 1 of the patent application, wherein the metal atom is selected from one of hafnium, zirconium and aluminum. The method for manufacturing a semiconductor device as described in item 1 of the patent application range, wherein the processing process includes a two-step heating process having a first temperature followed by a second temperature higher than the first temperature. The method of manufacturing a semiconductor device as described in item 1 of the patent application range, wherein the element is located in an upper portion of the etch stop layer with a higher concentration than in a lower portion of the etch stop layer. The method for manufacturing a semiconductor device as described in item 1 of the scope of patent application further includes forming a cap layer on the etch stop layer, wherein the formation of the cap layer and the processing process include using the same precursor. A method of manufacturing a semiconductor device, including: Providing a substrate with a first dielectric layer and a conductive feature embedded in the first dielectric layer; Forming an etch stop layer on the first dielectric layer and the conductive feature, wherein the etch stop layer includes a metal oxide; Depositing a silicon-containing dopant to the etch stop layer, wherein the silicon-containing dopant reacts with the metal oxide to generate an M-O-Si group, and M represents a metal atom in the metal oxide; Forming a second dielectric layer on the etch stop layer; and A conductive structure is formed in the second dielectric layer, wherein the conductive structure is electrically connected to the conductive feature. The method for manufacturing a semiconductor device as described in item 13 of the patent application range, wherein the silicon-containing dopant is a monomer having four functional groups bonded to a silicon atom. The method for manufacturing a semiconductor device as described in item 14 of the patent application range, wherein at least one of the four functional groups is selected from methyl, ethyl or phenyl. The method for manufacturing a semiconductor device as described in item 13 of the patent application scope further includes a plasma surface treatment after depositing the silicon-containing dopant. The method for manufacturing a semiconductor device as described in item 13 of the patent application range, wherein after depositing the silicon-containing dopant, the etch stop layer is substantially free of a hydroxyl group. A semiconductor device, including: A first conductive element disposed in a first dielectric layer; An etch stop layer is disposed on the first dielectric layer, wherein the etch stop layer includes an M-O-X group, M represents a metal element, and X represents an element other than hydrogen; A second dielectric layer disposed on the etch stop layer; and A second conductive element is buried in the second dielectric layer and passes through the etch stop layer, wherein the second conductive element is in physical contact with the first conductive element. The semiconductor device as described in item 18 of the patent application range, wherein the element other than hydrogen has a higher concentration in an upper portion of the etching stop layer than in a lower portion of the etching stop layer. The semiconductor device as described in item 18 of the patent application range, wherein the thickness of the etch stop layer is less than 50 angstroms.

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