TW202016501A - On-chip curvature correction structure and method thereof - Google Patents

Abstract

An on-chip curvature correction method includes: measuring an unknown value with a sensor and converting a measured value into a digital code to generate a digitally-converted value; transmitting the digitally-converted value to a process-variation correction unit and further providing a correction value to the process-variation calibration unit for process-variation calibration; further providing the correction value to a curvature correction unit to generate a curvature correction value; and correcting the digitally-converted value with the curvature correction value to obtain a corrected digitally-converted value. The on-chip curvature correction method is successful in simplifying the correction process, reducing hardware cost and effectively minimizing errors.

Description

Chip built-in curvature correction structure and method

The present invention relates to an on-chip curvature correction architecture and method; in particular, to an on-chip curvature correction architecture and method; more particularly, to an on-chip curvature correction architecture and method The on-chip curvature correction architecture and method for single-point calibration application of all-digital [all-digital] time-domain temperature sensor.

Conventional digital temperature sensing systems, such as the invention patent of the "Digital Temperature Sensing System" No. I275782 of the Republic of China, disclose a temperature sensing system. The temperature sensing system is used to convert a temperature to be measured into a corresponding digital signal. The temperature sensing system includes a temperature sensor and a time-to-digital conversion circuit. The temperature sensor is used to generate a time signal that changes with the temperature to be measured. The time-to-digital conversion circuit is electrically connected to the temperature sensor, and the time-to-digital conversion circuit is used to convert the time signal into the corresponding digital signal.

Another conventional digital temperature sensing system, such as the invention patent of Republic of China Patent Announcement No. I355485 "Time Domain Digital Temperature Sensing System and Method", discloses a digital temperature sensing system and method. The digital temperature sensing system can convert a temperature to be measured into a corresponding digital output. The digital temperature sensing system includes a temperature to time conversion circuit, an adjustable reference time circuit, a time comparator, a control logic circuit and a digital output. The temperature-to-time conversion circuit is used to generate a temperature-sensitive time signal whose time width is proportional to the temperature to be measured. The adjustable reference time circuit is used to Generate a low temperature sensitive time signal whose time width is controlled by its digital set value. The time comparator is used to compare the widths of the two time signals to generate time comparison signals. The control logic circuit is used to change the digital setting value of the adjustable reference time circuit according to the time comparison signal, so that the widths of the two time signals are closest. The digital output is electrically connected to the digital input terminal of the adjustable reference time circuit so that it also serves as the output terminal of the temperature sensing system.

However, the digital temperature sensing system of the aforementioned Patent Publication Nos. I275782 and I355485 still inevitably needs to further improve its overall circuit structure. The aforementioned patent is only a reference to the technical background of the present invention and illustrates the current state of technological development, and it is not intended to limit the scope of the present invention.

Figure 1 shows a block diagram of a conventional delay line based temperature sensor architecture. Please refer to FIG. 1, the conventional delay line-based temperature sensor 1 mainly includes a delay-line-based temperature sensor [delay-line-based temperature sensor] 10 and a time-to-digital converter circuit [time-to-digital converter [11], and the delay line-based temperature sensor 10 is appropriately connected to the time-to-digital conversion circuit 11 to form a temperature sensor.

Please refer to FIG. 1 again, take the trigger signal Start of a circuit as an operation signal, and input the trigger signal Start of the circuit to the delay line-based temperature sensor 10 (as shown on the left side of FIG. 1) , And convert a temperature to be measured in the delay line-based temperature sensor 10 to temperature-time pulse conversion [temperature sensing] to generate a temperature-dependent time pulse width signal t _p (T) for subsequent pulse width Measure.

Please refer to FIG. 1 again, and then input the temperature-dependent time pulse width signal t _p (T) to the time-to-digital conversion circuit 11 for pulse width measurement, and use a counter to measure the temperature dependence Time pulse width signal t _p (T) to generate a temperature logarithmic output signal or a temperature logarithmic output value N ( T ), as shown on the right side of Figure 1.

However, since the digital output value signal of the conventional delay line-based temperature sensor 1 is often affected by process variation or other factors, errors will inevitably occur, so it is necessary to properly correct the error value of the digital output value N ( T ) , For example: process variation correction or other variation parameter correction.

In view of this, the present invention provides a built-in curvature correction structure and method for the chip to output a digital conversion output value or a temperature logarithmic output value to a process variation correction unit and provide a correction Value to the process variation correction unit to perform process variation correction, and output the correction value to a curvature correction unit to generate a curvature error value, and use the curvature error value to adjust and correct the digital conversion output value or temperature logarithm The output value is used to generate a digital conversion output correction value or a temperature logarithmic output correction value. Therefore, the temperature logarithm error value can be greatly reduced relative to the conventional delay line-based temperature sensor.

The main object of the present invention is to provide a built-in curvature correction structure and method of the chip, which outputs a digital conversion output value or a temperature logarithmic output value to a process variation correction unit, and provides a correction value to the process variation correction Unit to perform process variation correction, and output the correction value to a curvature correction unit to generate a curvature error value, and use the curvature error value to adjust and correct the digital conversion output value or temperature logarithmic output value to generate a Digital conversion output correction value or a temperature logarithmic output correction value, in order to achieve the purpose of reducing the temperature logarithm error value.

In order to achieve the above objective, the on-chip curvature correction architecture of the preferred embodiment of the present invention includes: a delay line based measuring device for measuring and digitally converting a value to be measured to generate a digitally converted output value A process variation correction unit, which is connected to the delay line-based measuring device, and outputs the digital conversion output value to the process variation correction unit for adjustment and correction of the digital conversion output value, and provides a correction Value to the process variation correction unit to generate a process variation correction value; and a curvature correction unit connected to the delay line-based gauge and outputting the correction value to the curvature correction unit for adjustment and correction The digital conversion output value generates a curvature error value; wherein the curvature error value is used to adjust and correct the digital conversion output value, so as to generate a digital conversion output correction value.

In the preferred embodiment of the present invention, the correction value is a single-point correction value.

The curvature correction unit of the preferred embodiment of the present invention selects a high correction point relative to the single point correction value to perform a high point correction procedure.

The curvature correction unit of the preferred embodiment of the present invention selects a low correction point relative to the single point correction value to perform a low point correction procedure.

The curvature correction unit of the preferred embodiment of the present invention is a second-order curve curvature correction unit or a multi-order curve curvature correction unit.

In the preferred embodiment of the present invention, the process variation correction value is a single batch process variation correction value.

The curvature error value of the preferred embodiment of the present invention is applicable to the curvature error value of a single batch process.

In order to achieve the above objective, the on-chip curvature correction method of the preferred embodiment of the present invention includes: measuring and digitizing a value to be measured in a delay line-based gauge to generate a digitally converted output value; The digitally converted output value is output to a process variation correction unit and provides a correction value to the process variation correction unit to generate a process variation correction value; the correction value is output to a curvature correction unit to generate a curvature error value; And use the curvature error value to adjust and correct the digital conversion output Value to generate a digitally converted output correction value.

In the preferred embodiment of the present invention, the correction value is a single-point correction value.

The curvature correction unit of the preferred embodiment of the present invention selects a high correction point relative to the single point correction value to perform a high point correction procedure.

The curvature correction unit of the preferred embodiment of the present invention selects a low correction point relative to the single point correction value to perform a low point correction procedure.

The curvature correction unit of the preferred embodiment of the present invention is a second-order curve curvature correction unit or a multi-order curve curvature correction unit.

In the preferred embodiment of the present invention, the process variation correction value is a single batch process variation correction value.

The curvature error value of the preferred embodiment of the present invention is applicable to the curvature error value of a single batch process.

1‧‧‧ Conventional delay line based temperature sensor

10‧‧‧ Delay line-based temperature sensor

11‧‧‧Time digital conversion circuit

2‧‧‧Chip built-in curvature correction framework

2A‧‧‧Chip built-in curvature correction framework

20‧‧‧Intelligent temperature sensing architecture

21‧‧‧Intelligent temperature sensor

21A‧‧‧Delay line based measuring instrument

22‧‧‧ Process variation correction unit

23‧‧‧ Curvature correction unit

230‧‧‧Multi-degree curve curvature correction unit

Figure 1: Block diagram of a conventional delay line-based temperature sensor architecture.

Fig. 2: A schematic diagram of a smart temperature sensor applied to the on-chip curvature correction architecture of the preferred embodiment of the present invention.

Figure 3: Schematic diagram of the built-in curvature correction architecture of the chip according to the preferred embodiment of the present invention.

Fig. 3A: A schematic diagram of a built-in curvature correction structure of a chip according to another preferred embodiment of the present invention.

Fig. 4: A schematic diagram of a circuit structure of a multi-level curve curvature correction unit using a built-in curvature correction architecture of a chip according to a preferred embodiment of the present invention.

Fig. 5: A schematic diagram of a curve in which the built-in curvature correction architecture of the chip according to the preferred embodiment of the present invention corrects the curvature error of the digital value error curve to the ideal measured value.

FIG. 5A: A schematic diagram of curvature correction achieved by the built-in curvature correction structure of the chip according to the preferred embodiment of the present invention and its error curve.

Fig. 6: A schematic flow chart of a method for correcting a built-in curvature of a chip according to a preferred embodiment of the invention.

Figure 7: A schematic diagram of the relationship between the temperature value and the digital value of the ideal value, the uncorrected value, and the corrected value under actual operation measurement of the built-in curvature correction architecture of the chip according to the preferred embodiment of the present invention.

Fig. 8: The curve diagram of the relationship between the uncorrected value and the temperature value of the corrected value and the error value under actual operation measurement of the built-in curvature correction framework of the chip according to the preferred embodiment of the present invention.

In order to fully understand the present invention, preferred embodiments will be exemplified below and described in detail in conjunction with the accompanying drawings, and they are not intended to limit the present invention.

The on-chip curvature correction architecture and method applied to single-point calibration according to the preferred embodiment of the present invention are applicable to various digital conversion systems and methods, various time-to-digital conversion systems and methods, or various temperature sensing application systems and Methods, such as temperature monitoring systems, are also applicable to various automatic or semi-automatic temperature sensing operating systems and methods, such as system temperature measuring operating systems, but they are not intended to limit the scope of the present invention.

FIG. 2 shows a schematic diagram of a smart temperature sensor applied to the on-chip curvature correction architecture of the preferred embodiment of the present invention. Please refer to FIG. 2. For example, the on-chip curvature correction architecture of the preferred embodiment of the present invention is applicable to an intelligent temperature sensing architecture 20, and the intelligent temperature sensing architecture 20 includes an intelligent temperature sensing architecture. Detector [smart temperature sensor, STS] 21 and a process variation calibration circuit [process-variation calibration circuit, PVCC] 22.

FIG. 3 shows a schematic diagram of a built-in curvature correction structure of a chip according to a preferred embodiment of the present invention. Please refer to FIG. 3, for example, the preferred embodiment of the present invention selects an on-chip curvature correction architecture 2 including a smart temperature sensor 21, a process variation correction unit 22 and a curvature correction unit [curvature correction unit circuit〕23.

Please refer to FIG. 3 again. In the preferred embodiment of the present invention, the process variation correction unit 22 and the curvature correction unit 23 are configured in on-chip mode to improve the efficiency of process variation correction and curvature correction And convenience, the built-in curvature correction architecture 2 of the chip does not require additional configuration of an external process variation correction unit or an external curvature correction unit and its peripheral equipment.

Please refer to Figures 2 and 3, for example, the intelligent temperature sensor 21 [delay line-based temperature sensor or delay line-based sensor] is used to Value] for measurement, that is, using the intelligent temperature sensor 21 [delay line-based temperature sensor or delay line-based sensor] to perform temperature-to-digital conversion of the temperature to be measured [or a value to be measured], To generate a temperature logarithmic output value N ( T ) or a digital conversion output value, and the temperature logarithmic output value N ( T ) or digital conversion output value needs to be properly corrected in order to correct process variation and curvature variation to the temperature For digital output value N ( T ) or digital conversion output value.

Please refer to FIGS. 2 and 3 again. For example, the process variation correction unit 22 is appropriately connected to the intelligent temperature sensor 21 [delay line-based temperature sensor or delay line-based gauge], and The temperature logarithmic output value N ( T ) or digital conversion output value is output to the process variation correction unit 22 for adjustment and correction of the temperature logarithmic output value N ( T ) or digital conversion output value, and provides a correction value N _C to the process variation correcting unit 22, so as to generate a process variation correction value n, the process variation and outputs the correction value to the n [smart temperature sensor 21 temperature sensor or group delay amount of the delay line group Detector] to eliminate the process variation of the temperature logarithmic output value N ( T ) or digital conversion output value. In the preferred embodiment of the present invention, the process variation correction value n is a single batch process variation correction value.

FIG. 3A shows a schematic diagram of a built-in curvature correction structure of a chip according to another preferred embodiment of the present invention. Please refer to FIG. 3A. For example, another preferred embodiment of the present invention selects an on-chip curvature correction architecture 2A includes a delay line-based gauge 21A, a process variation correction unit 22 and a curvature correction unit 23.

FIG. 4 shows a schematic diagram of the circuit architecture of the built-in curvature correction architecture of the chip using a multi-level curvature correction unit. Please refer to FIGS. 3 and 4, for example, a multi-degree curve curvature correction unit 230 is connected to the intelligent temperature sensor 21 [delay line-based temperature sensor or delay line-based measuring device], And the correction value N _{C is} output to the curvature correction unit 23 to perform adjustment and correction to generate a curvature error value C ( N ( T )). The curvature error value of the preferred embodiment of the present invention is applicable to the curvature error value of a single batch process. In a preferred embodiment of the present invention, the calibration value can be selected as a one-point calibration value [one-point or single-point calibration]. Since [ N _diff ( T )] ² must be a positive value, there is no need to additionally judge the mechanism or circuit of the high temperature region and the low temperature region, so the on-chip curvature correction method and its structure of the preferred embodiment of the present invention can simplify the curvature The circuit of the correction unit thus improves its cost efficiency.

FIG. 5 shows a schematic diagram of a curve in which the built-in curvature correction architecture of the chip according to the preferred embodiment of the present invention corrects the curvature error of the digital value error curve to the ideal measured value. Please refer to FIG. 5, for example, the preferred embodiment of the present invention has a built-in curvature correction architecture suitable for a digital value error curve, and the digital value error curve has an error E ( N ( T )), and in the single After the point correction, the central digital value error E ( N _C ) = 0, and the total digital value error of the ideal measurement line [dashed line in Figure 5] is equal to zero.

FIG. 5A shows a schematic diagram of curvature error correction achieved by the built-in curvature correction structure of the chip according to a preferred embodiment of the present invention and its error curve. Please refer to FIG. 5A. For example, the preferred embodiment of the present invention uses the quadratic equation as follows: f ( x ) = c ₂ x ² + c ₁ x + c ₀

Where c ₂ , c ₁ , and c ₀ are the coefficients of the quadratic term, primary term, and constant term, respectively.

Organize the above quadratic equation as follows: f ( x )= α ( x - β ) ² + γ

g ( x )= αx ² , if β and γ are equal to 0, g ( x ) second order curve.

C(N(T))。簡言之，將該曲率誤差值C(N(T))假設為一左右對稱之曲線〔例如：二階曲線〕，且其具有一頂點〔即極值〕，如第5A圖之上半部所示。換言之，該曲率誤差值C(N(T))視為近似於g(x)，即該曲率誤差值C(N(T))

g(x)=α(x)²，其中x=N _diff (T)=N(T)-N _C ，N _diff (T)為差值，N _C 為校正值。一般而言，在傳統上需要採用三校正點方式決定校正曲線。反觀，本發明較佳實施例之晶片內建曲率校正方法及其架構僅需兩校正點〔中間點與一端點〕即可達成，且其所獲得之半邊區誤差曲線可用〝對稱(映射)方式〞獲得另一半邊，如此則可用較少之校正程序〔只需兩點〕，並在電路實作上僅需較精簡電路達成，因而提升曲率校正成本之效率。 Please refer to FIGS. 2, 3, 4 and 5A again. For example, the preferred embodiment of the present invention may select the curvature correction unit 23 as a second-order curve curvature correction unit or other multi-order curve curvature correction units. Uncurvature corrected digital value error is E ( N ( T )), while curvature corrected digital value error is E ( N _c ), and the ideal digital value is N _O ( T ), so E ( N ( T )) = N ( T )- N _O ( T ). At this time, since the preferred embodiment of the present invention chooses to adopt the single-point correction value, the central digital value error E ( N _C )=0, that is, E ( N ( T ))

C ( N ( T )). In short, the curvature error value C ( N ( T )) is assumed to be a symmetrical curve [for example: a second-order curve], and it has a vertex [ie, an extreme value], as shown in the upper half of Figure 5A Show. In other words, the curvature error value C ( N ( T )) is regarded as approximate to g ( x ), that is, the curvature error value C ( N ( T ))

g ( x )= α ( x ) ² , where x = N _diff ( T )= N ( T )- N _C , N _diff ( T ) is the difference, and N _C is the correction value. Generally speaking, traditionally, the calibration curve needs to be determined by using three calibration points. On the contrary, the on-chip curvature correction method and its structure of the preferred embodiment of the present invention can be achieved by only two correction points [middle point and one end point], and the error curve of the half-edge area obtained by it can be "symmetrical (mapped)""Obtaining the other half, so you can use fewer correction procedures [only two points], and in circuit implementation only need to achieve a more streamlined circuit, thus improving the efficiency of curvature correction costs.

Referring again to FIG. 5A, for example, the curvature correction unit 23 of the preferred embodiment of the present invention selects a high correction point [ N ( T _hc )] relative to the single-point correction value to perform a high-point correction procedure, As shown on the right of Figure 5A, the high correction point [ N ( T _hc )] can be obtained by measurement. Alternatively, the curvature correction unit 23 selects a low correction point [ N ( T _lc )] relative to the single point correction value to perform a low point correction procedure, as shown in the left side of FIG. 5A, and the low correction point [ N ( T _lc )] can be obtained by measurement.

Please refer to Figures 2, 3 and 4, for example, input the temperature logarithmic digital output value N ( T ) or digital conversion output value of which the process variation has been eliminated to the curvature correction unit 23 or the multi-level curve curvature correction The unit 230 subtracts the temperature logarithmic output value N ( T ) or digital conversion output value from the correction value N _C [single point correction value], thereby obtaining a difference value N _diff . Then, the difference N _{diff is} substituted into a second-order curvature correction circuit or a multi-order curvature correction circuit, thereby obtaining the curvature error value C ( N ( T )). Finally, the temperature logarithmic output value N ( T ) or the digital conversion output value is subtracted from the curvature error value C ( N ( T )) to obtain a temperature logarithmic output correction value N' ( T ) or digital conversion Output correction value.

Please refer to FIGS. 2, 3 and 4 again. For example, the second-order curvature correction circuit of the curvature correction unit 23 or the multi-order curve curvature correction unit 230 has a known parameter α , and the known parameter α is as follows:

Assuming that the values of E ( N ( T _hc )), E ( N ( T _lc )), N _C and N _{diff are known} , the second-order curve coefficient value α can be obtained, and the second-order curve coefficient value α can be selected by an appropriate calculation method obtain.

FIG. 6 shows a schematic flowchart of a method for correcting the built-in curvature of a chip according to a preferred embodiment of the present invention. Please refer to FIGS. 2-6. For example, the method for correcting the built-in curvature of the chip according to the preferred embodiment of the present invention includes step S1: First, a temperature to be measured or a value to be measured in the intelligent temperature sensing The device 21 [delay line-based temperature sensor or delay line-based measuring device or measuring device] performs appropriate measurement and temperature-to-digital conversion to generate the temperature-to-digital output value N ( T ) or digital conversion output value, That is, the digital output value of the uncorrected curvature, which contains E ( N' ( T )).

Please refer to FIGS. 2-6. For example, the on-chip curvature correction method of the preferred embodiment of the present invention includes step S2: Then, the temperature is outputted as a digital output value N ( T ) or a digitally converted output value to appropriate technical means is output to the process variation correcting unit 22, to adjust for correcting the temperature on the digital output value of the N (T) or digital conversion output value, and provides the correction value N _C to the process variation correcting unit 22, to generate the Process variation correction value n for adjustment and correction.

Refer to Section 2-6 shown below, for example, the wafer of the preferred embodiment of the present invention Example built-curvature correction method comprising the steps S3: Next, the correction value N _C to the output unit 23 at an appropriate curvature correction techniques , So as to generate the curvature error value C ( N ( T )), and the preferred embodiment of the present invention may choose to output the temperature logarithmic output value N ( T ) or the digitally converted output value to the curvature correction unit by appropriate technical means 23 for subsequent calibration operations.

Please refer to FIGS. 2 to 6, for example, the on-chip curvature correction method of the preferred embodiment of the present invention includes step S4: Next, the temperature error is adjusted and corrected using the curvature error value C ( N ( T )) Logarithmic digital output value N ( T ) or digital conversion output value, in order to produce the temperature logarithmic digital output correction value N' ( T ) or digital conversion output correction value, for example: the temperature logarithmic output value N ( T ) or digital The converted output value is subtracted from the curvature error value C ( N ( T )). In a preferred embodiment of the present invention, the curvature correction unit 23 may subtract the logarithmic temperature output value N ( T ) or the digitally converted output value from the curvature error value C ( N ( T )).

The preferred embodiment of the present invention can use the curvature error value C ( N ( T )) to adjust and correct the temperature logarithmic output value N ( T ) or digital conversion output value, so as to generate the temperature logarithmic output correction value N′ ( T ) Or digital conversion output correction value. Because the curvature of the second-order curve of a single batch of wafers is similar, the present invention can choose to use a single sample wafer correction coefficient to calibrate all the wafers to be tested. In other words, the curvature error value C ( N ( T )) applies to a single batch of process curvature error values.

Figure 7 shows the temperature and digital values of ideal value [ideal value], uncorrected value [uncorrected value] and corrected value [corrected value] under actual operation measurement of the built-in curvature correction architecture of the chip according to the preferred embodiment of the present invention Schematic diagram of the relationship. Please refer to FIG. 7, for example, the present invention selects eight chips to measure the temperature logarithm output value N _i ( T ) between -20 ℃ and 100 ℃, and generates its temperature pair after calibration. The digital output correction value N _i ' ( T ), and it shows that its temperature is consistent with the ideal value for the digital output correction value N _i ' ( T ).

FIG. 8 shows a schematic diagram of the relationship between the uncorrected value and the temperature value of the corrected value and the error value under actual operation measurement of the built-in curvature correction architecture of the chip according to the preferred embodiment of the present invention. Please refer to Figure 8 for example, for example, the relationship between the uncorrected value and the error value measured at a temperature of -20℃ to 100℃, as shown in the upper curve of Figure 8; The relationship between the temperature value and the error value is shown in the lower curve of FIG. 8, which shows that the present invention uses the on-chip curvature correction architecture to significantly improve the error after correction.

The foregoing preferred embodiment only exemplifies the present invention and its technical features, and the technology of this embodiment can still be appropriately implemented with various substantial equivalent modifications and/or replacements; therefore, the scope of the present invention is subject to the appended patent application The scope defined by the scope shall prevail.

2‧‧‧Chip built-in curvature correction framework

21‧‧‧Intelligent temperature sensor

22‧‧‧ Process variation correction unit

23‧‧‧ Curvature correction unit

Claims (10)

An on-chip curvature correction architecture includes: a measuring device for measuring and digitally converting a value to be measured to generate a digitally converted output value; a process variation correction unit connected to the delay Line-based measuring device, and output the digital conversion output value to the process variation correction unit, so as to adjust and correct the digital conversion output value, and provide a correction value to the process variation correction unit, so as to generate a process variation correction value ; And a curvature correction unit, which is connected to the delay line-based measuring device, and outputs the correction value to the curvature correction unit for adjustment and correction of the digitally converted output value to generate a curvature error value; wherein the curvature is used The error value is adjusted to correct the digital conversion output value, so as to generate a digital conversion output correction value. According to the on-chip curvature correction architecture described in item 1 of the patent scope, the correction value is a single-point correction value. The on-chip curvature correction architecture described in item 1 of the patent scope, wherein the curvature correction unit selects a high correction point relative to the single point correction value to perform a high point correction procedure; or, the curvature correction unit is relative to the single The point correction value selects a low correction point to perform a low point correction procedure. According to the on-chip curvature correction architecture described in item 1 of the patent scope, the curvature correction unit is a second-order curve curvature correction unit or a multi-order curve curvature correction unit. According to the on-chip curvature correction architecture described in item 1 of the patent application scope, the process variation correction value is a single batch process variation correction value. A built-in curvature correction method for a chip includes: measuring and digitally converting a value to be measured in a measuring device to generate a digitally converted output value; outputting the digitally converted output value to a process variation correction unit, And provide a correction value to the process variation correction unit to generate a process variation correction value; Output the correction value to a curvature correction unit to generate a curvature error value; and use the curvature error value to adjust and correct the digital conversion output value to generate a digital conversion output correction value. According to the on-chip curvature correction method described in item 6 of the patent scope, the correction value is a single-point correction value. According to the on-chip curvature correction method described in item 6 of the patent scope, wherein the curvature correction unit selects a high correction point with respect to the single point correction value to perform a high point correction procedure; or, the curvature correction unit with respect to the single The point correction value selects a low correction point to perform a low point correction procedure. According to the on-chip curvature correction frame method described in item 6 of the patent scope, the curvature correction unit is a second-order curve curvature correction unit or a multi-order curve curvature correction unit. According to the on-chip curvature correction frame method described in item 6 of the patent application range, the process variation correction value is a single batch process variation correction value.

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