TW202014895A - Memory with processing in memory architecture and operating method thereof - Google Patents

Abstract

A memory with processing in memory architecture and an operating method thereof are provided. The memory includes a memory array, a mode register, an artificial intelligence core, and a memory interface. The memory array includes a plurality of memory regions. The mode register stores a plurality of memory mode settings. The memory interface is coupled to the memory array and the mode register, and is externally coupled to a special function processing core. The artificial intelligence core is coupled to the memory array and the mode register. The plurality of memory regions are selectively addressed to the special function processing core and the artificial intelligence core according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core respectively access different memory regions in the memory array according to the plurality of memory mode settings.

Description

Memory body with operation structure in memory and operation method thereof

The present invention relates to a circuit architecture, and particularly to a memory having a processing in memory (PIM) architecture and an operation method thereof.

With the evolution of Artificial Intelligence (AI) computing, the application of artificial intelligence computing is becoming more and more widely used, such as image data analysis, voice data analysis, and neural data analysis via Neural network models. Neural network operations such as Natural language processing. Moreover, as the computational complexity of neural networks is getting higher and higher, the current computer equipment used to perform artificial intelligence computing has gradually been unable to cope with the current neural network computing needs to provide effective and fast computing performance.

Therefore, currently dedicated processing cores have been designed to utilize dedicated processing cores for neural network operations. However, although the neural network operation is independently executed by the dedicated processing core to fully utilize the computing power of the processing core, the processing speed of the dedicated processing core is still limited by the data access speed. Because the dedicated processing core and other special function processing cores read the data of the memory through the same general bus (Bus), when the other special function processing core occupies the general bus, the dedicated processing core cannot be real-time To obtain the data needed to perform artificial intelligence operations. In view of this, how to design a processing architecture that can quickly perform artificial intelligence operations, the solutions of several embodiments will be proposed below.

The invention provides a memory with an in-memory computing architecture and an operation method thereof, which can directly read the execution neural network stored in the memory chip by an artificial intelligence (Artificial Intelligence, AI) core integrated in the memory (Neural network) The data required for the operation to achieve the effect of fast neural network operation.

The memory with an in-memory computing architecture of the present invention includes a memory array, a mode register, a memory interface, and an artificial intelligence core. The memory array includes a plurality of memory areas. The mode register is used to store multiple memory mode settings. The memory interface is coupled to the memory array and the mode register, and is externally coupled to the special function processing core. The artificial intelligence core is coupled to the memory array and the mode register. The plurality of memory areas are selectively addressed to the special function processing core and the artificial intelligence core respectively according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core are based on The multiple memory mode settings are used to respectively access different memory areas in the memory array.

In an embodiment of the present invention, the above-mentioned special function processing core and artificial intelligence core respectively access different memory areas of the memory array through their own dedicated memory buses.

In an embodiment of the invention, the above-mentioned plurality of memory regions include a first memory region and a second memory region. The first memory area is used for exclusive access by the artificial intelligence core. The second memory area is used for exclusive access of the special function processing core.

In an embodiment of the invention, the aforementioned plurality of memory areas further include a plurality of data buffer areas. The artificial intelligence engine and the memory interface alternately access the multiple data buffer areas to access different data.

In an embodiment of the present invention, when the artificial intelligence core performs a neural network operation, the artificial intelligence core reads input data of one of the plurality of data buffer areas as input parameters, and reads the first A weight data of the memory area. The artificial intelligence core outputs characteristic data to the first memory area.

In an embodiment of the present invention, when the artificial intelligence core performs a neural network operation, the artificial intelligence core reads the characteristic data of the first memory area as the next input parameter, and reads the first memory area. Another weight information. The artificial intelligence core outputs the next feature map data to one of the multiple data buffers to overwrite one of the multiple data buffers.

In an embodiment of the present invention, the plurality of data buffer regions described above may be alternately addressed to the special function processing core and the artificial intelligence core, so that the first memory space corresponding to the artificial intelligence core includes the first One of the memory area and the plurality of data buffer areas, and the second memory space corresponding to the special function processing core includes the second memory area and the other one of the plurality of data buffer areas.

In an embodiment of the present invention, the width of the bus dedicated between the artificial intelligence core and the plurality of memory regions is larger than the width of the external bus between the special function processing core and the memory interface.

In an embodiment of the present invention, the aforementioned plurality of memory regions respectively correspond to a plurality of column buffer blocks, and the plurality of memory regions each include a plurality of memory banks. The width of a bus dedicated to the artificial intelligence core and the plurality of memory regions is greater than or equal to the number of data in a whole row of the plurality of memory banks.

In an embodiment of the invention, the above-mentioned memory is a dynamic random access memory chip.

The memory operation method with an in-memory computing architecture of the present invention is suitable for a memory including a memory array, a mode register, a memory interface, and an artificial intelligence core. The method includes the following steps: selectively addressing a plurality of memory regions in the memory to the special function processing core and the artificial intelligence core according to the plurality of memory mode settings of the mode register; and The special function processing core and the artificial intelligence core respectively access different memory areas in the memory array according to the plurality of memory mode settings.

In an embodiment of the present invention, the above-mentioned special function processing core and artificial intelligence core respectively access different memory areas of the memory array through their own dedicated memory buses.

In an embodiment of the present invention, the plurality of memory areas include a first memory area and a second memory area, the first memory area is used for exclusive access by the artificial intelligence core, and the second memory The body area is used for exclusive access to the special function processing core.

In an embodiment of the present invention, the aforementioned plurality of memory regions further include a plurality of data buffer regions, and the artificial intelligence engine and the memory interface alternately access the plurality of data buffer regions to access different data.

In an embodiment of the present invention, when the artificial intelligence core performs a neural network operation, the special function processing core and the artificial intelligence core are stored separately according to the plurality of memory mode settings of the mode register The steps of fetching different memory areas in the memory array include: reading the input data of one of the plurality of data buffer areas as input parameters by the artificial intelligence core; and reading the first memory by the artificial intelligence core Weight data of the body area; and output characteristic data to the first memory area through the artificial intelligence core.

In an embodiment of the present invention, when the artificial intelligence core performs a neural network operation, the special function processing core and the artificial intelligence core are stored separately according to the plurality of memory mode settings of the mode register The step of fetching different memory areas in the memory array further includes: reading the characteristic data of the first memory area by the artificial intelligence core as the next input parameter; reading the other memory area of the first memory area by the artificial intelligence core A weight data; and output the next feature map data to one of the multiple data buffers by the artificial intelligence core, to overwrite one of the multiple data buffers.

In an embodiment of the present invention, the plurality of data buffer regions described above may be alternately addressed to the special function processing core and the artificial intelligence core, so that the first memory space corresponding to the artificial intelligence core includes the first One of the memory area and the plurality of data buffer areas, and the second memory space corresponding to the special function processing core includes the second memory area and the other one of the plurality of data buffer areas.

In an embodiment of the present invention, the width of the bus dedicated to the artificial intelligence core and the plurality of memory regions is larger than the width of the external bus between the special function processing core and the memory interface.

In an embodiment of the present invention, the aforementioned plurality of memory regions respectively correspond to a plurality of column buffer blocks, and the plurality of memory regions each include a plurality of memory banks. The width of the bus dedicated to the artificial intelligence core and the plurality of memory regions is greater than or equal to the number of data in the entire row of the plurality of memory banks.

In an embodiment of the invention, the above-mentioned memory is a dynamic random access memory chip.

Based on the above, the memory and operation method of the present invention can enable external special function processing cores and artificial intelligence cores disposed in the memory to simultaneously access different memory areas in the memory array. Therefore, the memory of the present invention can quickly perform neural network operations.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

In order to make the content of the present invention easier to understand, the following specific embodiments are taken as examples on which the present invention can indeed be implemented. In addition, wherever possible, elements/components/steps with the same reference numerals in the drawings and embodiments represent the same or similar components.

FIG. 1 is a block diagram illustrating a memory according to an embodiment of the invention. Referring to FIG. 1, the memory 100 includes a memory array 110, a mode register 120, an artificial intelligence (AI) core 130, and a memory interface 140. The memory array 110 is coupled to the artificial intelligence core 130 and the memory interface 140. The mode register 120 is coupled to the memory array 110, the artificial intelligence core 130, and the memory interface 140. The memory array 110 includes a plurality of memory areas. The plurality of memory areas are used to store specific data (or data set). Moreover, in an embodiment, the memory 100 may further include a plurality of dedicated memory control units. The plurality of dedicated memory control units correspond to the plurality of memory regions one-to-one to perform data access operations respectively. In this embodiment, the memory interface 140 can be externally coupled to the special function processing core. In addition, the plurality of memory areas are selectively addressed to the special function processing core and the artificial intelligence core 130 according to the settings of the plurality of memory modes recorded in the mode register 120 to make the special The function processing core and the artificial intelligence core 130 can respectively access different memory areas in the memory array 110 according to the plurality of memory mode settings. Moreover, the memory 100 of this embodiment has the ability to perform artificial intelligence operations.

In this embodiment, the memory 100 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM) chip, and may be, for example, a circuit element such as control logic, arithmetic logic, and cache unit. Constructed in-memory (Processing In Memory, PIM) architecture. The artificial intelligence core 130 can be integrated in the peripheral circuit area of the memory 100 to directly access multiple memory banks of the memory array 110 through a dedicated memory controller and a dedicated bus (Bus) . In addition, the artificial intelligence core 130 may be designed in advance to have a function and characteristic of performing a specific neural network (Neural network) operation. In other words, the memory 100 of this embodiment has the function of performing artificial intelligence operations, and the artificial intelligence core 130 and the external special function processing core can access the memory array 110 at the same time to provide efficient data access and calculation effects.

In this embodiment, the special function processing core may be, for example, a central processing unit (Central Processing Unit, CPU) core, an image signal processor (Image Signal Processor, ISP) core, and a digital signal processor (Digital Signal Processor, DSP) ) Core, Graphics Processing Unit (GPU) core or other similar special function processing core. In this embodiment, the special function processing core is coupled to the memory interface 140 via a general-purpose bus (or standard bus) to access the memory array 110 via the memory interface 140. In this regard, the artificial intelligence core 130 accesses the memory array 110 through a dedicated bus inside the memory, so it is not limited to the width or speed of the memory interface 140, and the artificial intelligence core 130 can access based on specific data Mode to quickly access the memory array 130.

FIG. 2 is a schematic diagram illustrating the architecture of a memory and multiple special function processing cores according to an embodiment of the invention. Referring to FIG. 2, the memory 200 includes memory areas 211 and 213, column buffer blocks 212 and 214, a pattern register 220, an artificial intelligence core 230, and a memory interface 240. In this embodiment, the mode register 220 is coupled to the artificial intelligence core 230 and the memory interface 240 to provide multiple memory mode settings to the artificial intelligence core 230 and the memory interface 240, respectively. The artificial intelligence core 230 and the memory interface 240 operate independently to respectively access the memory array. The memory array includes memory areas 211 and 213 and column buffer blocks 212 and 214. The memory areas 211 and 213 each include a plurality of memory banks. The memory areas 211 and 213 can be data buffer areas. In this embodiment, the memory interface 240 is externally coupled to another memory interface 340. The memory interface 340 is coupled to the central processing unit core 351, the graphics processor core 352, and the digital signal processor core 353, for example, via a bus.

In this embodiment, when the central processing unit core 351, the graphics processor core 352, and the digital signal processor core 353 need to access the column buffer block 212 or the column buffer block 214, the central processing unit core 351, the graphics processor The core 352 and the digital signal processor core 353 need to access the column buffer block 212 or the column buffer block 214 through the memory interfaces 240 and 340 in sequence or in queue. However, the artificial intelligence core 230 can access different memory areas in the memory array at the same time regardless of the above-mentioned various special function processing cores currently accessing the memory array. In one embodiment, the memory area 211 or the memory area 213 may be suitable for accessing digital input data, weight data, or feature maps required to perform neural network operations or other machine learning operations, for example. ) Information etc.

It is worth noting that the above-mentioned various special function processing cores and artificial intelligence core 230 respectively access different memory areas of the memory array through their own dedicated memory buses. That is to say, when the above-mentioned various special function processing cores access the data in the memory area 211 through the column buffer block 212, the artificial intelligence core 230 can access the data in the memory area 213 through the column buffer block 214. Moreover, when the above-mentioned various special function processing cores access the data in the memory area 213 via the column buffer block 214, the artificial intelligence core 230 can access the data in the memory area 211 via the column buffer block 212. In other words, the aforementioned various special function processing cores and artificial intelligence core 230 can alternately access different data to the memory areas 211 and 213 as data buffer areas. In addition, in an embodiment, the artificial intelligence core 230 may further include a plurality of caches or queues, and the artificial intelligence core 230 may pass the plurality of caches or the plurality of queues Use the pipeline method to quickly access the data in the memory area 211 or the memory area 213.

FIG. 3 is a schematic diagram illustrating the architecture of a memory and multiple special function processing cores according to another embodiment of the invention. Referring to FIG. 3, the processor 400 of this embodiment includes memory regions 411, 413, 415, 417, column buffer blocks 412, 414, 416, 418, mode register 420, artificial intelligence core 430, and memory interface 440 . In this embodiment, the mode register 420 is coupled to the artificial intelligence core 430 and the memory interface 440 to provide multiple memory mode settings to the artificial intelligence core 430 and the memory interface 440, respectively. The memory interface 440 is coupled to the central processing unit core 351, the graphics processor core 352, and the digital signal processor core 353, for example, via a bus. In this embodiment, the artificial intelligence core 430 and the memory interface 440 operate independently to respectively access the memory array. The memory array includes memory areas 411, 413, 415, 417 and column buffer blocks 412, 414, 416, 418, and the memory areas 411, 413, 415, 417 each include multiple memory banks.

In this embodiment, the memory areas 413 and 415 can be data buffer areas. The memory area 411 provides exclusive access to the above-mentioned various special function processing cores, wherein the various special function processing cores may be, for example, a central processing unit core 351, a graphics processor core 352, and a digital signal processor core 353. The memory area 417 is exclusively accessed by the artificial intelligence core 430. That is to say, when the above-mentioned various special function processing cores and the artificial intelligence core 430 exclusively access the memory area 411 and the memory area 417 respectively, the above-mentioned various special function processing cores and the artificial intelligence core 430 will not affect each other Access action. For example, taking the execution of a neural network operation as an example, a whole row of multiple memory banks in the memory area 417 may store multiple weight values of weight data, for example. The artificial intelligence core 430 can sequentially and interleavedly read each row of the plurality of memory banks dedicated to the memory area 417 of the artificial intelligence core 430 through the row buffer block 418 to quickly obtain an execution neural network The information required for the calculation.

4A and 4B are schematic diagrams illustrating the exchange addressing of different memory blocks in different memory spaces according to an embodiment of the invention. Please refer to FIG. 3, FIG. 4A and FIG. 4B. In the following, an access method of the memory 400 will be described by taking the continuous execution of neural network operations on a plurality of image data as an example and with reference to FIGS. 4A and 4B. The artificial intelligence operations performed by the artificial intelligence core 430 may be, for example, deep learning network (Deep Neural Networks, DNN) operations, convolutional neural network (Convolutional Neural Networks, CNN) operations, or recurrent neural network (RNN) ) Calculation, etc., the present invention is not limited. In an implementation scenario, the memory area 417 includes sub-memory areas 417_1, 417_2. The sub-memory area 417_1 is used to store weight data having multiple weight values, for example, and the sub-memory area 417_2 is used to store feature map data having multiple feature values, for example. In this implementation scenario, the memory area 413 is, for example, addressed to the special function processing core 354, and the memory area 415 is, for example, addressed to the artificial intelligence core 430. The special function processing core 354 may be, for example, the central processing unit core 351, the graphics processor core 352, or the digital signal processor core 353 of FIG. Therefore, as shown in FIG. 4A, the memory space 450 corresponding to the special function processing core 354 includes memory areas 411 and 413, and the memory space 460 corresponding to the artificial intelligence core 430 includes memory areas 415 and 417.

In this implementation scenario, it is assumed that the special function processing core 354 is the digital signal processor core 353 of FIG. 3, so the memory area 415 may store digital input data previously stored by the digital signal processor core 353, such as image data. The artificial intelligence core 430 may, for example, perform a neural network operation to perform image recognition on the current image data stored in the memory area 415. The artificial intelligence core 430 can read the weight data of the memory area 417 through a dedicated bus, and read the image data of the memory area 415 as input parameters required for neural network operation to perform neural network operation. At the same time, the digital signal processor core 353 can store the next image data in the memory area 413 via the memory interfaces 340 and 440.

Then, after the image data of the memory area 415 is recognized by the artificial intelligence core 430, the addressed objects of the memory areas 413 and 415 can be exchanged through the setting mode register 420 to exchange the memory areas 413 and 415 Memory space. Therefore, after the memory areas 413 and 415 are exchanged by addressing, as shown in FIG. 4B, the memory space 450 ′ corresponding to the digital signal processor core 353 includes the memory areas 411 and 415 and corresponds to the memory of the artificial intelligence core 430 The body space 460' includes memory areas 413, 417. At this time, the artificial intelligence core 430 may continue to perform neural network operations to perform image recognition on the new image data stored in the memory area 413. The artificial intelligence core 430 can read the weight data of the memory area 417-1 through a dedicated bus, and read the next image data of the memory area 413 as input parameters required for neural network operation to perform a neural network Operation. At the same time, the digital signal processor core 353 can overwrite the memory area 415 via the memory interfaces 340, 440 to store the next image data to the memory area 415. According to this, the memory 400 of this embodiment can provide a highly efficient data access operation, and the memory 400 can realize a neural network operation with a high-speed execution effect.

5A and 5B are schematic diagrams illustrating the swap access of different memory blocks in the same memory space according to an embodiment of the invention. Please refer to FIG. 3, FIG. 5A and FIG. 5B. In the following, another method of accessing the memory 400 will be described by taking the neural network operation on the image data as an example and using FIGS. 4A and 4B. In the above scenario, at the input layer stage of the neural network operation, the memory space 550 corresponding to the artificial intelligence core 430 may include, for example, a memory area 415 and sub-memory areas 417_1, 417_2. The artificial intelligence core 430 can read the memory area 415 to obtain input data and use it as an input parameter. The memory area 415 stores image data previously stored by the digital signal processor core 353. And, the artificial intelligence core 430 reads the weight data of the sub-memory area 417_1. Therefore, the artificial intelligence core 430 performs a neural network operation according to the input parameters and the weight data to generate feature map data, and the artificial intelligence core 430 stores the feature map data to the sub-memory area 417_2.

Next, in the next hidden layer stage of the neural network operation, the memory space 550' corresponding to the artificial intelligence core 430 includes the memory area 415 and the sub-memory areas 417_1, 417_2. The artificial intelligence core 430 reads the feature map data previously stored in the sub-memory area 417_2 as an input parameter of the current hidden layer, and reads the weight data of the sub-memory area 417_1. Therefore, the artificial intelligence core 430 performs a neural network operation according to the input parameters and the weight data to generate new feature map data, and the artificial intelligence core 430 replicates the new feature map data to the memory area 415. In other words, the memory area addressed to the artificial intelligence core 430 remains unchanged, but the artificial intelligence core 430 reads and stores the target address exchange. By analogy, the artificial intelligence core 430 of this embodiment can use the memory area 415 and the sub-memory area 417_2 to alternately read the previously generated feature map data and store the artificial intelligence core 430 currently performing neural network operations. The current feature map data generated during the process. Since each memory area has its own independent bus, the artificial intelligence core 430 of this embodiment can quickly obtain input data and weight data, and quickly perform neural network operations and store output data.

FIG. 6 is a flowchart illustrating a memory operation method according to an embodiment of the invention. Referring to FIG. 6, the memory operation method of this embodiment may be at least applicable to the memory 100 of FIG. 1, so that the memory 100 executes steps S610 and S620. The memory interface 140 of the memory 100 can be externally coupled to the special function processing core. In step S610, multiple memory regions of the memory array 110 are selectively addressed to the memory spaces of the special function processing core and the artificial intelligence core 130 according to the multiple memory mode settings of the mode register 120, respectively . In step S620, the special function processing core and the artificial intelligence core 130 respectively access different memory areas in the memory array 110 according to the plurality of memory mode settings. Therefore, the memory operation method of this embodiment enables the memory 100 to be simultaneously accessed by the special function processing core and the artificial intelligence core 130 to provide a highly efficient memory operation effect.

In addition, regarding the internal components, implementations, and technical details of the memory 100 of this embodiment, reference may be made to the description of the above-described embodiments of FIGS. 1 to 5B to obtain sufficient teaching, suggestions, and implementation descriptions, and thus no further description is required.

In summary, the memory of the present invention and its operation method can be designed with a plurality of specific memory mode settings through a mode register, so that the multiple memory areas of the memory array can be based on the multiple specific The memory mode is set to be selectively addressed to the external special function processing core and the artificial intelligence core, respectively, so that the external special function processing core and the artificial intelligence core can simultaneously access different memory areas in the memory array. Therefore, the artificial intelligence core set in the memory can quickly execute the neural network operation.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100, 200, 400: memory 110: memory array 120, 220, 420: pattern register 130, 230, 430: artificial intelligence core 140, 240, 440: memory interface 211, 213, 411, 413, 415, 417: memory area 212, 214, 412, 414, 416, 418: column buffer block 340: Memory interface 351: Central processing unit core 352: graphics processor core 353: Digital signal processor core 354: Special function processing core 417_1, 417_2: Sub memory area 450, 450’, 460, 460’, 550, 550’: memory space S610, S620: steps

FIG. 1 is a block diagram illustrating a memory according to an embodiment of the invention. FIG. 2 is a schematic diagram illustrating the architecture of a memory and multiple special function processing cores according to an embodiment of the invention. FIG. 3 is a schematic diagram illustrating the architecture of a memory and multiple special function processing cores according to another embodiment of the invention. 4A and 4B are schematic diagrams illustrating the exchange addressing of different memory blocks in different memory spaces according to an embodiment of the invention. 5A and 5B are schematic diagrams illustrating the swap access of different memory blocks in the same memory space according to an embodiment of the invention. FIG. 6 is a flowchart illustrating a memory operation method according to an embodiment of the invention.

100: memory

110: memory array

120: Mode register

130: Artificial Intelligence Core

140: memory interface

Claims (20)

A memory with an in-memory computing architecture includes: A memory array, including multiple memory areas; A mode register for storing multiple memory mode settings; A memory interface, coupled to the memory array and the mode register, and externally coupled to a special function processing core; and An artificial intelligence core, coupled to the memory array and the mode register, The memory areas are selectively addressed to the special function processing core and the artificial intelligence core respectively according to the memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core According to the memory mode settings, different memory areas in the memory array are respectively accessed. The memory according to item 1 of the patent application scope, wherein the special function processing core and the artificial intelligence core respectively access different memory areas of the memory array through their own dedicated memory buses. The memory according to item 1 of the patent application scope, wherein the memory areas include a first memory area and a second memory area, the first memory area is used for exclusive access by the artificial intelligence core And the second memory area is used for exclusive access by the special function processing core. The memory according to item 3 of the patent application scope, wherein the memory areas further include a plurality of data buffer areas, and the artificial intelligence engine and the memory interface alternately access the data buffer areas to access different data. The memory as described in item 4 of the patent application scope, wherein when the artificial intelligence core performs a neural network operation, the artificial intelligence core reads an input data of one of the data buffer areas as an input parameter And read a weight data of the first memory area, wherein the artificial intelligence core outputs a characteristic data to the first memory area. The memory according to item 5 of the patent application scope, wherein when the artificial intelligence core performs the neural network operation, the artificial intelligence core reads the characteristic data of the first memory area as the next input parameter, and Reading another weight data of the first memory area, wherein the artificial intelligence core outputs the next feature map data to one of the data buffers to overwrite one of the data buffers. The memory as recited in item 4 of the patent application range, wherein the data buffer areas can be alternately addressed to the special function processing core and the artificial intelligence core, respectively, so that a first memory corresponding to the artificial intelligence core The body space includes one of the first memory area and the data buffer areas, and a second memory space corresponding to the special function processing core includes the second memory area and the data buffer areas The other. The memory according to item 1 of the patent application scope, wherein the width of a bus bar dedicated to the artificial intelligence core and the memory areas is larger than an exterior between the special function processing core and the memory interface The width of the bus bar. The memory according to item 1 of the patent application scope, wherein the memory areas respectively correspond to a plurality of column buffer blocks, and the memory areas each include a plurality of memory banks, of which the artificial intelligence is exclusive The width of a bus between the core and the memory regions is greater than or equal to the number of data in a whole row of the memory banks. The memory according to item 1 of the patent application scope, wherein the memory is a dynamic random access memory chip. A memory operation method with an in-memory computing architecture. The memory includes a memory array, a mode register, a memory interface, and an artificial intelligence core. The method includes: Selectively addressing the plurality of memory regions in the memory to the special function processing core and the artificial intelligence core according to the memory mode settings of the mode register; and The special function processing core and the artificial intelligence core respectively access different memory areas in the memory array according to the memory mode settings. The memory operation method as described in item 11 of the patent application range, wherein the special function processing core and the artificial intelligence core respectively access different memory areas of the memory array through their own dedicated memory buses. The memory operation method as described in item 11 of the patent application range, wherein the memory areas include a first memory area and a second memory area, the first memory area is used exclusively for the artificial intelligence core Access, and the second memory area is used for exclusive access by the special function processing core. The memory operation method as described in item 13 of the patent application scope, wherein the memory areas further include a plurality of data buffer areas, and the artificial intelligence engine and the memory interface alternately access the data buffer areas differently data. According to the memory operation method described in item 14 of the patent application scope, when the artificial intelligence core performs a neural network operation, wherein the processing core by the special function and the artificial intelligence core are based on the patterns of the pattern registers The steps of setting the memory mode to access different memory areas in the memory array include: Reading an input data of one of the data buffer areas by the artificial intelligence core as an input parameter; Reading weighting data of the first memory area by the artificial intelligence core; and The artificial intelligence core outputs a characteristic data to the first memory area. According to the memory operation method described in item 15 of the patent application scope, when the artificial intelligence core executes the neural network operation, wherein the special function processing core and the artificial intelligence core are based on the patterns of the pattern registers The step of setting the memory mode to separately access different memory areas in the memory array further includes: Reading the characteristic data of the first memory area as the next input parameter by the artificial intelligence core; Reading another weight data of the first memory area by the artificial intelligence core; and The artificial intelligence core outputs the next feature map data to one of the data buffers to overwrite one of the data buffers. The memory operation method as described in item 14 of the patent application range, wherein the data buffer areas can be alternately addressed to the special function processing core and the artificial intelligence core, so that a first corresponding to the artificial intelligence core A memory space includes one of the first memory area and the data buffer areas, and a second memory space corresponding to the special function processing core includes the second memory area and the data buffer areas One of them. The memory operation method as described in item 11 of the patent application scope, wherein the width of a bus dedicated to the artificial intelligence core and the memory areas is larger than that between the special function processing core and the memory interface The width of an external bus bar. The memory operation method as described in item 11 of the patent application scope, wherein the memory areas respectively correspond to a plurality of column buffer blocks, and the memory areas each include a plurality of memory banks, of which dedicated to the The width of a bus between the artificial intelligence core and the memory areas is greater than or equal to the number of data in a whole row of the memory banks. The memory operation method as described in item 11 of the patent application range, wherein the memory is a dynamic random access memory chip.

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