TW202011587A - Semiconductor device - Google Patents

Abstract

A semiconductor device according to an embodiment includes an N-well region, a first gate electrode, a single-crystal first semiconductor, and a first contact. The N-well region includes two P-type impurity diffusion regions. The first gate electrode is provided above the N-well region between the two P-type impurity diffusion regions. The first gate electrode is opposed to the N-well region via a gate insulating film. The single-crystal first semiconductor is provided in a columnar shape on the P-type impurity diffusion region. The first contact includes a polycrystalline second semiconductor. The second semiconductor is provided on the first semiconductor and includes P-type impurities.

Description

Semiconductor device and its manufacturing method

The embodiment relates to a semiconductor device and a manufacturing method thereof.

There is known a NAND (Not AND) type flash memory that can nonvolatilely store data.

The embodiment provides a semiconductor device capable of suppressing changes in characteristics of transistors and a method of manufacturing the same.

The semiconductor device of the embodiment includes an N-type well region, a first gate electrode, a first semiconductor, and a first contact. The N-type well region includes two P-type impurity diffusion regions. The first gate electrode is provided above the N-well region between the two P-type impurity diffusion regions via the gate insulating film. The first semiconductor is a single crystal semiconductor provided in a columnar shape on the P-type impurity diffusion region. The first contact includes a polycrystalline second semiconductor provided on the first semiconductor and containing P-type impurities.

Hereinafter, embodiments will be described with reference to the drawings. Each embodiment exemplifies a device or method for embodying the technical idea of the invention. If the drawings are schematic or conceptual, the sizes and proportions of the drawings may not be the same as the actual ones. The technical idea of the present invention is not specified by the shape, structure, and arrangement of constituent elements.

In addition, in the following description, constituent elements having substantially the same functions and configurations are denoted by the same symbols. The numbers after the characters constituting the reference symbol are referred to by reference symbols containing the same characters, and are used to distinguish elements having the same composition from each other. When there is no need to distinguish between elements shown by reference symbols containing the same text, these elements are referred to by reference symbols containing only text.

[1] The first embodiment FIG. 1 shows a configuration example of the semiconductor device 1 of the first embodiment. Hereinafter, the semiconductor device 1 of the first embodiment will be described.

[1-1] Structure of the semiconductor device 1 [1-1-1] Overall configuration of semiconductor device 1 The semiconductor device 1 is, for example, a NAND flash memory that can store data non-volatilely. The semiconductor device 1 is controlled by, for example, an external memory controller 2.

As shown in FIG. 1, the semiconductor device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a column decoder module 15, and a sense amplifier Module 16.

The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). The block BLK is a collection of a plurality of memory cells that can non-volatilely store data, for example, as a data erasing unit.

In addition, the memory cell array 10 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed structure of the memory cell array 10 is described below.

The command register 11 holds the command CMD received by the semiconductor device 1 from the memory controller 2. The command CMD includes, for example, a command to cause the sequencer 13 to perform a read operation, a write operation, an erase operation, and the like.

The address register 12 holds the address information ADD received by the semiconductor device 1 from the memory controller 2. The address information ADD includes, for example, a block address BA, a page address PA, and a row address CA. For example, the block address BA, page address PA, and row address CA are used to select the block BLK, word line, and bit line, respectively.

The sequencer 13 controls the operation of the entire semiconductor device 1. For example, the sequencer 13 controls the driver module 14, the column decoder module 15, the sense amplifier module 16, etc. based on the command CMD held in the command register 11, and performs a read operation, a write operation, and an erase operation Action etc.

The driver module 14 generates voltages used in read operations, write operations, erase operations, and the like. And, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line based on, for example, the page address PA held in the address register 12.

The column decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 12. And, the column decoder module 15 transmits, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

During the write operation, the sense amplifier module 16 applies the desired voltage to each bit line according to the write data DAT received from the memory controller 2. In addition, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line during the read operation, and transmits the determination result to the memory controller 2 as the read data DAT.

The communication between the semiconductor device 1 and the memory controller 2 supports, for example, the NAND interface specification. For example, in the communication between the semiconductor device 1 and the memory controller 2, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, and the ready busy signal RBn are used And input and output signal I/O.

The command latch enable signal CLE indicates that the input/output signal I/O received by the semiconductor device 1 is the signal of the command CMD. The address latch enable signal ALE indicates that the signal I/O received by the semiconductor device 1 is a signal of address information ADD. The write enable signal WEn is a signal that commands the input/output signal I/O of the semiconductor device 1. The read enable signal REn is a signal that commands the output of the input/output signal I/O to the semiconductor device 1.

The ready busy signal RBn notifies the memory controller 2 that the semiconductor device 1 is in a ready state to accept a command from the memory controller 2 or a busy state in which a command is not accepted. The input/output signal I/O is, for example, a signal of 8-bit width, and may include command CMD, address information ADD, data DAT, etc.

The semiconductor device 1 and the memory controller 2 described above may constitute one semiconductor device by a combination thereof. Examples of such semiconductor devices include memory cards such as SD ^TM cards and SSDs (solid state drives).

[1-1-2] Circuit configuration of memory cell array 10 FIG. 2 is an example of the circuit configuration of the memory cell array 10 included in the semiconductor device 1 of the first embodiment, and one block BLK of the plurality of blocks BLK included in the memory cell array 10 is extracted and displayed.

As shown in FIG. 2, the block BLK includes, for example, four string units SU0 to SU3. Each string unit SU includes a plurality of NAND strings NS.

The plurality of NAND strings NS are respectively associated with the bit lines BL0 to BLm (m is an integer of 1 or more). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2.

The memory cell transistor MT includes a control gate and a charge accumulation layer, and holds data non-volatilely. Each of the selection transistors ST1 and ST2 is used for selection of the string unit SU in various operations.

In each NAND string NS, the drain of the selection transistor ST1 is connected to the associated bit line BL. The source of the selection transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The other ends of the serially connected memory cell transistors MT0 to MT7 are connected to the drain of the selection transistor ST2.

In the same block BLK, the source of the selection transistor ST2 is commonly connected to the source line SL. The gates of the selection transistors ST1 in the string units SU0 to SU3 are respectively connected to the selection gate lines SGD0 to SGD3 in common. The control gates of the memory cell transistors MT0 to MT7 are respectively connected to the word lines WL0 to WL7 in common. The gate of the selection transistor ST2 is commonly connected to the selection gate line SGS.

In the circuit configuration of the memory cell array 10 described above, a plurality of NAND strings NS allocated with the same row address CA are commonly connected to the same bit line BL among the plurality of blocks BLK. The source line SL is commonly connected between the plurality of blocks BLK.

The set of a plurality of memory cell transistors MT connected to a common word line WL in one string unit SU is called a cell unit CU, for example. For example, the memory capacity of the cell unit CU of the memory cell transistor MT that includes each memory storing 1-bit data is defined as "1 page data". The cell unit CU may have a memory capacity of more than 2 pages of data according to the number of bits of data memorized by the memory cell transistor MT.

In addition, the circuit configuration of the memory cell array 10 included in the semiconductor device 1 of the embodiment is not limited to the configuration described above. For example, the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number. The number of string units SU included in each block BLK can be designed to be any number.

[1-1-3] Structure of memory cell array 10 Hereinafter, an example of the structure of the memory cell array 10 of the first embodiment will be described.

In the drawings referred to below, the X direction corresponds to the extending direction of the word line WL. The Y direction corresponds to the extending direction of the bit line BL. The Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate 20 forming the semiconductor device 1.

In the cross-sectional views referred to below, in order to facilitate the observation of the drawings, components such as an insulating layer (interlayer insulating film), wiring, and contacts are appropriately omitted. In addition, in order to facilitate the observation of the drawing, hatching is appropriately added in the plan view. The hatching attached to the top view may not necessarily be related to the material or characteristics of the constituent elements with hatching.

FIG. 3 is an example of the planar layout of the memory cell array 10 provided in the semiconductor device 1 of the embodiment, and a structure corresponding to each of the string units SU0 and SU1 is extracted and displayed.

As shown in FIG. 3, the area where the memory cell array 10 is formed includes, for example, a plurality of slits SLT, a plurality of string units SU, and a plurality of bit lines BL.

Plural slits SLT extend in the X direction and are arranged in the Y direction. Between the slits SLT adjacent in the Y direction, for example, one string unit SU is arranged.

Each string unit SU includes a plurality of memory columns MP. The plurality of memory columns MP are arranged in a zigzag shape along the X direction, for example. Each of the memory pillars MP functions as one NAND string NS, for example.

The plural bit lines BL extend in the Y direction and are arranged in the X direction. For example, each bit line BL is arranged so that each string unit SU overlaps with at least one memory column MP. Specifically, for example, two bit lines BL overlap each memory column MP.

A contact CP is provided between one of the plurality of bit lines BL overlapping the memory column MP and the memory column MP. Each memory column MP is electrically connected to the corresponding bit line BL via a contact CP.

In addition, the number of string units SU disposed between adjacent slits SLT can be designed to be any number. The number and configuration of the memory columns MP shown in FIG. 3 are just an example, and the memory column MP can be designed to have any number and configuration. The number of bit lines BL overlapping each memory column MP can be designed to be any number.

FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 3 and shows an example of the cross-sectional structure of the memory cell array 10 included in the semiconductor device 1 of the embodiment.

As shown in FIG. 4, the area where the memory cell array 10 is formed includes, for example, the electrical conductors 21-25, the memory pillar MP, the contact CP, and the slit SLT.

Specifically, an insulating layer UA is provided on the semiconductor substrate 20. On the insulating layer UA, a circuit such as a sense amplifier module 16 is provided. The circuit includes, for example, NMOS transistor TrN and PMOS transistor TrP. The details of the structure associated with the NMOS transistor TrN and the PMOS transistor TrP are described below.

On the insulating layer UA, a conductor 21 is provided. For example, the conductor 21 is formed in a plate shape extending along the XY plane and used as the source line SL. The conductor 21 includes, for example, silicon (Si).

Above the conductive body 21, a conductive body 22 is provided via an insulating layer. For example, the conductor 22 is formed in a plate shape extending along the XY plane, and is used as the selection gate line SGS. The conductor 22 includes, for example, silicon (Si).

Above the conductor 22, an insulating layer and a conductor 23 are alternately laminated. For example, the conductor 23 is formed in a plate shape extending along the XY plane. The plurality of laminated electrical conductors 23 are sequentially used as word lines WL0 to WL7 from the semiconductor substrate 20 side. The conductor 23 contains, for example, tungsten (W).

Above the uppermost conductive body 23, a conductive body 24 is provided via the insulating layer. The conductor 24 is formed in a plate shape extending along the XY plane, for example, and is used as a selection gate line SGD. The electrical conductor 24 contains, for example, tungsten (W).

Above the conductive body 24, a conductive body 25 is provided via an insulating layer. For example, the conductor 25 is formed in a linear shape extending in the Y direction, and is used as the bit line BL. That is, in a region not shown, a plurality of conductors 25 are arranged in the X direction. The conductor 25 contains, for example, copper (Cu).

The memory pillar MP is formed in a columnar shape extending in the Z direction, for example, passing through the conductors 22-24. Specifically, the upper end of the memory pillar MP is included in, for example, a layer between the layer provided with the conductor 24 and the layer provided with the conductor 25. The lower end of the memory pillar MP is included in, for example, a layer provided with a conductor 21.

In addition, the memory pillar MP includes, for example, a core member 30, a semiconductor 31, and a laminated film 32.

The core member 30 is formed in a columnar shape extending in the Z direction. The upper end of the core member 30 is included in, for example, an upper layer than the layer provided with the conductor 24. The lower end of the core member 30 is included in, for example, a layer provided with a conductor 21. The core member 30 includes an insulator such as silicon oxide (SiO ₂ ).

The core member 30 is covered by the semiconductor 31. The semiconductor 31 is in contact with the conductor 21 via the side of the memory pillar MP, for example. The semiconductor 31 is, for example, polycrystalline silicon (Si). The laminated film 32 covers the side and bottom surfaces of the semiconductor 31 except for the portion where the conductor 21 contacts the semiconductor 31.

FIG. 5 shows an example of the cross-sectional structure of the memory pillar MP parallel to the surface of the semiconductor substrate 20 and including the cross-section of the conductor 23.

As shown in FIG. 5, in the layer including the electric conductor 23, the core member 30 is disposed at the central portion of the memory pillar MP. The semiconductor 31 surrounds the side surface of the core member 30. The build-up film 32 surrounds the side surface of the semiconductor 31. The build-up film 32 includes, for example, a tunnel oxide film 33, an insulating film 34, and a blocking insulating film 35.

The tunnel oxide film 33 surrounds the side surface of the semiconductor 31. The insulating film 34 surrounds the side surface of the tunnel oxide film 33. The insulating film 35 is prevented from surrounding the side of the insulating film 34. The conductor 23 surrounds the side surface of the blocking insulating film 35.

The tunnel oxide film 33 contains, for example, silicon oxide (SiO ₂ ). The insulating film 34 contains, for example, silicon nitride (SiN). The blocking insulating film 35 contains, for example, silicon oxide (SiO ₂ ).

Returning to FIG. 4, a columnar contact CP is provided on the semiconductor 31. In the illustrated area, a contact CP corresponding to one of the two memory posts MP is displayed. The memory column MP in which the contact CP is not connected in this area is connected to the contact CP in the area not shown.

One conductor 25, that is, one bit line BL contacts the upper surface of the contact CP. The memory post MP and the conductive body 25 may be electrically connected through two or more contacts, or may be electrically connected through other wiring.

The slit SLT is formed in a plate shape extending in the Z direction, and for example, divides the conductors 22 to 24. Specifically, the upper end of the slit SLT is included, for example, between the layer containing the upper end of the memory pillar MP and the layer provided with the conductor 25. The lower end of the slit SLT is included in, for example, the layer provided with the conductor 21.

An insulator is provided inside the slit SLT. The insulator includes an insulator such as silicon oxide (SiO ₂ ). In addition, the slit SLT may be composed of plural kinds of insulators. For example, before embedding silicon oxide into the slit SLT, silicon nitride (SiN) may be formed as a sidewall of the slit SLT.

In the configuration of the memory pillar MP described above, for example, a portion where the memory pillar MP crosses the conductor 22 functions as the selection transistor ST2. The portion where the memory column MP crosses the conductor 23 functions as a memory cell transistor MT. The portion where the memory column MP crosses the conductor 24 functions as a selection transistor ST1.

That is, the semiconductor 31 is used as a channel for each of the memory cell transistor MT and the selection transistors ST1 and ST2. The insulating film 34 is used as a charge accumulation layer of the memory cell transistor MT.

In addition, in the structure of the memory cell array 10 described above, the number of conductors 23 is designed based on the number of word lines WL. In the selection of the gate line SGD, a plurality of conductors 24 arranged in a plurality of layers may also be allocated. In the selection of the gate line SGS, a plurality of conductors 22 arranged in a plurality of layers may also be allocated. In the case where the gate line SGS is selected to be a plurality of layers, a conductor different from the conductor 22 can also be used.

[1-1-4] Structure of NMOS transistor TrN and PMOS transistor TrP Hereinafter, an example of the structure of each of the NMOS transistor TrN and the PMOS transistor TrP of the first embodiment will be described.

(About the outline of the structure under the memory cell array 10) First, referring to FIG. 4, the outline of the structure including the NMOS transistor TrN and the PMOS transistor TrP disposed under the memory cell array 10 will be described.

The semiconductor substrate 20 includes, for example, a P-type well region PW, an N-type well region NW, and an element isolation region STI. The insulating layer UA includes, for example, conductors GC, D0, D1, and D2, contacts CS, C0, C1, and C2, and a barrier layer BaL.

Each of the P-type well region PW, the N-type well region NW, and the element isolation region STI is in contact with the upper surface of the semiconductor substrate 20. The N-well region NW and the P-well region PW are insulated by the element separation region STI.

The P-type well region PW includes n ⁺ impurity diffusion regions NP1 and NP2. The n ⁺ impurity diffusion region NP1 and the n ⁺ impurity diffusion region NP2 are arranged separately. Each of the n ⁺ impurity diffusion regions NP1 and NP2 is in contact with the upper surface of the semiconductor substrate 20. Each of the n ⁺ impurity diffusion regions NP1 and NP2 is doped with, for example, phosphorus (P).

The N-type well region NW includes p ⁺ impurity diffusion regions PP1 and PP2. The p ⁺ impurity diffusion region PP1 is arranged separately from the p ⁺ impurity diffusion region PP2. Each of the p ⁺ impurity diffusion regions PP1 and PP2 is in contact with the upper surface of the semiconductor substrate 20. Each of the p ⁺ impurity diffusion regions PP1 and PP2 is doped with, for example, boron (B).

The conductor GCn is provided above the P-type well region PW between the n ⁺ impurity diffusion regions NP1 and NP2. The conductor GCp is provided above the N-type well region NW between the p ⁺ impurity diffusion regions PP1 and PP2. Each conductor D0 is provided on the wiring higher than the conductors GCn and GCp. Each conductor D1 is provided on the wiring higher than the conductor D0. Each conductor D2 is provided on the wiring higher than the conductor D1.

Each contact CS is a columnar conductor provided between the semiconductor substrate 20 and the conductor D0. Each contact C0 is a columnar conductor disposed between the conductor GCn or GCp and the conductor D0. Each contact C1 is a columnar conductor disposed between the conductor D0 and the conductor D1. Each contact C2 is a columnar conductor disposed between the conductor D1 and the conductor D2.

Each of n ⁺ impurity diffusion regions NP1 and NP2 and p ⁺ impurity diffusion regions PP1 and PP2 are electrically connected to different electrical conductors D0 through a contact CS. Each of the electrical conductors GCn and GCp is electrically connected to a different electrical conductor D0 via a contact C0. The electrical conductor D0 and the electrical conductor D1 are electrically connected via a contact C1 as appropriate. The electrical conductor D1 and the electrical conductor D2 are electrically connected via a contact C2 as appropriate.

The barrier layer BaL is disposed on the insulating layer above the conductor D2. In other words, the barrier layer BaL is disposed between the structure corresponding to the memory cell array 10 and the circuit disposed under the memory cell array 10. When the barrier layer BaL forms a structure corresponding to the memory cell array 10 during the manufacturing process of the semiconductor device 1, impurities (such as hydrogen) generated from the structure are prevented from entering circuits under the memory cell array 10. The barrier layer BaL includes, for example, silicon nitride (SiN).

In the configuration described above, the group of the P-type well region PW, the n ⁺ impurity diffusion regions NP1 and NP2, and the conductor GCn function as the NMOS transistor TrN. The group of the N-type well region NW, the p ⁺ impurity diffusion regions PP1 and PP2, and the conductor GCp function as a PMOS transistor TrP.

That is, the conductor GCn is used as the gate electrode of the NMOS transistor TrN. One of the n ⁺ impurity diffusion regions NP1 and NP2 is used as the drain of the NMOS transistor TrN, and the other is used as the source of the NMOS transistor TrN.

Similarly, the conductor GCp is used as the gate electrode of the PMOS transistor TrP. One of the p ⁺ impurity diffusion regions PP1 and PP2 is used as the drain of the PMOS transistor TrP, and the other is used as the source of the PMOS transistor TrP.

(About the structure of NMOS transistor TrN) Next, an example of a more detailed structure of the NMOS transistor TrN will be described.

FIG. 6 shows an example of the cross-sectional structure of the NMOS transistor TrN disposed under the memory cell array 10 in the semiconductor device 1 of the first embodiment.

As shown in FIG. 6, the region of the NMOS transistor TrN includes the P-type well region PW described in FIG. 4, the n ⁺ impurity diffusion regions NP1 and NP2, the contacts CS and C0, the oxide film 40, the semiconductor layer 41, The conductive layer 42, the insulating layer 43, the oxide films 60, 61, 62, and 66, the nitride films 63 and 65, and the insulators 64 and 67.

Specifically, an oxide film 40 is provided on the P-type well region PW between the n ⁺ impurity diffusion regions NP1 and NP2. The oxide film 40 contains, for example, silicon oxide (SiO ₂ ), and is used as the gate insulating film of the NMOS transistor TrN.

On the oxide film 40, a semiconductor layer 41, a conductive layer 42 and an insulating layer 43 are sequentially deposited. The semiconductor layer 41 is an N-type semiconductor and is doped with polysilicon such as phosphorus (P).

The conductive layer 42 includes, for example, tungsten silicide (WSi) or a structure in which titanium nitride is laminated on the tungsten silicide (WSi/TiN). The insulating layer 43 includes, for example, silicon nitride (SiN). For example, the group of the semiconductor layer 41 and the conductive layer 42 is used as the gate electrode (conductor GCn) of the NMOS transistor TrN. The insulating layer 43 is used as an etching stopper, for example.

On the upper surface of the oxide film 40 and the side surfaces of the semiconductor layer 41, the conductive layer 42 and the insulating layer 43, oxide films 60 and 61 are provided in this order. Each of the oxide films 60 and 61 includes, for example, silicon oxide (SiO ₂ ), and is used as a sidewall of the gate electrode of the NMOS transistor TrN.

On the upper surface and side surfaces of the structure formed by the oxide film 40, the semiconductor layer 41, the conductive layer 42, the insulating layer 43, and the oxide films 60 and 61, and the upper surface of the P-type well region PW, successively set The oxide film 62 and the nitride film 63. That is, the oxide film 62 and the nitride film 63 cover the surface of the structure corresponding to the gate electrode of the NMOS transistor TrN and the semiconductor substrate 20.

An insulator 64 is provided on the nitride film 63. The upper surface of the insulator 64 corresponds to, for example, the upper surface of the nitride film 63 provided above the semiconductor layer 41. The insulator 64 is used as an interlayer insulating film formed with a layer corresponding to the gate electrode of the NMOS transistor TrN. The insulator 64 includes, for example, NSG (Non-doped silicate glass).

On the upper surface of the insulator 64 and the upper surface of the nitride film 63 provided above the semiconductor layer 41, a nitride film 65, an oxide film 66, and an insulator 67 are provided in this order. The nitride film 65 contains, for example, silicon nitride (SiN), and is used as, for example, an etching stopper.

The insulator 67 contains, for example, dTEOS. The so-called dTEOS is a silicon oxide formed from TEOS (Tetraethyl ortho-silicate: tetraethyl orthosilicate) by plasma CVD (Chemical Vapor Deposition). The insulator 67 is used as an interlayer insulating film.

In the region of the NMOS transistor TrN, the contact CS is provided on the n ⁺ impurity diffusion region NP, and penetrates (passes through) the insulator 67, the oxide film 66, the nitride film 65, the insulator 64, the nitride film 63, and the oxide film 62. The contact C0 is provided on the conductive layer 42 and penetrates (passes through) the insulator 67, the oxide film 66, the nitride film 65, the nitride film 63, the oxide film 62, and the insulating layer 43.

Each of the contacts CS and C0 corresponding to the NMOS transistor TrN includes conductors 70 and 71. The conductor 70 extends in the Z direction. The conductor 71 is provided so as to cover the side and bottom surfaces of the conductor 70. The conductor 71 includes, for example, titanium nitride (TiN), and is used as a barrier metal in the manufacturing process of the semiconductor device 1. The electric conductor 70 contains, for example, tungsten (W).

The bottom surface of the conductor 71 in the contact CS is in contact with the n ⁺ impurity diffusion region NP. The bottom surface of the conductor 71 in the contact C0 is in contact with the conductive layer 42. For example, the upper surfaces of the conductors 70 and 71 in the contact CS, the upper surfaces of the conductors 70 and 71 in the contact C0, and the upper surface of the insulator 67 coincide. On the wiring layer adjacent to the insulator 67, for example, a conductor D0 is provided.

(About the structure of PMOS transistor TrP) Next, an example of a more detailed structure of the PMOS transistor TrP will be described.

FIG. 7 shows an example of the cross-sectional structure of the PMOS transistor TrP provided under the memory cell array 10 in the semiconductor device 1 of the first embodiment.

As shown in FIG. 7, the region of the PMOS transistor TrP includes the N-type well region NW described in FIG. 4, the p ⁺ impurity diffusion regions PP1 and PP2, and the contacts CS and C0, the oxide film 50, and the nitride film 51 , Semiconductor layer 52, conductive layer 53, insulating layer 54, oxide films 60, 61, 62 and 66, nitride films 63 and 65, insulators 64 and 67, and epitaxial layer EP.

Specifically, an oxide film 50 is provided on the N-type well region NW between the p ⁺ impurity diffusion regions PP1 and PP2. The oxide film 50 contains, for example, silicon oxide (SiO ₂ ), and is used as the gate insulating film of the PMOS transistor TrP.

On the oxide film 50, a nitride film 51, a semiconductor layer 52, a conductive layer 53 and an insulating layer 54 are sequentially deposited. The nitride film 51 is, for example, silicon nitride (SiN), and inhibits impurities doped in the semiconductor layer 52 from diffusing in the semiconductor substrate 20. The semiconductor layer 52 is a P-type semiconductor, and is doped with polysilicon such as boron (B).

The conductive layer 53 includes, for example, tungsten silicide (WSi) or a structure in which titanium nitride is laminated on the tungsten silicide (WSi/TiN). The insulating layer 54 includes, for example, silicon nitride (SiN). For example, the group of the semiconductor layer 52 and the conductive layer 53 is used as the gate electrode (conductor GCp) of the PMOS transistor TrP. The insulating layer 54 is used as an etching stopper, for example.

On the upper surface of the oxide film 50 and the side surfaces of the nitride film 51, the semiconductor layer 52, the conductive layer 53 and the insulating layer 54, oxide films 60 and 61 are provided in this order. The oxide films 60 and 61 are used as sidewalls of the gate electrode of the PMOS transistor TrP.

On the upper surface and side surfaces of the structure formed by the oxide film 50, the nitride film 51, the semiconductor layer 52, the conductive layer 53, the insulating layer 54 and the oxide films 60 and 61, and the upper surface of the N-well region NW, in order An oxide film 62 and a nitride film 63 which are successively provided are provided. That is, the oxide film 62 and the nitride film 63 cover the surface of the structure corresponding to the gate electrode of the PMOS transistor TrP and the semiconductor substrate 20.

An insulator 64 is provided on the nitride film 63. The upper surface of the insulator 64 coincides with, for example, the upper surface of the nitride film 63 provided above the semiconductor layer 52. On the upper surface of the insulator 64 and the upper surface of the nitride film 63 provided above the semiconductor layer 52, a nitride film 65, an oxide film 66, and an insulator 67 are provided in this order.

The epitaxial layer EP is provided in a column shape on each of the p ⁺ impurity diffusion regions PP1 and PP2. In other words, the epitaxial layer EP is provided at the bottom of the contact hole extending in the Z direction and passing through the insulator 67, the oxide film 66, the nitride film 65, the insulator 64, the nitride film 63, and the oxide film 62.

The epitaxial layer EP is a single crystal semiconductor formed by epitaxial growth, such as undoped silicon (Si).

In addition, the epitaxial layer EP may also contain impurities (for example, boron and carbon). In this case, the p-type impurity concentration of the epitaxial layer EP is designed so as to be equal to or lower than the p-type impurity concentration of the p ⁺ impurity diffusion region PP. The impurities doped in the epitaxial layer EP may be doped when the epitaxial layer EP is formed, or may be doped by diffusion of impurities from constituent elements contacting the epitaxial layer EP.

In the area of the PMOS transistor TrP, the contact CS is provided on the epitaxial layer EP. The group of the contact CS and the epitaxial layer EP penetrates (passes) the insulator 67, the oxide film 66, the nitride film 65, the insulator 64, the nitride film 63, and the oxide film 62. The contact C0 is provided on the conductive layer 53 and penetrates (passes through) the insulator 67, the oxide film 66, the nitride film 65, the nitride film 63, the oxide film 62, and the insulating layer 54.

The contact CS corresponding to the PMOS transistor TrP includes the conductors 70 and 71 and the semiconductor 72. The configuration of the contact C0 corresponding to the PMOS transistor TrP is the same as the configuration of the contact C0 corresponding to the NMOS transistor TrN.

In the contact CS, the conductor 70 extends in the Z direction. The conductor 71 is provided so as to cover the side and bottom surfaces of the conductor 70. The semiconductor 72 is provided so as to cover the side and bottom surfaces of the conductor 71.

The semiconductor 72 is, for example, silicon (Si) doped with boron (B) or polysilicon (Si) doped with boron (B) and carbon (C). The boron concentration of the semiconductor 72 is, for example, 10 ¹⁹ (atoms/cm ³ ) or more. The carbon concentration of the semiconductor 72 doped with carbon is, for example, 10 ¹⁹ (atoms/cm ³ ) or more, and is designed to have the same concentration as boron.

In addition, in the semiconductor 72, the preferred boron concentration is 10 ²¹ (atoms/cm ³ ) level, and the preferred carbon concentration is 10 ²¹ (atoms/cm ³ ) level. The higher the boron concentration in the contact portion between the contact CS and the epitaxial layer EP, the smaller the contact resistance between the contact CS and the epitaxial layer EP.

The bottom surface of the semiconductor 72 in the contact CS is in contact with the epitaxial layer EP. The bottom surface of the conductor 71 in the contact C0 is in contact with the conductive layer 53. For example, the upper surfaces of the conductors 70 and 71 and the semiconductor 72 in the contact CS, the upper surfaces of the conductors 70 and 71 in the contact C0, and the upper surface of the insulator 67 coincide.

[1-2] Manufacturing method of semiconductor device 1 FIG. 8 is a flowchart showing an example of the manufacturing steps of the semiconductor device 1 of the first embodiment. Each of FIGS. 9 to 13 shows an example of a cross-sectional structure including a structure corresponding to the NMOS transistor TrN and the PMOS transistor TrP in the manufacturing step of the semiconductor device 1 of the first embodiment.

Hereinafter, an example of a series of manufacturing steps from the formation of the NMOS transistor TrN and the PMOS transistor TrP to the formation of the contacts CS and C0 according to the first embodiment will be described as appropriate.

First, as shown in FIG. 9, NMOS transistor TrN and PMOS transistor TrP are formed (step S1).

The structure of the NMOS transistor TrN shown in FIG. 9 is the same as the structure omitting the contacts CS and C0 from the structure of the NMOS transistor TrN explained using FIG. 6. The structure of the PMOS transistor TrP shown in FIG. 9 is the same as the structure omitting the contacts C0 and CS and the epitaxial layer EP from the structure of the PMOS transistor TrP described using FIG. 7.

Next, as shown in FIG. 10, a contact hole CHp1 corresponding to the contact CS of the PMOS transistor TrP is formed (step S2). As an etching method in this step, anisotropic etching such as RIE (Reactive Ion Etching) is used.

In this step, the contact hole CHp1 penetrates each of the insulator 67, the oxide film 66, the nitride film 65, the insulator 64, the nitride film 63, and the oxide film 62. Also, at the bottom of the contact hole CHp1, the surface of the p ⁺ impurity diffusion region PP is exposed.

Next, as shown in FIG. 11, an epitaxial layer EP is formed on the bottom of the contact hole CHp1 (step S3). Specifically, for example, epitaxial growth is performed based on silicon (Si) in the N-type well region NW, and single crystal silicon is formed on the upper surface of the p ⁺ impurity diffusion region PP. In addition, the epitaxial layer EP formed in this step may be doped with impurities or not.

Next, as shown in FIG. 12, a semiconductor 72 is formed on each of the upper surface of the insulator 67 and the side surface and bottom surface of the contact hole CHp1 (step S4). For example, the film thickness of the semiconductor 72 formed in this step is adjusted so that the contact hole CHp1 is not completely filled.

Next, as shown in FIG. 13, contact holes CHn1 and CHn2 corresponding to the contacts CS and C0 of the NMOS transistor TrN, and contact holes CHp2 corresponding to the contact C0 of the PMOS transistor TrP are formed (step S5). As the etching method in this step, anisotropic etching such as RIE is used.

In this step, the contact hole CHn1 penetrates each of the semiconductor 72, the insulator 67, the oxide film 66, the nitride film 65, the insulator 64, the nitride film 63, and the oxide film 62. Also, at the bottom of the contact hole CHn1, the surface of the n ⁺ impurity diffusion region NP is exposed.

The contact hole CHn2 penetrates each of the semiconductor 72, the insulator 67, the oxide film 66, the nitride film 65, the nitride film 63, the oxide film 62, and the insulating layer 43. And, at the bottom of the contact hole CHn2, the surface of the conductive layer 42 is exposed.

The contact hole CHp2 penetrates each of the semiconductor 72, the insulator 67, the oxide film 66, the nitride film 65, the nitride film 63, the oxide film 62, and the insulating layer 54. And, at the bottom of the contact hole CHp2, the surface of the conductive layer 53 is exposed.

Next, each of the contacts CS and C0 corresponding to the NMOS transistor TrN and the contacts CS and C0 corresponding to the PMOS transistor TrP are formed.

Specifically, first, the conductors 71 and 70 are sequentially formed by, for example, CVD (Chemical Vapor Deposition) (step S6). According to this step, each of the contact holes CHn1, CHn2, CHp1, and CHp2 is buried by the conductor 70.

Next, by CMP (Chemical Mechanical Polishing), the conductors 70 and 71 formed outside the contact holes CHn1, CHn2, CHp1, and CHp2 are removed (step S7). Thereafter, an etch-back process is performed to remove the semiconductor 72 formed on the upper surface of the insulator 67 (step S8).

As a result, as shown in FIG. 14, in the contact hole CHn1, a contact CS whose bottom surface is in contact with the n ⁺ impurity diffusion region NP is formed. In the contact hole CHn2, a contact C0 with a bottom surface in contact with the conductive layer 42 is formed. In the contact hole CHp1, a contact CS with a bottom surface in contact with the epitaxial layer EP is formed. In the contact hole CHp2, a contact C0 with a bottom surface in contact with the conductive layer 53 is formed.

As described above, in the manufacturing method of the semiconductor device 1 of the first embodiment, the structure of the NMOS transistor TrN described using FIG. 6 and the structure of the PMOS transistor TrP described using FIG. 7 are formed.

[1-3] Effects of the first embodiment Hereinafter, details of the effect of the semiconductor device 1 of the first embodiment will be described.

In a three-dimensional stacked semiconductor device with memory cells, in order to suppress the chip area, circuits such as sense amplifier modules can be arranged under the memory cell array. In the manufacturing process of the semiconductor device with such a structure, after forming circuits such as a sense amplifier module, a memory cell array is formed.

However, in a semiconductor device having such a structure, the heat treatment when the memory cell array is formed may deteriorate the characteristics of the transistor disposed under the memory cell array. For example, in the junction connected to the impurity diffusion region corresponding to the source or drain of the transistor, the heat treatment may cause the impurities in the impurity diffusion region to diffuse.

If impurities are diffused in the contact, the impurity concentration in the impurity diffusion region may decrease, and the contact resistance between the contact and the impurity diffusion region may increase. This phenomenon is particularly likely to occur in the junction connected to the p ⁺ impurity diffusion region doped with boron.

As a countermeasure, it is more effective to set the doping amount of boron corresponding to the p ⁺ impurity diffusion region of the PMOS transistor to a high concentration. Thereby, even if boron diffuses in the contact, a high concentration of boron can be maintained in the impurity diffusion region.

On the other hand, if the doping amount of boron in the p ⁺ impurity diffusion region is set to a high concentration, the p ⁺ impurity diffusion region in the N-type well region may expand due to heat treatment. In this case, since the interval between the gate electrode and the p ⁺ impurity diffusion region becomes shorter, the short channel characteristics of the transistor may deteriorate.

In this regard, the semiconductor device 1 of the first embodiment has a structure in which the impurity concentration of the p ⁺ impurity diffusion region PP is designed to be suitable for a short-channel characteristic and corresponds to the p ⁺ impurity diffusion region PP of the PMOS transistor TrP It is electrically connected to the contact CS via the epitaxial layer EP. In addition, the contact CS has a semiconductor 72 doped with boron at a high concentration, for example, in a portion in contact with the epitaxial layer EP.

When this case is configured perform the heat treatment time of the memory cell array is formed, due to the high concentration of boron-doped semiconductor p ⁺ impurity diffusion region 72 is formed separately from PP, so that p ⁺ impurity diffusion region is suppressed expanded PP.

Moreover, even if boron doped in the semiconductor 72 diffuses in the epitaxial layer EP or the conductors 70 and 71, the boron concentration of the semiconductor 72 can be maintained at a high state. In addition, the carbon doped in the semiconductor 72 suppresses the diffusion of boron doped in the semiconductor 72.

Furthermore, boron in the p ⁺ impurity diffusion region PP can also diffuse in the epitaxial layer EP, but the diffusion amount of impurities into the single crystal semiconductor is less than that of the p ⁺ impurity diffusion region PP and the contact CS made of metal The amount of impurities in the situation diffuses into the contact CS.

As a result, the semiconductor device 1 of the first embodiment can suppress the increase in the contact resistance between the contact CS and the epitaxial layer EP, and can suppress the decrease in the short-channel characteristics of the PMOS transistor TrP or the change in the impurity concentration of the p ⁺ impurity diffusion region PP . Therefore, the semiconductor device of the first embodiment can suppress the characteristic change of the transistor.

When another, in EP epitaxial layer is doped with boron in the case of p ⁺ impurity concentration of the impurity diffusion region of the PP, EP epitaxial layer and the p ⁺ impurity diffusion region between the impurity concentration gradient of the PP becomes smaller, and the semiconductor 72 The gradient of the impurity concentration between the epitaxial layer EP also becomes smaller.

In this case, during the heat treatment when the memory cell array is formed, the diffusion of impurities from the p ⁺ impurity diffusion region PP to the epitaxial layer EP can be suppressed, so that the change in the impurity concentration of the p ⁺ impurity diffusion region PP can be further suppressed. Similarly, since the diffusion of impurities from the semiconductor 72 to the epitaxial layer EP can also be suppressed, the change in the impurity concentration of the semiconductor 72 can be suppressed.

With this, the semiconductor device 1 of the first embodiment can suppress the unevenness of the characteristics of the PMOS transistor TrP, and can suppress the increase in the contact resistance between the contact CS and the p ⁺ impurity diffusion region PP.

In the semiconductor device 1 of the first embodiment described above, the semiconductor 72 in the contact CS is polysilicon doped with impurities. That is, the step of forming the semiconductor 72 in the first embodiment can be realized at a lower cost than in the case of ion implantation treatment or the formation of an epitaxial layer EP doped with impurities at a high concentration. Therefore, the semiconductor device 1 of the first embodiment can suppress the manufacturing cost.

[2] Second embodiment The semiconductor device 1 of the second embodiment differs from the first embodiment in the timing of performing the etch-back process on the semiconductor 72. Hereinafter, the difference from the first embodiment will be described for the semiconductor device 1 of the second embodiment.

[2-1] Structure of Transistor TrP FIG. 15 shows an example of the cross-sectional structure of the PMOS transistor TrP disposed under the memory cell array 10 in the semiconductor device 1 of the second embodiment.

As shown in FIG. 15, in the region including the PMOS transistor TrP of the second embodiment, for example, the structure of the contact CS is different from the structure described using FIG. 7 in the first embodiment.

Specifically, a columnar semiconductor 72 is provided on the epitaxial layer EP. The side and bottom surfaces of the conductor 70 extending in the Z direction are covered by the conductor 71. The bottom surface of the conductor 71 is in contact with the upper surface of the semiconductor 72. In the semiconductor device 1 of the second embodiment, the semiconductor 72 does not have a portion that is in contact with the wiring layer on the insulator 67.

In the contact CS, the side surface of the conductor 71 and the side surface of the semiconductor 72 are continuously provided. In other words, each of the conductor 71 and the semiconductor 72 is in contact with the side of the contact hole corresponding to the contact CS. Furthermore, the boundary portion of the conductor 71 and the semiconductor 72 is in contact with the side surface of the contact hole.

The other configuration of the semiconductor device 1 of the second embodiment described above is the same as that of the semiconductor device 1 of the first embodiment, so description will be omitted.

[2-2] Manufacturing method of semiconductor device 1 FIG. 16 is a flowchart showing an example of the manufacturing steps of the semiconductor device 1 of the second embodiment. 17 to 20 each show an example of a cross-sectional structure including a structure corresponding to the NMOS transistor TrN and the PMOS transistor TrP in the manufacturing step of the semiconductor device 1 of the second embodiment.

Hereinafter, referring to FIG. 16, an example of a series of manufacturing steps from the formation of the NMOS transistor TrN and the PMOS transistor TrP to the formation of the contacts CS and C0 in the second embodiment will be described.

First, the processes of steps S1 to S3 are executed in order. By this, the transistors TrN and TrP, the contact hole CHp1 and the epitaxial layer EP are formed respectively, and the same structure as that of FIG. 11 described in the first embodiment is formed, for example.

Next, the process of step S4 is performed, and as shown in FIG. 17, the semiconductor 72 is formed. In the process of step S4 of the second embodiment, for example, the semiconductor 72 is buried in the contact hole CHp1.

Next, the process of step S8 is performed, and as shown in FIG. 18, the semiconductor 72 is etched back. Specifically, in the process of step S4, the semiconductor 72 formed outside the contact hole is removed, and the semiconductor 72 inside the contact hole CHp1 is processed to a desired height.

Next, the process of step S5 is performed. As shown in FIG. 19, contact holes CHn1 and CHn2 corresponding to the contacts CS and C0 of the NMOS transistor TrN and contact holes CHp2 corresponding to the contact C0 of the PMOS transistor TrP are formed. .

Next, the process of step S6 is performed to form the conductors 71 and 70 in order. According to this step, each of the contact holes CHn1, CHn2, CHp1, and CHp2 is buried by the conductor 70.

Next, the process of step S7 is performed, and the conductors 70 and 71 formed outside the contact holes CHn1, CHn2, CHp1, and CHp2 are removed by CMP (Chemical Mechanical Polishing). The processing details of each of steps S5 to S8 of the second embodiment are the same as those of the first embodiment.

As a result, as shown in FIG. 20, in the contact hole CHn1, a contact CS whose bottom surface is in contact with the n ⁺ impurity diffusion region NP is formed. In the contact hole CHn2, a contact C0 with a bottom surface in contact with the conductive layer 42 is formed. In the contact hole CHp1, a contact CS with a bottom surface in contact with the epitaxial layer EP is formed. In the contact hole CHp2, a contact C0 with a bottom surface in contact with the conductive layer 53 is formed.

As described above, in the manufacturing method of the semiconductor device 1 of the second embodiment, the structure of the NMOS transistor TrN described using FIG. 6 in the first embodiment and the PMOS transistor described using FIG. 15 in the second embodiment are formed. The construction of TrP.

[2-3] Effect of the second embodiment In the semiconductor device 1 of the second embodiment, the etch-back process of the semiconductor 72 doped with boron at a high concentration is performed before the conductors 70 and 71 are formed.

In this case, the contact portion CS corresponding to the PMOS transistor TrP and the contact portion with the corresponding conductor D0 do not include the semiconductor 72. That is, the contact area between the conductors 70 and 71 and the conductor D0 is larger in the second embodiment than in the first embodiment.

As a result, in the semiconductor device 1 of the second embodiment, the contact resistance of the contact CS corresponding to the PMOS transistor TrP and the conductor D0 corresponding to the contact CS can be made smaller than that of the first embodiment.

[2-4] Variation of the second embodiment In the second embodiment, the case where the contact CS corresponding to the PMOS transistor TrP is formed by the conductors 70 and 71 and the semiconductor 72 is exemplified, but the structure of the contact CS corresponding to the PMOS transistor TrP may also be Other constructions.

FIG. 21 shows an example of a cross-sectional structure including a structure corresponding to the NMOS transistor TrN and the PMOS transistor TrP according to a modification of the second embodiment.

The structure of the area shown in FIG. 21 is different from the structure of the area shown in FIG. 20 described in the second embodiment, which corresponds to the structure of the contact CS of the PMOS transistor TrP.

Specifically, in the modified example of the second embodiment, the contact CS corresponding to the PMOS transistor TrP includes the semiconductor 72 and does not include the conductors 70 and 71. That is, in a variation of the second embodiment, in the contact hole CHp1 corresponding to the PMOS transistor TrP, a columnar semiconductor 72 is buried as a contact CS in a layer higher than the epitaxial layer EP.

Also, the upper surface of the columnar semiconductor 72 coincides with the upper surface of each of the contacts CS and C0 corresponding to the NMOS transistor TrN and the upper surface of the contact C0 corresponding to the PMOS transistor TrP. When the semiconductor device 1 has such a structure, the semiconductor 72 forming the contact CS corresponding to the PMOS transistor TrP is directly connected to the conductor D0 of the wiring layer provided on the insulator 67.

The structure of the contact CS corresponding to the PMOS transistor TrP in the modified example of the second embodiment described above is, for example, in the manufacturing method described using FIG. 16 in the second embodiment, the amount of etch back in step S8 is small Situation.

For example, when the semiconductor 72 on the insulator 67 is removed by the etch-back process in step S8, and the amount of depression of the semiconductor 72 in the contact hole CHp1 is small, a PMOS transistor corresponding to the variation of the second embodiment can be formed The structure of the TrP contact CS.

In this case, since the semiconductor 72 has a high concentration of boron, the contact resistance between the semiconductor 72 forming the contact CS corresponding to the PMOS transistor TrP and the conductor D0 contacting the semiconductor 72 can also be suppressed. Therefore, the structure of the contact CS of the PMOS transistor TrP corresponding to the modification of the second embodiment can obtain the same effect as the first embodiment.

[3] Other changes, etc. The semiconductor device of the embodiment includes an N-type well region, a first gate electrode, a first semiconductor, and a first contact. The N-type well region includes two P-type impurity diffusion regions. The first gate electrode via gate insulating film is provided above the N-well region between the two P-type impurity diffusion regions. The first semiconductor is a single crystal semiconductor provided in a columnar shape on the P-type impurity diffusion region. The first contact includes a polycrystalline second semiconductor provided on the first semiconductor and containing P-type impurities. Thereby, in the semiconductor device of the embodiment, the characteristic change of the transistor can be suppressed.

The manufacturing steps described in the above embodiments and modified examples are only examples, and other processes may be inserted between the manufacturing steps, and the manufacturing steps may be appropriately replaced. If the manufacturing steps of the semiconductor device 1 can form the structures described in the above-mentioned embodiments and modification examples, any manufacturing steps can be applied.

In the above-described embodiment, the nitride film is used as the etching stopper layer when forming the contact hole corresponding to the impurity diffusion region, but it is not limited to this. If it is a material that can be used as an etching stopper, other materials can be used instead of the nitride film 63.

In the manufacturing steps described in the above embodiments, the case where the semiconductor 72 doped with impurities is formed when forming the semiconductor 72 (polysilicon) is exemplified, but it is not limited thereto. For example, after the undoped semiconductor 72 is formed, the semiconductor 72 may be doped with impurities.

In the above embodiment, each of the contacts CS and C0 and the epitaxial layer EP have been described, but the epitaxial layer EP can also be regarded as a part of the contact CS. For example, in the first embodiment, the contact CS corresponding to the PMOS transistor TrP can also be regarded as including at least the semiconductor 72 and the epitaxial layer EP. Further, the contact is not limited to this case CS is set to p ⁺ impurity diffusion region of PP1 and PP2 on each person, CS may also be disposed on the contact p ⁺ impurity diffusion region PP1 and PP2 of at least one.

In the above embodiment, the structure of the memory cell array 10 may be other structures. For example, the memory pillar MP may be a structure in which a plurality of pillars are connected in the Z direction. For example, the memory pillar MP may be a structure in which a pillar penetrating the conductor 24 (select gate line SGD) and a pillar penetrating a plurality of conductors 23 (character line WL) are connected. In addition, the memory pillar MP may have a structure in which a plurality of pillars respectively penetrating a plurality of conductors 23 are connected in the Z direction.

In the above embodiment, the case where the semiconductor device 1 has a structure in which a circuit such as a sense amplifier module 16 is provided under the memory cell array 10 has been exemplified, but it is not limited thereto. For example, the semiconductor device 1 may have a structure in which the memory cell array 10 is formed on the semiconductor substrate 20. In this case, the memory pillar MP electrically connects the semiconductor 31 and the source line SL through the bottom surface of the memory pillar MP, for example.

In addition, in the above embodiments, the case where the semiconductor device 1 is a NAND flash memory is exemplified, but the structure of each of the NMOS transistor TrN and the PMOS transistor TrP described in each embodiment may be applied to other semiconductors. Device application. That is, the use of the semiconductor device having the structure of the NMOS transistor TrN and the PMOS transistor TrP is not limited to the semiconductor memory.

In this specification, "connected" means electrically connected, for example, it does not exclude that other elements are interposed therebetween.

In this specification, the "conductivity type" means N-type or P-type. For example, the first conductivity type corresponds to the P type, and the second conductivity type corresponds to the N type.

In this specification, "N-type impurity diffusion region" corresponds to n ⁺ impurity diffusion region NP. The “P-type impurity diffusion region” corresponds to the p ⁺ impurity diffusion region PP.

In this specification, "polycrystalline silicon" may be referred to as polycrystalline semiconductor.

In this specification, the "pillar shape" means a structure formed in the contact hole. Therefore, in this specification, regardless of the height of the epitaxial layer EP, for example, the epitaxial layer EP is regarded as a column.

In this specification, “the upper surface coincides” means that, for example, the surface of the semiconductor substrate 20 and the upper surface of a certain component are substantially the same in the Z direction from the target component. In addition, the “upper surface coincidence” may mean that, for example, the upper surface of the first component and the upper surface of the second component are in contact with the same wiring layer or insulating layer.

In this specification, "continuously provided on the side" means that the boundary between the first and second components formed in the same contact hole changes continuously between the outer diameter of the first component and the outer diameter of the first component. “Outer diameter” means, for example, the outer diameter of a cross section parallel to the semiconductor substrate 20.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or changes are included in the scope or gist of the invention, and are included in the invention described in the patent application scope and its equivalent scope. [Related application]

This application has priority based on Japanese Patent Application No. 2018-167710 (application date: September 7, 2018). This application includes all contents of the basic application by referring to the basic application.

1: Semiconductor device 2: Memory controller 10: Memory cell array 11: Command register 12: Address register 13: Sequencer 14: Driver module 15: Column decoder module 16: Sense amplifier Module 20: Semiconductor substrate 21-25: Conductor 30: Core member 31: Semiconductor 32: Lamination film 33: Tunnel oxide film 34: Insulation film 35: Insulation prevention film 40: Oxide film 41: Semiconductor layer 42: Conductive layer 43 : Insulating layer 50: oxide film (gate insulating film) 51: nitride film 52: semiconductor layer 53: conductive layer 54: insulating layer 60: oxide film 61: oxide film 62: oxide film 63: nitride film 64: insulator 65: nitride film 66: oxide film 67: insulator 70: conductor 71: conductor 72: semiconductor ADD: address information ALE: address latch enable signal BA: block address BaL: barrier layer BL: bit Element line BL0～BLm: Bit line BLK: Block BLK0～BLKn: Block C0: Contact C1: Contact C2: Contact CA: Row address CHn1: Contact hole CHn2: Contact hole CHp1: Contact hole CHp2: Contact hole CLE: command latch enable signal CMD: command CP: contact CS: contact CU: cell unit D0: conductor D1: conductor D2: conductor DAT: data EP: epitaxial layer GC: conductor GCn : Conductor GCp: Conductor I/O: Input/output signal MP: Memory column MT0～MT7: Memory cell transistor NP: n ⁺ impurity diffusion region NP1: n ⁺ impurity diffusion region NP2: n ⁺ impurity diffusion region NS: NAND string NW: N-type well area PA: Page address PP: p ⁺ impurity diffusion area PP1: p ⁺ impurity diffusion area PP2: p ⁺ impurity diffusion area PW: P-type well area RBn: ready busy signal REn: read enable Signals S1～S8: Steps SGD0～SGD3: Select gate line SGS: Select gate line SL: Source line SLT: Slit ST1: Select transistor ST2: Select transistor STI: Element separation area SU0～SU3: String unit TrN: NMOS transistor TrP: PMOS transistor UA: insulating layer WEn: write enable signal WL0～WL7: word line X: direction Y: direction Z: direction

FIG. 1 is a block diagram showing a configuration example of the semiconductor device of the first embodiment. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array included in the semiconductor device of the first embodiment. 3 is a plan view showing an example of the planar layout of the memory cell array included in the semiconductor device of the first embodiment. 4 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the semiconductor device of the first embodiment. 5 is a cross-sectional view showing an example of the cross-sectional structure of the memory pillar of the semiconductor device according to the first embodiment. 6 is a cross-sectional view showing an example of a cross-sectional structure of an NMOS (Negative Channel Metal Oxide Semiconductor) transistor disposed under a memory cell array in the semiconductor device of the first embodiment. 7 is a cross-sectional view showing an example of a cross-sectional structure of a PMOS (Positive Channel Metal Oxide Semiconductor) transistor provided under a memory cell array in the semiconductor device of the first embodiment. FIG. 8 is a flowchart showing an example of manufacturing steps of the semiconductor device of the first embodiment. 9 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of the manufacturing steps of the semiconductor device of the first embodiment. 10 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of the manufacturing steps of the semiconductor device of the first embodiment. 11 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of the manufacturing steps of the semiconductor device of the first embodiment. 12 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of the manufacturing steps of the semiconductor device of the first embodiment. 13 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of the manufacturing steps of the semiconductor device of the first embodiment. 14 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of the manufacturing steps of the semiconductor device of the first embodiment. 15 is a cross-sectional view showing an example of a cross-sectional structure of a PMOS transistor disposed under a memory cell array in the semiconductor device of the second embodiment. FIG. 16 is a flowchart showing an example of the manufacturing steps of the semiconductor device of the second embodiment. FIG. 17 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of the manufacturing steps of the semiconductor device of the second embodiment. 18 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of the manufacturing steps of the semiconductor device of the second embodiment. FIG. 19 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of the manufacturing steps of the semiconductor device of the second embodiment. 20 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of the manufacturing steps of the semiconductor device of the second embodiment. 21 is a cross-sectional view showing an example of a cross-sectional structure of NMOS transistors and PMOS transistors provided under a memory cell array in a semiconductor device according to a modification of the second embodiment.

50: oxide film (gate insulating film)

51: nitride film

52: Semiconductor layer

53: conductive layer

54: Insulation

60: oxide film

61: oxide film

62: oxide film

63: nitride film

64: insulator

65: nitride film

66: oxide film

67: insulator

70: electrical conductor

71: Conductor

72: Semiconductor

C0: contact

CS: Contact

EP: epitaxial layer

NW: N-well area

PP1: p ⁺ impurity diffusion region

PP2: p ⁺ impurity diffusion region

TrP: PMOS transistor

X: direction

Y: direction

Z: direction

Claims (20)

A semiconductor device including: N-type well region, which contains 2 P-type impurity diffusion regions; The first gate electrode is disposed above the N-well region between the two P-type impurity diffusion regions, and faces the N-well region through the gate insulating film; A single-crystal first semiconductor, which is provided in a columnar shape on the above-mentioned P-type impurity diffusion region; and The first contact includes a polycrystalline second semiconductor provided on the first semiconductor and containing P-type impurities. The semiconductor device according to claim 1, wherein the first contact further includes a first electrical conductor; and Each of the side surface of the first conductor and the bottom surface of the first conductor is covered by the second semiconductor; The upper surface of the first electrical conductor coincides with the upper surface of the second semiconductor. The semiconductor device according to claim 2, wherein the first conductor is metal. The semiconductor device according to claim 2, further comprising the second contact on the first gate electrode; and The upper surface of the second contact, the upper surface of the first conductor, and the upper surface of the second semiconductor coincide. The semiconductor device according to claim 4, wherein the second contact includes a second electrical conductor; and The first electrical conductor and the second electrical conductor include the same conductive material. The semiconductor device according to claim 1, wherein the first contact further includes a first electrical conductor; and The first electrical conductor is provided on the second semiconductor; The side surface of the first conductor and the side surface of the second semiconductor are continuously provided. The semiconductor device according to claim 6, wherein the first electrical conductor is a metal. The semiconductor device according to claim 6, further comprising the second contact on the first gate electrode; and The upper surface of the second contact coincides with the upper surface of the first conductor. The semiconductor device according to claim 8, wherein the second contact includes a second electrical conductor; and The first electrical conductor and the second electrical conductor include the same conductive material. The semiconductor device according to claim 1, further comprising the second contact on the first gate electrode; and The upper surface of the second contact coincides with the upper surface of the second semiconductor. The semiconductor device according to claim 10, wherein the second semiconductor is provided in a column shape. The semiconductor device according to claim 10, wherein the second contact includes metal. The semiconductor device according to claim 1, wherein the second semiconductor contains boron as the P-type impurity; the boron concentration of the second semiconductor is 10 ¹⁹ (atoms/cm ³ ) or more. The semiconductor device according to claim 1, wherein the second semiconductor further includes carbon; and the carbon concentration of the second semiconductor is 10 ¹⁹ (atoms/cm ³ ) or more. The semiconductor device according to claim 1, further comprising: a P-type well region including two N-type impurity diffusion regions; A second gate electrode disposed above the P-well region between the two N-type impurity diffusion regions, and facing the P-well region through the gate insulating film; and The third contact is provided on the N-type impurity diffusion region and does not have a columnar single crystal semiconductor between the N-type impurity diffusion region. The semiconductor device according to claim 1, further comprising: a laminate provided above the upper surface of the second semiconductor, and including alternately laminated insulating layers and conductive layers; and A plurality of columns, each of which passes through the above-mentioned laminate; and Each of the intersections of the plurality of pillars and the conductive layer functions as a memory cell. A method for manufacturing a semiconductor device, comprising the following steps: forming an N-well region on a substrate; Forming a gate electrode above the N-well region; Forming two P-type impurity diffusion regions via the gate electrode in a plan view; Forming a contact hole in such a way that the surface of the P-type impurity diffusion region is exposed; Forming a single-crystal first semiconductor on the P-type impurity diffusion region exposed at the bottom of the contact hole; and After forming the first semiconductor, a polycrystalline second semiconductor doped with P-type impurities is formed on the side surface of the contact hole and the first semiconductor. The method for manufacturing a semiconductor device according to claim 17, wherein in forming the second semiconductor, the second semiconductor is further doped with carbon. The method for manufacturing a semiconductor device according to claim 17, further comprising the steps of: after forming the second semiconductor, forming a conductor in the contact hole; and After forming the conductor, the second semiconductor formed outside the contact hole is removed. The method for manufacturing a semiconductor device according to claim 17, further comprising the steps of: after forming the second semiconductor, part of the second semiconductor formed outside the contact hole and the second semiconductor formed on the side surface of the contact hole are removed ;and After removing a part of the second semiconductor, a conductor is formed in the contact hole.

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