TW202009908A - Display device and compensation capacitor operating method - Google Patents

Abstract

A display device has a display area and a plurality of non-display areas. The display device includes a substrate, a plurality of pixel units, a plurality of first gate lines, a plurality of second gate lines, a plurality of first data lines, a plurality of second data lines, and a plurality of capacitor compensation structures. The pixel units are arranged on the substrate in a matrix. The first gate line and the second gate line are arranged in rows on the substrate. The first data line and the second data line are arranged in columns on the substrate. The capacitor compensation structures are arranged in a matrix in the non-display areas. The capacitor compensation structure includes a portion of the second gate line, an insulating layer, a semiconductor layer, and a portion of the second data line. The insulating layer is disposed on the portion of the second gate line. The semiconductor layer is disposed on the insulating layer. The portion of the second data line is disposed on the semiconductor layer. The portion of the second data lines and the portion of the second gate lines are disposed on opposite sides of the semiconductor layer.

Description

Display device and operation method of compensation capacitor

The present invention relates to a display device, and more particularly to a display device with a capacitance compensation structure and a method of operating a compensation capacitor.

At present, in electronic products with liquid crystal display devices (such as mobile phones), a notch is often provided in the upper center of the liquid crystal display device to place the camera or sensor; even the liquid crystal display device The four corners are rounded to meet consumers' needs in the appearance of electronic products. However, compared to other areas of the liquid crystal display device, the number of pixels corresponding to the gate lines at the concave holes and rounded corners is relatively small, thus making the gate load of the gate lines at the concave holes and rounded corners The gate loads of the gate lines in other areas are different, which in turn causes the LCD display device to have uneven display brightness and discontinuous pictures.

The present invention provides a display device including a capacitance compensation structure, which can have a relatively uniform display brightness, and can avoid the problem of discontinuous pictures.

The invention provides an operation method of compensating capacitance. By using the above display device with capacitance compensation structure, the problems of uneven display brightness and discontinuous picture can be improved.

A display device of the present invention has a display area and a plurality of non-display areas. The display device includes a substrate, multiple pixel units, multiple first gate lines, multiple second gate lines, multiple first data lines, multiple second data lines, and multiple capacitance compensation structures. The pixel unit matrix is arranged on the substrate and located in the display area. The first gate line and the second gate line are arranged in a row on the substrate and located in the display area. The first data line and the second data line are arranged in a row on the substrate and located in the display area. The capacitance compensation structure matrix is arranged in the non-display area. The capacitance compensation structure includes part of the second gate line, insulating layer, semiconductor layer and part of the second data line. The insulating layer is disposed on part of the second gate line. The semiconductor layer is disposed on the insulating layer. Part of the second data line is disposed on the semiconductor layer. Part of the second data line and part of the second gate line are respectively located on opposite sides of the semiconductor layer.

An operation method of a compensation capacitor of the present invention utilizes the above display device, and the operation method includes the following steps. When the gate load of the second gate line is larger than the gate load of the first gate line, the potential of the second data line in the capacitance compensation structure is increased to reduce the compensation capacitance and the second gate line Total capacitance. When the gate load of the second gate line is smaller than the gate load of the first gate line, by reducing the potential of the second data line in the capacitance compensation structure, the compensation capacitance and the second gate line are increased Total capacitance. When the potential drop time of the second gate line is slower than that of the first gate line, the potential of the second data line in the capacitance compensation structure is increased to reduce the compensation capacitance and the second gate line Total capacitance. When the potential drop time of the second gate line is faster than that of the first gate line, the compensation capacitor and the second gate line are increased by reducing the potential of the second data line in the capacitance compensation structure Total capacitance.

The display device in one of the above embodiments has a capacitance compensation structure, which can have a relatively uniform display brightness, and can avoid the problem of discontinuous pictures.

In the operation method of the compensation capacitor in one of the above embodiments, the problems of uneven display brightness and discontinuous picture can be improved.

Based on the above, the display device of this embodiment has multiple capacitance compensation structures arranged in the non-display area. The capacitance compensation structure includes part of the second gate line, insulating layer, semiconductor layer and part of the second data line. Wherein, the insulating layer is arranged on part of the second gate line, the semiconductor layer is arranged on the insulating layer, part of the second data line is arranged on the semiconductor layer, and part of the second data line and part of the second gate line are respectively Located on opposite sides of the semiconductor layer. With this design, the above-mentioned display device can have a relatively uniform display brightness and can avoid the problem of discontinuity in the picture.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

FIG. 1A is a schematic top view of a display device according to an embodiment of the invention. FIG. 1B is an enlarged view of the area A in FIG. 1A. FIG. 1C is an enlarged view of the crossover region R in FIG. 1B. FIG. 1D is a schematic cross-sectional view taken along line I-I' in FIG. 1C.

Please refer to FIGS. 1A and 1B at the same time. In this embodiment, the display device 100 has a display area 101 and a plurality of non-display areas 102a, 102b, 102c, 102d, and 102e. The display device 100 includes a substrate 110, a plurality of pixel units 120, a plurality of first gate lines 130, a plurality of second gate lines 140, a plurality of first data lines 150, a plurality of second data lines 160 and a plurality of Capacitance compensation structure 170. The pixel units 120 are arranged in a matrix on the substrate 110 and located in the display area 101. The first gate line 130 and the second gate line 140 are arranged in a row on the substrate 110 and are located in the display area 101. The first data line 150 and the second data line 160 are arranged in a row on the substrate 110 and are located in the display area 101. The capacitance compensation structures 170 are arranged in a matrix in the non-display areas 102a, 102b, 102c, 102d, and 102e (a plurality of capacitance compensation structures 170 in the non-display area 102a are schematically shown in FIG. 1B).

1C and FIG. 1D, the capacitance compensation structure 170 includes a part of the second gate line 140, an insulating layer 172, a semiconductor layer 174, and a part of the second data line 160. The insulating layer 172 is disposed on part of the second gate line 140. The semiconductor layer 174 is disposed on the insulating layer 172. Part of the second data line 160 is disposed on the semiconductor layer 172. Part of the second data line 160 and part of the second gate line 140 are respectively located on opposite sides of the semiconductor layer 174. In this embodiment, the potential difference between the second gate line 140 (gate G) and the second data line 160 (source S) of the capacitance compensation structure 170 can be changed (VGS=gate potential-source Potential) to determine whether the semiconductor layer 174 of the capacitance compensation structure 170 is a conductor or an insulator, thereby changing the size of the compensation capacitance of the capacitance compensation structure 170. Here, the material of the semiconductor layer 174 includes single crystal silicon, polycrystalline silicon, amorphous silicon, or other suitable semiconductor materials.

In detail, please refer to FIG. 1A again. In this embodiment, the planar profile 180 of the display device 100 has rounded corners 182 or concave holes 184. The non-display area 102a is located outside the concave hole 184 of the plane outline 180, and the non-display area 102b, 102c, 102d, 102e is located outside the rounded corner 182 of the plane outline 180.

In addition, in this embodiment, the first gate line 130, the second gate line 140, the first data line 150, and the second data line 160 are electrically connected to the pixel unit 120, respectively. Wherein, since the second gate line 140 extends into the non-display areas 102a, 102b, 102c, 102d, and 102e outside the rounded corner 182 or the concave hole 184, the pixels electrically connected to the second gate line 140 The number of cells 120 is smaller than the number of pixel cells 120 electrically connected to the first gate line 130.

Specifically, in this embodiment, the second gate line 140 and the second data line 160 may extend into the non-display areas 102a, 102b, 102c, 102d, and 102e, respectively, and in the non-display areas 102a, 102b, 102c , 102d, and 102e cross and overlap each other, thereby forming a plurality of cross-overlap regions R, as shown in FIG. 1B. Among them, the capacitance compensation structure 170 is located in the cross overlapping region R. In other words, in the plurality of overlapping regions R formed by the second gate line 140 and the second data line 160 crossing and overlapping each other, there is a capacitance compensation structure 170.

In short, the display device 100 of this embodiment has a plurality of capacitance compensation structures 170 arranged in the non-display areas 102a, 102b, 102c, 102d, 102e. The capacitance compensation structure 170 includes a portion of the second gate line 140, an insulating layer 172, a semiconductor layer 174, and a portion of the second data line 160. Among them, the insulating layer 172 is disposed on part of the second gate line 140, the semiconductor layer 174 is disposed on the insulating layer 172, part of the second data line 160 is disposed on the semiconductor layer 174, and part of the second data line 160 and Part of the second gate lines 140 are located on opposite sides of the semiconductor layer 174, respectively. With this design, the display device 100 of this embodiment can have a relatively uniform display brightness and can avoid the problem of discontinuity in the picture.

The following will list other embodiments as an explanation, and explain how to use a display device having a capacitance compensation structure to perform a compensation capacitor operation method. It must be noted here that the following embodiments follow the element numbers and partial contents of the foregoing embodiments, wherein the same reference numbers are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

2A is a schematic diagram of an operation method of a compensation capacitor according to an embodiment of the invention. Referring to FIG. 2A, the operation method of the compensation capacitor in this embodiment includes the display device 100a, the high-speed camera 200, the computer 210, and the lighting fixture 220. The computer 210 is electrically connected to the high-speed camera 200 and the lighting fixture 220. The high-speed camera 200 can capture the amount of flicker of each pixel unit 120 on the display device 100a, and transmit the result of the capture to the computer 210. The lighting fixture 220 can also be electrically connected to the driving element 190 on the display device 100a to drive the display device 100a.

In this embodiment, the display device 100a is the same as the display device 100 of FIG. 1A. Therefore, when the display device 100a is turned on, due to the amount of flicker of the pixel unit 120 on each second gate line 140 on the display device 100a It may be larger or smaller than the flicker amount of the pixel unit 120 on the first gate line 130, thus causing the display device 100a to have uneven display brightness and discontinuous picture. Therefore, in response to such a problem, the operation method of the compensation capacitor in this embodiment can be used to adjust the capacitance compensation structure 170 corresponding to each second gate line 140 as follows.

When the high-speed camera 200 detects that the amount of flicker of the pixel unit 120 on the second gate line 140 is greater than the amount of flicker of the pixel unit 120 on the first gate line 130, and the gate load of the second gate line 140 is Compared to when the gate load of the first gate line 130 is large, the potential of the second data line 160 in the capacitance compensation structure 170 can be increased by, for example, 2V before the potential of the second gate line 140 decreases. ~3V, for example, to change the potential of the second data line 160 from a negative potential to a positive potential to reduce the VGS of the capacitance compensation structure 170, reduce the compensation capacitance of the capacitance compensation structure 170, and reduce the total capacitance of the second gate line 140 . Specifically, since each second gate line 140 corresponds to a plurality of capacitance compensation structures 170 and a plurality of second data lines 160, each capacitance compensation structure 170 on each second gate line 140 can be targeted The potential of the second data line 160 in is adjusted to increase the number of positive potentials of the second data line 160 of the compensation capacitor, so that the compensation capacitance of the adjusted capacitance compensation structure 170 is reduced and the second gate line 140 The total capacitance of is reduced, which in turn reduces the flicker amount of the pixel unit 120 on the adjusted second gate line 140, as shown in FIG. 2B.

Conversely, when the high-speed camera 200 detects that the amount of flicker of the pixel unit 120 on the second gate line 140 is greater than the amount of flicker of the pixel unit 120 on the first gate line 130, and the gate of the second gate line 140 The pole load is smaller than the gate load of the first gate line 130. Before the potential of the second gate line 140 decreases, the capacitance of the second data line 160 in the capacitance compensation structure 170 can be reduced to increase the capacitance The VGS of the compensation structure 170, the compensation capacitance of the capacitance compensation structure 170 is increased, and the total capacitance of the second gate line 140 is increased. In other words, the number of the second data lines 160 of the compensation capacitor at a positive potential can be reduced, so that the compensation capacitance of the adjusted capacitance compensation structure 170 increases and the total capacitance of the second gate line 140 increases, thereby making the adjusted The amount of flicker of the pixel unit 120 on the second gate line 140 is reduced, as shown in FIG. 2C.

Then, after obtaining the adjustment conditions of the potential of the second data line 160 corresponding to each capacitance compensation structure 170 of each second gate line 140, these adjustment conditions can be burned into the driving element 190, so that The display device 100a adjusted by the operation method of the compensation capacitor of this embodiment can have a relatively uniform display brightness and can avoid the problem of discontinuous pictures.

FIG. 3A illustrates an operation method of a compensation capacitor according to another embodiment of the invention. Please refer to FIG. 3A. In the compensation capacitor operation method of this embodiment, the display device 100b may include a plurality of second gate lines G1~G8, and the second gate lines G1~G8 are sequentially arranged in the display device 100b . Next, multiple transistors T1, T3, T5, T7 are arranged in parallel, so that the second gate lines G1, G3, G5, G7 are electrically connected to the corresponding gates of each transistor T1, T3, T5, T7, respectively , And one end of the transistors T1, T3, T5, T7 is connected to the low potential 310, and the other end (output end) of the transistors T1, T3, T5, T7 is connected to the wave detection element 320 and another transistor T (A). At this time, one end of the transistor T(A) is connected to the high potential 330 and Vgs of the transistor T(A)=0.

Similar to the above method, multiple transistors T2, T4, T6, and T8 are arranged in parallel, so that the second gate lines G2, G4, G6, and G8 are electrically connected to the corresponding transistors T2, T4, T6, and T8, respectively. And connect one end of the transistors T2, T4, T6, T8 to the low potential 310a, and the other end (output end) of the transistors T2, T4, T6, T8 to the wave detection element 320a and the other Transistor T(B). At this time, one end of the transistor T(B) is connected to the high potential 330a and Vgs of the transistor T(B)=0.

Therefore, the signal of each second gate line G1~G8 can generate an amplified signal through the other end (output end) of the transistors T1~T8 electrically connected thereto, and then the wave detection element 320, 320a to show its wave pattern, as shown in Figure 3B.

Please refer to FIG. 3B, the solid line in the figure is the ideal potential change (can be regarded as the potential change of the first gate line), and the dotted line is the actual potential change of the second gate line G1, G3, G5. As can be seen from FIG. 3B, since the fall time of the potential of the second gate lines G1 and G3 is slower than the fall time of the ideal potential (the potential of the first gate line 130), it can be Before the two gate lines G1 and G3 are turned off, by increasing the potential of the second data line 160 in the capacitance compensation structure 170 (or increasing the number of the second data line 160 of the compensation capacitor to a positive potential and reducing the number of the compensation capacitor The two data lines 160 are the number of negative potentials) to reduce the compensation capacitance of the capacitance compensation structure 170 and the total capacitance of the second gate lines G1 and G3.

In addition, since the fall time of the potential of the second gate line G5 is faster than the fall time of the ideal potential (the potential of the first gate line 130), the second gate G5 can be framed in the next frame Before closing, by reducing the potential of the second data line 160 in the capacitance compensation structure 170 (or reducing the number of the second data line 160 of the compensation capacitor to a positive potential and the second data line 160 increasing the compensation capacitor to a negative potential To increase the compensation capacitance of the capacitance compensation structure 170 and the total capacitance of the second gate line G5.

In summary, in the display device and the operation method of the compensation capacitor of this embodiment, since the display device has multiple capacitance compensation structures in the non-display area, and the capacitance compensation structure includes a portion of the second gate line and the insulating layer , Semiconductor layer and part of the second data line. Therefore, when the gate load of the second gate line is larger (or smaller) than the gate load of the first gate line, the potential of the second data line in the structure can be compensated for by increasing (or decreasing) To reduce (or increase) the compensation capacitance and the total capacitance of the second gate line. When the potential drop time of the second gate line is slower (or faster) than the potential drop time of the first gate line, the potential of the second data line in the structure can be compensated by increasing (or decreasing) to Reduce (or increase) the compensation capacitance and the total capacitance of the second gate line. With this design, the display device of this embodiment can have a more uniform display brightness and can avoid the problem of discontinuity of the picture, and the operation method of the compensation capacitor of this embodiment can be used to improve the problem of uneven display brightness and the discontinuity of the picture .

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100, 100a, 100b ‧‧‧ display device 101‧‧‧ display area 102a, 102b, 102c, 102d, 102e ‧‧‧ non-display area 110‧‧‧ substrate 120‧‧‧ pixel unit 130‧‧‧ first gate Polar line 140, G1, G2, G3, G4, G5, G6, G7, G8 ‧‧‧ second gate line 150‧‧‧ first data line 160‧‧‧ second data line 170‧‧‧ capacitance compensation structure 172‧‧‧Insulation layer 174‧‧‧Semiconductor layer 180‧‧‧ Plane profile 182‧‧‧Fillet 184‧‧‧Concave hole 190‧‧‧Drive element 200‧‧‧High speed camera 210‧‧‧‧Computer 220‧‧ ‧Lighting fixture 310, 310a ‧‧‧ Low potential 320, 320a ‧‧‧ Wave type detection element 330, 330a ‧‧‧ High potential A‧‧‧Region G‧‧‧Gate R‧‧‧ Crossover area S‧‧‧Source T1, T2, T3, T4, T5, T6, T7, T8, T(A), T(B)‧‧‧‧Transistor

FIG. 1A is a schematic top view of a display device according to an embodiment of the invention. FIG. 1B is an enlarged view of the area A in FIG. 1A. FIG. 1C is an enlarged view of the crossover region R in FIG. 1B. FIG. 1D is a schematic cross-sectional view taken along line I-I' in FIG. 1C. 2A is a schematic diagram of an operation method of a compensation capacitor according to an embodiment of the invention. 2B and 2C illustrate the application of the operation method of the compensation capacitor of FIG. 2A. 3A is a schematic diagram of an operation method of a compensation capacitor according to another embodiment of the invention. FIG. 3B illustrates the application of the operation method of the compensation capacitor of FIG. 3A.

140‧‧‧Second gate line

160‧‧‧Second data line

170‧‧‧capacity compensation structure

172‧‧‧Insulation

174‧‧‧semiconductor layer

G‧‧‧Gate

S‧‧‧Source

Claims (7)

A display device has a display area and a plurality of non-display areas. The display device includes: a substrate; a plurality of pixel units, arranged in a matrix on the substrate and located in the display area; a plurality of first gate lines and a plurality of A plurality of second gate lines arranged in a row on the substrate and located in the display area; a plurality of first data lines and a plurality of second data lines arranged in a row on the substrate and located in the display area; a plurality Capacitance compensation structure, the matrix is arranged in the non-display areas, each of the capacitance compensation structure includes: part of the second gate line; an insulating layer arranged on part of the second gate line; a semiconductor layer, arranged On the insulating layer; and part of the second data line is disposed on the semiconductor layer, wherein part of the second data line and part of the second gate line are respectively located on opposite sides of the semiconductor layer. The display device as described in item 1 of the patent application range, wherein a flat outline of the display device has a rounded corner or a concave hole, and the non-display areas are located outside the rounded corner or the concave hole of the flat outline. The display device according to item 1 of the patent application scope, wherein the first gate lines, the second gate lines, the first data lines, and the second data lines are electrically connected to the respective ones For pixel units, the number of the pixel units electrically connected by the second gate lines is smaller than the number of the pixel units electrically connected by the first gate lines. The display device as described in item 1 of the patent application scope, wherein the second gate lines and the second data lines extend into the non-display areas and overlap each other, and have a plurality of overlapping overlapping areas. The display device as described in item 4 of the patent application scope, wherein the capacitance compensation structures are located in the overlapping areas. The display device as described in item 1 of the patent application range, wherein the semiconductor layer comprises single crystal silicon, polycrystalline silicon or amorphous silicon. An operation method of a compensation capacitor, using the display device as described in item 1 of the patent application scope, and the operation method includes: when the gate loads of the second gate lines are compared to those of the first gate lines When the gate load is large, by increasing a potential of the second data lines in the capacitance compensation structures, the compensation capacitance and the total capacitance of the second gate lines are reduced; when the second gate lines The gate load of is smaller than the gate load of the first gate lines, and by reducing the potential of the second data lines in the capacitance compensation structures, the compensation capacitance and the second gates are increased The total capacitance of the pole lines; when the potential drop times of the second gate lines are slower than the potential drop times of the first gate lines, the second data in the capacitance compensation structure is added by increasing the capacitance The potential of the line to reduce the compensation capacitance and the total capacitance of the second gate lines; when the potential decline time of the second gate lines is faster than that of the first gate lines, By reducing the potential of the second data lines in the capacitance compensation structures, the compensation capacitance and the total capacitance of the second gate lines are increased.

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