TW202009698A - Method and computer program product and apparatus for adjusting operating frequencies - Google Patents

Abstract

A method for adjusting operating frequencies, performed by a processing unit of a device side, includes: collecting an interface-activity parameter; selecting one from multiple frequencies according to the interface-activity parameter; and driving a clock generator to output a clock signal at the selected frequency, thereby enabling a host access interface and/or a flash access interface to operate at a corresponding operating frequency.

Description

Operation frequency adjustment method and computer program product and device

The invention relates to a flash memory device, in particular to an operating frequency adjustment method and a computer program product and device.

Flash memory devices are generally divided into NOR flash memory devices and NAND flash memory devices. The NOR flash memory device is a random access device. The host can provide any address for accessing the NOR flash memory device on the address pin, and timely access the data pin of the NOR flash memory device. Get the data stored at that address. In contrast, NAND flash memory devices are not random access, but sequential access. The NAND flash memory device cannot access any random address like the NOR flash memory device. Instead, the host needs to write the value of the sequence of bytes (Bytes) to the NAND flash memory device to define the request The type of command (eg, read, write, erase, etc.) and the address used on this command. The address can point to a page (the smallest block of data written to the flash memory device) or a block (the smallest block of data erased from the flash memory device).

Power saving is usually an important issue for flash memory devices. Traditionally, the host can control the flash memory device to work in different sleep modes (Sleep Mode) when saving data without using the flash memory device to save power consumption. The flash memory device selectively turns on or off all or part of the circuit according to different sleep modes to achieve the purpose of saving power. However, such control does not apply to the Active Mode when transferring data between the host and the flash memory device. Therefore, the present invention provides an operating frequency adjustment method and a computer program product and device, which can be applied in an active mode to achieve a better power saving effect.

In view of this, how to mitigate or eliminate the above-mentioned deficiencies in related fields is really a problem to be solved.

The present invention provides an operating frequency adjustment method, a computer program product, and a device. The method is implemented by a processing unit on the device side when loading and executing firmware or software code, including: collecting interface activity parameters; Select one of the frequencies; and drive the clock generator to output the clock signal of the selected frequency, so that the host access interface and/or the flash memory access interface operate at the corresponding operating frequency.

The present invention also provides a computer program product for operating frequency adjustment, which includes the following program code: collecting interface activity parameters; selecting one from a plurality of frequencies according to the interface activity parameters; and driving a clock generator to output a clock of the selected frequency The signal enables the host access interface and/or flash memory access interface to operate at the corresponding operating frequency.

The invention provides an operating frequency adjustment device, including: a clock generator and a processing unit. The processing unit collects the interface activity parameters; selects one of a plurality of frequencies according to the interface activity parameters; and drives the clock generator to output the clock signal of the selected frequency, so that the host access interface and/or the flash memory access interface operate in corresponding Operating frequency.

The interface activity parameters include data transmission information of the host access interface and/or flash memory access interface.

One of the advantages of the above embodiments is that the device side can actively activate the control mechanism to save power consumption in the active mode (Active Mode) without having to passively wait for the command from the host side.

Another advantage of the above embodiment is that the device side can adjust the time generated by the clock generator to be provided to the processing unit and/or the access interface according to the data transmission status between the device side and the host side or between the device side and the storage unit Pulse signal for finer power consumption control.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

The following description is a preferred implementation of the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. The actual content of the invention must refer to the scope of the following claims.

It must be understood that the words "comprising", "including", etc. used in this specification are used to indicate the existence of specific technical features, values, method steps, work processes, components and/or components, but do not exclude the addition of More technical features, values, method steps, job processing, components, components, or any combination of the above.

The terms such as "first", "second", and "third" are used in the claims to modify the elements in the claims, not to indicate that there is a priority order, pre-relationship, or is an element Prior to another component, or the time sequence when performing method steps, is only used to distinguish components with the same name.

It must be understood that when an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, and intermediate elements may appear. Conversely, when an element is described as "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements can also be interpreted in a similar manner, such as "between" relative to "directly between", or "adjacent" relative to "directly adjacent" and so on.

Refer to Figure 1. The flash memory system architecture 100 includes a host 110, a device 130, and a storage unit 150. This system architecture can be implemented in personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, digital cameras and other electronic products. The device end 130 may include a processing unit 133. The host 110 and the device 130 can communicate with each other via a flash memory communication protocol (for example, Universal Flash Storage UFS). The flash memory controller 133 is electrically connected (coupled) to the host terminal 110 through the data connection layer 132 and the physical layer 131. The flash memory controller 133 can read the user data obtained from the storage unit 150 from the data buffer (not shown in FIG. 1) through the direct memory access controller (not shown in FIG. 1), and connect through the drive data The layer 132 and the physical layer 131 are sequentially knocked out to the host 110. The flash memory controller 133 can store the user data to be written by the host 110 to the data buffer through a direct memory access controller (not shown in FIG. 1). The processing unit 134 can be implemented in various ways, for example, using general-purpose hardware, such as a single processor, a multi-processor with parallel processing capability, a graphics processor, a light-weight general-purpose processor (Lightweight General-Purpose Processor), or other tools A computing power processor, and when executing instructions, macrocode, or microcode, it provides the functions described later. The flash memory controller 133 may be a UFS controller, and communicates with the host 110 through the UFS communication protocol. Although the embodiment of the present invention uses the UFS communication protocol as an example, the present invention can also be applied to other communication protocols, such as Universal Serial Bus (USB), advanced technology attachment (ATA), and serial advanced technology. Attachment (serial advanced technology attachment, SATA), peripheral component interconnect express (PCI-E) or other interface communication protocol.

The device end 130 further includes a flash memory access interface 139, so that the processing unit 134 can communicate with the storage unit 150 through the flash memory access interface 139. In detail, a double data rate (Double Data Rate DDR) communication protocol can be used, for example, open NAND flash (Open NAND Flash Interface ONFI), double data rate switch (DDR Toggle) or other interface. The processing unit 134 writes user data to the specified address (destination address) in the storage unit 150 through the flash memory access interface 139, and reads the user data from the specified address (source address) in the storage unit 150. The flash memory access interface 139 uses several electronic signals to coordinate the transfer of data and commands between the processing unit 134 and the storage unit 150, including data lines, clock signals, and control signals. The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transfer chip enable (Chip Enable CE), address extraction enable (Address Latch Enable ALE), command extraction enable ( Command Latch Enable CLE), Write Enable WE and other control signals.

The storage unit 150 may include a plurality of storage subunits. Each storage subunit uses its associated access subinterface to communicate with the processing unit 134. One or more storage subunits can be packaged in a die. The flash memory access interface 139 may include j access sub-interfaces, and each access sub-interface is connected to i storage sub-units. The access sub-interface and subsequent storage sub-units can be collectively referred to as I/O channels, and can be identified by Logic Unit Number (LUN). In other words, the i storage subunits share an access subinterface. For example, when the device side 130 includes 4 I/Os and each input/output is connected to 4 storage subunits, the device side 130 can access 16 storage subunits. The processing unit 134 can drive one of the access sub-interfaces to read from or write data to the designated storage sub-unit. Each storage subunit has an independent chip enable (CE) control signal. In other words, when reading or writing data to a specified storage subunit, the associated access subinterface needs to be driven to enable the chip enable control signal of the storage subunit. Refer to Figure 2. The processing unit 134 can select one of the connected storage subunits 150_0_0 to 150_0_i using the independent chip enable control signals 230_0_0 to 230_0_i through the access sub-interface 139_0, and then, from the selected storage through the shared data line 210 Read the data at the specified address of the subunit, or send the user data to be written to the specified address to the selected storage subunit.

Refer to Figure 1. The device end 130 further includes a clock generator (Clock Generator) 136_1. The clock generator 136_1 is a circuit that generates a clock signal CLK1, and outputs the clock signal CLK1 to the processing unit 134 for synchronizing the extraction, decoding, execution, and writing back of firmware commands, macrocodes, or microcodes. In some embodiments, when the host 110 expects not to access the storage unit 150 for a long time, it may send a command to the device 130 to allow the device 130 to enter the power saving mode. For example, the host 110 may send a primitive DME_HIBERNATE_ENTER to enter the sleep mode (Sleep Mode) to the device 130. When the flash memory controller 133 receives the primitive DME_HIBERNATE_ENTER, it can turn off the clock generator 136_1 to save power consumption. Alternatively, the host 110 may send a Start Stop Unit (Start Stop Unit SSU) command to the device 130 to force the device 130 to enter a sleep state (Sleep State). When the flash memory controller 133 receives the start-stop unit command to enter the sleep state, it blocks the clock signal CLK1 generated by the clock generator 136_1, so that the clock signal CLK1 cannot be provided to the processing unit 134. The data format and sending details of the primitives DME_HIBERNATE_ENTER and start-stop unit commands can be referred to version 2.1 of the general flash memory storage standard published in June 2016. When the processing unit 134 is not driven by the clock signal CLK1, it cannot run, so that power consumption can be saved. It should be noted here that when the processing unit 134 is not driven by the clock signal CLK1, it cannot execute any firmware or software commands, macro code or micro code. However, in the active mode, the host 110 does not have any control mechanism that allows the device 130 to save power consumption.

To solve this defect, an embodiment of the present invention proposes a power saving mechanism in the operation mode, which is actively controlled by the device terminal 130, and can respond to the data transmission status between the device terminal 130 and the host terminal 110 or between the device terminal 130 and the storage unit 150 , Adjust the clock signal generated by the clock generator to be provided to the processing unit and/or the access interface. For example, when only a lower transmission rate is required between the two devices, the clock generator can be used to generate a lower frequency clock signal to save power consumption.

Refer to Figure 1. The device end 130 further includes a clock generator 136_2. The clock generator 136_2 is a circuit that generates a clock signal CLK2, and outputs the clock signal CLK2 to a general flash memory storage interconnect layer 170 (UFS InterConnect Layer—UIC, which includes a physical layer 131, a data connection layer 132, and flash memory The controller 133) and the flash memory access interface 139 are used to synchronize data transmission and reception operations. The general flash memory storage interconnect layer 170 may be referred to as a host access interface. The clock generators 136_1 and 136_2 adjust the frequencies of the output clock signals CLK1 and CLK2 according to the settings of the registers 138_1 and 138_2, respectively.

In order to provide better power saving effect, the device end 130 can preset multiple frequencies for the processing unit 134 and the flash memory access interface 139 respectively. For example, the frequency of the clock signal CLK1 output to the processing unit 134 may be 500, 250, 125 MHz, etc., and the clock signal output to the access interface (including the general flash memory storage interconnect layer 170 and the flash memory access interface 139) The frequency of CLK2 can be 300, 150, 75MHz, etc. Refer to Figure 3. The method shown in FIG. 3 may be implemented by the processing unit 134 when loading and executing specific firmware or software instructions, macro code or micro code. The processing unit 134 first collects interface activity parameters, including general flash memory storage interconnect layer 170 and/or data transfer related information of the flash memory access interface 139 (step S310). For example, the interface activity parameter may indicate whether the device terminal 130 enters an idle state, whether the flash memory access interface 139 is used for background operations, and the data transmission mode of the general flash memory storage interconnect layer 170. The processing unit 134 selects one of the above-mentioned frequencies for the processing unit 134 and the access interface according to the interface activity parameters (step S330), and drives the clock generator 136_1 to output the clock signal CLK1 to the processing unit 134 at the selected frequency And drive the clock generator 136_2 to output the clock signal CLK2 to the access interface at the selected frequency, so that the processing unit 134, the general flash memory storage interconnect layer 170 and the flash memory access interface 139 can run at the specified operating frequency (step S350) . In some embodiments of step S350, the processing unit 134 may only adjust the frequency of the clock signal CLK2 output by the clock generator 136_2, and fix the frequency of the clock signal CLK1 output by the pulse generator 136_1 at a higher level .

Refer to Figure 4. The method shown in FIG. 4 can be implemented by the processing unit 134 when loading and executing specific firmware or software instructions, macro code or micro code. The processing unit 134 can periodically perform a loop (steps S410 to S460), and collect interface activity parameters in each round, and determine the clock signals CLK1 and CLK2 output by the clock generators 136_1 and 136_2 according to the interface activity parameters Frequency, and drives the clock generators 136_1 and 136_2 to output the clock signals CLK1 and CLK2 at the determined frequency.

The device end 130 further includes a timer 135. The processing unit 134 may set the timer 135 to restart counting for a specified period of time, such as 2, 3, or 5 milliseconds ms, at the beginning or at the end of each round. Whenever the timer 135 counts to the specified time, an interrupt is issued to the processing unit 134 so that the processing unit 134 can start a new round of operation frequency adjustment (step S410).

當處理單元134決定裝置端130需要運行在高速時，可驅動時脈產生器136_1以400~600MHz間的一個頻率輸出時脈訊號CLK1並且驅動時脈產生器136_2以250~350MHz間的一個頻率輸出時脈訊號CLK2。當決定裝置端130需要運行在中速時，可驅動時脈產生器136_1以200~300MHz間的一個頻率輸出時脈訊號CLK1並且驅動時脈產生器136_2以125~175MHz間的一個頻率輸出時脈訊號CLK2。當決定裝置端130需要運行在低速時，可驅動時脈產生器136_1以100~150MHz間的一個頻率輸出時脈訊號CLK1並且驅動時脈產生器136_2以62.5~87.5MHz間的一個頻率輸出時脈訊號CLK2。裝置端130的製造商可於出廠前可將時脈訊號CLK1及CLK2的三個水平的預設頻率儲存至非揮發記憶體(未顯示於圖1)，使得處理單元134可於執行操作頻率調整方法時使用。In some embodiments, the frequencies of the clock signals CLK1 and CLK2 can be adjusted to one of three levels according to the collected interface activity parameters. The frequency range of the example is shown in Table 1: Table 1

When the processing unit 134 determines that the device 130 needs to run at high speed, it can drive the clock generator 136_1 to output the clock signal CLK1 at a frequency between 400 and 600 MHz and drive the clock generator 136_2 to output at a frequency between 250 and 350 MHz. Clock signal CLK2. When it is determined that the device 130 needs to operate at a medium speed, the clock generator 136_1 can be driven to output the clock signal CLK1 at a frequency between 200 and 300 MHz and the clock generator 136_2 can output the clock at a frequency between 125 and 175 MHz. Signal CLK2. When it is determined that the device terminal 130 needs to run at a low speed, the clock generator 136_1 can be driven to output the clock signal CLK1 at a frequency between 100 and 150 MHz and the clock generator 136_2 can output the clock at a frequency between 62.5 and 87.5 MHz. Signal CLK2. The manufacturer of the device end 130 can store the preset frequencies of the three levels of the clock signals CLK1 and CLK2 in the non-volatile memory (not shown in FIG. 1) before leaving the factory, so that the processing unit 134 can perform the operation frequency adjustment Method.

When the processing unit 134 detects an interrupt issued by the timer 135 (step S410), it can first determine whether the device 130 needs to perform a background operation (step S420). The register 137_2 can 1-bit latch information on whether the device terminal 130 needs to perform a background operation, for example, “1” means needed; “0” means not needed. The processing unit 134 can read the value of the register 137_2 to determine whether the device 130 needs to perform a background operation. The background operation is not initiated by the host 110, but the data access initiated by the device 130, which can be garbage collection GC process, wear leveling process, and read recycling process ( read reclaim process) or read reflash process.

For example, after multiple accesses, a physical page may contain valid and invalid segments (also known as expired segments), where valid segments store valid user data and invalid segments store invalid (old ) User data. When detecting that the available space of the storage unit 150 is insufficient, the processing unit 134 may set a register (may be referred to as a background-operation register) 137_2, indicating that the device 130 needs to perform a background operation (such as a garbage collection procedure). In the garbage collection process, the processing unit 134 drives the flash memory access interface 139 and rewrites the collected valid user data to empty physical pages of idle blocks or active blocks, so that these data containing invalid user data The block can be changed to an idle block, and after erasing, it can be provided to other users for data storage.

For another example, due to a certain number of erasures (for example, 500 times, 1000 times, or 5000 times), the physical block in the storage unit 150 is classified as a bad block due to poor data retention (Data Retention) capability. No longer use. In order to extend the service life of physical blocks, the processing unit 134 continuously monitors the number of erasures of each physical block. When the number of erasing of a data block exceeds the erasing threshold, the processing unit 134 may set the register 137_2 to indicate that the device 130 needs to perform background operations (such as loss averaging procedures). In the wear-leveling process, the processing unit 133 drives the flash memory access interface 139 to read the user data in this data block (source block). Next, the processing unit 133 selects an idle block with the least number of erasures as the destination block, and drives the flash memory access interface 139 to write the previously read user data to the available physical page in the selected destination block.

In addition, when the start condition of the read recovery program or the read update program is satisfied, the processing unit 134 can also set the register 137_2 to indicate that the device terminal 130 needs to perform a background operation (such as the read recovery program or the read update program).

Since the background operation needs to execute a series of commands to read data from the storage unit 150 and write data to the storage unit 150, the faster the processing unit 134, the flash memory access interface 139, and the storage unit 150 operate, the better. When it is determined that the device terminal 130 needs to perform the background operation (the path of "YES" in step S420), the clock generator 136_1 is driven to output the clock signal CLK1 to the processing unit 134 at the highest frequency selectable and the clock generator 136_2 is driven to The highest selectable frequency output clock signal CLK2 is provided to the general flash memory storage interconnect layer 170 and the flash memory access interface 139, so that the processing unit 134, the general flash memory storage interconnect layer 170 and the flash memory access interface 139 can operate at the highest Operating frequency (step S430). For example, the processing unit 134 may set the register 138_1 to a value that conforms to the third level of CLK1 (that is, between 400 and 600 MHz) as shown in Table 1, so that the clock generator 136_1 outputs the clock signal CLK1 at a corresponding frequency according to the set value To the processing unit 134; and the setting register 138_2 becomes a value that conforms to the third level of CLK2 (that is, between 250 and 350 MHz) as shown in Table 1, so that the clock generator 136_2 outputs the clock signal CLK2 at a corresponding frequency according to the setting value to general Flash memory storage interconnect layer 170 and flash memory access interface 139. It should be noted here that during the background operation, the access commands issued by the host 110 can also be interleaved.

In the case where no background operation is required, the processing unit 134 can allow the processing unit 134, the flash memory access interface 139, and the storage unit 150 to operate at a matching operating frequency according to the data transmission mode between the device side 130 and the host side 110. When it is determined that the device terminal 130 does not need to perform a background operation (the path of "No" in step S420), the processing unit 134 obtains the running state of the device terminal 130 and the data transmission mode between the device terminal 130 and the host terminal 110 (step S440).

高速檔HS-G1的A級速率為1248Mbps，而高速檔HS-G1的B級速率為1248Mbps，高速檔HS-G2的A級速率為2496Mbps，而高速檔HS-G2的B級速率為2915.2Mbps，依此類推。表3列舉UFS規範所定義不同脈波寬度調變檔(PWMS-GEARs)的資料速率： 表3

低速檔PWM-G0的資料速率介於0.01至3Mbps之間，低速檔PWM-G1的資料速率介於3至9Mbps之間，低速檔PWM-G2的資料速率介於6至18Mbps之間，依此類推。The UFS interface can be operated in pulse-width modulation gear (PWM, Pulse-Width Modulation gear) or high-speed gear (HS, High-Speed gear). The pulse width modulation file can be 0.5Gbps (Gigabits per second) or lower speed, and the high speed file can be 1.4Gbps or higher. The pulse width modulation gear may be referred to as a low gear. For example, Table 2 lists the data rates of different high-speed files (HS-GEARs) defined by the UFS specification: Table 2

High-speed HS-G1 has a Class A rate of 1248Mbps, while high-speed HS-G1 has a Class B rate of 1248Mbps, high-speed HS-G2 has a Class A rate of 2496Mbps, and high-speed HS-G2 has a Class B rate of 2915.2Mbps ,So on and so forth. Table 3 lists the data rates of different pulse width modulation files (PWMS-GEARs) defined by the UFS specification: Table 3

The data rate of low-speed PWM-G0 is between 0.01 and 3Mbps, the data rate of low-speed PWM-G1 is between 3 and 9Mbps, and the data rate of low-speed PWM-G2 is between 6 and 18Mbps, and so on analogy.

當模式改變命令指示裝置端130運行於脈波寬度調變的第0檔，快閃記憶控制器133分別設定模式寄存器及檔位寄存器為”0b00”及”0b000”。當模式改變命令指示裝置端130運行於自動脈波寬度調變的第0檔，快閃記憶控制器133分別設定模式寄存器及檔位寄存器為”0b01”及”0b000”。脈波寬度調變或自動脈波寬度調變的其餘檔位設定可依此類推，不再贅述以求簡潔。當模式改變命令指示裝置端130運行於高速的第1檔，快閃記憶控制器133分別設定模式寄存器及檔位寄存器為”0b10”及”0b001”。當模式改變命令指示裝置端130運行於自動高速的第1檔，快閃記憶控制器133分別設定模式寄存器及檔位寄存器為”0b11”及”0b001”。 高速或自動高速的其餘檔位設定可依此類推，不再贅述以求簡潔。The device side 130 may be configured with a register 137_1 to store the data transmission mode between the device side 130 and the host side 110. Register 137_1 can latch the value of at least 5 bits, of which 2 bits (also known as mode register) represent the transmission mode (transmission mode), and the other 3 bits (also known as gear register) represent the file Bit. For example, the mode register stores "0b00", "0b01", "0b10" and "0b11" respectively representing the UFS interface running in pulse width modulation, PWM-auto gear, high-speed gear and Automatic high-speed gear (HS-auto gear). The register stores one of "0b000" to "0b111" which represents the corresponding one of the 0th to 7th gear respectively. The host 110 can send a mode change command to the device 130 to configure the data transmission mode between the device 130 and the host 110. When the flash memory controller 133 receives the mode change command, the mode register and the gear register are set according to the instruction of the mode change command. Table 4 describes the setting examples of the mode register and gear register for different data transmission modes: Table 4

When the mode change command instructs the device terminal 130 to operate at the 0th gear of the pulse width modulation, the flash memory controller 133 sets the mode register and the gear register to "0b00" and "0b000", respectively. When the mode change command instructs the device terminal 130 to operate at the 0th gear from the arterial wave width modulation, the flash memory controller 133 sets the mode register and gear register to "0b01" and "0b000", respectively. Pulse wave width modulation or other gear settings from arterial wave width modulation can be deduced by analogy, and will not be repeated for simplicity. When the mode change command instructs the device terminal 130 to run at the first gear of high speed, the flash memory controller 133 sets the mode register and the gear register to "0b10" and "0b001", respectively. When the mode change command instructs the device terminal 130 to run in the first high-speed automatic gear, the flash memory controller 133 sets the mode register and the gear register to "0b11" and "0b001", respectively. The rest of the gear settings for high-speed or automatic high-speed can be deduced by analogy.

When the device terminal 130 is running in a self-arterial wave width modulation gear position or an automatic high-speed gear, and there is no data transmission with the host terminal 110 for a preset period of time, the device terminal 130 will automatically enter an idle state (idle state) , To close some circuits and save power consumption. The device terminal 130 may further be provided with a register (not shown in FIG. 1), coupled to the processing unit 134, for latching information on whether the device terminal 130 enters an idle state.

After the processing unit 134 obtains the operating state of the device 130 and the data transmission mode between the device 130 and the host 110 (step S440), it selects one of the multiple frequencies accordingly (step S450). Refer to Table 1 for the division of frequency levels. The processing unit 134 can determine the frequency of the processing unit 134, the flash memory access interface 139, and the storage unit 150 according to the content of the register 137_1: (1) When the device 130 enters the idle state, regardless of the data transmission mode, select A level of frequency; (2) When the device 130 does not enter the idle state and the data transmission mode is pulse width modulation or self-arterial wave width modulation, regardless of the gear position, select a frequency that meets the first level; (3) When the device 130 does not enter the idle state and the data transmission mode is high-speed or automatic high-speed level 1, select the frequency that meets the second level; and (4) When the device 130 does not enter the idle state and the data transmission mode is high-speed or automatic For high-speed 2nd or 3rd gear, select a frequency that meets the third level.

After the processing unit 134 selects one of the multiple frequencies according to the data transmission mode (step S450), the clock generator 136_1 is driven to output the clock signal CLK1 to the processing unit 134 at the selected frequency and the clock generator 136_2 is driven to select the frequency The clock signal CLK2 is output to the general flash memory storage interconnect layer 170 and the flash memory access interface 139, so that the processing unit 134, the general flash memory storage interconnect layer 170 and the flash memory access interface 139 can run at a specified operating frequency (step S460 ). For example, when the data transmission mode is high-speed or automatic high-speed first gear, the processing unit 134 may set the register 138_1 to a value that complies with the second level of CLK1 (that is, between 200 and 300 MHz) as shown in Table 1, so that the clock The generator 136_1 outputs the clock signal CLK1 to the processing unit 134 at a corresponding frequency according to the set value; and the set register 138_2 becomes a value that complies with the second level of CLK2 (that is, between 125 and 175 MHz) as shown in Table 1, so that the clock generator 136_2 The clock signal CLK2 is output to the general flash memory storage interconnect layer 170 and the flash memory access interface 139 at a corresponding frequency according to the set value. In some embodiments of step S460, the processing unit 134 may only adjust the frequency of the clock signal CLK2 output by the clock generator 136_2, and keep the frequency of the clock signal CLK1 output by the pulse generator 136_1 at a specific level.

The interface activity parameters described in step S310 in FIG. 3 may include all or part of the values in the registers 137_1 and 137_2.

The device end 130 of the flash memory system architecture 100 shown in FIG. 1 can be further modified to allow the processing unit 134 to control only one clock generator, allowing the processor 134 and the access interface (including the general flash memory storage interconnection layer) 170 and flash memory access interface 139) operate at different operating frequencies. Refer to Figure 5. The modified device end 530 may be provided with a frequency divider 535 coupled between the clock generator 136_1, the general flash memory storage interconnection layer 170 and the flash memory access interface 139 for inputting a frequency from the clock generator 136_1 The clock signal CLK1 generates the clock signal CLK2 of 1/2, 3/5 or 2/3 frequency, and outputs the clock signal CLK2 to the general flash memory storage interconnection layer 170 and the flash memory access interface 139. In response to the modified device terminal 530, step S430 shown in FIG. 4 can be modified as follows: the processing unit 134 sets the register 138_1 to a value that conforms to the third level of CLK1 (that is, between 400 and 600 MHz) as shown in Table 1, and drives the clock The generator 136_1 outputs the clock signal CLK1 to the processing unit 134 and the frequency divider 535 at the corresponding frequency according to the set value, so that the frequency divider 535 generates and outputs the clock signal CLK2 of 2/5, 1/2 or 2/3 frequency to Universal flash memory storage interconnect layer 170 and flash memory access interface 139. In addition, as shown in FIG. 4, step S460 can be modified to drive the clock generator 136_1 to select the frequency to output the clock signal CLK1 to the processing unit 134 and the frequency divider 535, so that the frequency divider 535 generates and outputs 1/2, 3 The clock signal CLK2 of /5 or 2/3 selects the frequency to the general flash memory storage interconnection layer 170 and the flash memory access interface 139.

It should be noted that when the processing unit 134 further includes a circuit for adjusting the clock signal CLK1, the frequency of the clock signal CLK1 is not necessarily equal to the operating frequency when the processing unit 134 is running. When the host access interface 170 or the flash access interface 139 further includes a circuit for adjusting the clock signal CLK2, the output frequency of the clock signal CLK2 is not necessarily equal to the operation of the host access interface 170 or the flash access interface 139 during operation frequency. However, those skilled in the art can understand that the faster output frequency of the clock signal CLK1 will cause the operating frequency of the processing unit 134 to run faster, and vice versa. The faster output frequency of the clock signal CLK2 will cause the operating frequency of the host access interface 170 and the flash memory access interface 139 to run faster, and vice versa.

Several use cases are proposed below to explain how to apply the above-mentioned operating frequency adjustment device and method.

In the first use case, it is assumed that the device side 130 does not perform background operations: At the beginning, the host side 110 sends a mode change command to the device side 130, instructing the device side 130 to run at a specific speed of automatic high speed. When the flash memory controller 133 receives the mode change command, it sets the register 137_1 to latch the information of the data transmission mode. At this time, the device end 130 enters an active state. Next, the processing unit 134 reads the register 137_1 (step S440), and drives the clock generator 136_1 according to the data transmission mode to output the clock signal CLK1 to the processing unit 134 at a corresponding frequency (for example, a frequency corresponding to the second or third level of CLK1). And drive the clock generator 136_2 to output the clock signal CLK2 to the access interface at a corresponding frequency (for example, a frequency corresponding to the second or third level of CLK2), so that the processing unit 134, the general flash memory storage interconnection layer 170 and the flash memory access The interface 139 can operate at a desired operating frequency (steps S450 to S460). Then, there is no data transmission with the host 110 for a preset period of time, and the device 130 automatically enters the idle state. The processing unit 134 detects that it has entered the idle state (step S440), drives the clock generator 136_1 to output the clock signal CLK1 to the processing unit 134 at a frequency corresponding to the first level of CLK1 and drives the clock generator 136_2 to meet the first level of CLK2 The frequency signal CLK2 is output to the access interface so that the processing unit 134, the general flash memory storage interconnect layer 170 and the flash memory access interface 139 can operate at a slower operating frequency, thereby saving power consumption (steps S450 to S460) .

In the second use case, it is assumed that the device 130 does not perform background operations: At the beginning, the host 110 sends a mode change command to the device 130, instructing the device 130 to run at a specific gear of high speed or automatic high speed. When the flash memory controller 133 receives the mode change command, it sets the register 137_1 to latch the information of the data transmission mode. Next, the processing unit 134 reads the register 137_1 (step S440), drives the clock generator 136_1 according to the data transmission mode to output the clock signal CLK1 to the processing unit 134 at a corresponding frequency (for example, a frequency corresponding to the second or third level of CLK1) and The driving clock generator 136_2 outputs the clock signal CLK2 to the access interface at a corresponding frequency (for example, a frequency corresponding to the second or third level of CLK2), so that the processing unit 134, the general flash memory storage interconnection layer 170, and the flash memory access interface 139 may operate at a desired operating frequency (steps S450 to S460). Then, the host terminal 110 sends a mode change command to the device terminal 130, instructing the device terminal 130 to operate in a specific gear of pulse wave width modulation or self-arterial wave width modulation (that is, the changed data transmission mode). When the flash memory controller 133 receives the mode change command, it sets the register 137_1 to latch the information of the changed data transmission mode. Next, the processing unit 134 reads the register 137_1 (step S440), drives the clock generator 136_1 according to the changed data transmission mode, and outputs the clock signal CLK1 to the processing unit 134 at a frequency corresponding to the first level of CLK1 and drives the clock generator 136_2 The clock signal CLK2 is output to the access interface at a frequency that meets the first level of CLK2, so that the processing unit 134, the general flash memory storage interconnect layer 170, and the flash memory access interface 139 can operate at a slower operating frequency, thereby saving power consumption (Steps S450 to S460).

In the third use case, it is assumed that the device side 130 does not perform background operations: At the beginning, the host side 110 sends a mode change command to the device side 130, instructing the device side 130 to run at the second or third speed of high speed or automatic high speed. When the flash memory controller 133 receives the mode change command, it sets the register 137_1 to latch the information of the data transmission mode. Next, the processing unit 134 reads the register 137_1 (step S440), drives the clock generator 136_1 according to the data transmission mode to output the clock signal CLK1 to the processing unit 134 at a frequency corresponding to the third level of CLK1, and drives the clock generator 136_2 to comply with The third level frequency of CLK2 outputs the clock signal CLK2 to the access interface, so that the processing unit 134, the general flash memory storage interconnect layer 170 and the flash memory access interface 139 can operate at a desired operating frequency (steps S450 to S460). Then, the host terminal 110 sends a mode change command to the device terminal 130, instructing the device terminal 130 to operate at the first speed of the high-speed or automatic high-speed (that is, the changed data transmission mode). When the flash memory controller 133 receives the mode change command, it sets the register 137_1 to latch the information of the changed data transmission mode. Next, the processing unit 134 reads the register 137_1 (step S440), drives the clock generator 136_1 according to the changed data transmission mode, and outputs the clock signal CLK1 to the processing unit 134 at a frequency corresponding to the second level of CLK1 and drives the clock generator 136_2 The clock signal CLK2 is output to the access interface at a frequency that conforms to the second level of CLK2, so that the processing unit 134, the general flash memory storage interconnect layer 170, and the flash memory access interface 139 can operate at a slower operating frequency, thereby saving power consumption (Steps S450 to S460).

The method steps of the operation frequency adjustment performed by the processing unit 134 can be implemented by a computer program product composed of one or more functional modules. These functional modules are stored in the non-volatile storage device, and can be loaded and executed by the processing unit 134 at a specific time point. Refer to Figure 6. The processing unit 133 executes an interrupt handler module (Interrupt Handler Module) 610 to complete part of the operation in step S310 and the operation in step S410, executes the background operation detection module 620 to complete the operation in step S420, and executes device-side operation status and data transmission mode detection The measuring module 630 completes part of the operations in step S310 and the operation in step S440, executes the frequency selection module 640 to complete the operations in steps S330 and S450, and executes the clock generator driving module 650 to complete the steps S350, S430 and S460 operating. The background operation detection module 620 can call one of the device running state and the data transmission mode detection module 630 and the clock generator driving module 650 according to the detection result. The background operation detection module 620 and the frequency selection module 640 can use parameters to transmit the selected frequency to the clock generator driving module 650.

All or part of the steps in the method of the present invention can be implemented by a computer program, such as a computer operating system, a specific hardware driver in the computer, or a software application program. In addition, it can also be implemented in other types of programs as shown above. Those of ordinary skill in the art can write the method of the embodiments of the present invention into a computer program, which will not be described for simplicity. A computer program implemented according to the method of the embodiment of the present invention. It can be stored in a suitable computer-readable data carrier, such as a DVD, CD-ROM, USB disk, or hard disk, or placed on a network (for example, the Internet Network server.

Although the above-described elements are included in FIGS. 1 and 5, it is not excluded that more other additional elements are used without violating the spirit of the invention, and a better technical effect has been achieved. In addition, although the flowcharts of FIGS. 3 and 4 are executed in a specified order, without violating the spirit of the invention, those skilled in the art can modify the order between these steps on the premise of achieving the same effect. The invention is not limited to using only the order described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers obvious modifications and similar settings for those skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest way to include all obvious modifications and similar settings.

100‧‧‧Flash memory system

110‧‧‧Host

130‧‧‧device side

131‧‧‧ physical layer

132‧‧‧Data link layer

133‧‧‧Flash memory controller

134‧‧‧ processing unit

135‧‧‧Timer

136_1, 136_2‧‧‧ clock generator

137_1, 137_2, 138_1, 138_2

139‧‧‧Flash access interface

150‧‧‧storage unit

170‧‧‧General flash memory storage interconnection layer

CLK1, CLK2 ‧‧‧ clock signal

139_0‧‧‧Accessor interface

150_0_0～150_0_i‧‧‧storage subunit

210‧‧‧Data cable

230_0～230_i‧‧‧Chip enable control signal

S310～S350‧‧‧Method steps

S410～S460‧‧‧Method steps

500‧‧‧Flash memory system

530‧‧‧device side

535‧‧‧ frequency divider

610～650‧‧‧Program module

FIG. 1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the invention.

FIG. 2 is a schematic diagram of connection between an access sub-interface and multiple storage sub-units.

FIG. 3 is a flowchart of a method for adjusting an operating frequency according to an embodiment of the invention.

4 is a flowchart of a method for periodically adjusting the clock signal output by the clock generator according to an embodiment of the invention.

FIG. 5 is a schematic diagram of a system architecture of a flash memory according to another embodiment of the invention.

6 is a schematic diagram of a functional module for adjusting the operating frequency according to an embodiment of the invention.

S310~S350‧‧‧Method steps

Claims (20)

A computer program product for loading and execution by a processing unit on a device side, including the following code: collecting an interface activity parameter, wherein the interface activity parameter includes a host access interface and/or a flash memory access interface Data transmission information; select one from a plurality of first frequencies according to the interface activity parameters; and drive a first clock generator to output a first clock signal of the selected first frequency, so that the host stores The fetch interface and/or the flash memory access interface operate at a first operating frequency. The computer program product according to claim 1, including the following program code: selecting one from a plurality of second frequencies according to the interface activity parameters; and driving a second clock generator to output the selected second frequency A second clock signal causes the processing unit to run at a second operating frequency. The computer program product of claim 1, wherein the first clock signal of the selected first frequency is output to the processing unit so that the processing unit operates at a second operating frequency: the selected first The first clock signal of the frequency is output to a frequency divider; and the frequency divider outputs a second clock signal of the second frequency to the host access interface and/or the flash memory access interface. The computer program product according to claim 1, wherein the interface activity parameter indicates that the device needs to perform a background operation, and the selected first frequency is the largest of the first frequencies. The computer program product according to claim 4, wherein the background operation is not initiated by an instruction from the host, but is a data access initiated by the device. The computer program product according to claim 1, wherein the interface activity parameter indicates that the device does not need to perform background operations and the device enters an idle state; and the selected first frequency is the smallest of the first frequencies By. The computer program product according to claim 1, wherein the interface activity parameter indicates that the device does not need to perform background operations, the device does not enter an idle state, and the data transmission mode of a host and the device is pulse wave Width modulation or self-arterial wave width modulation; and the selected first frequency is the smallest of the first frequencies. The computer program product according to claim 1, wherein the interface activity parameter indicates that the device does not need to perform background operations, the device does not enter an idle state, and the data transmission mode of a host and the device is high-speed or Automatic high-speed 2nd or 3rd gear; and the selected first frequency is the largest of the first frequencies. The computer program product according to claim 1, wherein the interface activity parameter indicates that the device does not need to perform background operations, the device does not enter an idle state, and the data transmission mode of a host and the device is high-speed or Automatic high-speed 1st gear; and the selected first frequency is lower than the largest of the first frequencies. An operation frequency adjustment method, executed by a processing unit on a device side, includes: collecting an interface activity parameter, wherein the interface activity parameter includes data transmission information of a host access interface and/or a flash memory access interface; according to the interface The active parameter selects one from a plurality of first frequencies; and drives a first clock generator to output a first clock signal of the selected first frequency, so that the host accesses the interface and/or the flash memory The interface is run at a first operating frequency. An operating frequency adjustment device includes: a first clock generator; and a processing unit, coupled to the first clock generator, to collect an interface activity parameter, wherein the interface activity parameter includes a host access interface and/or Or data transfer information of a flash memory access interface; selecting one of a plurality of first frequencies according to the interface activity parameters; and driving the first clock generator to output a first clock of the selected first frequency The signal enables the host access interface and/or the flash memory access interface to operate at a first operating frequency. The operation frequency adjusting device according to claim 11, comprising: a second clock generator coupled to the processing unit, wherein the processing unit selects one of a plurality of second frequencies according to the interface activity parameter; driving A second clock generator outputs a second clock signal of the selected second frequency, so that the processing unit operates at a second operating frequency. The operation frequency adjusting device according to claim 11, comprising: a frequency divider coupled to the first clock generator, wherein the first clock signal of the selected first frequency is output to the processing unit So that the processing unit operates at a second operating frequency: the first clock signal of the selected first frequency is output to the frequency divider; and the frequency divider outputs a second clock of a second frequency The signal provides the host access interface and/or the flash memory access interface. The operation frequency adjusting device according to claim 13, wherein the second frequency is 1/2, 3/5, or 2/3 of the first frequency. The operation frequency adjusting device according to claim 11, wherein the interface activity parameter indicates that the device needs to perform a background operation, and the selected first frequency is the largest of the first frequencies, and is between 250~ Between 350MHz. The operation frequency adjusting device according to claim 15, wherein the background operation is a garbage collection procedure, a wear-average procedure, a read recycling procedure or a read update procedure. The operation frequency adjusting device according to claim 11, wherein the interface activity parameter indicates that the device does not need to perform background operations and the device enters an idle state; and the selected first frequency is the first frequency The smallest, and between 62.5 ~ 87.5MHz. The operation frequency adjusting device according to claim 11, wherein the interface activity parameter indicates that the device does not need to perform background operations, the device does not enter an idle state, and the data transmission mode of a host and the device is pulse Wave width modulation or self-arterial wave width modulation; and the selected first frequency is the smallest of the first frequencies. The operation frequency adjusting device according to claim 11, wherein the interface activity parameter indicates that the device does not need to perform background operations, the device does not enter an idle state, and the data transmission mode of a host and the device is high speed Or the 2nd or 3rd gear of automatic high speed; and the selected first frequency is the largest of the first frequency, and is between 250~350MHz. The operation frequency adjusting device according to claim 11, wherein the interface activity parameter indicates that the device does not need to perform background operations, the device does not enter an idle state, and the data transmission mode of a host and the device is high speed Or automatic high-speed 1st gear; and the selected first frequency is lower than the largest of the first frequency and is between 125~175MHz.

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