TW202008375A - Semiconductor device - Google Patents

Abstract

The present invention utilizes a new method to provide a semiconductor device having a function of generating inherent data. The NAND flash memory of the present invention has the memory cell array, a page buffer/sensing circuit, and a differential sense amplifier that detects the potential difference of a bit line pair of a dummy array when the dummy array of the memory cell array is read out, wherein the NAND type flash memory outputs the inherent data of the semiconductor device according to the detection result of the differential sense amplifier.

Description

Semiconductor device

The present invention relates to a semiconductor device having a function of generating inherent information, and particularly relates to the generation of inherent information using a NAND flash memory.

As the security of electronic devices or electronic devices is strengthened, in order to prevent counterfeiting or counterfeiting of semiconductor devices physically mounted on the above devices, corresponding solutions are required. In a certain method, when the inherent information is given to the semiconductor device and the inherent information is verified, the semiconductor device can be regarded as a genuine product and allowed to be used. The inherent information can be stored in the non-volatile memory of the semiconductor device, for example, but this method may analyze the semiconductor device so that the inherent information is read, or improperly access the semiconductor device from the outside so that the inherent information is read. .

In recent years, PUF (Physical Unclonable Function), which cannot be copied physically, has received considerable attention. PUF is a technology that uses unpredictable, highly concealed and persistent physical information as inherent data. For example, there are proposals for PUF using an arbiter circuit, PUF using a ring oscillator, and PUF using SRAM. In addition, NAND flash memory has disclosed PUF (patent document 1) using erasure verification, PUF (patent document 2) using a voltage adjustment unit, and the like.

Prior Art Literature Patent Literature 1: US Patent Publication No. 2015/0007337A1 Patent Literature 2: US Patent Publication No. 2015/0055417A1

In the design/manufacture of semiconductor devices, by suppressing unevenness (variation) of circuit elements, wiring, etc., or minimizing unevenness, a reproducible and highly reliable semiconductor device is provided. On the other hand, minimizing the non-uniformity of circuit elements and wiring will bring uniformity to the circuit elements or wiring, which may reduce the randomness (unpredictability) of PUF or inherent data. Therefore, it would be desirable to have a PUF technology that can maintain the reproducibility and reliability while ensuring the randomness of inherent data.

The object of the present invention is to provide a semiconductor device with a function of generating inherent data through a new method.

The semiconductor device of the present invention includes: a memory array including a NAND type serial; a selection member to select a specific field of the memory array; a reading member to read out a specific field selected by the selection member; a detection member, Detecting a potential difference of a bit line pair in a specific area read by the reading means; and generating means for generating unique data of the semiconductor device based on the detection result of the detecting means.

According to the present invention, the potential difference of a bit line pair in a specific field read out from the memory cell array, and unique data is output based on the detection result. Therefore, the unique data can be maintained while maintaining the reproducibility or reliability of the semiconductor device. Randomness.

Next, an embodiment of the present invention will be described with reference to the drawings. The semiconductor device of the present invention has a function of generating inherent data inherent in the semiconductor device and outputting it to the outside. In one embodiment, the semiconductor device of the present invention includes a NAND-type flash memory, and uses the NAND-type flash memory to generate inherent data and output it to the outside. The semiconductor device of the present invention may be a NAND flash memory itself, or may be a semiconductor circuit having other functions. [Example]

FIG. 1 shows the structure of a NAND flash memory according to an embodiment of the invention. The flash memory 100 of this embodiment includes: a memory cell array 110 formed by a plurality of memory cells arranged in rows and columns; an I/O buffer 120 connected to an external I/O terminal I/O and holding I/O data; bits The address register 130 receives the address data from the I/O buffer 120; the controller 140 supplies the control units according to the command data from the I/O 120 and external control signals (CLE, ALE, etc.); The line selection circuit 150 performs block selection and page selection based on the column address information Ax from the address register 130; the paging buffer/sensor 160 maintains the data read from the selected page and Keep the data to be programmed into the selected page; the row selection circuit 170 selects the data in the paging buffer/sensing circuit 160 according to the row address information Ay from the address register 130; internal voltage generation The circuit 180 generates voltages (write voltage Vpgm, pass voltage Vpass, erase voltage Vers, read voltage Vread, etc.) required for reading, programming, erasing, etc. of data.

The memory cell array 110 has m memory blocks BLK(0), BLK(1), ..., BLK(m-1) in the row direction, and one memory block is formed with a plurality of NAND strings as shown in FIG. 2. A NAND string includes a plurality of memory cells MCi (i=0, 1, ..., 62, 63) connected in series, a bit line selection transistor TR1 connected to the drain side of the memory cell MC63, and connected to the memory cell MC0 The source line on the source side of the select transistor TR2. The control gate of the memory cell MCi is connected to the corresponding word line WLi, the gate of the selection transistor TR1 on the bit line side is connected to the selection gate line SGD, and the gate of the selection transistor TR2 on the source line side is connected to the selection gate Line SGS. In each operation state, the word line selection circuit 150 selectively drives the selection gate transistors TR1 and TR2 through the selection gate signals SGD and SGS according to the column address Ax.

The NAND string may be in the form of a two-dimensional array formed on the surface of the substrate, or may be in the form of a three-dimensional array using a semiconductor layer formed on the surface of the substrate. Furthermore, a memory cell can be in the form of SLC storing one bit (binary data) or in the form of MLC storing multiple bits.

Each NAND string of each block is connected to the general bit lines GBL0, GBL1, ... GBLn through the bit line selection transistor TR1, and the general bit lines GBL0, GBL1, ... GBLn are connected to the paging buffer/sensing circuit 160. Each general-purpose bit line is composed of, for example, metal wiring, and extends from the block (0) of the memory cell array 110 toward the block (m-1).

Next, the paging buffer 160 will be described. As shown in FIG. 3, the paging buffer 160 includes a bit line selection circuit 200 for selecting even-numbered general-purpose bit lines or odd-numbered general-purpose bit lines. FIG. 3 shows a pair of general bit lines including an even bit line GBL_e connected to one NAND string NU and an odd bit line GBL_o connected to one NAND string NU. The bit line selection circuit 200 selects the even bit line GBL_e or odd bit line GBL_o during reading or programming, and electrically connects the selected even bit line GBL_e or odd bit line GBL_o to the paging buffer Sensor circuit (sensor node SNS) of the sensor/sensor circuit 160. That is, although the page buffer/sensing circuit 160 corresponds to the amount of one page, one page buffer/sensing circuit 160 is shared by a pair of even bit lines GBL_e and odd bit lines GBL_o.

The bit line selection circuit 200 includes: a bit line selection transistor BLS, which is electrically connected to the sensing node SNS during reading; an even number selection transistor SEL_e, connected in series to the node N1 of the bit line selection transistor BLS and the even number bit Between element lines GBL_e; odd-numbered transistor SEL_o, connected in series between node N1 of bit-line selected transistor BLS and odd-numbered bit line GBL_o; even-biased selected transistor YSEL_e, connected between even-numbered bit line GBL_e and imaginary Between the potential VPRE; and the odd bias selection transistor YSEL_o, connected between the odd bit line GBL_o and the virtual potential VPRE.

Bit line selection transistor BLS, even selection transistor SEL_e, odd selection transistor SEL_o, even bias selection transistor YSEL_e, odd bias selection transistor YSEL_o are composed of NMOS transistors, each gate will be applied from the connection The control signal of the device 140. In addition, the virtual potential VPRE is supplied by the internal voltage generation circuit 180 with various bias voltages or precharge voltages according to the operating state due to the control of the controller 140.

For example, in the read operation, even-numbered transistor SEL_e, bit-line selected transistor BLS are turned on, odd-numbered transistor SEL_o is not turned on, even-numbered bit line GBL_e is selected, odd-numbered bit Line GBL_o is not selected. In addition, the even-bias selection transistor YSEL_e is non-conducting, the odd-bias selection transistor YSEL_o is conducting, and the odd-numbered bit line GBL_o that is not selected is supplied from the supply virtual potential VPRE to GND. On the other hand, when reading odd pages, odd selection transistor SEL_o and bit line selection transistor BLS are turned on, even selection transistor SEL_e is non-conductive, odd bit line GBL_o is selected, and even bit line GBL_e is not select. In addition, the odd-bias selection transistor YSEL_o is turned off, the even-bias selection transistor YSEL_e is turned on, and the even-numbered bit line GBL_e that is not selected is supplied from the supply virtual potential VPRE to GND. In this way, bit line mask readout of even pages and odd pages is performed.

In addition, when programming, the even-numbered pages and the odd-numbered pages are alternately programmed, and the unselected pages are supplied with voltages for suppressing the programming interference by the virtual potential VPRE.

FIG. 4 is an example of a page buffer/sensing circuit 160. The configuration of the paging buffer/sensing circuit 160 includes: a transistor BLPRE to precharge the voltage supplied by the voltage supply part V1 to the bit line; a transistor BLCLAMP to clamp the bit line; a sensing node SNS; a transistor The BLCD transmits the charge between the sensing node SNS and the latch node N2; the latch circuit is connected to the latch node N2. The transistor BLCLAMP is connected to the bit line selection transistor BLS of the bit line selection circuit 200 of the bit line selection circuit 200.

During the read operation, the precharge voltage supplied from the voltage supply unit V1 is applied to the even bit line GBL_e or the odd bit line GBL_o selected by the bit line selection circuit 200 through the transistors BLPRE and BLCLAMP. After that, the read voltage is applied to the selected word line, and the read pass voltage is applied to the unselected word line. When the memory cell of the selected word line is turned on, the precharge voltage of the general bit line is discharged to the source line SL, the sensing node SNS becomes the GND level. When the memory cell is turned off, the general-purpose bit line is isolated from the source line SL, and the sensing node SNS is maintained at the precharge voltage. The charge of the sensing node SNS is transferred to the node N2 through the transistor BLCD, and the latch circuit LAT maintains the H or L level by the potential of the node N2.

FIG. 5 shows an example of the inherent data generating circuit of this embodiment. The inherent data generating circuit 300 is connected to the page buffer/sensing circuit 160, and when a specific area of the memory cell array 110 is read out, the potential difference of the sensing node connected to the adjacent pair of general bit lines is detected , Use this test result to generate inherent data and output it.

Specifically, the inherent data generating circuit 300 includes a differential sense amplifier 310_0 connected to adjacent page buffers PB_0, PB_1, a differential sense amplifier 310_1 connected to adjacent page buffers PB_2, PB_3, ..., connected to adjacent The differential sense amplifier 310_n-1/2 of the paging buffers PB_n-1 and PB_n (differential amplifier 310 when collectively called a differential amplifier). If the number of page buffer/sense circuits 160 is one page, the number of differential sense amplifiers 310 is 1/2 page.

The differential sense amplifier 310_0 detects the potential difference between the sensing node SNS_0 of the paging buffer PB_0 and the sensing node SNS_1 of the paging buffer PB_1 adjacent thereto, and outputs data Dout_0 indicating the detection result. Similarly, the other differential sense amplifier 310 detects the potential difference of the sensing node of the adjacent page buffer, and outputs data Dout_1,..., Dout_n-1/2 indicating the detection result. When the even bit lines are selected by the bit line selection circuit 200, the differential sense amplifier 310 detects the potential difference of the sensing node connected to the adjacent even bit lines, and when the odd bit lines are bit lines When the selection circuit 200 selects, the differential sense amplifier 310 detects the potential difference of the sensing node connected to the adjacent odd bit line. The differential sense amplifier 310 is activated by the controller 140 when the inherent data is generated.

FIG. 6 is a table showing an example of the bias voltage applied during each operation of the flash memory. During the read operation, a certain positive voltage is applied to the bit line, a certain read voltage (eg 0V) is applied to the selected word line, and a read pass voltage Vpass (eg 4.5V) is applied to the unselected word line, Apply a positive voltage (for example, 4.5V) to the selection gate lines SGD and SGS, turn on the bit line selection transistor and the source line selection transistor of the NAND string, and apply 0V to the common source line. During the programming (writing) operation, a high-voltage programming voltage Vpgm (15 to 20V) is applied to the selected word line, and an intermediate potential (for example, 10V) is applied to the unselected word line. The line-side selection transistor is turned on, the source line-side selection transistor is turned off, and the potential of the data corresponding to "0" or "1" is supplied to the bit line. During the erasing operation, 0V is applied to the selected word line in the block, and a high voltage (for example, 20V) is applied to the P well to extract the electrons of the floating gate to the substrate, thereby erasing the data in block units. The bias when generating unique data will be described later.

Next, the operation of generating the unique data of the NAND flash memory of this embodiment will be described. Fig. 7 is a flowchart for explaining the operation of generating inherent data. The controller 140 is composed of, for example, a microcomputer or a state machine capable of executing software programs. The controller 140 can control the generation of inherent data in addition to the control of the general reading operation, programming operation, and erasing operation according to external control signals or external commands.

In a certain implementation form, the controller 140 has a function of determining whether to generate the inherent data (S100). For example, when the controller 140 receives an instruction from the outside instructing the generation of the unique data, the controller 140 executes the generation of the unique data. Alternatively, the controller 140 executes the generation of inherent data when executing the power-on procedure when the power is loaded, or when performing a predetermined action.

When the controller 140 determines that the inherent data is to be generated, the controller 140 starts the virtual array readout of the memory cell array 110 through the word line selection circuit 150 (S110). The virtual array is a specific field on the memory cell array suitable for generating inherent data. The address information used to preselect the virtual array will be removed from the memory of the controller 140 and so on. In a certain embodiment, as shown in FIG. 8, the virtual array is set in the block BLK(m−1) at the farthest distance from the page buffer/sensing circuit 160 or a block near it. In other words, the virtual array DA is the area where the wiring length of the general-purpose bit line connecting the block and the page buffer/sensing circuit 160 is the longest. In addition, the virtual array DA may be an area that cannot be accessed by a user, or may be an area that uses a memory that the user can access.

The farthest block BLK (m-1) has a longer wiring length than the other blocks, so the uneven wiring (such as line width, film thickness, spacing, etc.) will greatly affect the wiring RC value (time constant). Therefore, the characteristics of charge and discharge tend to vary greatly between adjacent bit lines.

The readout of the virtual array DA is the same as the general readout, the even bit lines or odd bit lines selected by the bit line selection circuit 200 are precharged, and the odd bit lines or even bits that are not selected The element wire is supplied to GND. After precharging, the word line selection circuit 150 applies a pass voltage Vpuf that has nothing to do with the memory state of the memory cell and the memory cell is turned on to all word lines of the block selected as the most virtual array DA. In other words, the pass voltage Vpuf, as shown in Figure 9, is a much higher voltage than the threshold when the erase memory cell (data "1") and the programmed memory cell (data "0") are turned on. In addition, the pass voltage Vpuf may be the same level as the pass voltage applied to the unselected word line during the read operation (see FIG. 6 ).

The virtual array DA is applied with the pass voltage Vpuf, so all the memory cells of the virtual array DA are turned on, and the precharge voltage of the general bit line, that is, the voltage of the sensing node sns is discharged to the GND level through the NAND string Source line SL. Simultaneously with this sensing, with the differential sense amplifier 300 connected to the sensing node SNS, the potential difference of the adjacent bit line pair is detected (S120). For example, when SNSk>SNSk+1, the differential sense amplifier 300 outputs “0” as Dout_k; when SNSk≦SNSk+1, the differential sense amplifier 300 outputs “1” as Dout_k.

The controller 140 detects the potential difference of the bit line pair by reading the virtual array DA, and then outputs inherent data to the outside according to the detection result (S130). When generating inherent data, the readout of the virtual array DA may be either an even bit line or an odd bit line, or both the even bit line and the odd bit line. The output method of the unique data is arbitrary, and for example, all the detected data may be output, or the bit line or the data of the number of bits determined in advance by the row selection circuit 170 may be output. In addition, the number of bits of the unique data to be output may be adjusted according to the input and output terminals of the NAND flash memory. In addition, when the NAND flash memory is equipped with the SPI (Serial Peripheral Interface) function. It can output inherent data in synchronization with external sequence clock.

According to the present embodiment, the potential difference of the bit line pair is detected during the reading of the virtual array, and the inherent data of the semiconductor device is generated. Therefore, it is possible to obtain the non-predictive inherent data with high reproducibility by a relatively simple structure.

Next, other embodiments of the present invention will be described. FIG. 10 shows the structure of the inherent data generating circuit 300A of other embodiments. In this embodiment, the intrinsic data generating circuit 300A is provided with output data Dout_0, Dout_1, ..., Dout_n-1/2 that will receive the output of complex differential sense amplifiers 310_0, 310_1, ..., 300_n-1/2, and use these data as The calculation circuit 320 of the calculation process. The calculation circuit 320 may, for example, mask a part of the output data of the differential sense amplifier 310, or encode (compress) the output data, or logically calculate the output data of the even bits and the output data of the odd bits, Output the result as inherent data Dout_x.

In the above embodiment, when generating the unique data, all word lines of the virtual array DA are applied with voltage to read out, but only a specific page of the virtual array DA may be read out. A specific page can set any page of WL0 to WL63. The selected word line of a specific page is applied with the same read voltage (for example, 0V) as the normal read, except for the unselected word lines The pass voltage Vpuf (eg 4.5V) will be applied. In this case, the memory cell of the specific page needs to be set as the erase memory cell storing the data "1". With this, it is possible to perform reading for generating unique data under the same bias conditions as in a general reading operation.

In the above embodiment, the differential sense amplifier 310 detects the potential difference between adjacent bit lines during reading, but this is only an example, and may be other forms. For example, the differential sense amplifier 310 may also detect the potential difference between the even-numbered paging buffer/sensing circuits and the odd-numbered paging buffer/sense circuits. In addition, the potential difference of each sensing node of the selected page buffer/sensing circuit may be detected according to a predetermined rule.

Furthermore, in the above embodiment, although the page buffer/sensing circuit 160 corresponds to one page and the differential sense amplifier 310 corresponds to 1/2 page, the number of differential sense amplifiers 310 is arbitrary. As long as the unpredictability (randomness) as inherent data can be obtained, it may be a number less than 1/2 page.

In the above embodiment, the example of the masked readout of the even-numbered bitline or the odd-numbered bitline selected by the bitline selection circuit is shown, but the masked readout is not necessary in the present invention. In this case, the readout of the selected page is performed on all bit lines, and the differential sense amplifier can detect the potential difference between the physically adjacent even bit lines and odd bit lines.

In addition, in the above embodiment, the memory cell is used as a unit connected to the word line of the virtual array DA. However, in the present invention, a general MOS transistor can be used instead of the memory cell. That is to say, part or all of the memory cells constituting the NAND string of the virtual array DA can be replaced with general MOS transistors. Here, the general MOS transistor refers to a MOS transistor whose threshold value does not change when it is turned on due to programming or erasing. Representative MOS transistors are descriptive, enhanced, or internal. Using any type of MOS transistor to replace the memory cell can also be used to generate inherent data readout.

Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to a specific embodiment, and various modifications and changes can be made within the scope of the gist of the invention described in the patent application.

100‧‧‧Flash memory BLK‧‧‧Memory block 110‧‧‧Memory cell array BLS‧‧‧Bit line selection transistor 120‧‧‧I/O buffer BLCD‧‧‧Transistor 130‧‧‧ Address register BLCLAMP‧‧‧Transistor 140‧‧‧Controller BLPRE‧‧‧Transistor 150‧‧‧Character line selection circuit Dout_i‧‧‧Inherent data 160‧‧‧Paging buffer/sensing circuit GBL_e ‧‧‧Even-numbered bit line 170‧‧‧Line selection circuit GBL_o‧‧‧Odd-numbered bit line 180‧‧‧‧Internal voltage generation circuit MCi‧‧‧Memory cell 200‧‧‧Bit line selection circuit SEL_e‧‧‧Even number Select transistor 300‧‧‧Intrinsic data generation circuit SEL_o‧‧‧Odd select transistor 310‧‧‧Differential sense amplifier LAT‧‧‧Latch circuit 320‧‧‧Calculation circuit NU‧‧‧NAND series PB_i‧‧ ‧Paging buffer TR1‧‧‧Bit line selection transistor SGD on the drain side‧‧‧‧Select gate line TR2‧‧‧Bit line selection transistor on the source side SGS‧‧‧Select gate line WLi‧ ‧‧Character line SNS‧‧‧sensing node YSEL_e‧‧‧even bias selection transistor SL‧‧‧ source line YSEL_o‧‧‧ odd bias selection transistor VPRE‧‧‧imaginary potential

FIG. 1 shows the structure of a NAND flash memory according to an embodiment of the present invention. FIG. 2 shows the structure of the NAND string of the memory cell array according to the embodiment of the invention. FIG. 3 shows an example of the bit line selection circuit of the embodiment of the present invention. FIG. 4 shows an example of a page buffer/sensing circuit according to an embodiment of the invention. Fig. 5 shows an example of the inherent data generating circuit of the embodiment of the present invention. Fig. 6 is a table showing the bias voltage applied when the NAND flash memory operates. FIG. 7 is a flowchart illustrating the operation of generating unique data according to the embodiment of the present invention. FIG. 8 illustrates an example of selecting a virtual array according to an embodiment of the present invention. FIG. 9 illustrates an example of the word line voltage applied to the virtual array. Fig. 10 illustrates a modification of the present invention.

100‧‧‧Flash memory

110‧‧‧Memory Cell Array

160‧‧‧Page buffer/sensing circuit

300‧‧‧Intrinsic data generating circuit

DA‧‧‧Virtual Array

Dout_i‧‧‧ inherent data

PB_i‧‧‧Paging buffer

SGD‧‧‧Select gate line

SGS‧‧‧Select gate line

WLi‧‧‧character line

Claims (12)

A semiconductor device, including: a memory array including a NAND-type serial; a selection member to select a specific field of the memory array; a reading member to read a specific field selected by the selection member; a detection member to detect A potential difference of a bit line pair in a specific area read by the reading means; and a generating means, which generates unique data of the semiconductor device based on the detection result of the detecting means. The semiconductor device as described in item 1 of the patent application range, wherein the specific field is a block physically farthest from the readout member. The semiconductor device as described in item 1 of the patent application scope, wherein the specific field is a page included in a block physically farthest from the readout member. The semiconductor device as described in item 1 of the patent application scope, wherein the specific field is an area that cannot be accessed by the user. The semiconductor device as described in item 1 of the patent application scope, in which the specific field is a MOS transistor connected to a NAND type tandem. The semiconductor device as described in item 2 or 3 of the patent application range, wherein the selection member applies a voltage irrelevant to the memory state of the memory cell and turns on the voltage of the memory cell to all character lines in the selected block. The semiconductor device according to any one of claims 1 to 5, wherein the detection member is electrically connected to the sensing node of the reading member, and the detection member includes a means for detecting the sensing node Differential sense amplifier with potential difference. The semiconductor device as described in any one of claims 1 to 5, wherein the bit line pair is the adjacent bit line during the read operation. The semiconductor device according to any one of items 1 to 5 of the patent application range, wherein when the readout means reads an even bit line or an odd bit line, the bit line pair is an adjacent even bit line Or odd bit lines. The semiconductor device as described in any one of claims 1 to 5, wherein the bit line pair is a bit line selected according to a predetermined rule. The semiconductor device according to any one of claims 1 to 5, wherein the generating means includes a calculation circuit for calculating data indicating the detection result of the detection means, and the generating means calculates the calculation circuit The result is output as inherent data. The semiconductor device as described in any one of the items 1 to 5 of the patent application scope further includes: a control component to control the generation of inherent data; wherein the control component controls the selection component during the boot process or in response to an external request, The reading member, the detecting member, and the generating member generate the inherent data.

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