TW202008368A - Memory device and programming method thereof - Google Patents

Abstract

Provided is a programming method for a memory device including a memory array and a controller. The programming method includes: controlling programming on a first page of a first word line of a memory array of the memory device by the controller; controlling programming on a first page of a second word line of the memory array by the controller, the second word line being adjacent to the first word line; controlling for performing a first programming operation on a second page of the first word line of the memory array by the controller; controlling programming on a first page of a third word line of the memory array by the controller, the third word line being adjacent to the second word line; controlling for performing the first programming operation on a second page of the second word line of the memory array by the controller; and controlling for performing a second programming operation on the second page of the first word line of the memory array by the controller.

Description

Memory device and its programming method

The invention relates to a memory device and its programming method.

Recently, applications of non-volatile semiconductor memory devices (such as flash memory) have become more and more widespread. Flash memory can retain data without power supply, so there is a high market demand. In order to increase the storage density of flash memory, multi-level storage cell (MLC) memory has been developed. A single MLC memory cell can store multiple bits of data.

For MLC, each physical page can store two or more logical pages. Taking an MLC memory that can store two bits in a single cell as an example, the logical page can be divided into a high page and a low page, where the page written first is called the high page , And the page that is written later is called the low page.

Figure 1 shows the current programming method according to the prior art. The curve 110 represents the critical voltage distribution of the physical page before programming. In this case, all the memory cells on the physical page are in an unprogrammed state. After that, a programming voltage is applied to the high page of the physical page, so that the memory cells have critical voltage distributions 120 and 130, wherein the high page with a logic 1 state has a critical voltage distribution 120, and the high page with a logic 0 state The page has a threshold voltage distribution 130. Afterwards, a programming voltage is applied to the lower page of the physical page, so that the memory cells with logic state 11 have a critical voltage distribution 140, and the memory cells with logic state 10 have a critical voltage distribution 150 with logic The memory cells in state 00 have a critical voltage distribution 160, and the memory cells in logic state 01 have a critical voltage distribution 170.

Incremental step pulse programming (Incremental Step Pulse Programming, ISPP) is currently a commonly used programming method. In ISPP, the programming voltage supplied to the memory cell is gradually increased until the programming voltage reaches a level sufficient to program the memory cell to a desired state. After providing the programming voltage to the memory cell, a verification voltage is applied to the memory cell to verify whether the memory cell has been successfully programmed. When the threshold voltage of the memory cell is higher than the verification voltage, the memory cell has been successfully programmed, otherwise, the programming voltage is increased until the threshold voltage of the memory cell is higher than the verification voltage.

Figure 2 shows the programming sequence of the ISPP of the conventional technology. As shown in Figure 2, P1-P5 respectively represent 5 different programming voltages, where P1=Vpgm, P2=Vpgm+∆Vt, P3=Vpgm+2∆Vt, P4=Vpgm+3∆Vt, P5=Vpgm +4∆Vt, Vpgm represents the initial programming voltage, and ∆Vt represents the voltage increase. L1-L5 represent the critical voltage distributions obtained after applying the programming voltages P1-P5, respectively. L0 represents the threshold voltage distribution before programming.

After the programming voltage P1 is applied, the critical voltage distribution of the memory cell is L1. Next, it is determined whether the critical voltage distribution L1 of the memory cell is higher than the verification voltage Vvfy, and if not, the next programming voltage P2 is applied. Until the critical voltage distribution of the memory cell is higher than the verification voltage Vvfy.

However, when programming a memory cell, the surrounding memory cells may be affected. The memory cell that should not be programmed may cause the critical voltage of the memory cell to be increased due to the programming of the peripheral memory cell, which in turn may cause the reliability of the memory to decrease.

Therefore, there is a need for a new type of memory device and its programming method, which can improve the reliability of the memory.

According to an embodiment of the present case, a programming method for a memory device is provided. The memory device includes a memory array and a controller. The memory array includes a plurality of memory cells. The programming method includes: by the control The controller controls programming a first page of a first word line of the memory array; the controller controls programming a first page of a second word line of the memory array, the second The word line is adjacent to the first word line; the controller controls the first programming of a second page of the first word line of the memory array; the controller controls the memory Programming a first page of a third word line of the array, the third word line is adjacent to the second word line; the controller controls the second word line of the memory array A second page performs the first programming; and the controller controls the second page of the first word line of the memory array to perform a second programming.

According to another embodiment of the present case, a memory device is provided, including: a memory array including a plurality of memory cells; and a controller coupled to the memory array. The controller controls: programming a first page of a first word line of the memory array; programming a first page of a second word line of the memory array, the second character The line is adjacent to the first word line; a first programming is performed on a second page of the first word line of the memory array; a first of a third word line of the memory array Programming pages, the third word line is adjacent to the second word line; performing the first programming on a second page of the second word line of the memory array; and A second programming is performed on the second page of the first word line.

In order to have a better understanding of the above and other aspects of the present invention, the following examples are specifically described in conjunction with the accompanying drawings as follows:

The technical terms of this specification refer to the idioms in the technical field. If this specification describes or defines some terms, the interpretation of these terms shall be based on the description or definition of this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those skilled in the art can selectively implement some or all of the technical features in any of the embodiments, or selectively combine some or all of the technical features in these embodiments.

FIG. 3 shows a functional block diagram of a memory device according to an embodiment of this case. Of course, FIG. 3 is a simplified display. Those of ordinary skill in the art should know that the memory device 300 may further include other necessary components. The memory device 300 includes a memory array 310 and a controller 320.

The memory array 310 includes a plurality of memory cells arranged in an array, a plurality of word lines and a plurality of bit lines.

The controller 320 is coupled to the memory array 310 to control operations (such as programming) on the memory array 310.

Referring now to FIG. 4, a programming method of a memory device according to an embodiment of this case is shown. WL0 to WL3 represent the 0th to 3rd character lines of the memory array 310. As shown in Figure 4, when programming, the programming sequence is: first program the upper page of word line WL0, then, program the upper page of word line WL1, then, perform the lower page of word line WL0 First programming, then, program the upper page of word line WL2, then, first program the lower page of word line WL1, then, second program the lower page of word line WL0, then, word The high page programming of element line WL3, the rest can be deduced by analogy.

As is known, after programming the lower page of the previous word line, the latter word line will be programmed, but this may affect the lower page programming result of the previous word line. Therefore, in the embodiment of the present invention, the advantage of performing multi-level programming on the low page is that the second low page programming can reduce program disturbance. For example, programming the upper page of word line WL1 or/and the lower page may interfere with the result of the first programming of the lower page of word line WL0. Therefore, in the embodiment of the present invention, the lower page of the word line WL0 is programmed twice to reduce the programming interference caused by the programming of the adjacent word line WL1.

Below, the programming takes ISPP as an example to illustrate, and after applying the programming voltage once, three verification voltages PV1, PV2 and PV3 are applied for verification. To facilitate understanding, the programming voltage of ISPP is described by taking 14V-23V as an example, and 14V-17V is a programming voltage range (also called the first programming voltage range), and 17V-20V is a programming voltage range (also Called the second programming voltage range), 20V-23V is a programming voltage range (also can be referred to as the third programming voltage range). But be aware that this case is not limited to this.

Please refer to Figure 4 again. In Figure 4, the logic states S1, S2, S3, and S4 represent logic 11, logic 10, logic 00, and logic 01, respectively.

The curve 410 represents the critical voltage distribution of the physical page after the erase operation but before programming, so all memory cells have a critical voltage distribution 410.

Program the upper page of the physical page (such as word line WL0), for example, apply a programming voltage within the programming voltage range (17V-20V) to the memory cells, so that the upper page has a memory of logic 1 The body cell has a threshold voltage distribution 420, and the memory cell with a logic 0 in the high page has a threshold voltage distribution 430, where the threshold voltage distribution 420 is lower than the first verification voltage PV1 and the threshold voltage distribution 430 is higher than the second verification The voltage PV2 is lower than the third verification voltage PV3. That is, a programming voltage of 17V is first applied, and then, it is verified whether the threshold voltage distribution 430 is higher than the second verification voltage PV2. If the threshold voltage distribution 430 is not higher than the second verification voltage PV2, the programming voltage is increased (for example, but not limited to, from 17V to 17.5V) until the verification threshold voltage distribution 430 is higher than the second verification voltage PV2 .

After that, perform the first programming on the lower page of the physical page (such as the word line WL0), for example, apply a programming voltage within the programming voltage range (20V-23V) to the memory cells, so as to have a logic 00 The memory cell has a critical voltage distribution 440 and the memory cell with a logic 01 has a critical voltage distribution 450, wherein the critical voltage distribution 440 is higher than the second verification voltage PV2 but lower than the third verification voltage PV3, and the critical voltage distribution 450 Higher than the third verification voltage PV3. That is, a programming voltage of 20V is first applied, and then, it is verified whether the threshold voltage distribution 450 is higher than the third verification voltage PV3. If not, the programming voltage is increased (for example, but not limited to, from 20V to 23.5V) until the critical voltage distribution 450 is higher than the third verification voltage PV3.

Perform second programming on the lower page of the physical page (such as word line WL0), for example, apply a programming voltage within the programming voltage range (14V-17V) to the memory cells, so that the memory with logic 11 The cell has a threshold voltage distribution 460 and the memory cell with a logic 10 has a threshold voltage distribution 470, wherein the threshold voltage distribution 460 is lower than the first verification voltage PV1, and the threshold voltage distribution 470 is higher than the first verification voltage PV1 but lower than The second verification voltage PV2. In addition, due to the application of the programming voltage, the threshold voltage distributions 440 and 450 become the threshold voltage distributions 480 and 490, but the threshold voltage distribution 480 is higher than the second verification voltage PV2 but lower than the third verification voltage PV3, and the threshold voltage distribution 490 Higher than the third verification voltage PV3. That is, a program voltage of 14V is applied, and then, it is verified whether the threshold voltage distribution 470 is higher than the first verification voltage PV1. If not, the programming voltage is increased (for example, but not limited to, from 14V to 14.5V) until the verification threshold voltage distribution 470 is higher than the first verification voltage PV1.

In this way, the programming of the memory cell can be completed. As shown in FIG. 4, the memory cell with logic 11 (S1) has a critical voltage distribution 460 (lower than the first verification voltage PV1) and has logic 10( S2) the memory cell has a critical voltage distribution 470 (higher than the first verification voltage PV1 but lower than the second verification voltage PV2), and the memory cell with a logic 00 (S3) has a critical voltage distribution 480 (higher than the first The second verification voltage PV2 is lower than the third verification voltage PV3). The memory cell with logic 01 (S4) has a critical voltage distribution 490 (higher than the third verification voltage PV3).

Please note that the right half of Figure 4 shows the programming sequence for all word lines of the entire memory array, and the left half of Figure 4 shows the programming sequence for one word line.

As described above, in the embodiment of the present invention, since the second page is programmed again, it is possible to reduce the programming interference caused by the adjacent word line programming.

Referring now to FIG. 5, a programming method of a memory device according to an embodiment of this case is shown. In Figure 5, the programming sequence for all word lines of the entire memory array is the same as in Figure 4.

The curve 510 represents the critical voltage distribution of the physical page after the erase operation but before the programming, so all memory cells have a critical voltage distribution 510.

Program the upper page of the physical page (such as word line WL0), for example, apply a programming voltage within the programming voltage range (17V-20V) to the memory cells, so that the upper page has a memory of logic 1 The body cell has a threshold voltage distribution 520, and the memory cell with a logic 0 in the high page has a threshold voltage distribution 530, where the threshold voltage distribution 520 is lower than the first verification voltage PV1 and the threshold voltage distribution 530 is higher than the second verification The voltage PV2 is lower than the third verification voltage PV3.

After that, perform the first programming on the lower page of the physical page (such as the word line WL0), for example, apply a programming voltage within the programming voltage range (14V-17V) to the memory cells, so as to have a logic 11 The memory cell has a threshold voltage distribution 540 and the memory cell with a logic 10 has a threshold voltage distribution 550, wherein the threshold voltage distribution 540 is lower than the first verification voltage PV1, and the threshold voltage distribution 550 is higher than the first verification voltage PV1. Lower than the second verification voltage PV2. That is, a programming voltage of 14V is applied first, and then, it is verified whether the threshold voltage distribution 550 is higher than the first verification voltage PV1. If the threshold voltage distribution 550 is not higher than the first verification voltage PV1, the programming voltage is increased (for example, but not limited to, from 14V to 14.5V) until the verification threshold voltage distribution 550 is higher than the first verification voltage PV1 .

Perform second programming on the lower page of the physical page (such as word line WL0), for example, apply a programming voltage within the programming voltage range (20V-23V) to the memory cells, so that a memory with logic 00 The cell has a critical voltage distribution 590 and the memory cell with a logic 01 has a critical voltage distribution 595, wherein the critical voltage distribution 590 is higher than the second verification voltage PV2 but lower than the third verification voltage PV3, and the critical voltage distribution 595 is high At the third verification voltage PV3. In addition, due to the application of the programming voltage, the threshold voltage distributions 540 and 550 will become the threshold voltage distributions 570 and 580, but the threshold voltage distribution 570 is still lower than the first verification voltage PV1, and the threshold voltage distribution 580 is still higher than the first verification The voltage PV1 is lower than the second verification voltage PV2. That is, a programming voltage of 20V is applied, and then, it is verified whether the threshold voltage distribution 595 is higher than the third verification voltage PV3. If not, the programming voltage is increased (for example, but not limited to, from 20V to 20.5V) until the critical voltage distribution 595 is higher than the third verification voltage PV3.

In this way, the programming of the memory cell can be completed. As shown in FIG. 5, the memory cell with logic 11 (S1) has a critical voltage distribution 570 (lower than the first verification voltage PV1) and has logic 10 ( S2) the memory cell has a critical voltage distribution 580 (higher than the first verification voltage PV1 but lower than the second verification voltage PV2), and the memory cell with a logic 00 (S3) has a critical voltage distribution 590 (higher than the first The second verification voltage PV2 is lower than the third verification voltage PV3). The memory cell with logic 01 (S4) has a critical voltage distribution 595 (higher than the third verification voltage PV3).

Referring now to FIG. 6, a programming method of a memory device according to an embodiment of the present case is shown. In Figure 6, the programming sequence for all word lines of the entire memory array is the same as in Figure 4.

The curve 610 represents the critical voltage distribution of the physical page after the erase operation but before programming, so all memory cells have a critical voltage distribution 610.

Program the upper page of the physical page (such as word line WL0), for example, apply a programming voltage within the programming voltage range (14V-17V) to the memory cells, so that the upper page has a memory of logic 1 The body cell has a threshold voltage distribution 620, and the memory cell with a logic 0 in the high page has a threshold voltage distribution 630, where the threshold voltage distribution 620 is lower than the first verification voltage PV1 and the threshold voltage distribution 630 is higher than the first verification The voltage PV1 is lower than the second verification voltage PV2.

After that, perform the first programming on the lower page of the physical page (such as the word line WL0), for example, apply a programming voltage within the programming voltage range (17V-20V) to the memory cells, so as to have a logic 11 The memory cell has a critical voltage distribution 640, the memory cell with logic 10 has a critical voltage distribution 650, and the memory cells with logic 00 and 01 have a critical voltage distribution 660, wherein the critical voltage distribution 640 is lower than the first For the verification voltage PV1, the threshold voltage distribution 650 is higher than the first verification voltage PV1 but lower than the second verification voltage PV2, and the threshold voltage distribution 660 is higher than the second verification voltage PV2 but lower than the third verification voltage PV3. That is, a programming voltage of 17V is applied first, and then, it is verified whether the threshold voltage distribution 650 is higher than the first verification voltage PV1 and the threshold voltage distribution 660 is higher than the second verification voltage PV2. If not, increase the programming voltage (for example, but not limited to, from 17V to 17.5V) until the critical voltage distribution 650 is higher than the first verification voltage PV1 and the critical voltage distribution 660 is higher than the second verification voltage PV2 .

Perform second programming on the lower page of the physical page (such as word line WL0), for example, apply a programming voltage within the programming voltage range (20V-23V) to the memory cells, so that a memory with logic 00 The cell has a critical voltage distribution 690 and the memory cell with a logic 01 has a critical voltage distribution 695, wherein the critical voltage distribution 690 is higher than the second verification voltage PV2 but lower than the third verification voltage PV3, and the critical voltage distribution 695 is high At the third verification voltage PV3. In addition, after applying a programming voltage within the programming voltage range (20V-23V), the threshold voltage distributions 640 and 650 may become the threshold voltage distributions 670 and 680, but the threshold voltage distribution 670 is still lower than the first verification voltage PV1, and The threshold voltage distribution 680 is still higher than the first verification voltage PV1 but lower than the second verification voltage PV2. That is, a programming voltage of 20V is applied, and then, it is verified whether the critical voltage distribution 695 is higher than the third verification voltage PV3. If not, the programming voltage is increased (for example, but not limited to, from 20V to 20.5V) until the critical voltage distribution 695 is higher than the third verification voltage PV3.

In this way, the programming of the memory cell can be completed. As shown in FIG. 6, the memory cell with logic 11 (S1) has a critical voltage distribution 670 (lower than the first verification voltage PV1) and has logic 10( S2) the memory cell has a critical voltage distribution 680 (higher than the first verification voltage PV1 but lower than the second verification voltage PV2), and the memory cell with a logic 00 (S3) has a critical voltage distribution 690 (higher than the first The second verification voltage PV2 is lower than the third verification voltage PV3). The memory cell with logic 01 (S4) has a critical voltage distribution 695 (higher than the third verification voltage PV3).

Referring now to FIG. 7, a programming method of a memory device according to an embodiment of the present case is shown. In Figure 7, the programming sequence for all word lines of the entire memory array is the same as in Figure 4.

The curve 710 represents the critical voltage distribution of the physical page after the erase operation but before programming, so all memory cells have a critical voltage distribution 710.

Program the upper page of the physical page (such as word line WL0), for example, apply a programming voltage within the programming voltage range (14V-17V) to the memory cells, so that the upper page has a memory of logic 1 The body cell has a threshold voltage distribution 715, and the memory cell with a logic 0 in the high page has a threshold voltage distribution 720, where the threshold voltage distribution 715 is lower than the first verification voltage PV1 and the threshold voltage distribution 720 is higher than the first verification The voltage PV1 is lower than the second verification voltage PV2.

After that, perform the first programming on the lower page of the physical page (such as the word line WL0), for example, apply a programming voltage within the programming voltage range (17V-20V) to the memory cells, so as to have a logic 11 The memory cell has a critical voltage distribution 725 and the memory cell with a logic 10 has a critical voltage distribution 730, and the memory cells with logic 00 and 01 have the same critical voltage distribution 735, wherein the critical voltage distribution 725 is lower than the first For a verification voltage PV1, the threshold voltage distributions 730 and 735 are higher than the first verification voltage PV1. In addition, the continuous application of the programming voltage allows the critical voltage distribution 750 of the memory cell with logic 00 to be separated from the critical voltage distribution 755 of the memory cell with logic 01, but both are higher than the first verification voltage PV1. In addition, the critical The voltage distributions 725 and 730 may become the threshold voltage distributions 740 and 745, but the threshold voltage distribution 740 is still lower than the first verification voltage PV1, and the threshold voltage distribution 745 is higher than the first verification voltage PV1 but lower than the second verification voltage PV2. That is, a program voltage of 17V is applied first, and then, it is verified whether the threshold voltage distribution 730 is higher than the first verification voltage PV1. If the threshold voltage distribution 730 is not higher than the first verification voltage PV1, the programming voltage is raised (for example, but not limited to, from 17V to 17.5V) until the threshold voltage distribution 730 is higher than the first verification voltage PV1. In addition, in the first programming of the lower page, the programming voltage is continuously increased until the critical voltage distribution 750 of the memory cell with logic 00 is separated from the critical voltage distribution 755 of the memory cell with logic 01.

Perform second programming on the lower page of the physical page (such as word line WL0), for example, apply a programming voltage within the programming voltage range (20V-23V) to the memory cells, so that a memory with logic 00 The cell has a critical voltage distribution 770 and the memory cell with a logic 01 has a critical voltage distribution 775, wherein the critical voltage distribution 770 is higher than the second verification voltage PV2 but lower than the third verification voltage PV3, and the critical voltage distribution 775 is high At the third verification voltage PV3. In addition, due to the application of the programming voltage, the threshold voltage distributions 740 and 745 will become the threshold voltage distributions 760 and 765, but the threshold voltage distribution 760 is lower than the first verification voltage PV1, and the threshold voltage distribution 765 is higher than the first verification voltage PV1 but Lower than the second verification voltage PV2. That is, a programming voltage of 20V is applied, and then, it is verified whether the threshold voltage distribution 770 is higher than the second verification voltage PV2 and the threshold voltage distribution 775 is higher than the third verification voltage PV3. If not, increase the programming voltage (for example, but not limited to, from 20V to 20.5V) until the critical voltage distribution 770 is higher than the second verification voltage PV2, and the critical voltage distribution 775 is higher than the third verification voltage PV3 until.

In this way, the programming of the memory cell can be completed. As shown in FIG. 7, the memory cell with logic 11 (S1) has a critical voltage distribution 760 (lower than the first verification voltage PV1) and has logic 10( S2) the memory cell has a critical voltage distribution 765 (higher than the first verification voltage PV1 but lower than the second verification voltage PV2), and the memory cell with a logic 00 (S3) has a critical voltage distribution 770 (higher than the first The second verification voltage PV2 is lower than the third verification voltage PV3). The memory cell with logic 01 (S4) has a critical voltage distribution 775 (higher than the third verification voltage PV3).

Referring now to FIG. 8, a programming method of a memory device according to an embodiment of the present case is shown. In Figure 8, the programming sequence for all word lines of the entire memory array is the same as in Figure 4.

The curve 810 represents the critical voltage distribution of the physical page after the erase operation but before programming, so all memory cells have a critical voltage distribution 810.

Program the upper page of the physical page (such as word line WL0), for example, apply a programming voltage within the programming voltage range (14V-17V) to the memory cells, so that the upper page has a memory of logic 1 The body cell has a threshold voltage distribution 820, and the memory cell with a logic 0 in the high page has a threshold voltage distribution 830, wherein the threshold voltage distribution 820 is lower than the first verification voltage PV1, and the threshold voltage distribution 830 is higher than the first verification The voltage PV1 is lower than the second verification voltage PV2.

After that, perform the first programming on the lower page of the physical page (such as the word line WL0), for example, apply a programming voltage within the programming voltage range (14V-17V) to the memory cells, so as to have a logic 11 The memory cell has a critical voltage distribution 840 (lower than the first verification voltage PV1) and the memory cells with logic 10, 00, and 01 have the same critical voltage distribution 850, wherein the critical voltage distribution 850 is higher than the first verification The voltage PV1 is lower than the second verification voltage PV2. That is, a programming voltage of 14V is applied first, and then, it is verified whether the threshold voltage distribution 850 is higher than the first verification voltage PV1. If the threshold voltage distribution 850 is not higher than the first verification voltage PV1, the programming voltage is raised (for example, but not limited to, from 14V to 14.5V) until the threshold voltage distribution 850 is higher than the first verification voltage PV1.

Perform a second programming on the lower page of the physical page (such as word line WL0), for example, apply a programming voltage within the programming voltage range (17V-23V) to the memory cells to make a memory with logic 10 The cell has a critical voltage distribution 870, the memory cell with a logic 00 has a critical voltage distribution 880 and the memory cell with a logic 01 has a critical voltage distribution 890, wherein the critical voltage distribution 870 is higher than the first verification voltage PV1 but Below the second verification voltage PV2, the threshold voltage distribution 880 is higher than the second verification voltage PV2 but lower than the third verification voltage PV3, and the threshold voltage distribution 890 is higher than the third verification voltage PV3. That is, a programming voltage of 17V is applied, and then, it is verified whether the threshold voltage distribution 880 is higher than the second verification voltage PV2, and whether the threshold voltage distribution 890 is higher than the third verification voltage PV3. If not, increase the programming voltage (for example, but not limited to, from 17V to 17.5V) until the critical voltage distribution 880 is higher than the second verification voltage PV2, and the critical voltage distribution 890 is higher than the third verification voltage PV3 until.

In this way, the programming of the memory cell can be completed. As shown in FIG. 8, the memory cell with logic 11 (S1) has a critical voltage distribution 860 (lower than the first verification voltage PV1) and has logic 10( S2) the memory cell has a critical voltage distribution 870 (higher than the first verification voltage PV1 but lower than the second verification voltage PV2), and the memory cell with a logic 00 (S3) has a critical voltage distribution 880 (higher than the first The second verification voltage PV2 is lower than the third verification voltage PV3). The memory cell with logic 01 (S4) has a critical voltage distribution 890 (higher than the third verification voltage PV3).

As described above, in the above embodiment of the present invention, since the second page is programmed again, it is possible to reduce the programming interference caused by the programming of adjacent word lines.

In summary, although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application.

110-170‧‧‧ Critical voltage distribution P1-P5‧‧‧ Programming voltage L0-L5‧‧‧ Critical voltage distribution Vvfy‧‧‧Verification voltage Vpgm‧‧‧Initial programming voltage ΔVt‧‧‧Voltage increase 300‧ ‧‧Memory device 310‧‧‧Memory array 310320‧‧‧Controller WL0-WL3‧‧‧Character line 410-490, 510-595, 610-695, 710-775, 810-890‧‧‧critical Voltage distribution S1-S4‧‧‧Logic state PV1-PV3‧‧‧Verification voltage

Figure 1 shows the current programming method according to the prior art. Figure 2 shows the programming sequence of the ISPP of the conventional technology. FIG. 3 shows a functional block diagram of a memory device according to an embodiment of this case. FIG. 4 shows the programming method of the memory device according to an embodiment of the present case. FIG. 5 shows a programming method of a memory device according to an embodiment of the present case. FIG. 6 shows a programming method of a memory device according to an embodiment of the present case. FIG. 7 shows the programming method of the memory device according to an embodiment of the present case. FIG. 8 shows a programming method of a memory device according to an embodiment of the present case.

WL0-WL3‧‧‧character line

410-490‧‧‧critical voltage distribution

S1-S4‧‧‧Logic state

PV1-PV3‧‧‧Verification voltage

Claims (12)

A programming method of a memory device, the memory device includes a memory array and a controller, the memory array includes a plurality of memory cells, the programming method includes: the controller controls the memory array A first page of a first word line is programmed; a first page of a second word line of the memory array is controlled by the controller, the second word line is adjacent to the first A word line; the controller controls a second programming of a second page of the first word line of the memory array; the controller controls a third word line of the memory array Programming a first page of the first word, the third word line is adjacent to the second word line; the controller controls the first page of the second word line of the memory array to perform the first Programming; and the controller controls a second programming of the second page of the first word line of the memory array. The programming method as described in item 1 of the patent application range, wherein the controller controlling the programming of the first page of the first word line of the memory array includes: applying a voltage within a second programming range At least one programming voltage to the memory cells, so that the memory cells have a first threshold voltage distribution and a second threshold voltage distribution, wherein the first threshold voltage distribution is lower than a first verification voltage And the second threshold voltage distribution is higher than a second verification voltage; controlling the controller to perform the first programming on the second page of the first word line of the memory array includes: applying a third programming At least one programming voltage within the voltage range to the memory cells, so that the memory cells with a third logic state have a third threshold voltage distribution and the memory cells with a fourth logic state The cell has a fourth threshold voltage distribution, wherein the third threshold voltage distribution is higher than the second verification voltage but lower than a third verification voltage, and the fourth threshold voltage distribution is higher than the third verification voltage; The controller controlling the second programming of the second page of the first word line of the memory array includes: applying at least one programming voltage within a first programming voltage range to the memory cells, so that The memory cells with a first logic state have a fifth threshold voltage distribution and the memory cells with a second logic state have a sixth threshold voltage distribution, wherein the fifth threshold voltage distribution Below the first verification voltage, the sixth threshold voltage distribution is higher than the first verification voltage but lower than the second verification voltage; wherein, the first verification voltage is lower than the second verification voltage, and the second verification The voltage is lower than the third verification voltage; and the first programming voltage range is lower than the second programming voltage range, and the second programming voltage range is lower than the third programming voltage range. The programming method as described in item 1 of the patent application range, wherein the controller controlling the programming of the first page of the first word line of the memory array includes: applying a voltage within a second programming range At least one programming voltage to the memory cells, so that the memory cells have a first threshold voltage distribution and a second threshold voltage distribution, wherein the first threshold voltage distribution is lower than a first verification voltage And the second threshold voltage distribution is higher than a second verification voltage; controlling the controller to perform the first programming on the second page of the first word line of the memory array includes: applying a first programming At least one programming voltage within the voltage range to the memory cells, so that the memory cells with a first logic state have a third threshold voltage distribution, and the memory cells with a second logic state The cell has a fourth threshold voltage distribution, wherein the third threshold voltage distribution is lower than the first verification voltage, and the fourth threshold voltage distribution is higher than the first verification voltage but lower than the second verification voltage; controlled by the control The controller controlling the second programming of the second page of the first word line of the memory array includes: applying at least one programming voltage within a third programming voltage range to the memory cells so that The memory cells of a third logic state have a fifth threshold voltage distribution and the memory cells of a fourth logic state have a sixth threshold voltage distribution, wherein the fifth threshold voltage distribution is high At the second verification voltage but lower than a third verification voltage, the sixth threshold voltage distribution is higher than the third verification voltage; wherein, the first verification voltage is lower than the second verification voltage, and the second verification voltage Is lower than the third verification voltage; and the first programming voltage range is lower than the second programming voltage range, and the second programming voltage range is lower than the third programming voltage range. The programming method as described in item 1 of the patent application range, wherein the controller controlling the programming of the first page of the first word line of the memory array includes: applying a voltage within a first programming range At least one programming voltage to the memory cells, so that the memory cells have a first threshold voltage distribution and a second threshold voltage distribution, wherein the first threshold voltage distribution is lower than a first verification voltage And the second threshold voltage distribution is higher than the first verification voltage; controlling the controller to perform the first programming on the second page of the first word line of the memory array includes: applying a second programming At least one programming voltage within the voltage range to the memory cells, so that the memory cells with a first logic state have a third threshold voltage distribution and the memory cells with a second logic state The memory cells having a fourth threshold voltage distribution and having a third and a fourth logic state have a fifth threshold voltage distribution, wherein the third threshold voltage distribution is lower than the first verification voltage, The fourth threshold voltage distribution is higher than the first verification voltage but lower than a second verification voltage, and the fifth threshold voltage distribution is higher than the second verification voltage but lower than a third verification voltage; controlled by the controller Performing the second programming on the second page of the first word line of the memory array includes: applying at least one programming voltage within a third programming voltage range to the memory cells so as to have the first The memory cells of three logic states have a sixth threshold voltage distribution and the memory cells of the fourth logic state have a seventh threshold voltage distribution, wherein the sixth threshold voltage distribution is higher than the The second verification voltage is lower than the third verification voltage, and the seventh threshold voltage distribution is higher than the third verification voltage; wherein, the first verification voltage is lower than the second verification voltage, and the second verification voltage is lower The third verification voltage; and the first programming voltage range is lower than the second programming voltage range, and the second programming voltage range is lower than the third programming voltage range. The programming method as described in item 1 of the patent application range, wherein the controller controlling the programming of the first page of the first word line of the memory array includes: applying a voltage within a first programming range At least one programming voltage to the memory cells, so that the memory cells have a first threshold voltage distribution and a second threshold voltage distribution, wherein the first threshold voltage distribution is lower than a first verification voltage And the second threshold voltage distribution is higher than the first verification voltage; controlling the controller to perform the first programming on the second page of the first word line of the memory array includes: applying a second programming At least one programming voltage within the voltage range to the memory cells, so that the memory cells with a first logic state have a third threshold voltage distribution and the memory cells with a second logic state The cell has a fourth threshold voltage distribution, and a fifth threshold voltage distribution of the memory cells having a third logic state is separated from a sixth threshold of the memory cells having a fourth logic state Voltage distribution, wherein the third threshold voltage distribution is lower than the first verification voltage, the fourth threshold voltage distribution is higher than the first verification voltage but lower than a second verification voltage, and the fifth and sixth thresholds The voltage distribution is higher than the second verification voltage; controlling the second programming of the second page of the first word line of the memory array by the controller includes: applying at least at least a third programming voltage range A programming voltage to the memory cells, so that the memory cells with the third logic state have a seventh threshold voltage distribution and the memory cells with the fourth logic state have an eighth A threshold voltage distribution, wherein the seventh threshold voltage distribution is higher than the second verification voltage but lower than a third verification voltage, and the eighth threshold voltage distribution is higher than the third verification voltage; wherein, the first verification voltage Is lower than the second verification voltage, and the second verification voltage is lower than the third verification voltage; and the first programming voltage range is lower than the second programming voltage range, and the second programming voltage range is lower than the third programming voltage range. The programming method as described in item 1 of the patent application range, wherein the controller controlling the programming of the first page of the first word line of the memory array includes: applying a voltage within a first programming range At least one programming voltage to the memory cells, so that the memory cells have a first threshold voltage distribution and a second threshold voltage distribution, wherein the first threshold voltage distribution is lower than a first verification voltage , The second threshold voltage distribution is higher than the first verification voltage but lower than a second verification voltage; the controller controls the first programming of the second page of the first word line of the memory array The method includes: applying at least one programming voltage within the first programming voltage range to the memory cells, so that the memory cells with a first logic state have a third threshold voltage distribution and have a second , The memory cells of a third and a fourth logic state have a fourth threshold voltage distribution, wherein the third threshold voltage distribution is lower than the first verification voltage, and the fourth threshold voltage distribution is higher than the The first verification voltage is lower than the second verification voltage; controlling the second programming of the second page of the first word line of the memory array by the controller includes: applying a second and a first At least one programming voltage within the three programming voltage ranges to the memory cells, so that the memory cells with the second logic state have a fifth threshold voltage distribution, and the memories with the third logic state The body cell has a sixth threshold voltage distribution, and the memory cells with the fourth logic state have a seventh threshold voltage distribution, wherein the fifth threshold voltage distribution is higher than the first verification voltage but lower than The second verification voltage, the sixth threshold voltage distribution is higher than the second verification voltage but lower than a third verification voltage, and the seventh threshold voltage distribution is higher than the third verification voltage; wherein, the first verification voltage is low At the second verification voltage, and the second verification voltage is lower than the third verification voltage; and the first programming voltage range is lower than the second programming voltage range, and the second programming voltage range is lower than the third programming voltage range. A memory device includes: a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller controls: a first character line for the memory array Programming a first page of; programming a first page of a second word line of the memory array, the second word line is adjacent to the first word line; of the memory array Performing a first programming on a second page of the first word line; programming a first page of a third word line on the memory array, the third word line being adjacent to the second word Element lines; performing the first programming on a second page of the second word line of the memory array; and performing a second programming on the second page of the first word line of the memory array. The memory device as described in item 7 of the patent application scope, wherein, when programming the first page of the first word line of the memory array, the controller controls: applying a second programming voltage range At least one programming voltage in the memory cells, so that the memory cells have a first threshold voltage distribution and a second threshold voltage distribution, wherein the first threshold voltage distribution is lower than a first verification Voltage and the second threshold voltage distribution is higher than a second verification voltage; when performing the first programming on the second page of the first word line of the memory array, the controller controls: the application belongs to a third At least one programming voltage within the programming voltage range to the memory cells, so that the memory cells with a third logic state have a third threshold voltage distribution and the memories with a fourth logic state The cell has a fourth threshold voltage distribution, wherein the third threshold voltage distribution is higher than the second verification voltage but lower than a third verification voltage, and the fourth threshold voltage distribution is higher than the third verification voltage; When performing the second programming on the second page of the first word line of the memory array, the controller controls: applying at least one programming voltage belonging to a first programming voltage range to the memory cells, The memory cells with a first logic state have a fifth threshold voltage distribution and the memory cells with a second logic state have a sixth threshold voltage distribution, wherein the fifth threshold voltage The distribution is lower than the first verification voltage, the sixth threshold voltage distribution is higher than the first verification voltage but lower than the second verification voltage; wherein, the first verification voltage is lower than the second verification voltage, and the second The verification voltage is lower than the third verification voltage; and the first programming voltage range is lower than the second programming voltage range, and the second programming voltage range is lower than the third programming voltage range. The memory device as described in item 7 of the patent application scope, wherein, when programming the first page of the first word line of the memory array, the controller controls: applying a second programming voltage range At least one programming voltage in the memory cells, so that the memory cells have a first threshold voltage distribution and a second threshold voltage distribution, wherein the first threshold voltage distribution is lower than a first verification Voltage and the second threshold voltage distribution is higher than a second verification voltage; when the first programming is performed on the second page of the first word line of the memory array, the controller controls: the application belongs to a first programming At least one programming voltage within the voltage range to the memory cells, so that the memory cells with a first logic state have a third threshold voltage distribution, and the memory cells with a second logic state The cell has a fourth threshold voltage distribution, wherein the third threshold voltage distribution is lower than the first verification voltage, and the fourth threshold voltage distribution is higher than the first verification voltage but lower than the second verification voltage; When the second programming is performed on the second page of the first word line of the volume array, the controller controls: applying at least one programming voltage within a third programming voltage range to the memory cells so that The memory cells of a third logic state have a fifth threshold voltage distribution and the memory cells of a fourth logic state have a sixth threshold voltage distribution, wherein the fifth threshold voltage distribution is high At the second verification voltage but lower than a third verification voltage, the sixth threshold voltage distribution is higher than the third verification voltage; wherein, the first verification voltage is lower than the second verification voltage, and the second verification voltage Is lower than the third verification voltage; and the first programming voltage range is lower than the second programming voltage range, and the second programming voltage range is lower than the third programming voltage range. The memory device as described in item 7 of the patent application range, wherein, when programming the first page of the first word line of the memory array, the controller controls: applying a first programming voltage range At least one programming voltage in the memory cells, so that the memory cells have a first threshold voltage distribution and a second threshold voltage distribution, wherein the first threshold voltage distribution is lower than a first verification Voltage and the second threshold voltage distribution is higher than the first verification voltage; when performing the first programming on the second page of the first word line of the memory array, the controller controls: At least one programming voltage within the programming voltage range to the memory cells, so that the memory cells with a first logic state have a third threshold voltage distribution and the memories with a second logic state The memory cells have a fourth threshold voltage distribution and the memory cells having a third and a fourth logic state have a fifth threshold voltage distribution, wherein the third threshold voltage distribution is lower than the first verification voltage , The fourth threshold voltage distribution is higher than the first verification voltage but lower than a second verification voltage, and the fifth threshold voltage distribution is higher than the second verification voltage but lower than a third verification voltage; for the memory When the second programming is performed on the second page of the first word line of the array, the controller controls: applying at least one programming voltage within a third programming voltage range to the memory cells so as to have the The memory cells of the third logic state have a sixth threshold voltage distribution and the memory cells of the fourth logic state have a seventh threshold voltage distribution, wherein the sixth threshold voltage distribution is higher than The second verification voltage is lower than the third verification voltage, and the seventh threshold voltage distribution is higher than the third verification voltage; wherein, the first verification voltage is lower than the second verification voltage, and the second verification voltage Is lower than the third verification voltage; and the first programming voltage range is lower than the second programming voltage range, and the second programming voltage range is lower than the third programming voltage range. The memory device as described in item 7 of the patent application range, wherein, when programming the first page of the first word line of the memory array, the controller controls: applying a first programming voltage range At least one programming voltage in the memory cells, so that the memory cells have a first threshold voltage distribution and a second threshold voltage distribution, wherein the first threshold voltage distribution is lower than a first verification Voltage and the second threshold voltage distribution is higher than the first verification voltage; when the first programming is performed on the second page of the first word line of the memory array, the controller controls: At least one programming voltage within the programming voltage range to the memory cells, so that the memory cells with a first logic state have a third threshold voltage distribution and the memories with a second logic state The cell has a fourth threshold voltage distribution, and a fifth threshold voltage distribution of the memory cells with a third logic state is separated from a sixth of the memory cells with a fourth logic state A threshold voltage distribution, wherein the third threshold voltage distribution is lower than the first verification voltage, the fourth threshold voltage distribution is higher than the first verification voltage but lower than a second verification voltage, and the fifth and the sixth The threshold voltage distribution is higher than the second verification voltage; when the second programming is performed on the second page of the first word line of the memory array, the controller controls: applying a voltage within a third programming voltage range At least one programming voltage to the memory cells, such that the memory cells with the third logic state have a seventh threshold voltage distribution and the memory cells with the fourth logic state have a first Eight critical voltage distributions, wherein the seventh critical voltage distribution is higher than the second verification voltage but lower than a third verification voltage, and the eighth critical voltage distribution is higher than the third verification voltage; wherein, the first verification The voltage is lower than the second verification voltage, and the second verification voltage is lower than the third verification voltage; and the first programming voltage range is lower than the second programming voltage range, and the second programming voltage range is lower than the third Programming voltage range. The memory device as described in item 7 of the patent application range, wherein, when programming the first page of the first word line of the memory array, the controller controls: applying a first programming voltage range At least one programming voltage in the memory cells, so that the memory cells have a first threshold voltage distribution and a second threshold voltage distribution, wherein the first threshold voltage distribution is lower than a first verification Voltage, the second threshold voltage distribution is higher than the first verification voltage but lower than a second verification voltage; when performing the first programming on the second page of the first word line of the memory array, the control Device control: applying at least one programming voltage belonging to the first programming voltage range to the memory cells, so that the memory cells with a first logic state have a third critical voltage distribution and have a first 2. The memory cells in a third and a fourth logic state have a fourth threshold voltage distribution, wherein the third threshold voltage distribution is lower than the first verification voltage, and the fourth threshold voltage distribution is higher than The first verification voltage is lower than the second verification voltage; when the second programming is performed on the second page of the first word line of the memory array, the controller controls: At least one programming voltage within the third programming voltage range to the memory cells, so that the memory cells with the second logic state have a fifth threshold voltage distribution, and the ones with the third logic state The memory cell has a sixth threshold voltage distribution, and the memory cells with the fourth logic state have a seventh threshold voltage distribution, wherein the fifth threshold voltage distribution is higher than the first verification voltage but lower At the second verification voltage, the sixth threshold voltage distribution is higher than the second verification voltage but lower than a third verification voltage, and the seventh threshold voltage distribution is higher than the third verification voltage; wherein, the first verification voltage Is lower than the second verification voltage, and the second verification voltage is lower than the third verification voltage; and the first programming voltage range is lower than the second programming voltage range, and the second programming voltage range is lower than the third programming voltage range.

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