TW202002286A - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a substrate, an ESD poly-silicon layer, an insulation layer, a metal layer, a first contact and a second contact. The ESD poly-silicon layer is disposed above a gate pad region defined on the substrate and electrically isolated from the substrate. The ESD poly-silicon layer includes a first doped region ~ a third doped region having first electricity and a fourth doped region having second electricity. The first doped region is located around the gate pad region and connected to the second doped region. The fourth doped region is disposed among the first doped region ~ third doped region. The metal layer includes a first part and a second part and an isolation portion is disposed between them. The first contact is electrically connected to the first doped region and first part. The second contact is electrically connected to the third doped region and second part.

Description

Semiconductor components

The present invention relates to a semiconductor element, and in particular to a semiconductor element having an electrostatic discharge protection function.

Conventionally known semiconductor devices with electrostatic discharge protection function, taking metal oxide half field effect transistor switching devices as an example, the electrostatic discharge protection device is usually arranged around the source or drain of a larger area. The electrostatic discharge current passes through the peripheral circuit, which results in a longer reaction time of the electrostatic discharge and makes the component design more complicated.

Therefore, in the prior art, the ESD protection device is arranged in the gate pad area of the semiconductor device. The advantage is that when the ESD event occurs, it can be eliminated at the gate terminal without passing through the peripheral circuit, so the reaction time can be shortened and the device design It is relatively simple, but because the area of the gate pad area is relatively smaller than that of the source/drain pad area, the protection provided by the ESD protection element is also quite limited.

Please refer to FIGS. 1A and 1B. FIGS. 1A and 1B respectively illustrate a top view and a cross-sectional view of a conventional semiconductor device having an electrostatic discharge protection function.

As shown in FIG. 1A, the ESD protection element ESD can be disposed around the gate metal layer GM of the metal oxide half field effect transistor. As shown in FIG. 1B, the ESD protection polysilicon layer of the conventional ESD protection device ESD may include a first doped region N-POLY, a second doped region P-POLY, and a third doped region N-POLY. A PN junction is formed between the first doped region N-POLY and the second doped region P-POLY and between the second doped region P-POLY and the third doped region N-POLY. The gate metal layer GM is disposed above the first doped region N-POLY and the two are electrically separated by the insulating layer ILD, and the first doped region N-POLY and the third doped region N-POLY are in contact through the gate respectively The portion GCT and the source contact portion SCT couple the gate metal layer GM and the external source metal layer SM.

When the semiconductor element 1 is working normally, since its operating voltage is usually lower than the breakdown voltage of the ESD protection element ESD, the gate metal layer GM and the source metal layer SM at both ends of the ESD protection element ESD are not conductive to each other; When a discharge event occurs, the PN junction in the ESD protection element ESD will be turned on due to collapse, so that the ESD current I _ESD will enter the ESD protection element ESD from the gate metal layer GM through the gate contact GCT, and then pass through the source The electrode contact portion SCT enters the source metal layer SM and flows out.

However, the first doped region N-POLY of the conventional ESD protection element ESD under the gate metal layer GM is only a large piece of N-type polysilicon, and does not provide any function. In other words, the electrostatic discharge current I _{ESD can only be} diverted to the ESD protection element ESD by the gate contact GCT located under the gate metal layer GM, but the conductive area of the gate contact GCT is limited, so that it can provide static electricity The discharge protection capability is quite limited.

In view of this, the present invention provides a semiconductor device to solve the problems mentioned in the prior art.

A preferred embodiment of the present invention is a semiconductor device. In this embodiment, the semiconductor device includes a substrate, an electrostatic discharge protection polysilicon layer, a first insulating layer, a first metal layer, a first contact, and a second contact. The substrate defines a gate pad area. The ESD protection polysilicon layer is disposed above the gate pad area of the substrate and is electrically isolated from the substrate. The ESD protection polysilicon layer includes a first doped region having a first electrical property, a second doped region and a third doped region, and a fourth doped region having a second electrical property. The first doped region is located around the gate pad region. The first doped region is connected to the second doped region. The fourth doped region is disposed between the first doped region, the second doped region and the third doped region. The first insulating layer is disposed above the ESD protection polysilicon layer. The first metal layer is disposed above the first insulating layer. The first metal layer includes a first part and a second part. A partition is provided between the first part and the second part. The first contact portion and the second contact portion are disposed in the first insulating layer and penetrate the first insulating layer. The first contact is electrically connected to the first doped region and the first portion of the first metal layer. The second contact portion is electrically connected to the third doped region and the second portion of the first metal layer.

In an embodiment of the invention, the second doped region and the third doped region have a patterned configuration and are separated from each other.

In one embodiment of the present invention, the semiconductor device further includes a second metal layer, disposed on the first insulating layer, and having a second corresponding to the first doped region, the second doped region, and the third doped region Metal layer pattern.

In one embodiment of the present invention, the semiconductor device further includes a second insulating layer disposed between the second metal layer and the ESD protection polysilicon layer. The second insulating layer includes a plurality of contacts, respectively connecting the first doped region, the second doped region and the third doped region, and corresponding to the first doped region, the second doped region and the third doped region The second metal layer pattern.

In an embodiment of the invention, the second portion of the first metal layer is electrically isolated from the second doped region and its corresponding second metal layer.

In one embodiment of the invention, the doping concentration of the ESD protection polysilicon layer disposed at the center of the gate pad area is higher than the doping concentration of the ESD protection polysilicon layer disposed at the peripheral position of the gate pad area concentration.

In an embodiment of the present invention, when the semiconductor device operates normally, its operating voltage is lower than the breakdown voltage of the ESD protection polysilicon layer, and the first doped region and the third doped region are not conductive to each other.

In an embodiment of the present invention, when an electrostatic discharge event occurs, the electrostatic discharge protection polysilicon layer is turned on due to collapse, so that the current path from the first doped region to the second doped region is turned on, and the electrostatic discharge current flows from the first metal The first part of the layer flows into and sequentially flows through the first contact and the third doped region, the fourth doped region, and the second doped region to the first doped region and then through the first metal layer. Two parts flow out.

Compared with the prior art, the semiconductor device with electrostatic discharge protection function of the present invention can achieve the following advantages and effects: (1) A plurality of electrostatic discharge protection devices are provided in the idle area of the gate pad area to increase its contact area and It can conduct the electrostatic discharge current more efficiently and improve its electrostatic discharge protection ability; (2) The electrostatic discharge protection elements can be arranged in the idle area of the gate pad area by patterning and coupled to the gate pad Busbars around the pad area to derive the ESD current more evenly; and (3) Adjust the doping concentration distribution of the ESD protection polysilicon layer placed above the gate pad area to make the doping concentration at the center The doping concentration is higher than the edge, so that the path of the electrostatic discharge current can be more evenly dispersed without being excessively concentrated.

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

1, 2, 3 ‧‧‧ semiconductor components

ESD‧‧‧Electrostatic discharge protection element

N-POLY‧‧‧First doped region, third doped region

P-POLY‧‧‧Second doped region

I _ESD ‧‧‧ Electrostatic discharge current

AA’、BB’‧‧‧Profile

ER‧‧‧Gate pad area

SUB‧‧‧Base

OXI‧‧‧Insulation

POLY‧‧‧Electrostatic discharge protection polysilicon layer

ILD‧‧‧Insulation

M1‧‧‧Metal layer

GM‧‧‧Gate metal layer

SM‧‧‧Source metal layer

PV‧‧‧Insulation

GCT‧‧‧Gate contact

SCT‧‧‧Source Contact

R1~R4‧‧‧‧First doped region~Four doped region

CT‧‧‧Insulation

TP1~TP3‧‧‧Contact

M2‧‧‧Metal layer

MP1~MP3‧‧‧Metal layer pattern

IMD‧‧‧Insulation

VIA‧‧‧Through hole

1A and 1B respectively illustrate a top view and a cross-sectional view of a conventional semiconductor device with an electrostatic discharge protection function.

2A is a cross-sectional view of a semiconductor device 2 in a preferred embodiment of the present invention.

2B illustrates a top view of the ESD protection polysilicon layer POLY in the semiconductor device 2 including the first doped region R1, the second doped region R2, the third doped region R3, and the fourth doped region R4.

FIG. 3A is a cross-sectional view of a semiconductor device 3 in another preferred embodiment of the present invention.

3B shows a top view of the second metal layer M in the semiconductor device 3 having second metal layer patterns MP1~MP3 corresponding to the first doped region R1, the second doped region R2, and the third doped region R3, respectively .

4A and 4B respectively illustrate other different embodiments in which the second doped region R2 and the third doped region R3 have a comb-like staggered patterned configuration and are separated from each other.

Reference will now be made in detail to exemplary embodiments of the present invention, and examples of the exemplary embodiments will be described in the accompanying drawings. Elements/components with the same or similar reference numerals used in the drawings and embodiments are used to represent the same or similar parts.

A preferred embodiment according to the present invention is a semiconductor device. In this embodiment, the semiconductor element may be a metal oxide half field effect transistor provided with an electrostatic discharge protection element, but it is not limited thereto.

2A and 2B, FIG. 2A shows a cross-sectional view of the semiconductor device 2 in this embodiment; FIG. 2B shows the ESD protection polysilicon layer POLY in the semiconductor device 2 includes the first doped region R1, the second doped Top view of the impurity region R2, the third doped region R3, and the fourth doped region R4. The cross-sectional view of the semiconductor device 2 shown in FIG. 2A is taken along the AA' cross-section of the semiconductor device 2 in FIG. 2B.

As shown in FIG. 2A, the semiconductor device 2 includes a substrate SUB, an insulating layer OXI, an electrostatic discharge protection polysilicon layer POLY, an insulating layer ILD, a gate contact GCT, a source contact SCT, a metal layer M1, and an insulating layer PV. The metal layer M1 includes a first part and a second part. In this embodiment, the first part is the gate metal layer GM and the second part is the source metal layer SM, but not limited to this.

The substrate SUB defines a gate pad region (ER). The ESD protection polysilicon layer POLY is located above the gate pad region ER of the substrate SUB. The insulating layer OXI is disposed between the substrate SUB and the ESD protection polysilicon layer POLY to electrically isolate the ESD protection polysilicon layer POLY and the substrate SUB. The insulating layer ILD is disposed above the electrostatic discharge protection polysilicon layer POLY. The metal layer M1 and the insulating layer PV are disposed above the electrostatic discharge protection polysilicon layer POLY, and the insulating layer PV is located between the gate metal layer GM and the source metal layer SM in the metal layer M1 to serve as the gate metal layer GM and the source The isolation between the polar metal layers SM. The gate contact GCT and the source contact SCT are disposed in the insulating layer ILD and penetrate the insulating layer ILD. The gate contact portion GCT is used to electrically connect the first doped region R1 in the ESD protection polysilicon layer POLY and the gate metal layer GM in the metal layer M1. The source contact portion SCT is used to electrically connect the third doped region R3 in the polysilicon layer POLY and the source metal layer SM in the metal layer M1.

As can be seen from FIGS. 2A and 2B: the electrostatic discharge protection polysilicon layer POLY includes a first doped region R1, a second doped region R2, a third doped region R3 and a fourth doped region R4, and the first doped region R1 The second doped region R2 and the third doped region R3 have a first electrical property and the fourth doped region R4 has a second electrical property, that is, the electrical property of the fourth doped region R4 is different from that of the first doped region R1 2. Electrical properties of the second doped region R2 and the third doped region R3.

For example, the first doped region R1, the second doped region R2, and the third doped region R3 can form an N-type doped region by doping an N-type dopant with a first electrical property, and the first The four-doped region R4 can form a P-type doped region by doping a P-type dopant with second electrical properties, but it is not limited thereto.

The first doped region R1 is located around the gate pad region ER, and the first doped region R1 is connected to the second doped region R2. In the embodiment shown in FIG. 2B, the upper end of the second doped region R2 is connected to the first doped region R1 and the lower end of the second doped region R2 is not connected to the first doped region R1, but not This is limited.

The second doped region R2 and the third doped region R3 have a patterned configuration and are separated from each other. The fourth doped region R4 is disposed between the first doped region R1, the second doped region R2, and the third doped region R3. In the embodiment shown in FIG. 2A and FIG. 2B, the second doped region R2 and the third doped region R3 have a comb-tooth-shaped staggered pattern configuration and are separated from each other. The fourth doped region R4 is disposed between the first doped region R1 and the third doped region R3 and between the second doped region R2 and the third doped region R3, but not limited thereto.

In practical applications, the doping concentration of the ESD protection polysilicon layer POLY disposed at the central position of the gate pad region ER will be higher than that of the ESD protection polysilicon layer POLY disposed at the peripheral position of the gate pad region ER Miscellaneous concentration. In the embodiment shown in FIGS. 2A and 2B, since the first doped region R1 is disposed at the peripheral position of the gate pad region ER, the doping concentration of the first doped region R1 will be lower than that The doping concentration of the second doped region R2 and the third doped region R3 at the center of the gate pad region ER.

When the semiconductor device 2 operates normally, its operating voltage will be lower than the breakdown voltage of the ESD protection polysilicon layer POLY. At this time, the electrostatic discharge protects the first doped region R1 and the third doped region R3 in the polysilicon layer POLY from conducting with each other.

When an electrostatic discharge event occurs, in the electrostatic discharge protection polysilicon layer POLY of the semiconductor device 2, the current path from the first doped region R1 to the third doped region R3 will be turned on due to collapse, and the electrostatic discharge current will flow from the metal layer M1 The gate metal layer GM flows into the first doped region R3, the fourth doped region R4, and the second doped region R2 in the gate contact GCT and the electrostatic discharge protection polysilicon layer POLY in sequence to the first After the doped region R1, it then flows out of the source metal layer SM in the metal layer M1 through the source contact portion SCT, thereby providing the function of electrostatic discharge protection.

Next, please refer to FIGS. 3A and 3B, FIG. 3A illustrates a cross-sectional view of the semiconductor device 3 in another preferred embodiment of the present invention; FIG. 3B illustrates that the second metal layer M in the semiconductor device 3 has corresponding Top views of the second metal layer patterns MP1~MP3 in the first doped region R1, the second doped region R2, and the third doped region R3. The cross-sectional view of the semiconductor element 3 shown in FIG. 3A is taken along the BB' cross-section of the semiconductor element 3 in FIG. 3B.

As shown in FIG. 3A, the semiconductor element 3 includes a substrate SUB, an insulating layer OXI, an electrostatic discharge protection polysilicon layer POLY, an insulating layer CT, a metal layer M2, an insulating layer IMD, a metal layer M1, and an insulating layer PV. The metal layer M1 includes a first part and a second part. In this embodiment, the first part is the gate metal layer GM and the second part is the source metal layer SM, but not limited to this.

The electrostatic discharge protection polysilicon layer POLY includes a first doped region R1, a second doped region R2, a third doped region R3 and a fourth doped region R4, a first doped region R1, a second doped region R2 and a first The three doped regions R3 have a first electrical property and the fourth doped regions R4 have a second electrical property. The first doped region R1 is located around the gate pad region ER, and the first doped region R1 is connected to the second doped region R2. The second doped region R2 and the third doped region R3 have a patterned configuration and are separated from each other. The fourth doped region R4 is disposed between the first doped region R1, the second doped region R2, and the third doped region R3.

The substrate SUB defines a gate pad region ER. The ESD protection polysilicon layer POLY is located above the gate pad region ER of the substrate SUB. The insulating layer OXI is disposed between the substrate SUB and the electrostatic discharge protection polysilicon layer POLY to electrically isolate the electrostatic discharge protection polysilicon layer POLY from the substrate SUB. The insulating layer CT is disposed above the electrostatic discharge protection polysilicon layer POLY and the insulating layer CT includes a plurality of contact portions TP1~TP3. The metal layer M2 is disposed above the insulating layer CT and has a plurality of metal layer patterns MP1~MP3. The metal layer patterns MP1~MP3 respectively correspond to the first doped region R1 and the second doped region in the ESD protection polysilicon layer POLY Region R2 and third doped region R3.

The contact portions TP1~TP3 provided in the insulating layer CT are respectively used to connect the metal layer pattern MP1 in the metal layer M2 and the first doped region R1 in the ESD protection polysilicon layer POLY, and the metal layer in the metal layer M2 The pattern MP2 and the second doped region R2 in the electrostatic discharge protection polysilicon layer POLY and the metal layer pattern MP3 in the metal layer M2 and the third doped region R3 in the electrostatic discharge protection polysilicon layer POLY.

The insulating layer IMD is disposed above the metal layer M2. The insulating layer IMD is provided with a plurality of through holes VIA and the through holes VIA penetrate the insulating layer IMD. The through holes VIA correspond to the metal layer patterns MP1 and MP3 in the metal layer M2, respectively. The metal layer M1 and the insulating layer PV are disposed above the insulating layer IMD, and the insulating layer PV is located between the gate metal layer GM and the source metal layer SM in the metal layer M1 to serve as the gate metal layer GM and the source metal layer The isolation between SM.

In this embodiment, between the metal layer patterns MP2 and MP3 in the metal layer M2 and between the metal layer pattern MP2 in the metal layer M2 and the gate metal layer GM in the metal layer M1 are electrically isolated by the insulating layer IMD . In addition, the source metal layer SM in the metal layer M1 is electrically isolated from the second doped region R2 in the ESD protection polysilicon layer POLY and the metal layer pattern MP2 in the corresponding metal layer M2.

The gate metal layer GM in the metal layer M1 is sequentially connected to the electrostatic discharge protection polysilicon layer POLY through the via VIA in the insulating layer IMD, the metal layer pattern MP3 in the metal layer M2 and the contact portion TP3 in the insulating layer CT The third doped region R3 in the middle; the source metal layer SM in the metal layer M1 sequentially passes through the via VIA in the insulating layer IMD, the metal layer pattern MP1 in the metal layer M2 and the contact portion TP1 in the insulating layer CT It is connected to the first doped region R1 in the ESD protection polysilicon layer POLY.

When the semiconductor device 3 operates normally, its operating voltage will be lower than the breakdown voltage of the ESD protection polysilicon layer POLY. At this time, the electrostatic discharge protects the first doped region R1 and the third doped region R3 in the polysilicon layer POLY from conducting with each other.

When an electrostatic discharge event occurs, in the electrostatic discharge protection polysilicon layer POLY of the semiconductor device 3, the current path from the first doped region R1 to the third doped region R3 will be turned on due to collapse, and the electrostatic discharge current will flow from the metal layer M1 The gate metal layer GM flows into and sequentially passes through the via VIA in the insulating layer IMD, the metal layer pattern MP3 in the metal layer M2, the contact portion TP3 in the insulating layer CT and the third doping in the ESD protection polysilicon layer POLY The impurity region R3, the fourth doped region R4, and the second doped region R2 flow to the first doped region R1, and then sequentially pass through the contact portion TP1 in the insulating layer CT and the metal layer pattern MP1 in the metal layer M2 After passing through the via VIA in the insulating layer IMD, it flows out from the source metal layer SM in the metal layer M1 to provide the function of electrostatic discharge protection.

Next, please refer to FIG. 4A and FIG. 4B. FIG. 4A and FIG. 4B respectively illustrate other different embodiments in which the second doped region R2 and the third doped region R3 have a comb-like staggered pattern configuration and are separated from each other.

As shown in FIG. 4A, the second doped regions R2 and the third doped regions R3 have a comb-tooth-like staggered pattern configuration and are separated from each other. The upper end and the lower end of each second doped region R2 are connected to the first doped region R1, so as to derive the electrostatic discharge current more evenly, but not limited thereto.

As shown in FIG. 4B, the second doped regions R2 and the third doped regions R3 have a comb-like staggered patterned configuration and are separated from each other. The second doped regions R2 are sequentially connected to the first doped region R1 with their upper ends or lower ends. For example, the upper end of the odd-numbered second doped regions R2 is connected to the first doped region R1 and the lower end of the even-numbered second doped regions R2 is connected to the first doped region R1, so as to more evenly discharge the electrostatic discharge current Export, but not limited to this.

Compared with the prior art, the semiconductor device with electrostatic discharge protection function of the present invention can achieve the following advantages and effects: (1) A plurality of electrostatic discharge protection devices are provided in the idle area of the gate pad area to increase its contact area and Can conduct the electrostatic discharge current more efficiently, so it can enhance its electrostatic discharge protection ability; (2) The electrostatic discharge protection elements are arranged in the idle area of the gate pad area through patterning, and are coupled to the gate Busbars around the pad area to draw out the ESD current more evenly; and (3) Adjust the doping concentration distribution of the ESD protection polysilicon layer placed above the gate pad area to dope at the center The concentration is higher than the doping concentration at the edge, so that the path of the electrostatic discharge current can be more evenly dispersed without excessive concentration.

With the above detailed description of the preferred embodiments, it is hoped that the features and spirit of the present invention can be described more clearly, rather than limiting the scope of the present invention with the preferred embodiments disclosed above. On the contrary, it is intended to cover various changes and equivalent arrangements within the scope of the patent application of the present invention.

2‧‧‧Semiconductor components

ER‧‧‧Gate pad area

SUB‧‧‧Base

OXI‧‧‧Insulation

POLY‧‧‧Electrostatic discharge protection polysilicon layer

ILD‧‧‧Insulation

M1‧‧‧Metal layer

GM‧‧‧Gate metal layer

SM‧‧‧Source metal layer

PV‧‧‧Insulation

GCT‧‧‧Gate contact

SCT‧‧‧Source Contact

R1~R4‧‧‧‧First doped region~Four doped region

Claims (8)

A semiconductor device includes: a substrate defining a gate pad area; an electrostatic discharge protection polysilicon layer disposed above the gate pad area of the substrate and electrically isolated from the substrate, the electrostatic discharge protection polysilicon layer It includes: a first doped region with a first electrical property, a second doped region and a third doped region; and a fourth doped region with a second electrical property, wherein the first doped region The impurity region is located at the periphery of the gate pad region, the first doped region is connected to the second doped region, and the fourth doped region is disposed in the first doped region, the second doped region, and the third Between doped regions; a first insulating layer disposed above the ESD protection polysilicon layer; a first metal layer disposed above the first insulating layer, the first metal layer includes a first portion and a A second part, an isolation part is provided between the first part and the second part; and a first contact part and a second contact part are provided in the first insulating layer and penetrate the first part An insulating layer, the first contact is electrically connected to the first doped region and the first portion of the first metal layer, the second contact is electrically connected to the third doped region and the first metal The second part of the layer. The semiconductor device as described in item 1 of the patent application range, wherein the second doped region and the third doped region have a patterned configuration and are separated from each other. The semiconductor device as described in item 1 of the patent application scope further includes: a second metal layer, disposed on the first insulating layer, and having corresponding to the first doped region, the second doped region, and the The second metal layer pattern of the third doped region. The semiconductor device as described in item 3 of the patent application scope further includes: a second insulating layer disposed between the second metal layer and the ESD protection polysilicon layer, the second insulating layer including a plurality of contact portions, Respectively connecting the first doped region, the second doped region and the third doped region and the second metal corresponding to the first doped region, the second doped region and the third doped region Layer pattern. The semiconductor device of claim 3, wherein the second portion of the first metal layer is electrically isolated from the second doped region and the corresponding second metal layer. The semiconductor device as described in item 1 of the patent application range, wherein the doping concentration of the ESD protection polysilicon layer disposed at a central position of the gate pad region is higher than that provided at a periphery of the gate pad region The electrostatic discharge at the location protects the doping concentration of the polysilicon layer. The semiconductor device as described in item 1 of the patent application range, wherein when the semiconductor device operates normally, its operating voltage is lower than the breakdown voltage of the ESD protection polysilicon layer, the first doped region and the third doped region Not connected to each other. The semiconductor device as described in item 1 of the patent scope, wherein when an electrostatic discharge event occurs, the electrostatic discharge protection polysilicon layer is turned on due to breakdown, resulting in a current path from the first doped region to the second doped region On, an electrostatic discharge current flows from the first portion of the first metal layer and sequentially passes through the first contact and the third doped region, the fourth doped region, and the second doped region After flowing to the first doped region, it flows out through the second portion of the first metal layer.

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