TW201939284A - Mapping table management method applied to solid state storage device - Google Patents

Abstract

A mapping table management method applied to solid state storage device is provided. The method includes steps of: when a write command is received by a control circuit, the control circuit storing write data to a non-volatile memory and updating a mapping table in a DRAM; when a power down command is received by the control circuit, the control circuit storing the entire mapping table to the non-volatile memory; and when an update requirement is met judged by the control circuit, the control circuit storing a portion of the mapping table to the non-volatile memory.

Description

Correspondence table management method for solid-state storage device

The invention relates to a processing method of a solid-state storage device, and in particular, to a mapping table management method of a solid-state storage device.

As we all know, Solid State Storage Device (Solid State Storage Device) has been widely used in various electronic products, such as SD card, solid state hard disk, and so on. The solid-state storage device includes a non-volatile memory. After the data is written into the non-volatile memory, once the system power is turned off, the data is still stored in the non-volatile memory.

Please refer to FIG. 1, which is a schematic diagram of a conventional solid-state storage device. The control circuit 10 of the solid-state storage device 100 is connected to the host 150 via an external bus 110. The external bus 110 may be a USB bus, a SATA bus, a PCIe bus, an M.2 bus, or a U.2. Busbars and more.

Furthermore, the solid-state storage device 100 includes a control circuit 10, a dynamic random access memory (DRAM) 30, and a non-volatile memory 20. The control circuit 10 is connected to the non-volatile memory 20 and the DRAM 30.

Generally, the host 150 and the control circuit 10 access data using a logical block address (Logical Block Address, hereinafter referred to as an LBA address). The control circuit 10 and the non-volatile memory 20 use a physical allocation address (Physical Allocation Address, hereinafter referred to as a PAA address) to access data.

Therefore, a mapping table 32 is stored in the DRAM 30 of the solid-state storage device 100 to serve as a correspondence relationship between the LBA address and the PAA location. This correspondence table 32 is also referred to as a logical-to-physical address mapping table. The operation principle of the correspondence table 32 is described below.

When the host 150 writes data into the solid-state storage device 100, the host 150 sends a write instruction to the solid-state storage device 100. At this time, the write command includes the LBA address and the write data. Next, the control circuit 10 records the correspondence between the LBA address and the PAA address in the correspondence table 32 of the DRAM 30, and stores the written data in the storage space of the PAA address in the non-volatile memory.

When the host 150 wants to read data from the solid-state storage device 100, the host 150 sends a read command, and the read command includes an LBA address. When the control circuit 10 receives the read instruction, it finds the PAA address in the corresponding table 32 according to the LBA address. After that, the control circuit 10 obtains the read data from the storage space of the PAA address in the non-volatile memory 20 and transfers the read data to the host 150.

It can be known from the above description that when the solid-state storage device 100 is writing data, the control circuit 10 must simultaneously record the correspondence table 32 so that the control circuit 10 can grasp all the written data stored in the non-volatile memory 20 and is effective Management of data.

Since the correspondence table 32 is stored in the DRAM 30, and the data stored in the DRAM 30 will disappear once the system power is turned off, when the solid-state storage device 100 receives a power down command, the control circuit 10 must first After the mapping table 32 is stored in the non-volatile memory 20, the power can be turned off.

When the solid-state storage device 100 is powered again, the control circuit 10 must load the corresponding table in the non-volatile memory 20 into the DRAM 30 before the solid-state storage device 100 can operate normally.

As can be seen from the above description, the correspondence table 32 in the DRAM 30 records the correspondence relationship between the LBA address and the PAA address.

However, if the solid-state storage device 100 operates normally and accesses a lot of data, and the power supplied to the solid-state storage device 100 is suddenly cut off, the data of the corresponding table 32 in the DRAM 30 will be deleted.

In this way, when the solid-state storage device 100 is powered again, the control unit 10 can only load the old correspondence table from the non-volatile memory 20 into the DRAM 30. Next, the control circuit 10 must search all the storage spaces in the non-volatile memory 20, and gradually modify and rebuild the correspondence table 32.

After the control circuit 10 searches all the storage spaces in the non-volatile memory 20, the corresponding table 32 is rebuilt, and the solid-state storage device 100 can operate normally. However, the reconstruction of the correspondence table 32 described above takes a considerable time.

The invention relates to a correspondence table management method for a solid-state storage device. The solid-state storage device includes a control circuit, a dynamic random access memory, and a non-volatile memory. The correspondence table management method includes the following steps: when the control When the circuit receives a write command, the control circuit stores the write data into the non-volatile memory and updates a corresponding table in the dynamic random access memory; when the control circuit receives a shutdown command, the control circuit The control circuit stores the complete correspondence table in the dynamic random access memory to the non-volatile memory; and when the control circuit determines that an update condition is met, the control circuit stores a part of the dynamic random access memory The corresponding table is stored in the non-volatile memory.

In order to have a better understanding of the above and other aspects of the present invention, the embodiments are exemplified below and described in detail with the accompanying drawings as follows:

Please refer to FIG. 2, which illustrates a correspondence table management method according to the first embodiment of the present invention. Basically, the correspondence table management method disclosed in the first embodiment is applied to the solid-state storage device 100 in FIG. 1, and the structure of the solid-state storage device is not described here again.

During the normal operation of the solid-state storage device 100, when the control circuit 10 receives a write command from the host 150, the control circuit 10 will simultaneously record the written data in the DRAM 30 in addition to storing the written data in the non-volatile memory 20. The corresponding table 32.

According to the first embodiment of the present invention, when the solid-state storage device 100 is operating normally and no shutdown instruction is received (step S210), the control circuit 10 determines whether the update condition is met (step S320). When the control circuit 10 determines that the update conditions have been met (step S230), the control circuit 10 stores the complete correspondence table 32 in the DRAM 30 to the non-volatile memory 20 (step S240). Conversely, when the control circuit 10 determines that the update condition has not been met (step S230), it returns to step S210.

For example, the control circuit 10 may preset a data amount of 10 Mbyte as a judgment criterion for the update condition. Specifically, the control circuit 10 continuously calculates the total amount of data stored in the non-volatile memory 20. When the total amount of data written in the data reaches an integer multiple of the preset data amount, it means that the update conditions are met. . At this time, the control circuit 10 stores the complete correspondence table 32 in the DRAM 30 to the non-volatile memory 20.

In other words, when the stored write data reaches an integer multiple of 10 Mbytes (ie, 10 Mbyte, 20 Mbytes, 30 Mbytes ...), the control circuit 10 stores the complete correspondence table 32 in the DRAM 30 to the non-volatile memory 20. Conversely, when the stored written data does not reach an integer multiple of 10 Mbytes, the control circuit 10 only continues to calculate the total amount of data written, and does not store the corresponding table 32 in the DRAM 30 to the non-volatile memory 20.

Of course, if the solid-state storage device 100 receives the shutdown command (step S210), the control circuit 10 directly stores the complete correspondence table 32 in the DRAM 30 to the non-volatile memory (step S220). After that, the solid-state storage device 100 can be turned off.

During the normal operation of the solid-state storage device 100, the correspondence table 32 in the DRAM 30 is continuously updated. It can be known from the above description that during the normal operation of the solid-state storage device 100 of the present invention, the updated correspondence table 32 in the DRAM 30 is stored in the non-volatile memory 20. Therefore, when the solid-state storage device 100 is abnormally powered off, a newer correspondence table may be stored in the non-volatile memory 20.

In this way, when the solid-state storage device 100 is powered again, the control unit 10 can load the latest correspondence table stored in the non-volatile memory 20 before the power-off to the DRAM 30. The control circuit 10 then rebuilds the correct correspondence table based on the latest correspondence table 32. Since there are relatively few parts to be modified in the latest correspondence table 32, the time for rebuilding the correspondence table 32 can be effectively reduced.

As can be seen from the above description, using the correspondence table management method of the first embodiment of the present invention, when the solid-state storage device 100 is abnormally powered off and power is supplied to the solid-state storage device 100 again, the control circuit 10 can quickly reconstruct the correspondence table 32, and enables the solid-state storage device 100 to operate normally.

However, when the host 150 continuously stores written data to the solid-state storage device 100, the use of the first embodiment of the present invention may cause the write performance of the solid-state storage device 100 to decrease. described as follows:

Basically, the size of the correspondence table 32 is related to the total capacity of the non-volatile memory 20. As the total capacity of the non-volatile memory 20 increases, the size of the correspondence table also increases.

When the host 150 continuously stores a large amount of written data to the solid-state storage device 100, the control circuit 10 needs to continuously store the written data to the non-volatile memory 20 according to an instruction of the host 150. However, in the method disclosed in the first embodiment, when the total amount of data accumulated by the control circuit 10 reaches an integer multiple of the preset data amount, the control circuit 10 temporarily suspends storing the written data in the non-volatile memory 20, And the complete correspondence table 32 is stored in the non-volatile memory 20.

After the complete correspondence table 32 is stored in the non-volatile memory 20, the control circuit 10 will continue to store the written data in the non-volatile memory 20.

As can be seen from the above description, in the process of the host 150 continuously storing a large amount of written data to the solid-state storage device 100, the control circuit 20 will interrupt a period of time to store the corresponding table 32 after storing a preset amount of written data. Stored in non-volatile memory 20. After that, after the write data of the preset data amount is stored again, it is interrupted for a period of time to store the correspondence table 32 to the non-volatile memory 20, and is continuously repeated.

Obviously, in the above-mentioned operation process, the longer the time it takes to store the correspondence table 32, the more severely the write performance of the solid-state storage device 100 decreases. In other words, when the total capacity of the non-volatile memory 20 is larger and the size of the correspondence table 32 is larger, the write performance of the solid-state storage device 100 is more severely reduced.

Please refer to FIG. 3, which illustrates a correspondence table management method according to a second embodiment of the present invention. Similarly, the correspondence table management method disclosed in the second embodiment is applied to the solid-state storage device 100 in FIG. 1. In addition, the second embodiment differs from the first embodiment only in step S340. Only this step is described below, and the other steps are not repeated here.

When the control circuit 10 determines that the update conditions have been met (step S230), the control circuit 10 stores the correspondence table 32 of the part of the DRAM 30 to the non-volatile memory 20 (step S340).

According to the second embodiment of the present invention, the control circuit 10 divides the correspondence table 32 into M parts. When the control circuit 10 determines that the update conditions have been met, the control circuit 10 stores only the content of one of the M parts in the correspondence table 32 to the non-volatile memory 20. In this way, less time can be spent on storage.

For example, the data volume of 10 Mbyte is preset in the control circuit 10, and the control circuit 10 divides the correspondence table 32 into M parts. Furthermore, the control circuit 10 continuously calculates the total amount of data stored in the non-volatile memory 20. When the control circuit 10 determines that the update conditions have been met, the control circuit 10 stores the content of the first part of the corresponding table 32 to Non-volatile memory 20.

Similarly, when the control circuit 10 determines again that the update conditions have been met, the control circuit 10 stores the content of the second part of the correspondence table 32 to the non-volatile memory 20. Furthermore, after the control circuit 10 performs the Mth storage and stores the content of the M part of the corresponding table 32 to the non-volatile memory 20, it can be determined that the control circuit 10 has stored the entire content of the corresponding table 32 to the non-volatile memory. Sex memory 20.

Then, when the control circuit 10 performs the (M + 1) th storage, the control circuit 10 stores the contents of the first part of the correspondence table 32 to the non-volatile memory 20 again. And so on. In other words, whenever the control circuit 10 determines that the update conditions are met, the control circuit 10 sequentially selects one of the M sections in the correspondence table 32 in a circular manner and stores its content in the non-volatile memory 20.

During the normal operation of the solid-state storage device 100, the correspondence table 32 in the DRAM 30 is continuously updated. It can be known from the above description that during the normal operation of the solid-state storage device 100 of the present invention, the updated correspondence table 32 in the DRAM 30 is stored in the non-volatile memory 20. Therefore, when the solid-state storage device 100 is abnormally powered off, a newer correspondence table may be stored in the non-volatile memory 20. Therefore, when the solid-state storage device 100 is powered on again, the time taken to rebuild the correct correspondence table 32 can be effectively reduced.

Furthermore, since the control circuit 10 divides the correspondence table 32 into M parts, the time it takes to store a part of the contents of the correspondence table 32 each time is relatively short. Therefore, the correspondence table management method disclosed in the second embodiment can make the solid-state storage device 100 maintain a better write performance.

In the first embodiment and the second embodiment of the present invention, whether or not the total amount of stored written data reaches an integral multiple of a preset amount of data is used as a judgment criterion for the update condition. Of course, the present invention is not limited to this. Those skilled in the art may use other conditions to decide whether to store the updated correspondence table 32 in the non-volatile memory 20. For example, the control circuit 10 may calculate the total time taken to store the written data. When the accumulated total time reaches an integer multiple of a preset time, the updated correspondence table 32 is stored in the non-volatile memory. 20 moves.

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧Control circuit

20‧‧‧Non-volatile memory

30‧‧‧DRAM

32‧‧‧ Correspondence table

100‧‧‧ solid state storage device

110‧‧‧External bus

150‧‧‧host

FIG. 1 is a schematic diagram of a conventional solid-state storage device. FIG. 2 is a correspondence table management method according to the first embodiment of the present invention. FIG. 3 is a correspondence table management method according to a second embodiment of the present invention.

Claims (6)

A correspondence table management method for a solid-state storage device. The solid-state storage device includes a control circuit, a dynamic random access memory, and a non-volatile memory. The correspondence table management method includes the following steps: When the control circuit receives a When a command is written, the control circuit stores the written data in the non-volatile memory and updates a corresponding table in the dynamic random access memory; when the control circuit receives a shutdown command, the control circuit will The complete corresponding table in the dynamic random access memory is stored in the non-volatile memory; and when the control circuit determines that an update condition is met, the control circuit stores the corresponding part of the dynamic random access memory The watch is stored in the non-volatile memory. The correspondence table management method described in item 1 of the scope of patent application, wherein the correspondence table is a logical-to-physical address correspondence table. The correspondence table management method described in item 1 of the scope of patent application, further comprising the following steps: the control circuit calculates a total amount of data of the written data stored in the non-volatile memory; and when the total amount of data reaches When an integer multiple of a preset data amount, the control circuit determines that the update condition is met. The correspondence table management method described in item 1 of the scope of patent application, further comprising the following steps: the control circuit calculates a total time consumed for storing and writing data; and when the total time reaches an integer multiple of a preset time , The control circuit determines that the update condition is met. The correspondence table management method described in item 1 of the scope of patent application, wherein the correspondence table is divided into M parts, and when the control circuit determines that the update condition is met, the control circuit makes the M parts in the correspondence table One of the contents is stored in the non-volatile memory. According to the correspondence table management method described in item 1 of the scope of patent application, wherein the correspondence table is divided into M parts, and whenever the control circuit determines that the update condition is met, the control circuit sequentially selects the Correspond to one of the M parts in the table, and store its contents in the non-volatile memory.