TW201935644A - Semiconductor packages and methods of forming the semiconductor packages - Google Patents

Abstract

A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.

Description

Semiconductor package and method for forming semiconductor package

The present disclosure relates generally to semiconductor packages and methods of forming and testing the semiconductor packages. Cross-reference to related applications

This application claims the priority of Korean Application No. 10-2018-0013120 and Korean Application No. 10-2018-0112409, filed on February 1, 2018 and September 19, 2018, respectively, as described in the Korean patent The entire application is incorporated herein by reference.

Each semiconductor package is configured to include a package substrate on which at least one semiconductor wafer is mounted. The package substrate includes interconnection lines electrically connected to the semiconductor wafer. A part of the interconnection line may be coated with a plating layer. The plating layer can improve the bondability and conductivity between the interconnection line and the connector.

According to one embodiment, a semiconductor package includes: a semiconductor wafer; and a package substrate on which the semiconductor wafer is mounted. The package substrate includes: a base layer having a first surface and a second surface opposite to each other; a first bonding finger, the first bonding finger being provided on the base layer; On a first surface; a plated lead disposed on the first surface of the base layer in a manner spaced from the first bonding finger; a first conductive via, the A first conductive via is provided to substantially penetrate the base layer and is electrically connected to the first bonding finger; a second conductive via is provided to substantially penetrate the base layer and Electrically connected to the plated lead; a first ball pad and a second ball pad, the first ball pad and the second ball pad being disposed on the second surface of the base layer And are respectively connected to the first conductive via and the second conductive via; a first remaining part, the first remaining part is electrically connected to the first conductive via; a second remaining part, the first Two remaining portions are electrically connected to the second conductive through hole; and an opening, the opening is coupled to Remaining between said first portion and said second remaining portion to the remainder of the first portion and the second portion remaining spaced apart. The first ball soldering base may be electrically connected to the first remaining portion, the second ball soldering base may be electrically connected to the second remaining portion, and wherein the first ball soldering base and the first Both ball joints are coupled to substantially the same operating voltage.

According to one embodiment, a semiconductor package includes: a semiconductor wafer; and a package substrate on which the semiconductor wafer is mounted. The package substrate includes a base layer having a first surface and a second surface opposite to each other; a plurality of wires of the first layer, and the plurality of wires of the first layer are disposed on the base layer. On the first surface; a plurality of wires of the second layer, the plurality of wires of the second layer being disposed on the second surface of the base layer and electrically connected to the plurality of wires of the first layer A corresponding one of the plurality of wires; a plated lead electrically connected to a first wire of the plurality of wires of the first layer; a first remainder, the first remainder being electrically coupled to the A second wire of the plurality of wires of the second layer; a second remaining portion, the second remaining portion being electrically coupled to a third wire of the plurality of wires of the second layer; and an opening, the opening Coupling between the first remaining portion and the second remaining portion to space the first remaining portion from the second remaining portion. Both the second and third wires may be wires and may be coupled to substantially the same operating voltage.

According to one embodiment, a semiconductor package includes: a semiconductor wafer; and a package substrate on which the semiconductor wafer is mounted. The package substrate includes: a base layer having a first surface and a second surface opposite to each other; a first group of wires and a second group of wires, the first group of wires and the second group of wires being disposed On the first surface of the base layer; a third group of wires, the third group of wires being disposed on the second surface of the base layer and electrically connected to the first group of wires A corresponding wire; a fourth group of wires, the fourth group of wires being disposed on the second surface of the base layer and electrically connected to the corresponding wires in the second group of wires; The first plated lead is connected to a first wire in the first group of wires; the second plated lead is connected to a second wire in the second group of wires; A hole, the first opening is coupled between the first remaining portion and the second remaining portion to separate the first remaining portion and the second remaining portion, and to electrically connect the third group of wires to each other Open; and a second opening, the second opening is coupled between the third remaining portion and the fourth Between the remainder, to the remaining portion of the third and the fourth remaining portion spaced apart, and the fourth set of wires electrically disconnected from each other. Both the first remaining portion and the second remaining portion are wires and are coupled to a first operating voltage. Both the third remaining portion and the fourth remaining portion are another wire and are coupled to a second operating voltage different from the first operating voltage.

According to one embodiment, a method of forming a semiconductor package includes the steps of: forming a package substrate having a base layer whose first surface and second surface are opposed to each other; mounting a semiconductor wafer on the package substrate; A first bonding finger is provided on the first surface; a plated lead is provided on the first surface of the base layer in a manner spaced from the first bonding finger; A first conductive through hole electrically connected to the first bonding finger in the base layer; a second conductive through hole substantially passing through the base layer to be electrically connected to the plated lead; A first ball pad and a second ball pad are provided on the second surface, and the first ball pad and the second ball pad are respectively connected to the first conductive via and the second ball pad. A conductive via connection; providing a first temporary bridge line on the second surface of the base layer to electrically connect the first conductive via to the second conductive via; and forming a penetrating through Dielectric layer on the first temporary bridge line and The first temporary bridge connection openings cut open, to provide a first portion and a second remaining portion remaining spaced apart from each other. The first ball soldering base may be electrically coupled to the first remaining portion, and the second ball soldering base may be electrically coupled to the second remaining portion.

According to one embodiment, a method of forming a semiconductor package includes the steps of: forming a package substrate having a base layer whose first surface and second surface are opposed to each other; mounting a semiconductor wafer on the package substrate; A plurality of wires of a first layer are provided on the first surface; a plurality of wires of a second layer are provided on the second surface of the base layer, and the plurality of wires of the second layer are electrically connected to the A corresponding one of the plurality of wires of the first layer; electrically connecting the plated lead to the first one of the plurality of wires of the first layer; and using a temporary bridge wire to electrically electrically connect the plurality of wires of the second layer to each other Connecting; and forming an opening that penetrates a dielectric layer on the temporary bridge line and cuts the temporary bridge line to provide a first remaining portion and a second remaining portion spaced apart from each other. A second wire of the plurality of wires of the second layer may be electrically coupled to the first remaining portion, and a third wire of the plurality of wires of the second layer may be electrically coupled to the second remaining portion. .

According to one embodiment, a method of forming a semiconductor package includes the steps of: forming a package substrate having a base layer whose first surface and second surface are opposed to each other; mounting a semiconductor wafer on the package substrate; A first group of wires and a second group of wires are provided on the first surface; a third group of wires are provided on the second surface of the base layer, and the third group of wires is electrically connected to the first group of wires Corresponding wires in the group of wires; providing a fourth group of wires on the second surface of the base layer, and electrically connecting the fourth group of wires to corresponding wires in the second group of wires; A plated lead is connected to a first wire of the first set of wires; a second plated lead is connected to a second wire of the second set of wires; a first set of temporary bridge wires is provided to connect the third A group of wires is electrically connected to each other; a second group of temporary bridge wires is provided to electrically connect the fourth group of wires to each other; a dielectric layer penetrating the first group of temporary bridge wires is formed and the first group of temporary bridge wires One of the temporary Wiring a cut first opening to provide a first remainder and a second remainder spaced from each other; and forming a temporary bridge that penetrates the dielectric layer and bridges another one of the first set of temporary bridge lines The second opening is cut by wire to provide a third remaining portion and a fourth remaining portion spaced apart from each other.

The terms used herein may correspond to words selected in consideration of their function in the embodiment, and the meaning of the terms may be interpreted differently according to those skilled in the art to which the embodiment belongs. If a term is defined in detail, it can be interpreted according to the definition. Unless otherwise defined, terms (including scientific and technical terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

It should be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another and are not used to define the element itself or to mean a particular sequence.

It will also be understood that when an element or layer is referred to as being "above", "above", "below", "below", or "outside" another element or layer, the element or layer may be associated with another element or layer. The layers are in direct contact, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers should be interpreted in a similar fashion (for example, "between" and "directly between" or "adjacent to" and " Directly next to ").

Spatially relative terms such as "below", "below", "lower", "above", "upper", "top", "bottom", etc. may be used to describe, for example, the figures The relationship between an element and / or feature shown and another element and / or feature. It should be understood that spatially relative terms are intended to cover different directions of the device in use and / or operation in addition to the directions shown in the figures. For example, when the device in the figures is turned over, elements described as below and / or below other elements or features would then be oriented above other elements or features. The device may be otherwise oriented (rotated 90 degrees or in other directions) and the spatially relative descriptors used herein interpreted accordingly.

The semiconductor package may include an electronic device such as a semiconductor wafer or a semiconductor wafer. A semiconductor wafer or semiconductor wafer can be obtained by separating a semiconductor substrate such as a wafer into a plurality of pieces using a die sawing process. The semiconductor chip may correspond to a memory chip, a logic chip (including an application-specific integrated circuit (ASIC) chip), or a system-on-chip (SoC). The memory chip may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, an inverse-type flash memory circuit, an inverse-or-type flash memory circuit integrated on a semiconductor substrate , Magnetic random access memory (MRAM) circuit, resistive random access memory (ReRAM) circuit, ferroelectric random access memory (FeRAM) circuit or phase change random access memory (PcRAM) circuit. The logic chip may include a logic circuit integrated on a semiconductor substrate. Semiconductor packages can be used in communication systems such as mobile phones, electronic systems related to biotechnology or healthcare, or wearable electronic systems.

In the description, the same reference numerals denote the same elements. Although a reference numeral is not mentioned or described with reference to a drawing, the reference numeral may be mentioned or described with reference to another drawing. In addition, even if a reference sign is not shown in one drawing, the reference sign may be shown in another drawing.

In a semiconductor package, a semiconductor wafer may be mounted on a package substrate. The package substrate may be configured to include interconnect lines electrically connected to the semiconductor wafer. Some portions of the interconnect lines may be coated with a plating layer that is in contact with the connector of the semiconductor package. The plating layer can improve the joinability between the interconnection line and the connector and the conductivity of the interconnection line.

The plating layer can be formed using an electroplating process. Interconnect lines can be connected to the plated lines to form a plated layer using a plating process. The plated line may be a long conductive pattern extending from an edge of the package substrate to connect with an interconnection line (used as a signal line). The plated wire may be a wire required for an electroplating process. However, the plated line does not function as an interconnection line for a signal line during a semiconductor packaging operation.

When a semiconductor package is operated, a plated line can be used as an undesired transmission line such as a stub. If the plated line is connected to the signal line, the plated line can be used as a circuitous path of a signal or a reflection path of a signal. Since the plated line undesirably reflects a signal, the plated line can degrade the transmission speed of the signal, the operating characteristics of the semiconductor package, or the signal integrity of the semiconductor package. The present disclosure provides semiconductor packages each including a package substrate having a reduced total length of plated lines.

Changes in the external environment such as humidity or temperature may cause the electrochemical migration (ECM) of the package substrate to fail. The present disclosure provides semiconductor packages each employing a package substrate capable of suppressing or preventing ECM failure.

FIG. 1 is a cross-sectional view schematically showing a semiconductor package 10 according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view schematically showing a package substrate 100 included in a semiconductor package according to an embodiment. The package substrate 100 of FIG. 2 corresponds to the package substrate 100F shown in FIG. 1 before the opening 117 of the package substrate 100F is formed. FIG. 3 is a plan view schematically showing a top circuit layout 101 of the package substrate 100 shown in FIG. 2. FIG. 4 is a plan view schematically showing a bottom circuit layout 102 of the package substrate 100 shown in FIG. 2.

Referring to FIG. 1, the semiconductor package 10 may include a semiconductor wafer 130 mounted on a package substrate 100F. The package substrate 100F may include a plated lead 121, a first remaining portion 122A of the temporary bridge line 126 for plating, and a second remaining portion 122B of the temporary bridge line 126 for plating. The opening 117 can cut the temporary bridge line 126 into two parts, the first remaining part 122A and the second remaining part 122B, which face each other. That is, the first remaining portion 122A and the second remaining portion 122B of the temporary bridge line 126 for plating may be separated from each other by the opening 117. The first remaining portion 122A and the second remaining portion 122B of the temporary bridge line 126 may be connected to the interconnection lines to which the same operating voltage is applied, respectively.

The semiconductor wafer 130 may be mounted on the first dielectric layer 115 of the package substrate 100F. The mold layer 139 may be disposed on the first dielectric layer 115 of the package substrate 100F to cover the semiconductor wafer 130. A bonding wire 135 may be provided to electrically connect the contact pads 131 of the semiconductor wafer 130 to the bonding fingers 140 of the package substrate 100F. The bonding wire 135 may be connected to the bonding finger 140 through the first plating layer 151. The package substrate 100F may further include a second plating layer 152 to which the solder balls 136 serving as external connectors may be attached.

Referring to FIG. 2, the package substrate 100 may correspond to a pre-packaged substrate having a state before the opening 117 shown in FIG. 1 is formed. The package substrate 100 may include a base layer 110 and a plated line disposed on the base layer 110. The base layer 110 may be a dielectric layer used as a body or a core of the package substrate 100. The plated line may include a plated lead 121 and a temporary bridge line 126 for plating. The temporary bridge line 126 may include a first temporary bridge line 122. As shown in FIG. 3, the temporary bridge line 126 may further include a second temporary bridge line 123, a third temporary bridge line 124, and a fourth temporary bridge line 125.

The base layer 110 may have a first surface 111 and a second surface 112 opposite to each other. The first dielectric layer 115 may be disposed on the first surface 111 of the base layer 110, and the second dielectric layer 116 may be disposed on the second surface 112 of the base layer 110. Each of the first dielectric layer 115 and the second dielectric layer 116 may be formed of a material layer including a solder resist layer. The package substrate 100 may be a printed circuit board (PCB). The package substrate 100 may have a ball gate array (BGA) structure.

The package substrate 100 may include a boundary region 104 and an inner region 103 surrounded by the boundary region 104 in a plan view. The package substrate 100 may further include another inner region 103 ′ adjacent to the inner region 103, and the other inner region 103 ′ may be connected to the inner region 103 through the boundary region 104.

The semiconductor wafer 130 may be mounted on the inner region 103 of the package substrate 100. Interconnection lines electrically connected to the semiconductor wafer 130 may be provided in the inner region 103. The semiconductor wafer 130 may be mounted on the first surface 111 of the base layer 110. The semiconductor wafer 130 may be attached to the first dielectric layer 115. The boundary region 104 may be removed in the final step of the packaging process that encapsulates the semiconductor wafer 130. After the plurality of semiconductor wafers (including the semiconductor wafer 130) mounted on the package substrate 100 are molded through the molding layer (139 of FIG. 1), the boundary region may be removed by a cutting process for separating discrete semiconductor packages from each other. 104.

Referring to FIG. 3, the top circuit layout 101 may include a top interconnection line disposed on the first surface 111 of the base layer 110. As shown in the top circuit layout 101 of FIG. 3, the top interconnection line may include a bonding finger 140, a trace pattern 160 on the first layer, and a plated lead 121.

The engagement fingers 140 may be disposed on the first surface 111 of the base layer 110 in a manner of being spaced apart from each other. For example, the engagement fingers 140 may include a first engagement finger 141, a second engagement finger 142, and a third engagement finger 143 disposed on the first surface 111 of the base layer 110 in a spaced-apart manner from each other. And fourth engagement fingers 144. The bonding fingers 140 may be provided in a periphery of the semiconductor wafer 130 to be electrically connected to the semiconductor wafer 130.

The first, third, and fourth bonding fingers 141, 143, and 144 of the bonding fingers 140 may be used as portions of a signal line that transmits a signal to the semiconductor wafer 130. The signals transmitted by the first engagement finger 141, the third engagement finger 143, and the fourth engagement finger 144 may include a data signal, an address signal, and a command signal. Therefore, a signal may be transmitted to or output from the semiconductor wafer 130 through the first, third, and fourth bonding fingers 141, 143, and 144. In addition, the second engaging finger 142 may be a part of any non-signal line. Non-signal lines may include power lines and ground lines. Therefore, a power supply voltage or a ground voltage may be applied to the semiconductor wafer 130 through the second bonding finger 142.

The trace pattern 160 of the first layer may be a wire extending from the bonding finger 140. The trace pattern 160 of the first layer may electrically connect the bonding fingers 140 to the conductive vias 180. The trace pattern 160 of the first layer may include a first trace pattern 161, a second trace pattern 162, a third trace pattern 163, and a fourth trace pattern 164.

2 and 4, the bottom circuit layout 102 may include a bottom interconnection line disposed on the second surface 112 of the base layer 110. As shown in the bottom circuit layout 102 of FIG. 4, the bottom interconnection line may include a ball pad 190, a trace pattern 170 of the second layer, and a temporary bridge line 126 for plating. The trace pattern 170 of the second layer may be disposed on the second surface 112 of the base layer 110.

The conductive via 180 may electrically connect the trace pattern 160 of the first layer to the trace pattern 170 of the second layer. The first ends of the conductive vias 180 may be respectively connected to the trace patterns 160 of the first layer, and the second ends of the conductive vias 180 may be respectively connected to the trace patterns 170 of the second layer. The conductive via 180 may be a conductive pattern that vertically penetrates the base layer 110. The trace pattern 170 of the second layer may include a fifth trace pattern 171, a sixth trace pattern 172, a seventh trace pattern 173, and an eighth trace pattern 174. The terms "first" to "eighth" used in the trace patterns 160 and 170 should not be limited by these terms. These terms "first" to "eighth" are only used to distinguish one element from another element, and are not used to limit the element itself or to mean a specific sequence.

The ball pads 190 may be electrically connected to the trace patterns 170 of the second layer, respectively. The trace pattern 170 of the second layer may electrically connect the conductive via 180 to the ball pad 190. An external connector (not shown) may be attached to the ball pad 190 to electrically connect the package substrate 100 to an external device or an external system. The outer connector may include solder balls.

2 and 3, the bonding fingers 140 may be connected to the semiconductor wafer 130 through an internal connector. For example, the first bonding finger 141 may be electrically connected to one of the contact pads 131 of the semiconductor wafer 130 through one of the bonding wires 135. Although FIG. 3 shows an example in which the bonding wire 135 is used as the internal connector, the internal connector may be a conductive member other than the bonding wire 135. For example, in some other embodiments, the inner connector may be a conductive bump.

The first plating layer 151 may be formed on a part of each of the bonding fingers 140. The first plating layer 151 may improve the bondability between the bonding wire 135 and the bonding finger 140. In addition, the first plating layer 151 may improve a contact resistance value between the bonding wire 135 and the bonding finger 140. If the bonding fingers 140 are formed of a copper layer, the first plating layer 151 may be formed of a material layer capable of preventing corrosion and contamination of the copper layer. The first plating layer 151 may be formed using an electroplating process. The first plating layer 151 may be formed to include a conductive material different from the bonding finger 140. For example, the first plating layer 151 may be formed to include a nickel layer and a gold layer.

Referring to FIGS. 2 and 4, a second plating layer 152 may be formed on each of the ball pads 190. The second plating layer 152 may be formed of a material layer capable of preventing the ball pad 190 from being oxidized. The second plating layer 152 may be formed of a material layer capable of suppressing excessive formation of an intermetallic compound material when an external connector (for example, a solder ball) is attached to the ball pad 190. The first plating layer 151 and the second plating layer 152 may be formed simultaneously using a single plating process. Alternatively, the first plating layer 151 and the second plating layer 152 may be independently formed using two separate plating processes.

Referring again to FIG. 2, the plating process used to form the first plating layer 151 and the second plating layer 152 may require a plating current to be applied to the bonding fingers 140 and the ball pad 190. In this case, a plating current may be applied to the bonding fingers 140 and the ball pad 190 through a plating line structure including a plating lead 121, a temporary bridge line 126 for plating, and a plating bus 129 on.

Referring to FIG. 3, a plating bus 129 may be disposed in a boundary region 104 of the package substrate 100. The plating bus 129 may be formed on the first surface 111 of the base layer 110 in the boundary region 104 of the package substrate 100. The plated lead 121 may be a lead branched from the plated bus 129. The plated lead 121 may extend from the plated bus 129 and may be electrically connected to the second bonding finger 142. For example, the plated lead 121 may be coupled to the second trace pattern 162 and may be electrically connected to the second bonding finger 142 through the second trace pattern 162. Although not shown in the drawings, in some other embodiments, the plated lead 121 may be directly connected to the second bonding finger 142 without any intermediate element.

The plated lead 121 may be disposed on the first surface 111 of the base layer 110, and may be connected only to the second bonding finger 142 among the bonding fingers 140 disposed on the first surface 111 of the base layer 110. The plated lead 121 may be connected to the second bonding finger 142 through the second trace pattern 162. The plated leads 121 may be disposed on the first surface 111 of the base layer 110 in a manner spaced apart from the first bonding fingers 141. The plated lead 121 may not be directly connected to the first trace pattern 161, the third trace pattern 163, and the fourth trace pattern 164 on the first surface 111 of the base layer 110. The plated lead 121 may not be directly connected to the first bonding finger 141, the third bonding finger 143, and the fourth bonding finger 144 on the first surface 111 of the base layer 110.

The second bonding finger 142 and the second trace pattern 162 may constitute a part of any one of non-signal lines such as a power line and a ground line. In contrast, the first joint finger 141 and the first trace pattern 161 may constitute a part of any one of the signal lines, and the third joint finger 143 and the third trace pattern 163 may constitute a part of the signal line. A part of another signal line, and the fourth bonding finger 144 and the fourth trace pattern 164 may constitute a part of another signal line among the signal lines. The plated lead 121 may be connected only to non-signal lines provided on the first surface 111 of the base layer 110, and may not be directly connected to signal lines provided on the first surface 111 of the base layer 110.

Referring to FIG. 2, when the plating lead 121 and the plating bus 129 are disposed on the first surface 111 of the base layer 110, a temporary bridge line 126 for plating may be disposed on the second surface 112 of the base layer 110. That is, the plating lead 121 may be provided on the surface of the base layer 110 opposite to the temporary bridge line 126 for plating, and the temporary bridge line 126 for plating may be provided on the base layer 110 and the plating The lead 121 is on the opposite surface.

Referring to FIG. 4, the temporary bridge lines 126 for plating may electrically connect the conductive vias 180 spaced apart from each other. Therefore, a plating current between the conductive vias 180 may flow through the temporary bridge line 126 for plating during the plating process, and the temporary bridge line 126 for plating may be cut after the plating. The plating current applied on the plating lead 121 may flow through the temporary bridge line 126 and the conductive via 180 for plating to reach the first bonding finger 141, the third bonding finger 143, and the fourth bonding Fingers 144.

2 and 4, a fifth trace pattern 171 electrically connected to the first ball pad 191 in the ball pad 190 may be disposed on the second surface 112 of the base layer 110. The first ball pad 191 may be electrically connected to the first conductive via 181 in the conductive via 180. The fifth trace pattern 171 may be connected to the first conductive via 181 and may be electrically connected to the first trace pattern 161 through the first conductive via 181. The first ball pad 191 may be electrically connected to the first bonding finger 141 through the fifth trace pattern 171, the first conductive via 181, and the first trace pattern 161. The first ball pad 191, the fifth trace pattern 171, the first conductive through hole 181, the first trace pattern 161, and the first bonding finger 141 may provide one of the signal lines.

The second ball soldering base 192 of the ball soldering bases 190 may be disposed to be spaced apart from the first ball soldering base 191. The second ball pad 192 may be electrically connected to the second conductive via 182. The first temporary bridge line 122 of the temporary bridge lines 126 may electrically connect the first ball pad 191 to the second ball pad 192. The first temporary bridge line 122 may electrically connect the fifth trace pattern 171 to the sixth trace pattern 172. The fifth trace pattern 171 may electrically connect the first ball pad 191 to the first conductive via 181. The sixth trace pattern 172 may electrically connect the second ball pad 192 to the second conductive via 182. The first ball pad 191 may be electrically connected to the second ball pad 192 through the first temporary bridge line 122, the fifth trace pattern 171, and the sixth trace pattern 172. The first temporary bridge line 122 may electrically connect the first conductive via 181 to the second conductive via 182. The second ball pad 192, the sixth trace pattern 172, the second conductive via 182, the second trace pattern 162, and the second bonding finger 142 may provide a power line or a ground line.

The fifth trace pattern 171 and the sixth trace pattern 172 may be conductive patterns provided on the second surface 112 of the base layer 110 in a manner spaced apart from each other. The second conductive via 182 may be disposed to be spaced apart from the first conductive via 181. The second conductive via 182 may be electrically connected to the plated lead 121 on the first surface 111 of the base layer 110. The first conductive via 181 may be electrically connected to the first bonding finger 141 on the first surface 111 of the base layer 110.

The first temporary bridge line 122 may connect the first conductive via 181 to the second conductive via 182. The first temporary bridge line 122 may electrically connect the first bonding finger 141 and the first ball pad 191 to the plated lead 121. A plating current applied through the plating lead 121 may flow through the first temporary bridge line 122 to reach the first bonding finger 141 and the first ball pad 191.

The plating current applied through the plating bus 129 may flow through the plating lead 121, the second trace pattern 162, the second conductive via 182, the sixth trace pattern 172, the first temporary bridge line 122, and the fifth trace. The line pattern 171, the first conductive via 181, and the first trace pattern 161 reach the first bonding finger 141. Since a plating current is applied to the first bonding fingers 141, the first plating layer 151 may be formed on the first bonding fingers 141 by a plating technique.

The plating current applied on the plating bus 129 may flow through the plating lead 121, the second trace pattern 162, the second conductive via 182, the sixth trace pattern 172, the first temporary bridge line 122, and the fifth The trace pattern 171 reaches the first ball pad 191. When a plating current is simultaneously applied to the first bonding finger 141 and the first ball soldering base 191, a first The plating layer 151 and the second plating layer 152.

The plating current applied on the plating bus 129 may flow through the plating lead 121, the second trace pattern 162, the second conductive via 182, and the sixth trace pattern 172 to reach the second ball pad 192. Since the second trace pattern 162 is connected to the second bonding finger 142 (see FIG. 3), the plating current applied through the plating bus 129 can also reach the second bonding finger 142. Therefore, the first plating layer 151 and the second plating layer 152 can be simultaneously formed on the second bonding fingers 142 and the second ball welding seat 192 by electroplating technology, respectively.

3 and 4, the second temporary bridge line 123 of the temporary bridge line 126 and the first temporary bridge line 122 of the temporary bridge line 126 may electrically connect the plated lead 121 to the third bonding finger 143 and the ball The third ball welding seat 193 in the welding seat 190. The second temporary bridge line 123 may electrically connect the first temporary bridge line 122 to the third conductive via 183 and a seventh trace pattern 173 connected to the third conductive via 183. Although FIG. 4 shows an example in which the second temporary bridge line 123 is directly connected to the first temporary bridge line 122, in some other embodiments, the second temporary bridge line 123 may be directly connected to the first ball welding seat 191 and the first A two-ball pad 192 or a fifth trace pattern 171 and a sixth trace pattern 172.

The third temporary bridge line 124 and the first temporary bridge line 122 and the second temporary bridge line 123 of the temporary bridge line 126 may electrically connect the plated lead 121 to the first of the fourth bonding fingers 144 and the ball pad 190. Four ball welding seat 194. The third temporary bridge line 124 may be electrically connected to the first temporary bridge line 122 through the second temporary bridge line 123. The fourth conductive via 184 of the conductive vias 180 may be electrically connected to the first temporary bridge line 122 through the second temporary bridge line 123 and the third temporary bridge line 124. The second temporary bridge line 123 may be electrically connected to the eighth trace pattern 174 and the fourth conductive via 184 through the third temporary bridge line 124.

A fourth temporary bridge line 125 of the temporary bridge lines may be extended to electrically connect the plated lead 121 to an additional bonding finger (not shown) in the bonding finger 140 and an additional ball bonding in the ball bonding pad 190. Block (not shown). That is, the plated lead 121 may be electrically connected to the additional bonding finger and the additional ball pad through the first temporary bridge line 122, the second temporary bridge line 123, the third temporary bridge line 124, and the fourth temporary bridge line 125. .

As described above, the temporary bridging wires 126 may be provided to electrically connect the ball bonding pads 190 to each other. The first bonding finger 141, the third bonding finger 143, and the fourth bonding finger 144 may not be directly connected to the plated lead 121 on the first surface 111 of the base layer 110. However, the first bonding finger 141, the third bonding finger 143, and the fourth bonding finger 144 may be electrically connected to the plated lead 121 through the temporary bridge line 126 and the conductive via 180.

Due to the existence of the temporary bridge line 126, an additional plated lead other than the plated lead 121 may not be needed on the first surface 111 of the base layer 110. That is, according to one embodiment, additional plating for directly connecting the first, third, and fourth bonding fingers 141, 143, and 144 to the plating bus 129 may not be required. lead.

When a plating current is applied through the plating bus 129, the plating lead 121, and the temporary bridge line 126, the first plating layer 151 and the second plating layer 152 may be formed by a plating technique. After the first plating layer 151 and the second plating layer 152 are formed, the temporary bridge line 126 may be cut. That is, each temporary bridge line 126 may be cut to have an electrically open state.

FIG. 5 is a cross-sectional view schematically showing a package substrate 100F including an opening 117 in one embodiment of the present disclosure. FIG. 6 is a plan view schematically showing a bottom surface 116S of the package substrate 100F including the opening 117 in one embodiment of the present disclosure. FIG. 7 is a plan view showing a top circuit layout 101 of the package substrate 100F shown in FIG. 5.

5 to 7, after the first plating layer 151 and the second plating layer 152 are formed, a central portion of the temporary bridge line 126 may be removed to form an opening 117. For example, the central portion 122C of the first temporary bridge line 122 may be removed to form one of the openings 117. The opening 117 may be formed at the bottom surface 116S of the package substrate 100F. The bottom surface 116S of the package substrate 100F may be provided by a surface of the second dielectric layer 116. The opening 117 may be formed to penetrate the second dielectric layer 116. The openings 117 may be formed using an etching process applied to a part of the second dielectric layer 116. One of the openings 117 may be formed by removing a portion of the second dielectric layer 116 to expose the central portion 122C of the first temporary bridge line 122 and by removing the exposed central portion 122C of the first temporary bridge line 122.

The side surface of the remaining portion of the temporary bridge line 126 may be exposed along the side wall 117W of the opening 117. For example, the side surfaces of the first remaining portion 122A and the second remaining portion 122B of the first temporary bridge line 122 may be exposed along the side wall 117W of one opening 117. The first remaining portion 122A and the second remaining portion 122B may be separated by the opening 117. When the central portion 122C corresponding to the junction of the first temporary bridge line 122 and the second temporary bridge line 123 is removed to form the opening 117, the first remaining portion 122A and the second remaining portion 122B of the first temporary bridge line 122 The side surface of the second side and the remaining surface 123A of the second temporary bridge line 123 may be exposed and defined by the side wall 117W of the opening 117.

An opening 117 may be provided in the second dielectric layer 116. A center portion 122C of the first temporary bridge line 122 may be removed to provide an opening 117. The first remaining portion 122A and the second remaining portion 122B are separated from each other by the opening 117. Since the first remaining portion 122A and the second remaining portion 122B of the first temporary bridge line 122 are physically spaced from each other, the first temporary bridge line 122 may have an electrically open state. A joint portion of the first temporary bridge line 122 and the second temporary bridge line 123 may be removed to provide an opening 117. The remaining portions 122A, 122B, and 123A are separated from each other by the opening 117.

The ball bonding pads 190 in FIG. 4 may be electrically connected to each other through a temporary bridge line 126. In FIGS. 5 to 7, since the temporary bridge line 126 is cut while forming the opening 117, the ball bonding pads 190 may be electrically isolated from each other. For example, the first ball pad 191 may be electrically disconnected from the second ball pad 192 to the fourth ball pad 194 through the opening 117.

4 and 6, the first ball bonding pad 191 may be connected to the first remaining portion 122A of the first temporary bridge line 122 through the fifth trace pattern 171. In addition, the second ball bonding pad 192 may be connected to the second remaining portion 122B of the first temporary bridge line 122 through the sixth trace pattern 172.

Referring to FIGS. 1, 4 and 6, the first ball pad 191 and the second ball pad 192 may correspond to ball pads to which an operating voltage for operating the semiconductor wafer 130 of the semiconductor package 10 is applied. The operating voltages applied to the first ball pad 191 and the second ball pad 192 may have the same voltage level. For example, when the semiconductor wafer 130 is operating, a voltage signal having 1.17 V may be applied to the first ball pad 191 and may be transmitted to the first bonding finger 141. Therefore, the electrical path between the first ball pad 191 and the first engaging finger 141 may correspond to a signal line transmitting a voltage signal having a voltage of 1.17 V. In addition, a power supply voltage of 1.17 V may be applied to the second ball pad 192. In this case, the electrical path between the second ball pad 192 and the second engagement finger 142 corresponds to a power line transmitting a power supply voltage of 1.17 V. As a result, a power supply voltage having the same voltage level as the voltage signal applied to the first ball pad 191 can be applied to the second ball pad 192. That is, the same operation voltage may be applied to both the first ball soldering base 191 and the second ball soldering base 192. The first ball bonding pad 191 and the second ball bonding pad 192 to which the same operating voltage is applied may be electrically connected to each other through the first temporary bridge line 122, as shown in FIG. 4. In this case, a power supply line having a power supply voltage different from 1.17 V or a ground line having a ground voltage may not be connected to the first temporary bridge line 122.

FIG. 8 is a plan view schematically showing a top circuit layout 101-1 of a package substrate 100-1 according to another embodiment of the present disclosure. FIG. 9 is a plan view schematically showing a bottom circuit layout 102-1 of the package substrate 100-1 shown in FIG. 8. In FIGS. 8 and 9, the same reference numerals as those in FIGS. 3, 4, 6, and 7 are used to denote the same elements.

Referring to FIG. 8, the top circuit layout 101-1 of the package substrate 100-1 may have a plated line structure including a first plated lead 121 and a second plated lead 121-1 spaced from each other and including The first group of temporary bridge lines 126 and the second group of temporary bridge lines 126-1 spaced from the first group of temporary bridge lines 126. The top circuit layout 101-1 may further include a first group of wires 160 and a second group of wires 160-1.

The first plated lead 121 and the second plated lead 121-1 may be disposed on the first surface 111 of the base layer 110 in a manner spaced apart from each other. The first plated lead 121 may be connected to one of the first group of wires 160, for example, the first wire 162. The first conductive line 162 may correspond to the second trace pattern 162 shown in FIG. 3. The first set of wires 160 may correspond to the trace pattern 160 of the first layer shown in FIG. 3. The first set of wires 160 may include a first trace pattern 161, a second trace pattern 162, a third trace pattern 163, and a fourth trace pattern 164.

The first set of wires 160 may connect the first set of bonding fingers 140 to the first set of conductive vias 180. The first set of engagement fingers 140 may correspond to the engagement fingers 140 shown in FIG. 3. Accordingly, the first set of engaging fingers 140 may include first to fourth engaging fingers 141 to 144. The first group of conductive vias 180 may correspond to the conductive vias 180 shown in FIG. 3. Therefore, the first group of conductive vias 180 may include first to fourth conductive vias 181 to 184.

The second plated lead 121-1 may be connected to one of the wires in the second group of wires 160-1, for example, the second wire 161-1. The second group of wires 160-1 may include a second wire 161-1, a third wire 162-1, and a fourth wire 163-1. The second set of wires 160-1 may connect the second set of bonding fingers 140-1 to the second set of conductive vias 180-1. The second set of engagement fingers 140-1 may include a fifth engagement finger 141-1, a sixth engagement finger 142-1, and a seventh engagement finger 143-1. The second group of conductive vias 180-1 may include a fifth conductive via 181-1, a sixth conductive via 182-1, and a seventh conductive via 183-1. The first group of wires 160 and the second group of wires 160-1 may be disposed on the first surface 111 of the base layer 110 in a manner of being spaced apart from each other.

Referring to FIG. 9, the third group of wires 170 and the fourth group of wires 170-1 may be disposed on the second surface 112 of the base layer 110. The first set of temporary bridge wires 126 may electrically connect the third set of wires 170 to each other. The third group of conductive lines 170 may correspond to the trace pattern 170 of the second layer shown in FIG. 4. Therefore, the third group of conductive lines 170 may include the fifth to eighth trace patterns 171 to 174. The second set of temporary bridge wires 126-1 may electrically connect the fourth set of wires 170-1 to each other. The fourth group of wires 170-1 may include a fifth wire 171-1, a sixth wire 172-1, and a seventh wire 173-1.

The second dielectric layer may be patterned to provide a first opening 117 and a second opening 117-1. The first opening 117 may penetrate the central portion 122C of the first temporary bridge line 122 among the first group of temporary bridge lines 126 to cut the first temporary bridge line 122 into a first remaining portion 122A and a second remaining portion separated from each other.部 122B. A central portion 122C of the first temporary bridge line 122 may be removed to form a first opening 117. A portion of the second temporary bridge line 123 may be removed by the first opening 117 in which the first temporary bridge line 122 is cut to provide a remaining portion 123A separate from the first remaining portion 122A and the second remaining portion 122B. A third opening 117-2 may be additionally provided in a manner spaced apart from the first opening 117.

The second opening 117-1 can penetrate the center portion 122C-1 of one of the temporary bridge lines 122-1 in the second group of temporary bridge lines 122-1 to cut the temporary bridge lines 122-1 into third ones separated from each other. The remaining portion 122A-1 and the fourth remaining portion 122B-1. A center portion 122C-1 of one temporary bridge line 122-1 in the second group of temporary bridge lines 122-1 may be removed to form a second opening 117-1. In addition, the second opening 117-1 can also cut a part of another temporary bridge line 123-1 in the second group of temporary bridge lines 126-1 to provide a third remaining portion 122A-1 and a fourth remaining portion 122B. -1 separates the remainder 123A-1.

The first remaining portion 122A and the second remaining portion 122B may be wires to which the same operating voltage having the first voltage level is applied. An operating voltage having a first voltage level may be applied to the first ball pad 191 and the second ball pad 192 connected to the first remaining portion 122A and the second remaining portion 122B, respectively. The first ball soldering base 191 and the second ball soldering base 192 may be included in a first group of ball soldering bases 190 corresponding to the ball soldering bases 190 shown in FIG. 4.

The second remaining portion 122B may be connected to a power line transmitting a power supply voltage, and the first remaining portion 122A may be connected to a signal line transmitting a data signal, an address signal, or a command signal.

The first remaining portion 122A may be connected to a signal line configured to transmit a data input / output (DQ) to a semiconductor wafer. The second remaining portion 122B may be connected to a power line configured to provide an output stage drain power voltage (VDDQ) to the semiconductor wafer.

The first remaining portion 122A may be connected to a first signal line that transmits at least one of a data signal, an address signal, and a command signal to the semiconductor wafer. The second remaining portion 122B may be connected to a second signal line.

The third remaining portion 122A-1 and the fourth remaining portion 122B-1 may be wires to which the same operating voltage having the second voltage level is applied. An operating voltage having a second voltage level may be applied to the first ball pad 191-1 and the second ball pad 192-1 connected to the third remaining portion 122A-1 and the fourth remaining portion 122B-1, respectively. The first ball soldering base 191-1 and the second ball soldering base 192-1 may be included in the second group of ball soldering bases 190-1. The third remaining portion 122A-1 may be connected to a first ground line coupled to the semiconductor wafer 130, and the fourth remaining portion 122B-1 may be connected to a second ground line coupled to the semiconductor wafer 130.

The operation voltage applied to the third group of wires 170 may have a voltage level different from the voltage level of the operation voltage applied to the fourth group of wires 170-1. Therefore, the operation voltages applied to the first and second remaining portions 122A and 122B may be different from the operation voltages applied to the third and fourth remaining portions 122A-1 and 122B-1. The second set of temporary bridge lines 126-1 may electrically connect only the interconnection lines having the same voltage level to each other.

Referring again to FIG. 1, the package substrate 100F of the semiconductor package 10 may include the first remaining portion 122A and the second remaining portion 122B of any one of the plated lead 121 and the first temporary bridge line 122 of the temporary bridge line 126.

Referring to FIGS. 1 and 7, the plated lead 121 may be limited to be connected to only the second conductive via 182 and the second bonding finger 142. In addition, as shown in FIGS. 6 and 7, the temporary bridge line 126 may be cut to have an electrically open state by forming an opening 117.

Referring again to FIGS. 2 and 3, the package substrate 100 may include a first layer of wires disposed on the first surface 111 of the base layer 110. The wires of the first layer may include a trace pattern 160 and bonding fingers 140 of the first layer. Referring to FIGS. 2 and 4, the package substrate 100 may include a second layer of wires disposed on the second surface 112 of the base layer 110. The wires of the second layer may include a trace pattern 170 and a ball pad 190 of the second layer. The wires of the second layer may be electrically connected to the wires of the first layer through the conductive vias 180. The plated lead 121 may be connected to a first trace pattern 161 corresponding to the first conductive line among the conductive lines of the first layer. The temporary bridge line 126 may electrically connect the wires of the second layer to each other.

A wire (for example, the second trace pattern 162) connected to the plated lead 121 may be used as a part of a power supply line that supplies a power supply voltage to the semiconductor wafer 130. Alternatively, the second trace pattern 162 may be used as a part of a ground line that supplies a ground voltage to the semiconductor wafer 130.

Referring to FIG. 5, a central portion 122C of the first temporary bridge line 122 may be cut to provide one of the openings 117. The first remaining portion 122A and the second remaining portion 122B are separated from each other by one of the openings 117. The first remaining portion 122A may be connected to a second wire among the wires of the second layer, and the second remaining portion 122B may be connected to the third wire among the wires of the second layer. The second conductive line may correspond to the fifth trace pattern 171, and the third conductive line may correspond to the sixth trace pattern 172. The same operating voltage may be applied to both the second wire connected to the first remaining portion 122A and the third wire connected to the second remaining portion 122B.

The second conductive line may be used as a signal line that applies a data signal, an address signal, or a command signal to the semiconductor wafer 130. The third conductive line may be used as a power supply line that supplies a power supply voltage to the semiconductor wafer 130. Alternatively, the second conductive line may be used as a first ground line coupled to the semiconductor wafer 130, and the third conductive line may be used as a second ground line coupled to the semiconductor wafer 130.

The second conductive line may be configured to transmit a data input / output (DQ) to the semiconductor wafer 130. The third wire may be configured to provide an output stage drain power supply voltage (VDDQ) to the semiconductor wafer 130.

The second conductive line may be configured to function as a first signal line that transmits at least one of a data signal, an address signal, and a command signal to the semiconductor wafer 130. The third conductive line may be configured to function as a second signal line.

FIG. 10 is a cross-sectional view showing the semiconductor package 10 to which the operating voltages V1 and V2 are applied. 11 is a cross-sectional view illustrating an electrochemical migration (ECM) phenomenon occurring in a package substrate 10R of a semiconductor package according to a comparative example.

Referring to FIG. 10, a reliability test may be performed on the semiconductor package 10. For example, a highly accelerated stress test (HAST) can be performed as a reliability test. The reliability of the semiconductor package 10 can be tested by applying a bias voltage to the semiconductor package 10 under high temperature and high humidity conditions. The bias voltage applied to the semiconductor package 10 may be a voltage bias whose level is substantially the same as the operating voltage of the semiconductor package 10. For example, a first voltage V1 may be applied to the second ball pad 192 of the semiconductor package 10, and a second voltage V2 may be applied to the first ball pad 191 of the semiconductor package 10. The first voltage V1 may be about 1.17 V, and the second voltage V2 may be about 1.17 V.

The second ball pad 192, the second conductive through hole 182, and the second bonding finger 142 may constitute a power line configured to supply a power voltage to the semiconductor wafer. The first ball pad 191, the first conductive through hole 181, and the first bonding finger 141 may constitute a signal line configured to transmit at least one of a data signal, an address signal, and a command signal to the semiconductor wafer.

The second ball pad 192, the second conductive via 182, and the second bonding finger 142 may constitute a signal line configured to transmit a data input / output (DQ) to the semiconductor wafer. The first ball pad 191, the first conductive through hole 181, and the first bonding finger 141 may constitute a power line configured to provide an output stage drain power voltage (VDDQ) to the semiconductor wafer.

The first ball pad 191, the first conductive via 181, and the first bonding finger 141 may constitute a first ground line configured to provide a ground voltage to the semiconductor wafer. The second ball pad 192, the second conductive via 182, and the second bonding finger 142 may constitute a second ground line configured to provide another ground voltage to the semiconductor wafer.

The first ball pad 191, the first conductive through hole 181, and the first bonding finger 141 may constitute a first signal line configured to transmit a first data input / output (DQ) to a semiconductor wafer. The second ball pad 192, the second conductive via 182, and the second bonding finger 142 may constitute a second signal line configured to transmit a second data input / output (DQ) to the semiconductor wafer.

The first ball pad 191, the first conductive via 181, and the first bonding finger 141 may constitute a power line configured to provide a drain power voltage (VDD) to the semiconductor wafer. The second ball pad 192, the second conductive via 182, and the second bonding finger 142 may constitute a signal line configured to transmit a row address (CA) to the semiconductor wafer.

Since the side surfaces of the first and second remaining portions 122A and 122B are exposed at the side walls of the opening 117, the HAST can be performed while the side surfaces of the first and second remaining portions 122A and 122B are exposed to the test environment . In this case, the same voltage (for example, a voltage of 1.17 V) may be applied to both the first remaining portion 122A and the second remaining portion 122B. That is, the voltage difference between the first remaining portion 122A and the second remaining portion 122B may be zero in theory. Therefore, the ECM phenomenon does not occur in a region between the first remaining portion 122A and the second remaining portion 122B.

Referring to FIG. 11, the package substrate 10R of the comparative example may include a base layer 5100 and first and second dielectric layers 5115 and 5116 provided on the top and bottom surfaces of the base layer 5100, respectively. An opening 5117 may be formed in the second dielectric layer 5116. The temporary bridge line may be cut to provide an opening 5117. The first remaining portion 5122A and the second remaining portion 5122B are spaced apart from each other by an opening 5117. Therefore, the first remaining portion 5122A and the second remaining portion 5122B are spaced apart from each other by the opening 5117. Therefore, the side surfaces of the first remaining portion 5122A and the second remaining portion 5122B may be exposed through the opening 5117. When a third voltage V3 is applied to the first remaining portion 5122A and a fourth voltage V4 different from the third voltage V3 is applied to the second remaining portion 5122B, a voltage between the first remaining portion 5122A and the second remaining portion 5122B may occur. difference. In this case, an ECM phenomenon may occur in a region between the first remaining portion 5122A and the second remaining portion 5122B. The ECM phenomenon may cause migration and precipitation of metal ions between the first remaining portion 5122A and the second remaining portion 5122B to generate an abnormal conductive layer 5119 between the first remaining portion 5122A and the second remaining portion 5122B. The abnormally conductive layer 5119 may cause an electrical short-circuit failure between the first remaining portion 5122A and the second remaining portion 5122B. That is, the abnormal conductive layer 5119 may electrically connect the first conductive line 5171 coupled with the first remaining portion 5122A to the second conductive line 5172 coupled with the second remaining portion 5122B.

Referring again to FIG. 10, since the same voltage is applied to both the first and second remaining portions 122A and 122B, it is possible to suppress the first and second remaining portions 122A and 122B while performing the HAST of the semiconductor package 10. ECM phenomenon. Therefore, the reliability of the semiconductor package 10 can be improved.

FIG. 12 is a plan view illustrating a top circuit layout 201 of a package substrate 200 included in a semiconductor package according to an embodiment of the present disclosure. FIG. 13 is a plan view showing a top circuit layout 301 of a package substrate 300 included in a semiconductor package according to a comparative example.

The top circuit layout 201 of the package substrate 200 shown in FIG. 12 shows interconnection lines provided on the inner region 203 of the package substrate 200. The plated leads 221-1, 221-2, and 221-3 may be designed not to be directly connected to the first lead 260S on the first surface 211 of the base layer of the package substrate 200. The first conductive line 260S may include a signal line that transmits a data signal or a command / address signal to the semiconductor wafer 230 mounted on the package substrate 200. The first conductive line 260S may include a first trace pattern 261-1, a first bonding finger 241-1, and a first conductive via 281.

Each of the plated leads 221-1, 221-2, and 221-3 may be provided to be connected to a non-signal line such as a power line or a ground plane. For example, the first plated lead 221-1 of the plated leads 221-1, 221-2, and 221-3 may branch from the plated bus 229 and may be connected to the second wire 260P. The second conductive line 260P may include a second trace pattern 262-1, a second bonding finger 242-1, and a second conductive via 282. The second conductive line 260P may constitute a first power supply line for supplying a power supply voltage to the semiconductor wafer 230. The second plated lead 221-2 of the plated leads 221-1, 221-2, and 221-3 may be provided to connect the plated bus 229 to the ground plane 262-2. The third plated lead 221-3 of the plated leads 221-1, 221-2, and 221-3 may be provided to connect the second power line to the plated bus 229.

The first plated lead 221-1, the second plated lead 221-1, and the third plated lead 221-3 may be provided to be connected to only the power line and the ground on the first surface 211 of the base layer of the package substrate 200 flat. In contrast, the top circuit layout 301 of the package substrate 300 shown in FIG. 13 includes a plurality of plated leads 322 branched from the plated bus 329. In the top circuit layout 301, the plated leads 322 may be connected to signal lines 362 which are respectively electrically connected to the semiconductor wafer 330 mounted on the package substrate 300. Thus, the number of plated leads 322 may be much larger than the number of plated leads 221-1, 221-2, and 221-3.

The plated leads 322 respectively connected to the signal lines 362 may function as stubs corresponding to an undesired transmission line during a semiconductor package operation. Therefore, when signals are input to or output from the semiconductor wafer 330, the plated leads 322 may cause unwanted signal reflection, thereby degrading the signal integrity of the semiconductor package.

As can be seen from FIGS. 12 and 13, the number of plated leads 221-1, 221-2, and 221-3 is much smaller than the number of plated leads 322. That is, the total length of the plated leads 221-1, 221-2, and 221-3 included in the package substrate 200 can be significantly reduced compared to the total length of the plated leads 322 included in the package substrate 300 . In addition, the plated leads 221-1, 221-2, and 221-3 in FIG. 12 may not be electrically connected to the signal line 260S. Therefore, the plated leads 221-1, 221-2, and 221-3 can be prevented from acting as stubs.

According to the embodiment, the number of plated leads provided in the semiconductor package can be significantly reduced. That is, the number of plated leads provided on the package substrate of the semiconductor package can be reduced. This can lead to a reduction in the overall length of the plated leads. Therefore, the plated leads can suppress the deterioration of the operating characteristics or signal integrity of the semiconductor package. The package substrate of the semiconductor package may be configured to prevent or suppress an ECM phenomenon.

FIG. 14 is a block diagram showing an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to the embodiment. The memory card 7800 includes a memory 7810 and a memory controller 7820 such as a non-volatile memory device. The memory 7810 and the memory controller 7820 may store data or read the stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one package according to an embodiment.

The memory 7810 may include a non-volatile memory device to which the technology of the embodiment of the present disclosure is applied. The memory controller 7820 may control the memory 7810 such that the stored data is read out or stored in response to a read / write request from the host 7830.

FIG. 15 is a block diagram showing an electronic system 8710 including at least one of the semiconductor packages according to the embodiment. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled to each other through a bus 8715 that provides a path for data movement.

In one embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to an embodiment of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands and the like to be executed by the controller 8711.

The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory can be installed to an information processing system such as a mobile terminal or a desktop computer. Flash memory can form a solid state drive (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

The electronic system 8710 may further include an interface 8714 configured to send data to and receive data from the communication network. The interface 8714 may be a wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, mobile systems can be in personal digital assistants (PDAs), portable computers, tablets, mobile phones, smartphones, wireless phones, laptops, memory cards, digital music systems, and information sending / receiving systems. anyone.

If the electronic system 8710 is a device capable of performing wireless communication, the electronic system 8710 can use CDMA (Divided Code Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Mobile Phone), E-TDMA (Enhanced Time Multiple Access), WCDAM (Wide Band Division Multiple Access), CDMA2000, LTE (Long Term Evolution) or Wibro (Wireless Broadband Internet) technology for use in communication systems.

Embodiments of the present disclosure have been disclosed for exemplary purposes. It will be understood by those skilled in the art that various modifications, additions and substitutions may be made without departing from the scope and spirit of the scope of the disclosure and the appended patents.

10‧‧‧Semiconductor Package

10R‧‧‧Packaging substrate

100‧‧‧ package substrate

100-1‧‧‧package substrate

100F‧‧‧package substrate

101‧‧‧Top Circuit Layout

101-1‧‧‧Top Circuit Layout

102‧‧‧Bottom Circuit Layout

102-1‧‧‧Bottom circuit layout

103‧‧‧Internal area

103’‧‧‧Internal area

104‧‧‧Border area

110‧‧‧ base layer

111‧‧‧ surface

112‧‧‧ surface

115‧‧‧ Dielectric layer

116‧‧‧ Dielectric layer

116S‧‧‧ bottom surface

117‧‧‧ opening

117-1‧‧‧Opening

117-2‧‧‧Opening

117W‧‧‧ sidewall

121‧‧‧ plated lead

121-1‧‧‧plated lead

122‧‧‧Temporary Bridge Line

122-1‧‧‧Temporary bridge line

122A‧‧‧Remaining

122A-1‧‧‧Remaining

122B‧‧‧Remaining

122B-1‧‧‧Remaining

122C‧‧‧Center

122C-1‧‧‧Center

123‧‧‧Temporary Bridge Cable

123-1‧‧‧Temporary bridge line

123A‧‧‧Remaining

123A-1‧‧‧Remaining

124‧‧‧Temporary Bridge Line

125‧‧‧Temporary Bridge Line

126‧‧‧Temporary bridge line

126-1‧‧‧Temporary bridge line

129‧‧‧plated bus

130‧‧‧Semiconductor wafer

131‧‧‧contact pad

135‧‧‧ bonding wire

136‧‧‧Solder Ball

139‧‧‧moulding layer

140‧‧‧ finger joints

140-1‧‧‧joining fingers

141‧‧‧joining fingers

141-1‧‧‧joining fingers

142‧‧‧joining fingers

142-1‧‧‧joining fingers

143‧‧‧joining fingers

143-1‧‧‧joining fingers

144‧‧‧joining fingers

151‧‧‧Plating

152‧‧‧Plating

160‧‧‧Wire

160-1‧‧‧Wire

161‧‧‧trace pattern

161-1‧‧‧Wire

162‧‧‧trace pattern

162-1‧‧‧Wire

163‧‧‧trace pattern

163-1‧‧‧Wire

164‧‧‧trace pattern

170‧‧‧Wire

170-1‧‧‧Wire

171‧‧‧trace pattern

171-1‧‧‧Wire

172‧‧‧trace pattern

172-1‧‧‧Wire

173‧‧‧trace pattern

173-1‧‧‧Wire

174‧‧‧trace pattern

180‧‧‧ conductive via

180-1‧‧‧ conductive via

181‧‧‧ conductive via

181-1‧‧‧ conductive via

182‧‧‧ conductive via

182-1‧‧‧Conductive via

183‧‧‧ conductive via

183-1‧‧‧ conductive via

184‧‧‧ conductive via

190‧‧‧Ball Welding Base

190-1‧‧‧Ball Welding Base

191‧‧‧Ball Welding Base

191-1‧‧‧Ball Welding Base

192‧‧‧ Ball Welding Base

192-1‧‧‧Ball Welding Base

193‧‧‧Ball Welding Base

194‧‧‧Ball Welding Base

200‧‧‧ package substrate

201‧‧‧Top Circuit Layout

203‧‧‧Internal area

211‧‧‧ surface

221-1‧‧‧Plated lead

221-2‧‧‧Plated lead

221-3‧‧‧Plated lead

229‧‧‧plated bus

230‧‧‧Semiconductor wafer

241-1‧‧‧joining fingers

261-1‧‧‧trace pattern

260S‧‧‧Wire

262-1‧‧‧trace pattern

262-2‧‧‧ ground plane

242-1‧‧‧joining fingers

281‧‧‧ conductive via

282‧‧‧ conductive via

300‧‧‧ package substrate

301‧‧‧Top circuit layout

322‧‧‧plated lead

329‧‧‧plated bus

330‧‧‧Semiconductor wafer

362‧‧‧Signal cable

5100‧‧‧Matrix

5115‧‧‧Dielectric layer

5116‧‧‧Dielectric layer

5117‧‧‧Opening

5119‧‧‧ abnormal conductive layer

5122A‧‧‧Remaining

5122B‧‧‧Remaining

5171‧‧‧Wire

5172‧‧‧Wire

7800‧‧‧Memory Card

7810‧‧‧Memory

7820‧‧‧Memory Controller

7830‧‧‧Host

8710‧‧‧Electronic System

8712‧‧‧Input / Output Device

8713‧‧‧Memory

8714‧‧‧Interface

FIG. 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

FIG. 2 is a cross-sectional view schematically showing a package substrate before an opening is formed in one embodiment of the present disclosure.

FIG. 3 is a plan view schematically showing a top circuit layout of the package substrate shown in FIG. 2.

FIG. 4 is a plan view schematically showing a bottom circuit layout of the package substrate shown in FIG. 2.

FIG. 5 is a cross-sectional view schematically showing a package substrate including an opening in an embodiment of the present disclosure.

6, 7, 8, and 9 are plan views schematically illustrating a package substrate including an opening in some embodiments of the present disclosure.

FIG. 10 is a cross-sectional view illustrating a state where a voltage is applied to a semiconductor package according to an embodiment of the present disclosure.

FIG. 11 is a cross-sectional view illustrating an example in which an electrochemical migration (ECM) phenomenon occurs in a semiconductor package.

FIG. 12 is a plan view illustrating a top circuit layout of a package substrate included in a semiconductor package according to an embodiment of the present disclosure.

13 is a plan view showing a top circuit layout of a package substrate included in a semiconductor package according to a comparative example.

FIG. 14 is a block diagram showing an electronic system employing a memory card including a semiconductor package according to an embodiment.

FIG. 15 is a block diagram illustrating another electronic system including a semiconductor package according to an embodiment.

Claims (26)

A semiconductor package includes: a semiconductor wafer; and a package substrate on which the semiconductor wafer is mounted, wherein the package substrate includes: a base layer, the base layer having first substrates facing each other; A surface and a second surface; a first bonding finger that is disposed on the first surface of the base layer; a plated lead, the plated lead to communicate with the first A bonding finger is disposed on the first surface of the base layer in a spaced manner; a first conductive via is provided to substantially penetrate the base layer and is electrically connected to the base layer. The first bonding finger; a second conductive via, the second conductive via being configured to substantially penetrate the base layer and be electrically connected to the plated lead; a first ball pad and a second ball bond A base, the first ball solder base and the second ball solder base are disposed on the second surface of the base layer and connected to the first conductive via and the second conductive via, respectively ; A first remaining part, the first remaining part is electrically connected to the first conductive via; a second remaining part, the second remaining part is electrically connected to the second conductive via; and an opening, the An opening is coupled between the first remaining portion and the second remaining portion to space the first remaining portion from the second remaining portion, wherein the first ball soldering socket is electrically connected to The first remaining part, the second ball joint are electrically connected to the second remaining part, and wherein both the first ball joint and the second ball joint are coupled to substantially the same operation Voltage. The semiconductor package according to claim 1, further comprising: a first plating layer, the first plating layer being formed on the first bonding finger; and a second plating layer, the A second plating layer is formed on the first ball pad and the second ball pad. The semiconductor package according to claim 1, wherein the second conductive via is electrically separated from the first conductive via through the opening, and the plated lead is separated from the first conductive via through the opening. An engaging finger is electrically separated. The semiconductor package according to claim 1, further comprising a second bonding finger spaced apart from the first bonding finger and electrically connected to the plating The manner of the lead is provided on the first surface of the base layer. The semiconductor package according to claim 4, wherein the second ball pad, the second conductive via, and the second bonding finger constitute a power source configured to supply a power source voltage to the semiconductor wafer. And wherein the first ball pad, the first conductive via, and the first bonding finger constitute at least one of a data signal, an address signal, and a command signal configured to transmit to the semiconductor wafer. A signal line. The semiconductor package according to claim 4, wherein the second ball pad, the second conductive via, and the second bonding finger constitute a data input / output configured to transmit to the semiconductor wafer And the first ball pad, the first conductive via, and the first bonding finger constitute a power line configured to provide an output stage drain power voltage to the semiconductor wafer . The semiconductor package according to claim 4, wherein the first ball pad, the first conductive via, and the first bonding finger constitute a first portion configured to provide a ground voltage to the semiconductor wafer. A ground wire; and wherein the second ball pad, the second conductive via, and the second bonding finger constitute a second ground wire configured to provide another ground voltage to the semiconductor wafer . The semiconductor package according to claim 4, wherein the second ball pad, the second conductive via, and the second bonding finger are configured to transmit a first data input to the semiconductor wafer. / Output of the first signal line; and wherein the second ball pad, the second conductive via, and the second bonding finger constitute a second data input / Output of the second signal line. According to the semiconductor package according to claim 4, the semiconductor package further comprises: a first trace pattern, the first trace pattern being disposed on the first surface of the base layer, so that the first trace pattern A bonding finger is connected to the first conductive via; and a second trace pattern that is spaced apart from the first trace pattern and connects the second bonding finger To the second conductive via. According to the semiconductor package of claim 9, the semiconductor package further comprises: a third bonding finger and a fourth bonding finger, the third bonding finger and the fourth bonding finger to communicate with all The first engaging finger and the second engaging finger are disposed on the first surface of the base layer in a manner spaced apart from each other; the third conductive via and the fourth conductive via, The third conductive via and the fourth conductive via are spaced apart from the first conductive via and the second conductive via; a third trace pattern, and the third trace pattern A third bonding finger is connected to the third conductive via; and a fourth trace pattern that connects the fourth bonding finger to the fourth conductive via. According to the semiconductor package according to claim 10, the semiconductor package further includes a third remaining portion, the third remaining portion is coupled between the third conductive via and the opening, wherein the opening will be The first remaining portion and the second remaining portion are spaced from the third remaining portion. A semiconductor package includes: a semiconductor wafer; and a package substrate on which the semiconductor wafer is mounted, wherein the package substrate includes: a base layer, the base layer having first substrates facing each other; A surface and a second surface; a plurality of wires of a first layer, the plurality of wires of the first layer being disposed on the first surface of the base layer; a plurality of wires of a second layer, the second A plurality of wires of a layer are disposed on the second surface of the base layer and are electrically connected to corresponding ones of the plurality of wires of the first layer; a plated lead electrically connected to A first wire of the plurality of wires of the first layer; a first remaining portion, the first remaining portion being electrically coupled to a second wire of the plurality of wires of the second layer; The second remaining portion is electrically coupled to a third wire of the plurality of wires of the second layer; and an opening is coupled between the first remaining portion and the second remaining portion to Will the first The remainder is spaced from the second remainder, wherein both the second lead and the third lead are leads and are coupled to substantially the same operating voltage. The semiconductor package according to claim 12, wherein the second conductive line is configured to function as a signal line that transmits at least one of a data signal, an address signal, and a command signal to the semiconductor wafer; and wherein the first The three wires are configured to be used as a power supply line for supplying a power supply voltage to the semiconductor wafer. The semiconductor package according to claim 12, wherein the second wire is configured to function as a first ground wire and is configured to provide a first ground voltage to the semiconductor wafer; and wherein the third wire is It is configured to function as a second ground line and is configured to provide a second ground voltage to the semiconductor wafer. The semiconductor package according to claim 12, wherein the second wire is configured to transmit data input / output to the semiconductor wafer; and wherein the third wire is configured to provide an output stage to the semiconductor wafer Drain Supply Voltage. The semiconductor package according to claim 12, wherein the second wire is configured to function as a first signal line that transmits at least one of a data signal, an address signal, and a command signal to the semiconductor wafer; and wherein The third conductive line is configured to function as a second signal line. The semiconductor package according to claim 12, further comprising: a first plating layer formed on a portion of each of the plurality of wires of the first layer; and Two plating layers, the second plating layer being formed on a part of each of the plurality of wires of the second layer. A semiconductor package includes: a semiconductor wafer; and a package substrate on which the semiconductor wafer is mounted, wherein the package substrate includes: a base layer, the base layer having first substrates facing each other; A surface and a second surface; a first group of wires and a second group of wires, the first group of wires and the second group of wires being disposed on the first surface of the base layer; a third group of wires, all The third group of wires is disposed on the second surface of the base layer and is electrically connected to a corresponding one of the first groups of wires; a fourth group of wires, the fourth group of wires being disposed on the On the second surface of the base layer and electrically connected to a corresponding wire in the second group of wires; a first plated lead connected to the first wire in the first group of wires A second plated lead, the second plated lead is connected to a second wire in the second set of wires; a first opening, the first opening is coupled to the first remaining portion and the second remaining Between the first remaining portion and the second remaining portion and electrically disconnecting the third group of wires from each other; and a second opening, the second opening is coupled to the first Between the three remaining portions and the fourth remaining portion to separate the third remaining portion from the fourth remaining portion and to electrically disconnect the fourth group of wires from each other, wherein the first remaining portion And the second remainder are both wires and are coupled to a first operating voltage, and wherein the third remainder and the fourth remainder are both other wires and are coupled to the first operation A second operating voltage having a different voltage. The semiconductor package according to claim 18, wherein the first remaining portion is connected to a signal line configured to transmit at least one of a data signal, an address signal, and a command signal to the semiconductor wafer; and wherein the The second remaining portion is connected to a power line configured to supply a power voltage to the semiconductor wafer. The semiconductor package according to claim 18, wherein the first remaining portion is connected to a signal line configured to transmit data input / output to the semiconductor wafer; and wherein the second remaining portion is configured to be A power line connection that provides an output stage drain power supply voltage to the semiconductor wafer. The semiconductor package according to claim 18, wherein the first remaining portion is connected to a first signal line that transmits at least one of a data signal, an address signal, and a command signal to the semiconductor wafer; and wherein the first The two remaining portions are connected to the second signal line. The semiconductor package according to claim 18, wherein the third remaining portion is connected to a first ground line configured to provide a first ground voltage to the semiconductor wafer; and wherein the fourth remaining portion is connected to the A second ground line connection configured to provide a second ground voltage to the semiconductor wafer. A method of forming a semiconductor package, the method comprising the steps of: forming a package substrate having a base layer having a first surface and a second surface facing each other; mounting a semiconductor wafer on the package substrate; A first bonding finger is provided on one surface; a plating lead is provided on the first surface of the base layer in a manner spaced from the first bonding finger; A first conductive via that is electrically connected to the first bonding finger; a second conductive via that is substantially penetrated through the base layer to be electrically connected to the plating lead; A first ball pad and a second ball pad are provided on the two surfaces, and the first ball pad and the second ball pad are respectively connected to the first conductive via and the second conductive via. Connecting; providing a first temporary bridge line on the second surface of the base layer to electrically connect the first conductive via to the second conductive via; and forming a penetration through the first temporary Bridge line The first temporary bridge line and an opening cut by the first temporary bridge line to provide a first remaining portion and a second remaining portion spaced apart from each other, wherein the first ball pad is electrically coupled to the first A remainder, and the second ball pad is electrically coupled to the second remainder. According to the method of claim 23, the method further comprises the steps of: on the first surface of the base layer, spaced apart from the first bonding finger and electrically connected to the plated lead A second engaging finger is provided in a manner; a third engaging finger is provided on the first surface of the base layer so as to be spaced apart from the first engaging finger and the second engaging finger A third conductive via is provided to substantially penetrate the base layer and is electrically connected to the third bonding finger through a trace pattern; a second temporary bridge line is provided to electrically connect the third conductive via to The first temporary bridge line; and using the opening to cut a joint portion of the first temporary bridge line and the second temporary bridge line to provide the second temporary bridge line with the first remaining And a remaining portion spaced from the second remaining portion. A method of forming a semiconductor package, the method comprising the steps of: forming a package substrate having a base layer having a first surface and a second surface facing each other; mounting a semiconductor wafer on the package substrate; A plurality of wires of a first layer are provided on one surface; a plurality of wires of a second layer are provided on the second surface of the base layer, and the plurality of wires of the second layer are electrically connected to the first layer A corresponding one of the plurality of wires of the first wire; electrically connecting the plated lead to the first wire of the plurality of wires of the first layer; electrically connecting the plurality of wires of the second layer to each other with a temporary bridge wire; and Forming an opening that penetrates the dielectric layer on the temporary bridge line and cuts the temporary bridge line to provide a first remaining portion and a second remaining portion spaced apart from each other, wherein A second wire of the plurality of wires is electrically coupled to the first remaining portion, and a third wire of the plurality of wires of the second layer is electrically coupled to the second remaining portion. A method of forming a semiconductor package, the method comprising the steps of: forming a package substrate having a base layer having a first surface and a second surface facing each other; mounting a semiconductor wafer on the package substrate; A first group of wires and a second group of wires are provided on one surface; a third group of wires is provided on the second surface of the base layer, and the third group of wires is electrically connected to the first group of wires A corresponding group of wires; a fourth group of wires is provided on the second surface of the base layer, and the fourth group of wires is electrically connected to a corresponding one of the second group of wires; a first plated lead Connected to a first wire of the first group of wires; connecting a second plated lead to a second wire of the second group of wires; providing a first group of temporary bridge wires to connect the third group of wires to each other Electrical connection; setting a second group of temporary bridge wires to electrically connect the fourth group of wires to each other; forming a dielectric layer penetrating the first group of temporary bridge wires and bridging the first group of temporary bridges A first opening in which a temporary bridging line in the line is cut to provide a first remainder and a second remainder spaced apart from each other; and forming the first set of temporary bridge lines penetrating the dielectric layer The second opening in the other temporary bridging line is cut to provide a third remaining portion and a fourth remaining portion spaced apart from each other.